Display device and driving method therefor

Abstract

A display device and a driving method therefor. Each pixel driving circuit (102) in the display device (100) comprises a driving transistor (T1) connected between a first voltage line and a light-emitting element (101), a first reset transistor (T2) and a data writing transistor (T5) connected to a gate electrode of the driving transistor (T1), a second reset transistor (T3) connected to a source electrode of the driving transistor (T1), and a first switch transistor (T4) connected between the first voltage line and a drain electrode of the driving transistor (T1). At moments when the first reset transistor (T2) and the data writing transistor (T5) are sequentially turned on, the driving transistor (T1) is turned on at both moments, and the first switch transistor (T4) is turned on and turned off at respective moments, thus improving the compensation effect for threshold voltages of driving transistors in a plurality of pixel driving circuits.

Description

Display device and its driving method

[0001] This application claims priority to Chinese patent application No. 202510370582.0, filed on March 26, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more specifically to display devices and their driving methods. Background Technology

[0003] In current self-emissive display products, when the pixel driving circuit is working in the data writing stage, the driving transistor is in the conducting state, which causes electrical conduction between the high-voltage signal line and the source of the driving transistor. This results in the potential of the source of the driving transistor being continuously charged by the high-voltage signal, causing the gate-source voltage of the driving transistor to include a distortion voltage during the light-emitting stage due to the rise of its source potential during the data writing stage. This distortion voltage is related to the threshold voltage of the driving transistor, weakening the compensation effect on the threshold voltage of the driving transistor in the pixel driving circuit. Invention Overview

[0004] The purpose of this application is to provide a display device and its driving method to improve the problem of weakened threshold voltage compensation effect in the pixel driving circuit of existing self-emissive display products.

[0005] In a first aspect, embodiments of this application provide a display device including a plurality of sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel driving circuit, the pixel driving circuit including:

[0006] A driving transistor, wherein one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element;

[0007] The first reset transistor is electrically connected to the gate of the driving transistor and is used to transmit a first reset signal to the gate of the driving transistor according to the first control signal.

[0008] The second reset transistor is electrically connected to the other of the source and drain of the driving transistor, and is used to transmit a second reset signal to the other of the source and drain of the driving transistor according to the second control signal.

[0009] The first switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor, and is used to control the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to the third control signal.

[0010] A data writing transistor is electrically connected to the gate of the driving transistor and is used to transmit a data signal to the gate of the driving transistor according to a fourth control signal.

[0011] When the first reset transistor is turned on in response to the first control signal, the drive transistor is turned on, and the first switch transistor is turned on in response to the third control signal;

[0012] When the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal;

[0013] Wherein, before the first reset transistor is turned on in response to the first control signal, the second reset transistor is turned on in response to the second control signal;

[0014] The pulse of the first control signal is in the same time period as the pulse of the third control signal.

[0015] Secondly, embodiments of this application provide a display device including a plurality of sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel driving circuit, the pixel driving circuit including:

[0016] A driving transistor, wherein one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element;

[0017] The first reset transistor is electrically connected to the gate of the driving transistor and is used to transmit a first reset signal to the gate of the driving transistor according to the first control signal.

[0018] The second reset transistor is electrically connected to the other of the source and drain of the driving transistor, and is used to transmit a second reset signal to the other of the source and drain of the driving transistor according to the second control signal.

[0019] The first switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor, and is used to control the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to the third control signal.

[0020] A data writing transistor is electrically connected to the gate of the driving transistor and is used to transmit a data signal to the gate of the driving transistor according to a fourth control signal.

[0021] When the first reset transistor is turned on in response to the first control signal, the drive transistor is turned on, and the first switch transistor is turned on in response to the third control signal;

[0022] When the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal.

[0023] Thirdly, embodiments of this application provide a driving method for a display device, applied to a pixel driving circuit and a light-emitting element electrically connected in the display device, wherein the pixel driving circuit includes:

[0024] A driving transistor, wherein one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element;

[0025] The first reset transistor is electrically connected to the gate of the driving transistor;

[0026] The second reset transistor is electrically connected to the other of the source and drain of the driving transistor;

[0027] The first switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor.

[0028] The data writing transistor is electrically connected to the gate of the driving transistor;

[0029] The driving method for the display device includes:

[0030] In the first stage, the first reset transistor is turned on in response to a first control signal to transmit a first reset signal to the gate of the driving transistor to turn on the driving transistor, and the first switching transistor is turned on in response to a third control signal.

[0031] In the second stage following the first stage, the data writing transistor is turned on in response to a fourth control signal to transmit a data signal to the gate of the driving crystal, thereby turning on the driving transistor, and the first switching transistor is turned off in response to the third control signal.

[0032] Beneficial effects: This application provides a display device and its driving method. By setting a first switching transistor electrically connected between a first voltage line and the drain of a driving transistor, and when the first reset transistor and the data writing transistor are turned on in sequence, the driving transistor is turned on and off respectively, so that the potential of the source of the driving transistor rises to "Vref-Vth" and can remain unchanged during data voltage writing. This avoids the source of the driving transistor from being charged by the first voltage signal and causing its potential to rise. As a result, when the light-emitting element emits light, the potential of the source of the driving transistor can compensate for the threshold voltage of the driving transistor, thus improving the compensation effect of the threshold voltage of the driving transistor in multiple pixel driving circuits. Attached Figure Description

[0033] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0034] Figure 1 is a schematic diagram of the architecture of the display device provided in an embodiment of this application.

[0035] Figures 2 and 3 are the circuit diagrams and corresponding timing diagrams of the sub-pixels provided in the comparative examples of this application, respectively.

[0036] Figures 4 and 5 are circuit diagrams and corresponding timing diagrams of a sub-pixel provided in an embodiment of this application, respectively.

[0037] Figures 6 and 7 are circuit diagrams and corresponding timing diagrams of sub-pixels provided in another embodiment of this application.

[0038] Figure 8 is a flowchart of a driving method for a display device provided in an embodiment of this application.

[0039] Figure 9 is a graph showing the potential of the source of the driving transistor corresponding to the multiple sub-pixels provided in the comparative example of this application. Implementation methods of this application

[0040] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified; "electrical connection" indicates that the two are conductive, and is not limited to a direct or indirect connection.

[0042] In addition, it should be noted that the accompanying drawings only provide structures and steps that are closely related to this application, and omit some details that are not closely related to the application. The purpose is to simplify the drawings and make the application points clear at a glance, rather than indicating that the actual device is exactly the same as the drawings, and it is not intended to limit the actual device.

[0043] This application provides a display device, which may include, but is not limited to, the following embodiments and combinations thereof.

[0044] In some embodiments, as shown in Figures 1, 4, and 6, the display device 100 includes a plurality of sub-pixels 10. Each sub-pixel 10 includes an electrically connected light-emitting element 101 and a pixel driving circuit 102. The pixel driving circuit 102 includes: a driving transistor T1, one of its source s and drain d being electrically connected to a first voltage line (for transmitting a first voltage signal VDD), and the other being electrically connected to the light-emitting element 101; a first reset transistor T2, electrically connected to the gate g of the driving transistor T1, for transmitting a first reset signal Vref to the gate g of the driving transistor T1 according to a first control signal REF; and a second reset transistor T3, electrically connected to the other of the source s and drain g of the driving transistor T1, for transmitting a second reset signal Vini to the other of the source s and drain g of the driving transistor T1 according to a second control signal INI. Switching transistor T4 is electrically connected between the first voltage line and one of the source s and drain d of the driving transistor T1, and is used to control the formation of a current path between the first voltage line and one of the source s and drain d of the driving transistor T1 according to the third control signal REF'. Data writing transistor T5 is electrically connected to the gate g of the driving transistor T1, and is used to transmit the data signal Vdata to the gate g of the driving transistor T1 according to the fourth control signal Gn. As shown in Figures 5 and 6, when the first reset transistor T2 is turned on in response to the first control signal REF, the driving transistor T1 is turned on, and the first switching transistor T4 is turned on in response to the third control signal REF'. When the data writing transistor T5 is turned on in response to the fourth control signal Gn, the driving transistor T1 is turned on, and the first switching transistor T4 is turned off in response to the third control signal REF'.

[0045] The display device 100 is, but is not limited to, an organic self-emissive display device or an inorganic self-emissive direct-view display device. As shown in Figure 1, the arrangement of multiple sub-pixels 10 in the display panel 20 of the display device 100 is used as an example. The display device 100 may also include multiple gate lines 30, multiple data lines 40, a source driver 50 electrically connected to the multiple data lines 40, and a gate driver 60 electrically connected to the multiple gate lines 30. The multiple gate lines 30, multiple data lines 40, and multiple sub-pixels 10 may also be located on the substrate of the display panel 20. The gate driver 60 may be a gate driving circuit located on the substrate of the display panel 20 or a chip set independently of the display panel 20 (Figure 1 only illustrates the former case).

[0046] Specifically, each gate line 30 is electrically connected to a plurality of pixel driving circuits 102 located in a plurality of sub-pixels 10 in a corresponding row, so as to output at least the corresponding fourth control signal Gn. In each frame, the fourth control signal Gn includes a first gate pulse p1 for controlling the corresponding plurality of pixel driving circuits 102 to turn on. The pixel driving circuits 102 in the plurality of rows of sub-pixels 10 are turned on sequentially under the control of the plurality of first gate pulses p1 in the plurality of fourth control signals Gn. Each data line 40 is connected to a plurality of pixel driving circuits 102 located in a plurality of sub-pixels 10 in a corresponding column to output the corresponding data signal Vdata. The data signal Vdata includes a plurality of data voltages Vd1 corresponding to the plurality of sub-pixels 10 and an invalid voltage Vd2 located between two adjacent data voltages Vd1. The plurality of data signals Vdata corresponding to the plurality of columns of sub-pixels 10 are set to transmit the corresponding plurality of data voltages Vd1 to the plurality of sub-pixels 10 in the corresponding row through the plurality of data lines 40 when each row of sub-pixels 10 is turned on. Among them, the invalid voltage Vd2 is used to space multiple data voltages Vd1 to reduce the risk of incorrect charging of data voltage Vd1.

[0047] Specifically, the gate driver 60 may include a multi-level gate driving module corresponding to multiple rows of sub-pixels 10. Each gate driving module includes multiple gate driving units for generating multiple gate signals. The multiple gate signals may include, but are not limited to, the first control signal REF, the second control signal INI, the third control signal REF', and the fourth control signal Gn mentioned above. That is, multiple sub-pixels 10 in the same row are controlled by multiple gate signals output by the same gate driving module. These multiple gate signals can control the on-time of multiple transistors in the multiple pixel driving circuits 102 of the same row, and together with multiple data signals Vdata output by the source driver 50, realize the light emission of the light-emitting element 101 in that row. In this way, the multiple row pixel driving circuits 102 operate sequentially under the control of the corresponding multiple gate driving modules and are sequentially loaded with multiple data voltages Vd1 corresponding to the multiple data signals Vdata, thereby displaying a frame of image.

[0048] It should be noted that, as shown in Figures 2 and 3, the pixel circuit 102 in the comparative example provided in this application, compared with the embodiment shown in Figure 4 above, does not have the aforementioned first switching transistor T4 disposed between the first voltage line and one of the source s or drain d of the driving transistor T1, that is, the two are electrically connected by a wire, and each sub-pixel 10 includes at least the following operating stages:

[0049] During the first comparison period t1', the second control signal INI is at the corresponding high potential, the second reset transistor T3 is turned on, and the second reset signal Vini is transmitted to the source s of the driving transistor T1 to reset it.

[0050] During the second comparison period t2' (including the first stage mentioned above), the second control signal INI and the first control signal REF are both at their respective high potentials. The second reset transistor T3 remains on, and the first reset transistor T2 is on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is on, and the first voltage signal VDD is transmitted through the driving transistor T1 to the source s of the driving transistor T1 to raise its potential until the driving transistor T1 is turned off. The potential of the source s of the driving transistor T1 is "Vref-Vth".

[0051] During the third comparison period t3', the fourth control signal Gn is at a high potential, the data writing transistor T5 is turned on, and the data voltage Vd1 corresponding to the data signal Vdata is transmitted to the gate g of the driving transistor T1. The driving transistor T1 is still turned on, but because the first voltage line and the driving transistor T1 are electrically connected, the first voltage signal VDD keeps pulling up the potential of the source s of the driving transistor T1, causing the final gate-source voltage Vgs of the driving transistor T1 to be distorted by the ΔV raised by the source s of the driving transistor T1, resulting in Vgs being approximately Vdata-(Vref-Vth+ΔV).

[0052] During the fourth comparison period t4', the fourth control signal Gn is at a corresponding low potential. Data writing transistor T5 is cut off, and driving transistor T1 is turned on, forming a current path between the first and second voltage lines. Driving transistor T1 generates a driving current flowing through the light-emitting element 101, causing it to emit light. The magnitude of the driving current is approximately k×{[Vdata-(Vref-Vth)]-Vth} 2 ≈k×(Vdata-Vref-ΔV) 2 k is a constant.

[0053] Therefore, as shown in Figure 9, a graph illustrating the potential Vs of the source s of the driving transistor T1 in multiple sub-pixels 10 of the same display panel 20 in the comparative example is shown. The horizontal axis represents the working time of the sub-pixel 10, and the vertical axis represents the potential Vs of the source s of the driving transistor T1.

[0054] Based on the analysis of the working stages of the comparative example above, it can be seen that during the third comparison period t3', since the first switching transistor T4 is not turned off to form a current break between the first voltage line and the source s of the driving transistor T1, that is, during the third comparison period t3' of the comparative example, the first voltage line and the source s of the driving transistor T1 have a current path. This causes the potential Vs of the source s of the driving transistor T1 of each sub-pixel 10 to be charged by the first voltage signal VDD, thus raising its potential. The degree of the rise is related to the threshold voltage Vth of each driving transistor T1. For example, L1 to L5 are five sub-pixels 10. The curve of the potential Vs of the source s of the driving transistor T1 shows that since the threshold voltage Vth of each of the five driving transistors T1 corresponding to L1 to L5 is different from the former, the potential Vs of the source s of the driving transistor T1 of each of L1 to L5 in the third comparison period t3 has differences of ΔV1, ΔV2, ΔV3, and ΔV4 respectively from the former. This results in the potential Vs of the source s of the five driving transistors T1 in the fourth period t4 still being different, ultimately causing the values ​​of the five corresponding driving currents to be different, making it impossible to effectively compensate for the threshold voltage Vth of all driving transistors T1.

[0055] As shown in Figures 4 to 7, for ease of description, the specification uses the following example: the source s of driving transistor T1 is directly electrically connected to the second reset transistor T3; the drain d of driving transistor T1 is directly electrically connected to the first switching transistor T4; multiple transistors in the pixel driving circuit 102 are all N-type transistors; and the first voltage signal VDD, the first reset signal Vref, and the second reset signal Vini are constant voltage signals. Each sub-pixel 10 includes at least the following operating stages:

[0056] When the first reset transistor T2 is turned on in response to the first control signal REF, the drive transistor T1 is turned on, and the first switching transistor T4 is turned on in response to the third control signal REF'.

[0057] That is, when the first reset transistor T2 transmits the first reset signal Vref to the gate g of the driving transistor T1 to reset its potential after the first control signal REF is turned on, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on. At the same time, the first switching transistor T4 turns on in response to the potential of the third control signal REF'. The first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the first switching transistor T4 and the driving transistor T1 to charge it until the gate-source voltage Vgs of the driving transistor T1 is less than or equal to its threshold voltage Vth, at which point the driving transistor T1 is turned off. Therefore, the potential of the source s of the driving transistor T1 is "Vref-Vth".

[0058] When the data writing transistor T5 is turned on in response to the fourth control signal Gn, the driving transistor T1 is turned on, and the first switching transistor T4 is turned off in response to the third control signal REF'.

[0059] That is, when the data writing transistor T5 transmits the corresponding data voltage Vd1 in the data signal Vdata to the gate g of the driving transistor T1 to write the data voltage Vd1 after the fourth control signal Gn is turned on, the gate-source voltage Vgs of the driving transistor T1 is also greater than its threshold voltage Vth to turn it on. However, at this time, the first switching transistor T4 is turned off at this potential in response to the third control signal REF'. At this time, the first voltage signal VDD will not be transmitted to the source s of the driving transistor T1 to charge it. That is, the potential of the source s of the driving transistor T1 is maintained at "Vref-Vth". Therefore, the gate-source voltage Vgs of the driving transistor T1 is "Vd1-Vref+Vth".

[0060] Understandably, in this embodiment, the second reset transistor T3 responds to the potential corresponding to the second control signal INI and resets the source s of the driving transistor T1 through the second reset signal Vini. When the first reset transistor T2 responds to the potential corresponding to the first control signal REF and resets the gate g of the driving transistor T1 through the first reset signal Vref, and responds to the potential corresponding to the fourth control signal Gn and writes the data voltage Vd1 to the gate g of the driving transistor T1 through the data voltage Vd1, the first switching transistor T4 is controlled to turn on and off sequentially. This allows the potential of the source s of the driving transistor T1 to rise to "Vref-Vth" and remain unchanged, preventing the source s of the driving transistor T1 from continuing to be charged by the first voltage signal VDD and causing its potential to rise. This allows the potential of the source s of the driving transistor T1 to compensate for the threshold voltage Vth of the driving transistor T1 when the light-emitting element 101 emits light, thus improving the compensation effect of the threshold voltage of the driving transistor T1 in the multiple pixel driving circuits 102.

[0061] In some embodiments, as shown in Figures 4 to 7, before the first reset transistor T2 is turned on in response to the first control signal REF, the second reset transistor T3 is turned on in response to the second control signal INI. That is, before the first reset signal Vref resets the gate g of the driving transistor T1 through the first reset transistor T2, the second reset transistor T3 can be turned on in response to the second control signal INI, so that the second reset signal Vini resets the source s of the driving transistor T1. Therefore, it can be considered that when the first reset transistor T2 is turned on in response to the first control signal REF, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on.

[0062] Specifically, after multiple light-emitting elements 101 have stabilized and emitted light in the previous frame, the differences in the on-state voltage drop of different colored light-emitting elements 101 cause differences in the potential of the source s of different driving transistors T1. Therefore, it is necessary to reset the potential of the source s of all driving transistors T1 using the same second reset signal Vini. Furthermore, since the potential of the source s of all driving transistors T1 may affect the potential of the anode or cathode of the light-emitting element 101, resetting the potential of the source s of all driving transistors T1 first can ensure that multiple light-emitting elements 101 are turned off, avoiding false emission of light-emitting elements 101 when the gate g of the driving transistors T1 is reset later.

[0063] The pixel driving circuit 102 may also include a storage capacitor Cst electrically connected between the gate g and the source s of the driving transistor T1. The storage capacitor Cst is used to maintain the voltage difference between the gate g and the source s of the driving transistor T1, thereby achieving the function of storing the threshold voltage Vth of the driving transistor T1, including but not limited to.

[0064] In some embodiments, as shown in Figures 4 and 5, the pulse period of the first control signal REF is the same as the pulse period of the third control signal REF', or as shown in Figures 6 and 7, the pulse period of the first control signal REF and the pulse period of the third control signal REF' are the same. Specifically, the potential corresponding to the pulse of the first control signal REF in Figures 4 and 6 can turn on the first reset transistor T2 to reset the gate g of the driving transistor T1, and the potential corresponding to the pulse of the third control signal REF' can turn on the first switching transistor T4 to raise the potential of the source s of the driving transistor T1.

[0065] As discussed above, as shown in Figures 4 and 5, this embodiment sets the pulse period of the first control signal REF to be included in the pulse period of the third control signal REF'. During the period of resetting the gate g of the driving transistor T1, the potential of the source s of the driving transistor T1 is included in the stage of raising the potential of the source s of the driving transistor T1, so that the potential of the source s of the driving transistor T1 can rise to "Vref-Vth".

[0066] Furthermore, as shown in Figures 6 and 7, in order to save on the types of signals, by reasonably setting the electrical characteristics of the first reset transistor T2 and the first switching transistor T4, the first control signal REF and the third control signal REF' can be the same signal, that is, the waveforms of the two can be the same. At this time, the pulse time period of the first control signal REF and the pulse time period of the third control signal REF' can be the same, and the above-mentioned function can also be achieved.

[0067] It should be noted that in the circuit diagram corresponding to Figure 4, the pulse time period of the first control signal REF and the pulse time period of the third control signal REF' can also be set to be the same, and the above function can be achieved in the same way.

[0068] In some embodiments, as shown in Figures 4 and 5, after the data writing transistor T5 is turned on in response to the fourth control signal Gn, the first switching transistor T4 is turned on in response to the third control signal REF'. It can be understood that when only the first switching transistor T4 is connected in series between the first voltage line and the drain d of the driving transistor T1, after the data voltage Vd1 corresponding to the data signal Vdata is written to the gate g of the driving transistor T1, the first switching transistor T4 needs to be turned on to form a current path between the first voltage line and the drain d of the driving transistor, in preparation for forming the driving current. Therefore, the first switching transistor T4 can also function as a current path for forming the driving current in the pixel driving circuit 102.

[0069] In some embodiments, as shown in FIG6, the pixel driving circuit 102 further includes: a second switching transistor T6, electrically connected between the first voltage line and one of the source s and drain d of the driving transistor T1, for controlling the formation of a current path between the first voltage line and one of the source s and drain d of the driving transistor according to the fifth control signal EM; as shown in FIG7, when the first switching transistor T4 (in response to the third control signal REF') is turned off and the data writing transistor T5 (in response to the fourth control signal Gn) is turned on, the second switching transistor T6 is turned off in response to the fifth control signal EM; after the data writing transistor T5 is turned on in response to the fourth control signal Gn, the second switching transistor T6 is turned on in response to the fifth control signal EM.

[0070] As discussed above, the first switching transistor T4 sequentially turns on and off when the data voltage Vd1 corresponding to the first reset signal Vref and the data signal Vdata is written to the gate g of the driving transistor T1. Based on this, in this embodiment, the second switching transistor T6 is also electrically connected between the first voltage line and one of the source s or drain d of the driving transistor T1. After the data voltage Vd1 corresponding to the data signal Vdata is written to the gate g of the driving transistor T1, the second switching transistor T6 turns on to form a current path between the first voltage line and the drain d of the driving transistor, preparing for the generation of the driving current. Therefore, by setting the second switching transistor T6, the function of providing the driving current in the pixel driving circuit 102 can be retained.

[0071] In particular, in order to ensure that a current break is formed between the first voltage line and the drain d of the driving transistor T1 when the above data voltage Vd1 is written, the second switching transistor T6 also needs to be cut off in response to the potential corresponding to the fifth control signal EM.

[0072] Furthermore, as shown in FIG6, the pixel driving circuit 102 further includes: a third switching transistor T7, electrically connected between the source s and drain d of the light-emitting element 101 and the driving transistor T1, for controlling the formation of a current path between the source s and drain d of the light-emitting element 101 and the driving transistor T1 according to the fifth control signal EM; as shown in FIG7, when the second reset transistor T3 is turned on in response to the second control signal INI, the third switching transistor T7 is turned off in response to the fifth control signal EM.

[0073] As discussed above, both the third switching transistor T7 and the second switching transistor T6 are controlled by the fifth control signal EM to be turned on or off. That is, both are turned off when the data voltage Vd1 mentioned above is written to the first switching transistor T4, and are turned on after the data voltage Vd1 is written to form the current path of the driving current. At the same time, since the third switching transistor T7 is electrically connected between the light-emitting element 101 and the source s of the driving transistor T1, in order to avoid the second reset signal Vini affecting the potential of the anode or cathode of the light-emitting element 101 when resetting the source s of the driving transistor T1, thus causing the light-emitting element 101 to emit light erroneously, the third switching transistor T7 can be turned off at this time.

[0074] In some embodiments, as shown in FIG6, one of the anode and cathode of the light-emitting element 101 is electrically connected to the second voltage line (for transmitting the second voltage signal VSS), and the other is electrically connected to the other of the source s and drain d of the driving transistor T1; the pixel driving circuit 102 further includes: a third reset transistor T8, electrically connected to the other of the anode and cathode of the light-emitting element 101, for transmitting a third reset signal Viano to the other of the anode and cathode of the light-emitting element 101 according to the second control signal INI.

[0075] For ease of description, the specification uses the example where the anode of the light-emitting element 101 is electrically connected to the second reset transistor T3 (and may further be electrically connected to the third reset transistor T8 and the third switching transistor T7), the cathode of the light-emitting element 101 is electrically connected to the second voltage line, and the third reset signal Viano and the second voltage signal VSS are also constant voltage signals.

[0076] It can be known from the above discussion that both the third reset transistor T8 and the second reset transistor T3 are controlled to be turned on or off by the second control signal INI, that is, they are turned on at the same time before the first reset signal Vref resets the gate g of the driving transistor T1, so that the second reset signal Vini and the third reset signal Viano respectively reset the source s of the driving transistor T1 and the anode of the light-emitting element 101.

[0077] It should be noted that, since resetting the gate g of the driving transistor T1 with the first reset signal Vref and resetting the source s of the driving transistor T1 with the second reset signal Vini requires the driving transistor T1 to be conductive, that is, the gate-source voltage Vgss=Vref-Vini of the driving transistor T1 needs to be greater than its threshold voltage Vth, therefore, the difference between the amplitudes of the second reset signal Vini and the first reset signal Vref is limited by the threshold voltage Vth. Meanwhile, since resetting the anode of the light-emitting element 101 with the third reset signal Viano needs to ensure that the light-emitting element 101 is turned off, therefore, Viano<VSS+Vth_oled, where Vth_oled is the turn-on voltage of the light-emitting element 101.

[0078] Therefore, in this embodiment, by providing the second reset transistor T3, the third reset transistor T8, and the third switching transistor T7 described above, resetting of the source s of the driving transistor T1 and the anode of the light-emitting element 101 can be achieved respectively, and when resetting the two, potential interference between them can be avoided due to the third switching transistor T7. Meanwhile, both the second reset transistor T3 and the third reset transistor T8 are controlled by the second control signal INI, which can effectively reduce the types of signals.

[0079] In some embodiments, with reference to FIG. 1 and FIG. 4 to FIG. 7, the data signal Vdata includes a plurality of the above data voltages Vd1 corresponding to the plurality of said light-emitting elements 101, and the fourth control signal Gn includes the above first gate pulse p1 for controlling the corresponding data writing transistor T5 to be turned on; wherein the start time of the first gate pulse p1 is ahead of the start time of the period where the corresponding data voltage Vd1 is located.

[0080] As shown in FIG. 5 and FIG. 7, the pulse drawn with a solid line in the fourth control signal Gn can be understood as the first comparative gate pulse p1' in the comparative example, and the pulse drawn with a broken line can be understood as the first gate pulse p1 in the present embodiment. It can be observed that the start time of the first comparative gate pulse p1' in the comparative example lags behind the start time of the period where the corresponding data voltage Vd1 is located, while in the present embodiment, since both the first switching transistor T4 and the second switching transistor T6 are turned off during the period when the first gate pulse p1 is located, the conduction of the driving transistor T1 does not cause the potential of its source s to be charged by the first voltage signal VDD and thus the potential to rise.

[0081] Therefore, compared with the comparative example, this embodiment advances the start time of the first gate pulse p1 to ahead of the start time of the corresponding data voltage Vd1. While avoiding the potential of the source s of the driving transistor T1 being charged by the first voltage signal VDD and causing its potential to rise, it can also increase the overlap time of the first gate pulse p1 and the corresponding data voltage Vd1, thereby giving the corresponding sub-pixel 10 a longer charging time. This is beneficial to the charging rate of the sub-pixel 10 under high refresh rates, especially under heavy load scenes. It can support higher refresh rates at the same resolution, or support higher resolutions at the same refresh rate.

[0082] Furthermore, as shown in Figures 1, 4 to 7, the third control signal REF' includes a second gate pulse p2 for controlling the corresponding first switching transistor T4 to turn on; wherein the interval between the end time of the second gate pulse p2 and the start time of the first gate pulse p1 is greater than or equal to 0.1×H, where H is the driving cycle of one row of sub-pixels 10 of the display device 100 within one frame.

[0083] The driving cycle of a row of sub-pixels 10 in a frame of the display device 100 can be understood as the time required for the row of pixel driving circuit 102 to be turned on to write at least the corresponding data voltage Vd. It can be calculated as follows: 1H = 1 / (refresh rate × number of vertical rows). The number of vertical rows can include the sum of the number of rows of multiple sub-pixels 10 in the display area of ​​the display panel 20 and the number of virtual rows in the non-display area. For example, for a display device 100 with a resolution of 1080p operating at a refresh rate of 60Hz, the corresponding 1H duration is approximately 15.6 microseconds.

[0084] Of course, considering that time is generally required for the system to perform operations such as buffering between the data voltages Vd1 of two adjacent frames, it can be assumed that 1H is slightly less than 1 / (refresh rate × number of vertical lines).

[0085] Understandably, in this embodiment, based on the fact that the start time of the first gate pulse p1 precedes the start time of the corresponding data voltage Vd1, the interval between the start time of the first gate pulse p1 and the end time of the second gate pulse p2 is set to be greater than or equal to 0.1×H. This avoids the first gate pulse p1 and the corresponding second gate pulse p2 having an overlapping period, which would cause the corresponding data voltage Vd1 to be written to the gate g of the driving transistor T1 before the potential of the source s of the driving transistor T1 reaches "Vref-Vth", resulting in inadequate compensation of the threshold voltage Vth.

[0086] Based on the above explanation of 1H, Figures 5 and 7 also use H to illustrate the pulse width of multiple signals and the interval between different pulses, but the above annotation is not intended to limit the waveform of the above signals in this application.

[0087] Furthermore, as shown in Figures 1, 4, and 7, the pulse width of the first gate pulse p1 differs at different refresh rates. Based on the above discussion, for the same display device 100, since the time reserved for the pixel driving circuit 102 to turn on within a frame to at least write the corresponding data voltage Vd differs at different refresh rates, for high refresh rates, it can be considered that the pulse widths of the different signals shown in Figures 4 and 6 are all reduced compared to lower refresh rates. The shorter scanning time for a row of sub-pixels 10 can easily lead to insufficient charging.

[0088] Understandably, since this embodiment can make the start time of the first gate pulse p1 precede the start time of the corresponding data voltage Vd1, and as shown in Figures 5 and 7, in order to avoid the problem of incorrect charging of data voltage Vd1, the end time of the first gate pulse p1 needs to be earlier than the end time of the corresponding data voltage Vd1 by a certain duration. Therefore, it can be considered that the interval between the end times of the corresponding data voltage Vd1 of different first gate pulses p1 is the same. Thus, this embodiment can differentiate the start time of the first gate pulse p1 at different refresh rates, that is, differentiate the pulse width of the first gate pulse p1. For example, compared with a lower refresh rate, the pulse width of the first gate pulse p1 can be set to be larger. In the case that the pulse width of the first gate pulse p1 and the duration of the corresponding data voltage Vd1 are both small, by maximizing the overlap duration of the two, the overlap duration of the first gate pulse p1 and the corresponding data voltage Vd1 at different refresh rates can be made more consistent, thereby improving the uniformity of the display of the display device 100 at different refresh rates.

[0089] This application provides a driving method for a display device, applied to a pixel driving circuit and a light-emitting element electrically connected in the display device. The pixel driving circuit includes: a driving transistor, one of the source and drain of the driving transistor being electrically connected to a first voltage line, and the other being electrically connected to the light-emitting element; a first reset transistor being electrically connected to the gate of the driving transistor; a second reset transistor being electrically connected to the other of the source and drain of the driving transistor; a first switching transistor being electrically connected between the first voltage line and one of the source and drain of the driving transistor; and a data writing transistor being electrically connected to the gate of the driving transistor. The specific circuit of this pixel driving circuit and its connection method with the light-emitting element can be referred to the discussion in Figures 1, 4 to 7 above.

[0090] As shown in Figure 8, the driving method of the display device includes, but is not limited to, the following steps and combinations thereof.

[0091] S1, in the first stage, the first reset transistor is turned on in response to a first control signal to transmit a first reset signal to the gate of the driving transistor to turn on the driving transistor, and the first switching transistor is turned on in response to a third control signal.

[0092] As discussed above, in the first stage, the potential of the first control signal REF controls the first reset transistor T2 to turn on, the first reset signal Vref is transmitted to the gate g of the driving transistor T1, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on, at the same time, the potential of the third control signal REF' controls the first switching transistor T4 to turn on, the first voltage signal VDD is transmitted to the source s of the driving transistor T1 until the driving transistor T1 is turned off, at this time the potential of the source s of the driving transistor T1 is "Vref-Vth";

[0093] S2, in the second stage after the first stage, the data writing transistor is turned on in response to the fourth control signal to transmit the data signal to the gate of the driving transistor, so as to turn on the driving transistor, and the first switching transistor is turned off in response to the third control signal.

[0094] As discussed above, in the second stage, the potential control of the fourth control signal Gn turns on the data writing transistor T5, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. The gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on. However, at this time, the potential control of the third control signal REF' turns off the first switching transistor T4. At this time, the first voltage signal VDD will not be transmitted to the source s of the driving transistor T1, that is, the potential of the source s of the driving transistor T1 is maintained at "Vref-Vth". Therefore, the gate-source voltage Vgs of the driving transistor T1 is "Vd1-Vref+Vth".

[0095] To better illustrate the display device and its driving method provided in this application, the working period of the sub-pixel 10 shown in Figure 6 is explained below in conjunction with the timing diagram shown in Figure 7:

[0096] During the first time period t1, the second control signal INI is at a corresponding high potential, and both the second reset transistor T3 and the third reset transistor T8 are turned on. The second reset signal Vini is transmitted to the source s of the driving transistor T1 to reset it, and the third reset signal Viano is transmitted to the anode of the light-emitting element 101 to reset it.

[0097] In the second time period t2 (including the first stage mentioned above), the second control signal INI, the first control signal REF, and the third control signal REF' are all at their corresponding high potentials. The second reset transistor T3 and the third reset transistor T8 remain on, and the first reset transistor T2 and the first switching transistor T4 are both on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is on, and the first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the first switching transistor T4 and the driving transistor T1 to raise its potential until the driving transistor T1 is turned off. The potential of the source s of the driving transistor T1 is "Vref-Vth".

[0098] In the third time period t3 (including the second stage mentioned above), the fourth control signal Gn is at a high potential, the data writing transistor T5 is turned on, and the data voltage Vd1 corresponding to the data signal Vdata is transmitted to the gate g of the driving transistor T1. The driving transistor T1 is still turned on, but the first switching transistor T4 and the second switching transistor T6 are both turned off. The potential of the source s of the driving transistor T1 is maintained at "Vref-Vth", so the gate-source voltage Vgs of the driving transistor T1 is "Vd1-Vref+Vth".

[0099] During the fourth time period t4, the fifth control signal EM is at a corresponding high potential. The second switching transistor T6, the third switching transistor T7, and the driving transistor T1 are all turned on, forming a current path between the first and second voltage lines. The driving transistor T1 generates a driving current flowing through the light-emitting element 101, causing the light-emitting element 101 to emit light. The magnitude of the driving current is approximately k×{[Vdata-(Vref-Vth)]-Vth} 2 ≈k×(Vdata-Vref) 2 k is a constant.

[0100] Referring to the discussion above regarding the first time period t1 to the fourth time period t4 shown in Figures 6 and 7, and as shown in Figures 4 and 5, the following working stages can also be included:

[0101] During the first time period t1, the second control signal INI and the third control signal REF' are both at their corresponding high potentials. Based on the reset of the source s of the driving transistor T1, the first voltage signal VDD is transmitted to the drain d of the driving transistor T1 to reset it.

[0102] In the second time period t2 (including the first stage mentioned above), the second control signal INI, the first control signal REF, and the third control signal REF' are all at their corresponding high potentials. The second reset transistor T3 and the first switching transistor T4 remain on, and the first reset transistor T2 is on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is on, and the first voltage signal VDD is further transmitted through the driving transistor T1 to the source s of the driving transistor T1 to raise its potential until the driving transistor T1 is turned off. The potential of the source s of the driving transistor T1 is "Vref-Vth".

[0103] In the third time period t3 (including the second stage mentioned above), the fourth control signal Gn is at a high potential, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. Similarly, in the third time period t3 of Figure 7 above, the final gate-source voltage Vgs of the driving transistor T1 is also "Vd1-Vref+Vth".

[0104] During the fourth time period t4, both the fourth control signal Gn and the third control signal REF' are at their corresponding high potentials. Data writing transistor T5 is cut off, while driving transistor T1 and the first switching transistor T4 are both turned on, forming a current path between the first and second voltage lines. Driving transistor T1 generates a driving current flowing through the light-emitting element 101, causing it to emit light. The magnitude of the driving current is approximately k × {[Vdata - (Vref - Vth)] - Vth} 2 ≈k×(Vdata-Vref) 2 k is a constant.

[0105] It should be noted that, as discussed above, since only the first switching transistor T4 is connected in series between the first voltage line and the drain d of the driving transistor T1 in Figure 4, the third control signal REF' needs to be set to the corresponding high potential in the fourth time period t4 in Figure 5 in order to form a current path between the first voltage line and the second voltage line.

[0106] It should be noted that each of the gate driver 60 and source driver 50 mentioned in this application may include a transistor, and further may include at least one of a capacitor and a resistor, as well as a wire electrically connected between different components. The specific configuration is not limited, as long as the function is achieved.

[0107] The structure of the display device and its driving method provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, wherein, It includes multiple sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel driving circuit, the pixel driving circuit including: A driving transistor, wherein one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element; The first reset transistor is electrically connected to the gate of the driving transistor and is used to transmit a first reset signal to the gate of the driving transistor according to the first control signal. The second reset transistor is electrically connected to the other of the source and drain of the driving transistor, and is used to transmit a second reset signal to the other of the source and drain of the driving transistor according to the second control signal. The first switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor, and is used to control the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to the third control signal. A data writing transistor is electrically connected to the gate of the driving transistor and is used to transmit a data signal to the gate of the driving transistor according to a fourth control signal. When the first reset transistor is turned on in response to the first control signal, the drive transistor is turned on, and the first switch transistor is turned on in response to the third control signal; When the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal; Wherein, before the first reset transistor is turned on in response to the first control signal, the second reset transistor is turned on in response to the second control signal; The pulse of the first control signal is in the same time period as the pulse of the third control signal.

2. The display device of claim 1, wherein, After the data writing transistor turns on in response to the fourth control signal, the first switching transistor turns on in response to the third control signal.

3. The display device of claim 1, wherein, The pixel driving circuit also includes: The second switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor, and is used to control the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to the fifth control signal. When the first switching transistor is off and the data writing transistor is on, the second switching transistor is off in response to the fifth control signal; After the data writing transistor turns on in response to the fourth control signal, the second switching transistor turns on in response to the fifth control signal.

4. The display device of claim 3, wherein, The pixel driving circuit also includes: The third switching transistor is electrically connected between the light-emitting element and the other of the source and drain of the driving transistor, and is used to control the formation of a current path between the light-emitting element and the other of the source and drain of the driving transistor according to the fifth control signal. When the second reset transistor is turned on in response to the second control signal, the third switching transistor is turned off in response to the fifth control signal.

5. The display device as claimed in claim 4, wherein, One of the anode and cathode of the light-emitting element is electrically connected to the second voltage line, and the other is electrically connected to the other of the source and drain of the driving transistor. The pixel driving circuit also includes: The third reset transistor is electrically connected to the other of the anode and cathode of the light-emitting element, and is used to transmit a third reset signal to the other of the anode and cathode of the light-emitting element according to the second control signal.

6. The display device according to any one of claims 1 to 5, wherein, The data signal includes multiple data voltages corresponding to the multiple light-emitting elements, and the fourth control signal includes a first gate pulse for controlling the corresponding data writing transistor to turn on; Wherein, the start time of the first gate pulse precedes the start time of the corresponding data voltage period.

7. The display device as claimed in claim 6, wherein, The third control signal includes a second gate pulse for controlling the corresponding first switching transistor to turn on; Wherein, the interval between the end time of the second gate pulse and the start time of the first gate pulse is greater than or equal to 0.1×H, where H is the driving cycle of one row of sub-pixels of the display device within one frame.

8. The display device as claimed in claim 6, wherein, The pulse width of the first gate pulse is different at different refresh rates.

9. A display device, wherein, It includes multiple sub-pixels, each sub-pixel including an electrically connected light-emitting element and a pixel driving circuit, the pixel driving circuit including: A driving transistor, wherein one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element; The first reset transistor is electrically connected to the gate of the driving transistor and is used to transmit a first reset signal to the gate of the driving transistor according to the first control signal. The second reset transistor is electrically connected to the other of the source and drain of the driving transistor, and is used to transmit a second reset signal to the other of the source and drain of the driving transistor according to the second control signal. The first switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor, and is used to control the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to the third control signal. A data writing transistor is electrically connected to the gate of the driving transistor and is used to transmit a data signal to the gate of the driving transistor according to a fourth control signal. When the first reset transistor is turned on in response to the first control signal, the drive transistor is turned on, and the first switch transistor is turned on in response to the third control signal; When the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal.

10. The display device as claimed in claim 9, wherein, Before the first reset transistor is turned on in response to the first control signal, the second reset transistor is turned on in response to the second control signal.

11. The display device as claimed in claim 9, wherein, The pulse of the first control signal is in the same time period as the pulse of the third control signal.

12. The display device as claimed in claim 9, wherein, After the data writing transistor turns on in response to the fourth control signal, the first switching transistor turns on in response to the third control signal.

13. The display device as claimed in claim 9, wherein, The pixel driving circuit also includes: The second switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor, and is used to control the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to the fifth control signal. When the first switching transistor is off and the data writing transistor is on, the second switching transistor is off in response to the fifth control signal; After the data writing transistor turns on in response to the fourth control signal, the second switching transistor turns on in response to the fifth control signal.

14. The display device as claimed in claim 13, wherein, The pixel driving circuit also includes: The third switching transistor is electrically connected between the light-emitting element and the other of the source and drain of the driving transistor, and is used to control the formation of a current path between the light-emitting element and the other of the source and drain of the driving transistor according to the fifth control signal. When the second reset transistor is turned on in response to the second control signal, the third switching transistor is turned off in response to the fifth control signal.

15. The display device as claimed in claim 14, wherein, One of the anode and cathode of the light-emitting element is electrically connected to the second voltage line, and the other is electrically connected to the other of the source and drain of the driving transistor. The pixel driving circuit also includes: The third reset transistor is electrically connected to the other of the anode and cathode of the light-emitting element, and is used to transmit a third reset signal to the other of the anode and cathode of the light-emitting element according to the second control signal.

16. The display device according to any one of claims 9 to 15, wherein, The data signal includes multiple data voltages corresponding to the multiple light-emitting elements, and the fourth control signal includes a first gate pulse for controlling the corresponding data writing transistor to turn on; Wherein, the start time of the first gate pulse precedes the start time of the corresponding data voltage period.

17. The display device as claimed in claim 16, wherein, The third control signal includes a second gate pulse for controlling the corresponding first switching transistor to turn on; Wherein, the interval between the end time of the second gate pulse and the start time of the first gate pulse is greater than or equal to 0.1×H, where H is the driving cycle of one row of sub-pixels of the display device within one frame.

18. The display device as claimed in claim 16, wherein, The pulse width of the first gate pulse is different at different refresh rates.

19. The display device according to any one of claims 9 to 18, wherein, The pixel driving circuit also includes: A storage capacitor is electrically connected between the gate of the driving transistor and the other of the source and drain of the driving transistor.

20. A driving method for a display device, wherein, The pixel driving circuit and the light-emitting element are electrically connected in the display device, the pixel driving circuit comprising: A driving transistor, wherein one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element; The first reset transistor is electrically connected to the gate of the driving transistor; The second reset transistor is electrically connected to the other of the source and drain of the driving transistor; The first switching transistor is electrically connected between the first voltage line and one of the source and drain of the driving transistor. The data writing transistor is electrically connected to the gate of the driving transistor; The driving method for the display device includes: In the first stage, the first reset transistor is turned on in response to a first control signal to transmit a first reset signal to the gate of the driving transistor to turn on the driving transistor, and the first switching transistor is turned on in response to a third control signal. In the second stage following the first stage, the data writing transistor is turned on in response to a fourth control signal to transmit a data signal to the gate of the driving transistor, thereby turning on the driving transistor, and the first switching transistor is turned off in response to the third control signal.

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