Display panel and display apparatus
Patent Information
- Application Number
- PCT/CN2025/087549
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-26
- Filing Date
- 2025-04-07
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025087549_01102026_PF_FP_ABST
Abstract
Description
Display panel and display device
[0001] This application claims priority to Chinese patent application No. 202510371724.5, filed on March 26, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology
[0003] With the development of display panel manufacturing technology, people have put forward higher requirements for the display effect and overall performance of display panels and display devices. Invention Overview
[0004] Organic light-emitting diode (OLED) display technology is gaining increasing attention due to its advantages such as low driving voltage, high brightness, and wide viewing angle. Currently, OLED display panels have a relatively wide bezel structure to accommodate numerous circuit structures and signal lines, resulting in a large bezel width and a low screen-to-body ratio.
[0005] Therefore, it is necessary to provide a display panel and display device to improve this deficiency.
[0006] In a first aspect, embodiments of this application provide a display panel, including a display area and a border area, wherein the border area is disposed around the periphery of the display area, and the display panel includes:
[0007] substrate;
[0008] A cathode is disposed on the substrate;
[0009] A power signal line is disposed on the substrate and located in the frame area;
[0010] The power signal line includes a first power signal sub-line, which is disposed on the side of the cathode away from the substrate and along the thickness direction of the display panel. The first power signal sub-line partially overlaps with the cathode and is connected to the cathode.
[0011] Secondly, embodiments of this application provide a display device, including the display panel as described above. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments disclosed. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 is a top view of the display panel provided in an embodiment of this application;
[0014] Figure 2 is a cross-sectional view of the first type of display panel provided in the embodiment of this application along the A-A' direction shown in Figure 1;
[0015] Figure 3 is a top view of the first power signal sub-line in the display panel provided in an embodiment of this application;
[0016] Figure 4 is a cross-sectional view of the second type of display panel provided in the embodiment of this application along the A-A' direction shown in Figure 1;
[0017] Figure 5 is a schematic diagram of the photomask used in the manufacturing method of the display panel provided in the embodiments of this application;
[0018] Figure 6 is a schematic diagram of a method for manufacturing a display panel according to an embodiment of this application;
[0019] Figure 7 is a schematic diagram of a display device provided in an embodiment of this application. Embodiments of the present invention
[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0021] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0022] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.
[0023] The embodiments of this application provide a display panel and a display device that can reduce the bezel width of the display panel.
[0024] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including a display area and a border area, wherein the border area is disposed around the periphery of the display area, and the display panel includes:
[0025] substrate;
[0026] A cathode is disposed on the substrate;
[0027] A power signal line is disposed on the substrate and located in the frame area;
[0028] The power signal line includes a first power signal sub-line, which is disposed on the side of the cathode away from the substrate and along the thickness direction of the display panel. The first power signal sub-line partially overlaps with the cathode and is connected to the cathode.
[0029] Optionally, the first power signal sub-line is disposed on the surface of the cathode away from the substrate.
[0030] Optionally, the first power signal sub-line is configured to at least partially surround the display area.
[0031] Optionally, the first power signal sub-line includes at least two first sub-segments, the first sub-segments being connected to the cathode, and the first sub-segments being disposed at least on opposite sides of the display area.
[0032] Optionally, the first power signal sub-line includes four first sub-segments, wherein two first sub-segments are respectively disposed on the upper and lower sides of the display area, and the other two first sub-segments are respectively disposed on the left and right sides of the display area, and adjacent first sub-segments are disconnected.
[0033] Optionally, the display panel includes at least one blocking portion, each of the blocking portions being disposed on the substrate and located in the border area, the blocking portions being disposed around the display area, and the first power signal sub-line being disposed on the side of at least one of the blocking portions near the display area.
[0034] Optionally, the frame area includes a first frame sub-area and a second frame sub-area, the first frame sub-area is arranged around the display area, the second frame sub-area is arranged around the first frame sub-area, the first power signal sub-line is arranged in the first frame sub-area, and the blocking part is arranged in the second frame sub-area.
[0035] The power signal line further includes a second power signal sub-line, which is disposed on the substrate and located in the first frame sub-region and the second frame sub-region. The second power signal sub-line is electrically connected to the cathode.
[0036] Optionally, the line width of the first power signal sub-line is greater than or equal to the line width of the second power signal sub-line.
[0037] Optionally, at least one of the blocking portions is partially overlapped with the second power signal sub-line along the thickness direction of the display panel.
[0038] Optionally, the display panel includes a source-drain layer disposed on the substrate, the cathode is disposed on the side of the source-drain layer away from the substrate, and the source-drain layer includes the second power signal sub-line.
[0039] Optionally, the power signal line further includes a third power signal sub-line, which is disposed on the side of the cathode near the substrate, located in the first frame sub-region, and overlaps with the cathode and the second power signal sub-line.
[0040] Wherein, along the thickness direction of the display panel, the first power signal sub-line and the third power signal sub-line are at least partially overlapped.
[0041] Optionally, the display panel further includes an anode layer disposed on the side of the cathode near the substrate, the anode layer including the third power signal sub-line.
[0042] Optionally, the display panel further includes a gate driving circuit disposed on the substrate and located in the bezel area. The cathode is disposed on the side of the gate driving circuit away from the substrate. Along the thickness direction of the display panel, the first power signal sub-line overlaps with the gate driving circuit.
[0043] Optionally, the line width of the first power signal sub-line is less than or equal to the width of the gate drive circuit.
[0044] Optionally, the display panel further includes a common layer disposed on the side of the cathode near the substrate. The common layer is disposed in the display area and the frame area. Along the thickness direction of the display panel, the first power signal sub-line partially overlaps with the common layer.
[0045] Optionally, the display panel further includes an encapsulation layer that covers the cathode and the first power signal sub-line.
[0046] Optionally, the thickness of the first power signal sub-line is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms.
[0047] According to a second aspect of this application, a display device is provided, including a display panel as described above.
[0048] In the display panel of this application embodiment, by setting the first power signal sub-line of the power signal line on the side of the cathode away from the substrate, and by partially overlapping the power signal line and the cathode in the thickness direction of the display panel, the space occupied by the cathode in the bezel area is used to place the first power signal sub-line of the power signal line. This reduces the width of the bezel area occupied by the power signal line, thereby reducing the width of the bezel area and increasing the screen ratio of the display panel.
[0049] An embodiment of this application provides a display panel, which includes a display area and a bezel area. The bezel area is disposed around the display area. The display panel includes a substrate, a cathode, and power signal lines. The cathode is disposed on the substrate, and the power signal lines are disposed on the substrate and located in the bezel area. The power signal lines include a first power signal sub-line, which is disposed on the side of the cathode away from the substrate. Along the thickness direction of the display panel, the first power signal sub-line partially overlaps with the cathode and is connected to the cathode.
[0050] In the embodiments of this application, by setting the first power signal sub-line of the power signal line on the side of the cathode away from the substrate, and by partially overlapping the power signal line and the cathode in the thickness direction of the display panel, the space occupied by the cathode in the bezel area is used to place the first power signal sub-line of the power signal line. This reduces the width of the bezel area occupied by the power signal line, thereby reducing the width of the bezel area and increasing the screen ratio of the display panel.
[0051] Please refer to Figure 1, which is a top view of a display panel provided in an embodiment of this application. The display panel 100 includes a display area AA and a border area BA, with the border area BA located around the display area AA.
[0052] Please refer to Figure 2. Figure 2 is a cross-sectional view of the first type of display panel provided in the embodiment of this application along the A-A' direction shown in Figure 1. The display panel 100 includes a substrate 1, a cathode 2, and a power signal line 3. The cathode 2 is disposed on the substrate 1 and is located in the display area AA and the border area BA. The power signal line 3 is disposed on the substrate 1 and is located in the border area BA. The power signal line 3 is connected to the cathode 2 and is used to transmit a low potential reference signal to the cathode 2.
[0053] In some embodiments, the power signal line 3 is grounded, meaning the potential of the low-potential reference signal transmitted from the power signal line 3 to the cathode 2 is 0. In other embodiments, the potential of the low-potential reference signal transmitted from the power signal line 3 to the cathode 2 is negative.
[0054] Please refer to Figure 2. The power signal line 3 includes a first power signal sub-line 31. The first power signal sub-line 31 is disposed on the side of the cathode 2 away from the substrate 1. Along the thickness direction of the display panel, the first power signal sub-line 31 partially overlaps with the cathode 2 and is electrically connected to the cathode 2.
[0055] It should be noted that the thickness direction of the display panel is the third direction Z shown in Figure 2. The plane defined by the first direction X and the second direction Y is set as the bearing surface of the display panel 100, and the third direction Z is perpendicular to the plane defined by the first direction X and the second direction Y.
[0056] In the embodiments of this application, by setting the first power signal sub-line 31 of the power signal line 3 on the side of the cathode 2 away from the substrate 1, and by partially overlapping the power signal line 3 and the cathode 2 in the thickness direction of the display panel, the space occupied by the cathode 2 in the bezel area BA is used to place the first power signal sub-line 31 of the power signal line 3. This can reduce the width of the bezel area BA occupied by the power signal line 3, thereby reducing the width of the bezel area BA and increasing the screen ratio of the display panel.
[0057] In some embodiments, referring to FIG2, the first power signal sub-line 31 is disposed on the surface of the cathode 2 away from the substrate 1. No insulating layer separates the first power signal sub-line 31 from the cathode 2, and the first power signal sub-line 31 is in direct contact with the surface of the cathode 2 away from the substrate 1. By forming the first power signal sub-line 31 directly on the surface of the cathode 2 away from the substrate 1, the contact area between the first power signal sub-line 31 and the cathode 2 can be increased, thereby reducing the contact resistance between the first power signal sub-line 31 and the cathode 2. This reduces the width of the bezel area BA of the display panel while simultaneously reducing the voltage drop of the cathode 2, thus improving the uniformity of the display panel's brightness.
[0058] In some embodiments, the first power signal sub-line 31 may be a single-layer metal conductive structure made of a metal material, which may include any one of copper, aluminum, silver, titanium, molybdenum, nickel and other metal materials with good conductivity and low resistance.
[0059] In some embodiments, the first power signal sub-line 31 is a single-layer metal conductive structure, and the thickness of the first power signal sub-line 31 is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms. For example, the thickness of the first power signal sub-line 31 is 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, or 4000 angstroms. If the thickness of the first power signal sub-line 31 is too thin, the sheet resistance of the first power signal sub-line 31 will be large, and there will be a voltage drop in the transmission of the low-potential reference signal on the first power signal sub-line 31, which may aggravate the uneven display brightness of the display panel. When the thickness of the first power signal sub-line 31 reaches a certain value, the sheet resistance of the first power signal sub-line 31 will no longer decrease. If the thickness of the first power signal sub-line 31 is continuously increased, it will not only make the process of depositing the first power signal sub-line 31 take longer, but also waste raw materials and increase production costs. This embodiment limits the thickness of the first power signal sub-line 31 to between 2000 angstroms and 4000 angstroms, which can balance the sheet resistance and thickness of the first power signal sub-line 31. This can reduce the voltage drop of the cathode 2 while ensuring that production efficiency and manufacturing costs are not affected, thereby improving the uniformity of the brightness of the display panel.
[0060] In some embodiments, the first power signal sub-line 31 may also be a double-layer or multi-layer metal conductive structure made of two or more metal materials. For example, the first power signal sub-line 31 may be any one of the following stacked metal conductive structures: molybdenum / aluminum / molybdenum, titanium / aluminum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, etc.
[0061] In some embodiments, an insulating layer may be provided between the first power signal sub-line 31 and the cathode 2 to separate them. The first power signal sub-line 31 can be connected to the cathode layer 2 through a via on the insulating layer. In this way, the voltage drop of the cathode 2 can also be reduced, and the uniformity of the display brightness of the display panel can be improved.
[0062] In some embodiments, the display panel 100 may include a touch layer disposed on the side of the cathode 2 away from the substrate. The touch layer includes at least one conductive layer, which includes a first power signal sub-line 31. The first power signal sub-line can be fabricated using any conductive layer in the touch layer. This can reduce the bezel width of the display panel and reduce the voltage drop of the cathode 2 without increasing the film structure and manufacturing process of the display panel, thereby improving the uniformity of the display brightness of the display panel.
[0063] In some embodiments, please refer to FIG3, which is a top view of the first power signal sub-line in the display panel provided in the embodiment of this application. The first power signal sub-line 31 is disposed in the frame area BA and at least partially surrounds the display area AA. The first power signal sub-line 31 overlaps with the cathode 2 disposed in the frame area BA and surrounding the display area AA. This can increase the contact area of the first power signal sub-line 31, thereby reducing the contact area between the first power signal sub-line 31 and the cathode 2, and can improve the uniformity of the potential of each part of the cathode 2, thereby reducing the voltage of the cathode 2, and thus improving the uniformity of the brightness of the display panel.
[0064] In some embodiments, referring to FIG3, the first power signal sub-line 31 includes at least two first segments 311, which overlap with the cathode 2. The first segments 311 are disposed at least on opposite sides of the display area AA. For example, the two first segments 311 are respectively disposed on the left and right sides of the display area AA, or the two first segments 311 are respectively disposed on the top and bottom sides of the display area AA. By simultaneously providing a low-potential reference signal to the cathode 2 through the two first segments 311 on opposite sides of the display area AA, the consistency of the potential of different parts of the cathode 2 can be improved, thereby reducing the voltage drop of the cathode 2 and improving the uniformity of the brightness of the display panel.
[0065] In some embodiments, please refer to FIG3, the first power signal sub-line 31 includes four first sub-segments 311, wherein two first sub-segments 311 are respectively disposed on the upper and lower sides of the display area AA, and the other two first sub-segments 311 are respectively disposed on the left and right sides of the display area AA. The four first sub-segments 311 are respectively connected to the cathode 2 of the corresponding area. This can further improve the consistency of the potential of the cathode 2 in different parts, so as to further reduce the voltage drop of the cathode 2, thereby further improving the uniformity of the brightness of the display panel.
[0066] In some embodiments, please refer to FIG3, adjacent first sub-segments 311 are disconnected, and the four first sub-segments 311 form a partially enclosing structure for the display area AA.
[0067] In some embodiments, referring to FIG3, the power signal line 3 further includes a second power signal sub-line 32. The second power signal sub-line 32 is disposed in the bezel area BA. The second power signal sub-line 32 is partially exposed in the bezel area BA at the four corners of the display area AA. When the first power signal sub-line 31 is deposited, the first segment 311 of the first power signal sub-line 31 is directly deposited on the exposed portion of the second power signal sub-line 32 to achieve the connection between the first power signal sub-line 31 and the second power signal sub-line 32, so that the second power signal sub-line 32 can transmit the low potential reference signal to the first power signal sub-line 31, and then the first power signal sub-line 31 can transmit the low potential reference signal to the cathode 2.
[0068] In some other embodiments, adjacent first segments 311 are interconnected, and the four first segments form a fully enclosing structure for the display area AA.
[0069] In some embodiments, please refer to FIG2, the display panel 100 includes at least one blocking part 4, each blocking part 4 is disposed on the substrate 1, the blocking part 4 is located in the border area BA, the blocking part 4 is disposed around the display area AA, and the first power signal sub-line 31 is disposed on the side of the at least one blocking part 4 near the display area AA.
[0070] In some embodiments, please refer to FIG2, the display panel includes an encapsulation layer 9, which covers the cathode 2 and the first power signal sub-line 31.
[0071] Specifically, the encapsulation layer 9 includes a first inorganic encapsulation layer 91, an organic encapsulation layer 92, and a second inorganic encapsulation layer 93. The first inorganic encapsulation layer 91 is disposed on the surface of the cathode 2 and the first power signal sub-line 31 away from the substrate 1. The organic encapsulation layer 92 is disposed on the surface of the first inorganic encapsulation layer 91 away from the substrate 1. The second inorganic encapsulation layer 93 is disposed on the surfaces of the organic encapsulation layer 92 and the first inorganic encapsulation layer 91 away from the substrate 1. The first inorganic encapsulation layer 91 and the second inorganic encapsulation layer 93 are disposed in the display area AA and the border area BA. The edges of the first inorganic encapsulation layer 91 and the second inorganic encapsulation layer 93 extend to the side of the blocking portion 4 away from the display area AA, and the first inorganic encapsulation layer 91 and the second inorganic encapsulation layer 93 cover the blocking portion 4.
[0072] An organic encapsulation layer 92 is disposed on the display area AA and the bezel area BA. The organic encapsulation material of the organic encapsulation layer 92 is fluid. The blocking part 4 can be regarded as a dam. The blocking part 4 can block the organic encapsulation layer 92 on the side of the blocking part 4 close to the display area AA, so as to prevent the organic encapsulation material from overflowing to the side of the blocking part 4 away from the display area AA and causing encapsulation failure.
[0073] It should be noted that the encapsulation effect of the blocking part 4 closer to the display area AA is better than that of the side farther away from the display area AA. If the first power signal sub-line 31 is placed on the side of the blocking part 4 away from the display area AA, moisture and oxygen from the external environment can easily corrode the first power signal sub-line 31, and may even cause display defects in the display panel. By placing the first power signal sub-line 31 on the side of the blocking part 4 closer to the display area AA, the probability of moisture and oxygen from the external environment corroding the first power signal sub-line 31 can be reduced, thereby improving the encapsulation effect of the display panel.
[0074] In some implementations, referring to Figure 2, the display panel 100 includes two blocking portions, namely, blocking portion 4, which includes a first blocking sub-part 41 and a second blocking sub-part 42. The first blocking sub-part 41 and the second blocking sub-part 42 are disposed in the bezel area BA. The first blocking sub-part 41 is disposed around the display area AA, and the outer second blocking sub-part 42 is disposed around the inner first blocking sub-part 41. The first power signal sub-line 31 is disposed on the side of the first blocking sub-part 41 near the display area AA. This further reduces the probability of organic encapsulation material overflowing, thereby further improving the encapsulation performance of the display panel. In practical applications, the number of blocking sub-parts included in blocking portion 4 is not limited to the two in the above embodiment. It can be set according to the width of the bezel area BA and the requirements for encapsulation performance. The number of blocking sub-parts in blocking portion 4 can be one, two, three, or more.
[0075] In some embodiments, please refer to FIG2, the border area BA includes a first border sub-area BA1 and a second border sub-area BA2. The first border sub-area BA1 is arranged around the display area AA, the second border sub-area BA2 is arranged around the first border sub-area BA1, the first power signal sub-line 31 is arranged in the first border sub-area BA1, and the blocking part 4 is arranged in the second border sub-area BA2.
[0076] In some embodiments, referring to FIG2, a second power signal sub-line 32 is disposed on the substrate 1. The second power signal sub-line 32 is located in the first frame sub-region BA1 and the second frame sub-region BA2, and is electrically connected to the cathode 2. By disposing the second power signal sub-line 32 in the frame region BA and connecting the second power signal sub-line 32 to the cathode 2, the potential consistency of the cathode 2 in different parts can be further improved, thereby further reducing the voltage drop of the cathode 2 and further improving the uniformity of the brightness of the display panel.
[0077] In some embodiments, the linewidth of the first power signal sub-line 31 is greater than the linewidth of the second power signal sub-line 32. This embodiment adds a first power signal sub-line 31 to the cathode 2 to replace part of the second power signal sub-line 32, thereby reducing the linewidth of the second power signal sub-line 32 so that the linewidth of the first power signal sub-line 31 is greater than or equal to the linewidth of the second power signal sub-line 32, thus further reducing the width of the border area BA.
[0078] In some embodiments, referring to FIG2, along the thickness direction of the display panel, the blocking portion 4 is partially overlapped with the second power signal sub-line 32, and the blocking portion 4 is disposed on the side of the second power signal sub-line 32 away from the substrate 1.
[0079] Referring to Figure 2, the blocking portion 4 includes a first blocking sub-portion 41 and a second blocking sub-portion 42. The second power signal sub-line 32 is disposed on the side of the second blocking sub-portion 42 closer to the display area AA, and the first blocking sub-portion 41 is disposed on the side of the second power signal sub-line 32 away from the substrate 1. Along the thickness direction of the display panel, the first blocking sub-portion 41 and the second power signal sub-line 32 partially overlap. By disposing the first blocking sub-portion 41 of the blocking portion 4 on the side of the second power signal sub-line 32 away from the substrate 1 and making the first blocking sub-portion 41 partially overlap with the second power signal sub-line 32, the space where the first blocking sub-portion 41 is placed can be used to place the second power signal sub-line 32. This reduces the width of the second bezel sub-area BA2 occupied by the second power signal sub-line 32, thereby further reducing the width of the bezel area BA.
[0080] In some embodiments, referring to FIG2, the display panel 100 includes a source-drain layer 5 disposed on a substrate 1, and a cathode 2 disposed on the side of the source-drain layer 5 away from the substrate 1. The source-drain layer 5 includes a second power signal sub-line 32. It should be noted that the source-drain layer 5 including the second power signal sub-line 32 means that the second power signal sub-line 32 is disposed in the same layer as the source-drain layer 5, and the second power signal sub-line 32 is made of the same material as the source-drain layer 5. The second power signal sub-line 32 is fabricated simultaneously using the fabrication process of the source-drain layer 5. In this way, the voltage drop of the cathode 2 can be reduced without increasing the film layer structure and fabrication process of the display panel, thereby improving the uniformity of the display brightness of the display panel.
[0081] In some embodiments, the display panel 100 may include two or three source-drain layers, such as a first source-drain layer and a second source-drain layer, wherein the first source-drain layer and the second source-drain layer are separated by an insulating layer, and either the first source-drain layer or the second source-drain layer includes a second power signal sub-line 32.
[0082] In some embodiments, referring to FIG2, the power signal line 3 further includes a third power signal sub-line 33, which is disposed on the side of the cathode 2 near the substrate 1. The third power signal sub-line 33 is located in the first bezel sub-region BA1 and overlaps with the cathode 2 and the second power signal sub-line 32. Along the thickness direction of the display panel, the first power signal sub-line 31 and the third power signal sub-line 33 are at least partially overlapped.
[0083] In this embodiment, by at least partially overlapping the first power signal sub-line 31 and the third power signal sub-line 33 along the thickness direction of the display panel, the width of the bezel area BA occupied by the third power signal sub-line 33 can be used to place the first power signal sub-line 31, thereby further reducing the width of the bezel area BA. By connecting the third power signal sub-line 33 to the cathode 2, the potential uniformity of different parts of the cathode 2 can be further reduced, thereby further reducing the voltage drop of the cathode 2 and further improving the uniformity of the brightness of the display panel.
[0084] In some embodiments, referring to FIG2, the display panel 100 further includes an anode layer 6, which is disposed on the side of the cathode 2 near the substrate 1, and includes a third power signal sub-line 33.
[0085] It should be noted that the inclusion of the third power signal sub-line 33 in the anode layer 6 means that the third power signal sub-line 33 is disposed in the same layer as the anode layer 6, and the third power signal sub-line 33 is made of the same material as the anode layer 6. The third power signal sub-line 33 is fabricated simultaneously using the manufacturing process of the anode layer 6. In this way, the voltage drop of the cathode 2 can be reduced without increasing the film layer structure and manufacturing process of the display panel, thereby improving the uniformity of the display brightness of the display panel.
[0086] In some embodiments, referring to FIG2, the display panel 100 includes a substrate 1, a driving circuit layer 12, and a light-emitting device layer. The driving circuit layer is disposed on the substrate 1, and the light-emitting device layer is disposed on the side of the driving circuit layer away from the substrate 1. The driving circuit layer 12 includes the source-drain layer 5 as described above. In addition, the driving circuit layer 12 may also include an active layer, a gate layer, and an insulating layer (not shown in the figure) disposed between the above-mentioned film layers to insulate and separate the above-mentioned film layers. The light-emitting device layer includes the anode layer 6 and the cathode 2 as described above. In addition, the light-emitting device layer also includes a pixel definition layer 10, a light-emitting layer 11, and a common layer 8 disposed on both sides of the light-emitting layer. The pixel definition layer 10 has a plurality of pixel openings in the portion corresponding to the display area AA, and the light-emitting layer 11 is disposed in the corresponding pixel opening. The common layer 8 may include, but is not limited to, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, etc., which are shared and disposed on the entire surface.
[0087] In some embodiments, referring to FIG2, the display panel further includes a gate driving circuit 7, which is disposed on the substrate 1 and located in the bezel area BA. The gate driving circuit 7 is part of the driving circuit layer 12. The cathode 2 is disposed on the side of the gate driving circuit 7 away from the substrate 1. Along the thickness direction of the display panel, the first power signal sub-line 31 overlaps with the gate driving circuit 7. In this way, the area in the bezel area BA used to house the gate driving circuit 7 can be used to house the first power signal sub-line 31, thereby reducing the space occupied by the first power signal sub-line 31 in the bezel area BA, and thus further reducing the width of the bezel area BA.
[0088] In some embodiments, referring to FIG2, the first power signal sub-line 31 is partially overlapped with the cathode 2 and the gate driving circuit 7 along the thickness direction of the display panel. The area in the bezel area BA used to place the cathode 2 can be used to simultaneously place the gate driving circuit 7 and the first power signal sub-line 31, thereby reducing the space occupied by the first power signal sub-line 31 and the gate driving circuit 7 in the bezel area BA, and thus further reducing the width of the bezel area BA.
[0089] In some embodiments, the line width of the first power signal sub-line 31 is less than or equal to the width of the gate driving circuit 7. The width of the gate driving circuit 7 refers to the width of the area between the side edge of the gate driving circuit 7 near the display area AA and the side edge of the gate driving circuit 7 away from the display area AA, so as to prevent the first power signal sub-line 31 from exceeding the edge of the gate driving circuit 7 and affecting the light transmittance of the display area AA and the encapsulation effect of the frame area BA.
[0090] In some embodiments, referring to FIG2, the line width of the first power signal sub-line 31 is smaller than the width of the gate driving circuit 7, and the orthographic projection of the first power signal sub-line 31 on the gate driving circuit 7 is located within the gate driving circuit 7. This can prevent the first power signal sub-line 31 from exceeding the edge of the gate driving circuit 7 and affecting the light transmittance of the display area AA and the encapsulation effect of the bezel area BA.
[0091] In some embodiments, the linewidth of the first power signal sub-line 31 is equal to the width of the gate driving circuit 7, and the first power signal sub-line 31 completely overlaps with the gate driving circuit 7. This allows the first power signal sub-line 31 to have the maximum linewidth, further reducing the voltage drop of the cathode 2, thereby improving the uniformity of display brightness. In some embodiments, referring to FIG2, the common layer 8 is disposed on the side of the cathode 2 near the substrate 1. The common layer 8 is located in the display area AA and the bezel area NA. Along the thickness direction of the display panel, the first power signal sub-line 31 and the common layer 8 partially overlap. It should be noted that the common layer 8 is formed using a full-area vapor deposition process. To ensure the uniformity of the film thickness of the common layer 8 in the display area AA, the film boundary of the common layer 8 extends from the display area AA to the bezel area NA, and the common layer 8 and the first power signal sub-line 31 partially overlap in the thickness direction of the display panel. On the one hand, by expanding the film-forming boundary of the common layer 8, the uniformity of the film formation of the common layer 8 is improved. On the other hand, the first power signal sub-line 31 is partially overlapped with the common layer 8. The first power signal sub-line 31 can work together with the cathode 2 to receive electrons from the external circuit and inject electrons into the electron transport layer in the common layer 8, driving electrons and holes to recombine in the light-emitting layer to excite the light-emitting material to generate photons, thereby improving the luminous efficiency of the display panel.
[0092] In some embodiments, please refer to FIG4, which is a cross-sectional view of the second type of display panel provided in the embodiments of this application along the A-A' direction shown in FIG1. Its structure is roughly the same as that of the display panel shown in FIG2, except that: the second frame sub-region BA2 is not provided with the second power signal sub-line 32. In the second frame sub-region BA2, only the blocking part 4 and the first inorganic encapsulation layer 91 and the second inorganic encapsulation layer 93 covering the blocking part 4 are provided. By removing the second power signal sub-line 32 in the second frame sub-region BA2, the width of the frame region BA can be further reduced.
[0093] The display panel provided in the above embodiments of this application can reduce the bezel width of the display panel by 300 micrometers to 500 micrometers compared to current display panels.
[0094] Based on the display panel provided in the above embodiments of this application, please refer to FIG2. An embodiment of this application also provides a method for manufacturing a display panel, the method comprising:
[0095] A cathode 2 is formed on substrate 1;
[0096] A first power signal sub-line 31 is formed on the side of the cathode 2 away from the substrate 1.
[0097] In some embodiments, along the thickness direction of the display panel, the first power signal sub-line 31 partially overlaps with the cathode 2, and the first power signal sub-line 31 and the cathode 2 are connected. By setting the first power signal sub-line 31 of the power signal line 3 on the side of the cathode 2 away from the substrate 1, and making the power signal line 3 and the cathode 2 partially overlap in the thickness direction of the display panel, the space occupied by the cathode 2 in the bezel area BA can be used to place the first power signal sub-line 31 of the power signal line 3. This can reduce the width of the bezel area BA occupied by the power signal line 3, thereby reducing the width of the bezel area BA and increasing the screen-to-body ratio of the display panel.
[0098] In some embodiments, please refer to Figures 3, 5, and 6. Figure 5 is a schematic diagram of the photomask used in the manufacturing method of the display panel provided in the embodiment of this application, and Figure 6 is a schematic diagram of the manufacturing method of the display panel provided in the embodiment of this application. Multiple openings 201 are provided around the periphery of the photomask 20. The openings 201 are elongated and spaced apart from each other, penetrating the photomask 20. The area indicated by the dashed frame inside the photomask 20 in Figure 6 corresponds to the display area AA of the display panel 100. No openings are provided in other areas of the photomask 20 besides the openings 201. When depositing the first power signal sub-line 31, the photomask 20 is used to cover the substrate 1. The conductive material is directly deposited on the cathode 2 through the openings 201 to form the first power signal sub-line 31. Material in other areas is blocked by the photomask 20 and deposited on the photomask 20.
[0099] In this embodiment, the first power signal sub-line 31 is directly formed on the cathode 2 by physical vapor deposition using the above-described manufacturing method, without the need for exposure, development and etching processes. This reduces damage to the cathode 2 and lowers the manufacturing difficulty of the display panel.
[0100] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to FIG7, which is a schematic diagram of the display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be elaborated upon here.
[0101] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel includes a display area and a bezel area. The display panel includes a substrate, a cathode, and power signal lines. By setting the first power signal sub-line of the power signal line on the side of the cathode away from the substrate, and making the power signal line and the cathode partially overlap in the thickness direction of the display panel, the space occupied by the cathode in the bezel area is used to place the first power signal sub-line of the power signal line. This can reduce the width of the bezel area occupied by the power signal line, thereby reducing the width of the bezel area and increasing the screen ratio of the display panel.
[0102] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0103] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0104] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0105] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel, comprising a display area and a border area, the border area being disposed around the periphery of the display area, the display panel comprising: substrate; A cathode is disposed on the substrate; A power signal line is disposed on the substrate and located in the frame area; The power signal line includes a first power signal sub-line, which is disposed on the side of the cathode away from the substrate and along the thickness direction of the display panel. The first power signal sub-line partially overlaps with the cathode and is connected to the cathode.
2. The display panel as claimed in claim 1, wherein, The first power signal sub-line is disposed on the surface of the cathode away from the substrate.
3. The display panel as claimed in claim 1, wherein, The first power signal sub-line is configured to at least partially surround the display area.
4. The display panel as claimed in claim 1, wherein, The first power signal sub-line includes at least two first sub-segments, the first sub-segments being connected to the cathode, and the first sub-segments being disposed at least on opposite sides of the display area.
5. The display panel as claimed in claim 4, wherein, The first power signal sub-line includes four first sub-segments, two of which are respectively located on the upper and lower sides of the display area, and the other two are respectively located on the left and right sides of the display area, with adjacent first sub-segments disconnected from each other.
6. The display panel as claimed in claim 1, wherein, The display panel includes at least one blocking portion, each of the blocking portions is disposed on the substrate and located in the border area, the blocking portions are disposed around the display area, and the first power signal sub-line is disposed on the side of at least one of the blocking portions close to the display area.
7. The display panel as claimed in claim 6, wherein, The frame area includes a first frame sub-area and a second frame sub-area. The first frame sub-area is arranged around the display area, and the second frame sub-area is arranged around the first frame sub-area. The first power signal sub-line is arranged in the first frame sub-area, and the blocking part is arranged in the second frame sub-area. The power signal line further includes a second power signal sub-line, which is disposed on the substrate and located in the first frame sub-region and the second frame sub-region. The second power signal sub-line is electrically connected to the cathode.
8. The display panel as claimed in claim 7, wherein, The line width of the first power signal sub-line is greater than or equal to the line width of the second power signal sub-line.
9. The display panel as claimed in claim 7, wherein, Along the thickness direction of the display panel, at least one of the blocking portions partially overlaps with the second power signal sub-line.
10. The display panel as claimed in claim 7, wherein, The display panel includes a source-drain layer disposed on the substrate, the cathode is disposed on the side of the source-drain layer away from the substrate, and the source-drain layer includes a second power signal sub-line.
11. The display panel as claimed in claim 7, wherein, The power signal line also includes a third power signal sub-line, which is disposed on the side of the cathode near the substrate. The third power signal sub-line is located in the first frame sub-region and overlaps with the cathode and the second power signal sub-line. Wherein, along the thickness direction of the display panel, the first power signal sub-line and the third power signal sub-line are at least partially overlapped.
12. The display panel as claimed in claim 11, wherein, The display panel further includes an anode layer disposed on the side of the cathode near the substrate, and the anode layer includes the third power signal sub-line.
13. The display panel as claimed in claim 1, wherein, The display panel further includes a gate driving circuit, which is disposed on the substrate and located in the frame area. The cathode is disposed on the side of the gate driving circuit away from the substrate. Along the thickness direction of the display panel, the first power signal sub-line overlaps with the gate driving circuit.
14. The display panel as claimed in claim 13, wherein, The line width of the first power signal sub-line is less than or equal to the width of the gate drive circuit.
15. The display panel as claimed in claim 1, wherein, The display panel further includes a common layer, which is disposed on the side of the cathode near the substrate. The common layer is disposed in the display area and the frame area. Along the thickness direction of the display panel, the first power signal sub-line partially overlaps with the common layer.
16. The display panel as claimed in claim 1, wherein, The display panel further includes an encapsulation layer that covers the cathode and the first power signal sub-line.
17. The display panel as claimed in claim 1, wherein, The thickness of the first power signal sub-line is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms.
18. A display device comprising a display panel as described in any one of claims 1 to 17.