Display panel and display terminal

Abstract

The present application relates to a display panel and a display terminal. The display panel comprises a substrate, an N-type charge layer, and a P-type charge layer, wherein the P-type charge layer is disposed on the side of the N-type charge layer that is away from the substrate, and the difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer and the highest occupied molecular orbital energy level of the P-type charge layer is less than or equal to 1.5 eV.

Description

Display panel and display terminal

[0001] This application claims priority to Chinese patent application No. 202510368658.6, filed on March 26, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0003] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology that has gradually attracted attention due to its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and has occupied a certain position in the field of panel display technology.

[0004] Multilayer OLED devices offer advantages in lifetime and temperature stability, leading to increased application demand. Multilayer OLED devices consist of multiple emitting layers connected by charge generation layers (CGLs) with anti-PN junctions, resulting in higher driving voltages and power consumption.

[0005] Therefore, it is urgent to solve the above-mentioned technical problems. Summary of the Invention

[0006] This application provides a display panel and a display terminal to improve the technical problems of high driving voltage and high power consumption of stacked OLED devices in the display panel.

[0007] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising:

[0008] substrate;

[0009] An N-type charge layer is disposed on one side of the substrate;

[0010] A P-type charge layer is disposed on the side of the N-type charge layer that is away from the substrate;

[0011] The difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer and the highest occupied molecular orbital energy level of the P-type charge layer is less than or equal to 1.5 eV.

[0012] According to a second aspect of this application, a display terminal is provided, including a display panel, the display panel comprising:

[0013] substrate;

[0014] An N-type charge layer is disposed on one side of the substrate;

[0015] A P-type charge layer is disposed on the side of the N-type charge layer that is away from the substrate;

[0016] The difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer and the highest occupied molecular orbital energy level of the P-type charge layer is less than or equal to 1.5 eV. Attached Figure Description

[0017] Figure 1 is a top view of a display panel provided in an exemplary embodiment of this disclosure;

[0018] Figure 2 is a schematic cross-sectional view of the CC section in Figure 1;

[0019] Figure 3 is a schematic diagram illustrating the principle of reducing the potential barrier difference between the N-type charge layer and the P-type charge layer in an exemplary embodiment of this disclosure.

[0020] Figure 4 is a schematic diagram of the structure of a display terminal provided in an exemplary embodiment of this disclosure. Embodiments of the present invention

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] To achieve the above objectives, as shown in Figures 1 and 2, according to a first aspect of this application, a display panel 1 is provided, comprising a substrate 10, an N-type charge layer 61, and a P-type charge layer 62. The N-type charge layer 61 is disposed on one side of the substrate 10; the P-type charge layer 62 is disposed on the side of the N-type charge layer 61 facing away from the substrate 10; wherein the difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 and the highest occupied molecular orbital energy level of the P-type charge layer 62 is less than or equal to 1.5 eV.

[0023] Display panel 1 is an OLED panel, etc. As shown in Figure 1, display panel 1 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA can be provided with multiple sub-pixels, which can include red sub-pixels, green sub-pixels, and blue sub-pixels, thereby realizing color display. The non-display area NA can be provided with driving circuits, such as gate driving circuits, which can provide driving signals to the sub-pixels.

[0024] The substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be made of glass, quartz, or silicon. The flexible substrate can be made of one of the following materials: polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET).

[0025] In some embodiments, the N-type charge layer 61 and the P-type charge layer 62 can be applied in a tandem OLED device, which is formed by stacking multiple light-emitting layers in series. In a tandem OLED device, all multiple light-emitting layers can emit light, thereby significantly improving the brightness of the display panel 1.

[0026] An N-type charge layer 61 and a P-type charge layer 62 can be disposed between two adjacent light-emitting layers. The P-type charge layer 62 is used to generate holes, and the N-type charge layer 61 is used to generate electrons. Electrons generated by the N-type charge layer 61 are injected into the light-emitting layer, and holes generated by the P-type charge layer 62 are injected into the light-emitting layer. Holes and electrons recombine in the light-emitting layer to emit light.

[0027] The N-type charge layer 61 has a high electron transport capability, which can provide sufficient electrons for the luminescent material. In terms of material design, electron-withdrawing groups can be introduced into the N-type charge layer 61 to deepen the lowest unoccupied molecular orbital energy level of the N-type charge layer 61.

[0028] The p-type charge layer 62 has a high hole transport capability, which can provide sufficient holes for the luminescent material. In terms of material design, electron-donating groups can be introduced into the p-type charge layer 62 to make the highest occupied molecular orbital energy level of the p-type charge layer 62 shallower.

[0029] As shown in Figure 3(a), there is a potential barrier difference between the N-type charge layer 61 (NCGL) and the P-type charge layer 62 (PCGL). The potential barrier difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 and the highest occupied molecular orbital energy level of the P-type charge layer 62 is relatively large. Charge carriers need to be driven by a relatively high driving voltage to overcome these barriers and turn on the entire device, thus requiring a large driving voltage. The charge carriers include holes and electrons.

[0030] As shown in Figure 3(b), in order to make it easier for charge carriers to cross the potential barrier between the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 (NCGL) and the highest occupied molecular orbital energy level of the P-type charge layer 62 (PCGL), this application makes the difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 and the highest occupied molecular orbital energy level of the P-type charge layer 62 less than or equal to 1.5 eV, i.e., LUMO. N-CGL -HOMO P-CGL ≤1.5eV, thereby more effectively reducing the driving voltage of stacked OLED devices and reducing power consumption.

[0031] In some embodiments, the energy difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 and the highest occupied molecular orbital energy level of the P-type charge layer 62 is 1.0 eV, 1.05 eV, 1.1 eV, 1.15 eV, 1.2 eV, 1.25 eV, 1.3 eV, 1.35 eV, 1.4 eV, 1.45 eV, 1.5 eV, etc.

[0032] Optionally, as shown in FIG2, the display panel 1 further includes an anode 20 and a first light-emitting layer 30. The anode 20 is disposed between the substrate 10 and the N-type charge layer 61. The first light-emitting layer 30 is disposed between the anode 20 and the N-type charge layer 61. The first light-emitting layer 30 includes a first light-emitting material layer 33 (EML) and a first electron transport layer 35 (ETL) stacked together. The first electron transport layer 35 is disposed on the side of the first light-emitting material layer 33 facing away from the substrate 10. The lowest unoccupied molecular orbital energy level of the N-type charge layer 61 is larger than the lowest unoccupied molecular orbital energy level of the first electron transport layer 35.

[0033] In some embodiments, the anode 20 may be a metal or metal oxide material, such as a stack of one or more of indium tin oxide, indium zinc oxide, silver, etc.

[0034] Holes generated at anode 20 are injected into the first light-emitting layer 30, and electrons generated at N-type charge layer 61 are injected into the first light-emitting layer 30. Holes and electrons recombine in the first light-emitting layer 30 to emit light.

[0035] In some embodiments, the first light-emitting layer 30 further includes a first hole transport layer 31 disposed between the anode 20 and the first light-emitting material layer 33. The first hole transport layer 31 is used to effectively transport holes injected from the anode 20 to the first light-emitting material layer 33, ensuring that holes and electrons in the first light-emitting material layer 33 effectively recombine to generate photons.

[0036] In some embodiments, as shown in FIG2, the first light-emitting layer 30 further includes a hole injection layer 71 (HIL) disposed between the anode 20 and the first hole transport layer 31. The hole injection layer 71 is used to reduce the energy barrier for injecting holes from the anode 20 to the first light-emitting material layer 33, so that holes can be transferred from the anode 20 to the first hole transport layer 31 more effectively, thereby improving the hole injection efficiency and thus improving the luminous efficiency and brightness of the pixel.

[0037] In some embodiments, the first light-emitting layer 30 further includes a first hole-blocking layer 34 disposed between the first light-emitting material layer 33 and the first electron transport layer 35. The first hole-blocking layer 34 is used to block holes from entering the first electron transport layer 35 through the first light-emitting material layer 33, so that holes and electrons combine in the first light-emitting material layer 33 to form excitons.

[0038] In some embodiments, the first electron transport layer 35 is used to effectively transport electrons from the N-type charge layer 61 to the first light-emitting material layer 33, so as to ensure that electrons can be quickly and effectively transported to the first light-emitting material layer 33 and recombine with holes to emit photons.

[0039] Optionally, as shown in Figure 2, the first light-emitting layer 30 further includes a first electron blocking layer 32 disposed between the first hole transport layer 31 and the first light-emitting material layer 33. The first light-emitting material layer 33 includes a red light-emitting layer 331, a green light-emitting layer 332, and a blue light-emitting layer 333. The first electron blocking layer 32 includes a first blocking layer 321, a second blocking layer 322, and a third blocking layer 323. The red light-emitting layer 331 is aligned with the first blocking layer 321, the green light-emitting layer 332 is aligned with the second blocking layer 322, and the blue light-emitting layer 333 is aligned with the third blocking layer 323.

[0040] In some embodiments, as shown in FIG2, the first electron blocking layer 32 is used to block electrons from entering the first hole transport layer 31 through the first light-emitting material layer 33, so that holes and electrons combine in the first light-emitting material layer 33 to form excitons.

[0041] In some embodiments, the first light-emitting material layer 33 can be fabricated using processes such as vapor deposition or inkjet printing. The first light-emitting material layer 33 includes a red light-emitting layer 331, a green light-emitting layer 332, and a blue light-emitting layer 333. The red light-emitting layer 331 emits red light when electrons and holes recombine. The green light-emitting layer 332 emits green light when electrons and holes recombine. The blue light-emitting layer 333 emits blue light when electrons and holes recombine.

[0042] In some embodiments, as shown in FIG2, the first electron blocking layer 32 includes a first blocking layer 321, a second blocking layer 322, and a third blocking layer 323. The first blocking layer 321 blocks electrons from passing through the red light-emitting layer 331 into the first hole transport layer 31, so that holes and electrons combine in the red light-emitting layer 331 to form excitons. The second blocking layer 322 blocks electrons from passing through the green light-emitting layer 332 into the first hole transport layer 31, so that holes and electrons combine in the green light-emitting layer 332 to form excitons. The third blocking layer 323 blocks electrons from passing through the blue light-emitting layer 333 into the first hole transport layer 31, so that holes and electrons combine in the blue light-emitting layer 333 to form excitons.

[0043] It should be understood that, as shown in Figure 2, in the first light-emitting layer 30, the hole injection layer 71, the first hole transport layer 31, the first hole blocking layer 34, and the first electron transport layer 35 are all integrally formed, that is, the first light-emitting material layers 33 of different colors share the hole injection layer 71, the first hole transport layer 31, the first hole blocking layer 34, and the first electron transport layer 35.

[0044] Optionally, the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 is 0.1 eV to 0.3 eV higher than the lowest unoccupied molecular orbital energy level of the first electron transport layer 35. With this configuration, a deeper lowest unoccupied molecular orbital energy level of the N-type charge layer 61 can be formed. For example, the lowest unoccupied molecular orbital energy level of the N-type charge layer 61 can be 0.1 eV, 0.15 eV, 0.2 eV, 0.25 eV, or 0.3 eV higher than the lowest unoccupied molecular orbital energy level of the first electron transport layer 35.

[0045] Optionally, both the N-type charge layer 61 and the P-type charge layer 62 are integrally formed. This means that the first light-emitting material layers 33 of different colors share the N-type charge layer 61; and the second light-emitting material layers 43 of different colors share the P-type charge layer 62.

[0046] Optionally, the N-type charge layer 61 is at least doped with either ytterbium or lithium.

[0047] The N-type charge layer 61 is doped with ytterbium at a mass percentage of 1% to 10%, or lithium at a mass percentage of 1% to 10%. Starting with material selection, a material with an intrinsically lowest unoccupied molecular orbital energy level and a deep N-type charge layer 61 is chosen, and then an active metal (such as ytterbium (Yb), lithium (Li), etc.) is doped into the N-type charge layer 61.

[0048] In some embodiments, the mass percentage content of ytterbium doped in the N-type charge layer 61 can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc.

[0049] In some embodiments, the mass percentage content of lithium doped in the N-type charge layer 61 can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc. Optionally, as shown in FIG2, the display panel 1 further includes a second light-emitting layer 40 and a cathode 50. The second light-emitting layer 40 is disposed on the side of the first light-emitting layer 30 away from the substrate 10; the cathode 50 is disposed on the side of the second light-emitting layer 40 away from the substrate 10; the second light-emitting layer 40 includes a second light-emitting material layer 43 and a second hole transport layer 41 stacked together, the second light-emitting material layer 43 being disposed on the side of the second hole transport layer 41 away from the substrate 10; wherein, the highest occupied molecular orbital energy level of the P-type charge layer 62 is smaller than the highest occupied molecular orbital energy level of the second hole transport layer 41.

[0050] In some embodiments, the cathode 50 may be made of one or more alloys of silver, aluminum, magnesium, etc.

[0051] In some embodiments, the second light-emitting layer 40 may have the same structure as the first light-emitting layer 30, thereby simplifying the manufacturing process of the display panel 1.

[0052] In some embodiments, the second light-emitting layer 40 may have a different structure from the first light-emitting layer 30.

[0053] As shown in Figure 2, the display panel 1 includes a tandem OLED device, which is formed by stacking multiple light-emitting layers in series through a charge generation layer (CGL). In the tandem OLED device, both the first light-emitting layer 30 and the second light-emitting layer 40 can emit light, thereby significantly improving the brightness of the display panel 1.

[0054] Specifically, holes generated in the P-type charge layer 62 are injected into the second light-emitting material layer 43, and electrons generated in the cathode 50 are injected into the second light-emitting layer 40. Holes and electrons recombine in the second light-emitting layer 40 to emit light.

[0055] In some embodiments, as shown in FIG2, the second light-emitting layer 40 further includes a second hole transport layer 41 disposed between the P-type charge layer 62 and the second light-emitting material layer 43. The second hole transport layer 41 is used to effectively transport holes injected from the P-type charge layer 62 to the second light-emitting material layer 43, ensuring that holes and electrons in the second light-emitting material layer 43 effectively recombine to generate photons.

[0056] In some embodiments, as shown in FIG2, the second light-emitting layer 40 further includes a second hole-blocking layer 44 disposed between the second light-emitting material layer 43 and the second electron transport layer 45. The second hole-blocking layer 44 is used to block holes from entering the second electron transport layer 45 through the second light-emitting material layer 43, so that holes and electrons combine in the second light-emitting material layer 43 to form excitons.

[0057] In some embodiments, as shown in FIG2, the second light-emitting layer 40 further includes a second electron transport layer 45 disposed between the second light-emitting material layer 43 and the cathode 50. The second electron transport layer 45 is used to efficiently transport electrons from the cathode 50 to the second light-emitting material layer 43, so as to ensure that electrons can be quickly and efficiently transported to the second light-emitting material layer 43 and recombine with holes to emit photons.

[0058] In some embodiments, as shown in FIG2, the second light-emitting layer 40 further includes an electron injection layer 72 disposed between the cathode 50 and the second electron transport layer 45. The electron injection layer 72 is used to reduce the energy barrier for electrons to be injected from the cathode 50 into the second light-emitting material layer 43, thereby improving the electron injection efficiency. At the same time, the electron injection layer 72 can also ensure good interface contact and energy level matching with the cathode 50 and the second electron transport layer 45, ensuring that electrons can be easily injected into the second light-emitting material layer 43 to participate in the light emission process.

[0059] Optionally, the highest occupied molecular orbital energy level of the P-type charge layer 62 is 0.1 eV to 0.3 eV lower than the highest occupied molecular orbital energy level of the second hole transport layer 41. For example, the highest occupied molecular orbital energy level of the P-type charge layer 62 is 0.1 eV, 0.15 eV, 0.2 eV, 0.25 eV, 0.3 eV, etc., lower than the highest occupied molecular orbital energy level of the second hole transport layer 41.

[0060] Optionally, as shown in FIG2, the second light-emitting layer 40 further includes a second electron blocking layer 42 disposed between the second hole transport layer 41 and the second light-emitting material layer 43; the second light-emitting material layer 43 includes a red sub-light-emitting layer 431, a green sub-light-emitting layer 432 and a blue sub-light-emitting layer 433; the second electron blocking layer 42 includes a first sub-blocking layer 421, a second sub-blocking layer 422 and a third sub-blocking layer 423; wherein, the red sub-light-emitting layer 431 is aligned with the first sub-blocking layer 421, the green sub-light-emitting layer 432 is aligned with the second sub-blocking layer 422, and the blue sub-light-emitting layer 433 is aligned with the third sub-blocking layer 423.

[0061] In some embodiments, as shown in FIG2, the second electron blocking layer 42 is used to block electrons from entering the second hole transport layer 41 through the second light-emitting material layer 43, so that holes and electrons combine in the second light-emitting material layer 43 to form excitons.

[0062] In some embodiments, the second light-emitting material layer 43 can be fabricated using processes such as vapor deposition or inkjet printing. The second light-emitting material layer 43 includes a red sub-light-emitting layer 431, a green sub-light-emitting layer 432, and a blue sub-light-emitting layer 433. The red light-emitting layer 431 emits red light when electrons and holes recombine. The green light-emitting layer 432 emits green light when electrons and holes recombine. The blue light-emitting layer 433 emits blue light when electrons and holes recombine.

[0063] The second electron blocking layer 42 includes a first sub-blocking layer 421, a second sub-blocking layer 422, and a third sub-blocking layer 423. The second electron blocking layer 42 blocks electrons from passing through the red sub-emitting layer 431 into the second hole transport layer 41, allowing holes and electrons to combine in the red sub-emitting layer 431 to form excitons. The second sub-blocking layer 422 blocks electrons from passing through the green sub-emitting layer 432 into the second hole transport layer 41, allowing holes and electrons to combine in the green sub-emitting layer 432 to form excitons. The third sub-blocking layer 423 blocks electrons from passing through the blue sub-emitting layer 433 into the second hole transport layer 41, allowing holes and electrons to combine in the blue sub-emitting layer 433 to form excitons.

[0064] It should be understood that in the second light-emitting layer 40, the second hole transport layer 41, the second hole blocking layer 44, the second electron transport layer 45, and the electron injection layer 72 are all integrally formed, that is, the second light-emitting material layers 43 of different colors share the second hole transport layer 41, the second hole blocking layer 44, the second electron transport layer 45, and the electron injection layer 72.

[0065] In one comparative example, LUMO N-CGL -HOMO P-CGL =1.5eV, the driving voltage when the multilayer device is working normally is recorded as 100%.

[0066] In a first embodiment, the N-type charge layer 61 is made of a quinolinyl o-phenanthroline compound, and the N-type charge layer 61 is doped with ytterbium at a mass percentage of 1%. The second hole transport layer 41 is made of a triphenylamine compound doped with an axialene compound. The axialene compound has a mass percentage content of 5%. In the first embodiment, LUMO N-CGL -HOMO P-CGL =1.5eV, the driving voltage of the stacked device when it is working normally is 80% of that of the comparative example, that is, the driving voltage of the stacked device in the first embodiment is reduced by 20% compared with the comparative example.

[0067] In the second embodiment, the N-type charge layer 61 is made of a quinolinyl o-phenanthroline compound, and the N-type charge layer 61 is doped with ytterbium at a mass percentage of 1%. The second hole transport layer 41 is made of a diphenylamine compound doped with an axialene compound. The axialene compound has a mass percentage content of 5%. In the second embodiment, LUMO N-CGL -HOMO P-CGL =1.45eV, the driving voltage of the stacked device when it is working normally is 77% of that of the comparative example, that is, the driving voltage of the stacked device in the second embodiment is reduced by 23% compared with the comparative example.

[0068] In the third embodiment, the N-type charge layer 61 is made of a quinolinyl o-phenanthroline compound, and the N-type charge layer 61 is doped with ytterbium at a mass percentage of 1%. The second hole transport layer 41 is made of a diphenylamine compound doped with an axialene compound. The axialene compound has a mass percentage content of 8%. In the third embodiment, LUMO N-CGL -HOMO P-CGL =1.3eV, the driving voltage of the stacked device when it is working normally is 69% of that of the comparative example, that is, the driving voltage of the stacked device in the third embodiment is reduced by 31% compared with the comparative example.

[0069] Experimental tests show that the driving voltage of the stacked devices in the exemplary embodiments of this disclosure is lower than that of the stacked devices in the comparative examples. That is, the driving voltage of the display panel 1 of this application is lower and the power consumption is lower.

[0070] As shown in Figure 4, according to a second aspect of this application, a display terminal 2 is provided, including the display panel 1 described above.

[0071] In this embodiment, as shown in FIG4, the display terminal 2 includes a display panel 1 and a terminal body 3, which are combined into one unit.

[0072] In this embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0073] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0075] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0076] The above description is merely a preferred embodiment of this application and does not constitute any limitation on this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel comprising: substrate; An N-type charge layer is disposed on one side of the substrate; A P-type charge layer is disposed on the side of the N-type charge layer that is away from the substrate; The difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer and the highest occupied molecular orbital energy level of the P-type charge layer is less than or equal to 1.5 eV.

2. The display panel according to claim 1, wherein, The display panel also includes: An anode is disposed between the substrate and the N-type charge layer; A first light-emitting layer is disposed between the anode and the N-type charge layer. The first light-emitting layer includes a first light-emitting material layer and a first electron transport layer stacked together. The first electron transport layer is disposed on the side of the first light-emitting material layer away from the substrate. The lowest unoccupied molecular orbital energy level of the N-type charge layer is greater than the lowest unoccupied molecular orbital energy level of the first electron transport layer.

3. The display panel according to claim 2, wherein, The lowest unoccupied molecular orbital energy level of the N-type charge layer is 0.1 eV to 0.3 eV higher than the lowest unoccupied molecular orbital energy level of the first electron transport layer.

4. The display panel according to claim 2, wherein, The first light-emitting layer further includes a first electron blocking layer disposed between the first light-emitting material layer and the anode. The first light-emitting material layer includes a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The first electron blocking layer includes a first blocking layer, a second blocking layer, and a third blocking layer. The red light-emitting layer is aligned with the first blocking layer, the green light-emitting layer is aligned with the second blocking layer, and the blue light-emitting layer is aligned with the third blocking layer.

5. The display panel according to claim 4, wherein, The first light-emitting layer further includes a first hole-blocking layer disposed between the first light-emitting material layer and the first electron transport layer.

6. The display panel according to claim 1, wherein, The display panel also includes: The second light-emitting layer is disposed on the side of the P-type charge layer away from the substrate. The second light-emitting layer includes a second hole transport layer and a second light-emitting material layer stacked together. The second light-emitting material layer is disposed on the side of the second hole transport layer away from the substrate. The cathode is disposed on the side of the second light-emitting layer opposite to the substrate; The highest occupied molecular orbital energy level of the P-type charge layer is smaller than that of the highest occupied molecular orbital energy level of the second hole transport layer.

7. The display panel according to claim 6, wherein, The highest occupied molecular orbital energy level of the P-type charge layer is 0.1 eV to 0.3 eV lower than the highest occupied molecular orbital energy level of the second hole transport layer.

8. The display panel according to claim 6, wherein, The second light-emitting layer further includes a second electron blocking layer disposed between the P-type charge layer and the second light-emitting material layer; the second light-emitting material layer includes a red sub-light-emitting layer, a green sub-light-emitting layer and a blue sub-light-emitting layer; the second electron blocking layer includes a first sub-blocking layer, a second sub-blocking layer and a third sub-blocking layer; The red sub-light-emitting layer is aligned with the first sub-blocking layer, the green sub-light-emitting layer is aligned with the second sub-blocking layer, and the blue sub-light-emitting layer is aligned with the third sub-blocking layer.

9. The display panel according to claim 8, wherein, The second light-emitting layer further includes a second hole-blocking layer disposed between the second light-emitting material layer and the cathode.

10. The display panel according to claim 1, wherein, The N-type charge layer and the P-type charge layer are uniformly arranged.

11. The display panel according to claim 1, wherein, The N-type charge layer is doped with ytterbium at a mass percentage of 1% to 10%, or with lithium at a mass percentage of 1% to 10%.

12. A display terminal, comprising a display panel, the display panel comprising: substrate; An N-type charge layer is disposed on one side of the substrate; A P-type charge layer is disposed on the side of the N-type charge layer that is away from the substrate; The difference between the lowest unoccupied molecular orbital energy level of the N-type charge layer and the highest occupied molecular orbital energy level of the P-type charge layer is less than or equal to 1.5 eV.

13. The display terminal according to claim 12, wherein, The display panel also includes: An anode is disposed between the substrate and the N-type charge layer; A first light-emitting layer is disposed between the anode and the N-type charge layer. The first light-emitting layer includes a first light-emitting material layer and a first electron transport layer stacked together. The first electron transport layer is disposed on the side of the first light-emitting material layer away from the substrate. The lowest unoccupied molecular orbital energy level of the N-type charge layer is greater than the lowest unoccupied molecular orbital energy level of the first electron transport layer.

14. The display terminal according to claim 13, wherein, The lowest unoccupied molecular orbital energy level of the N-type charge layer is 0.1 eV to 0.3 eV higher than the lowest unoccupied molecular orbital energy level of the first electron transport layer.

15. The display terminal according to claim 13, wherein, The first light-emitting layer further includes a first electron blocking layer disposed between the first light-emitting material layer and the anode. The first light-emitting material layer includes a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The first electron blocking layer includes a first blocking layer, a second blocking layer, and a third blocking layer. The red light-emitting layer is aligned with the first blocking layer, the green light-emitting layer is aligned with the second blocking layer, and the blue light-emitting layer is aligned with the third blocking layer.

16. The display terminal according to claim 12, wherein, The display panel also includes: The second light-emitting layer is disposed on the side of the P-type charge layer away from the substrate. The second light-emitting layer includes a second hole transport layer and a second light-emitting material layer stacked together. The second light-emitting material layer is disposed on the side of the second hole transport layer away from the substrate. The cathode is disposed on the side of the second light-emitting layer opposite to the substrate; The highest occupied molecular orbital energy level of the P-type charge layer is smaller than that of the highest occupied molecular orbital energy level of the second hole transport layer.

17. The display terminal according to claim 16, wherein, The highest occupied molecular orbital energy level of the P-type charge layer is 0.1 eV to 0.3 eV lower than the highest occupied molecular orbital energy level of the second hole transport layer.

18. The display terminal according to claim 16, wherein, The second light-emitting layer further includes a second electron blocking layer disposed between the P-type charge layer and the second light-emitting material layer; the second light-emitting material layer includes a red sub-light-emitting layer, a green sub-light-emitting layer and a blue sub-light-emitting layer; the second electron blocking layer includes a first sub-blocking layer, a second sub-blocking layer and a third sub-blocking layer; The red sub-light-emitting layer is aligned with the first sub-blocking layer, the green sub-light-emitting layer is aligned with the second sub-blocking layer, and the blue sub-light-emitting layer is aligned with the third sub-blocking layer.

19. The display terminal according to claim 12, wherein, The N-type charge layer and the P-type charge layer are uniformly arranged.

20. The display terminal according to claim 12, wherein, The N-type charge layer is doped with ytterbium at a mass percentage of 1% to 10%, or with lithium at a mass percentage of 1% to 10%.

Images