Level signal-based data uploading method and apparatus, device, and medium
Patent Information
- Application Number
- PCT/CN2025/089951
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2025-04-18
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025089951_01102026_PF_FP_ABST
Abstract
Description
A data uploading method, apparatus, device, and medium based on level signals Technical Field
[0001] This invention relates to the field of data transmission, and in particular to a data uploading method, apparatus, device, and medium based on level signals. Background Technology
[0002] In modern industrial control, the Internet of Things (IoT), and many other fields, bus systems, as an important communication architecture, are widely used to realize data transmission and interaction between master modules and multiple slave modules. Slave modules need to upload the collected data to the master module in a timely manner for subsequent processing, analysis, and decision-making. Therefore, an efficient and stable data upload method is crucial for the normal operation of the bus system.
[0003] Currently, in bus systems, slave modules typically upload data to master modules using either a fixed sequence or a polling mechanism. For example, data may be uploaded sequentially according to the slave modules' serial numbers, or the master module may query each slave module individually to see if it has data to upload.
[0004] The fixed sequence and polling methods in the existing technology are not very flexible and cannot make full use of the bus's idle time. In some cases where the data volume of slave modules is large or the data is updated frequently, it will lead to increased data upload delay and reduce the overall efficiency of the system. Summary of the Invention
[0005] This invention provides a data uploading method, apparatus, device, and medium based on level signals. By utilizing level signal arbitration, slave modules compete to upload data according to their numbers and time slots, solving the clock difference synchronization problem, avoiding competition conflicts, simplifying hardware and software design, reducing costs, and improving bus utilization and real-time data uploading performance.
[0006] According to one aspect of the present invention, a data uploading method based on level signals is provided, applied to a bus system, comprising: a master module and a slave module, the method comprising:
[0007] The master module and each slave module monitor the level signal. When the level signal is detected to be in a specified state, the timing function is started to obtain the timer value.
[0008] The competition status of each slave module is determined based on the timer value, which includes successful competition, non-participation in competition, and abandonment of competition;
[0009] In a competitive scenario, the slave module that wins the competition uploads data to the master module via the communication bus.
[0010] Optionally, the method further includes: when there is data in the buffer of the slave module, adjusting the level signal to a specified state through the control pin, wherein the specified state is adjusted from a first level position to a second level position, and then reset after a preset unit time slot.
[0011] Optionally, the contention status of each slave module is determined based on the timer value, including: designating each slave module as a target slave module; determining whether there is data in the buffer of the target slave module; if so, listening to the current level signal through the target slave module and determining the contention status of the target slave module based on the current level signal; otherwise, determining that the target slave module does not participate in the contention.
[0012] Optionally, the contention status of the target slave module is determined based on the current level signal, including: determining the slave upload time slot of the target slave module; determining whether the current level signal is detected to be adjusted from the first level position to the second level position within the slave upload time slot; if so, the contention status of the target slave module is determined to be abandonment of contention; otherwise, the contention status of the target slave module is determined to be successful contention.
[0013] Optionally, determining the slave upload timeslot of the target slave module includes: obtaining the slave number of the target slave module; calculating the product of the slave number and the preset unit timeslot, and using the product as the slave upload timeslot of the target slave module.
[0014] Optionally, in the event of a successful contention, the slave module uploads data to the master module via the communication bus, including: the slave module in the event of a successful contention adjusts the level signal to the second level position through the control pin and uploads its own buffer data to the master module via the communication bus.
[0015] Optionally, after the slave module that wins the competition uploads data to the master module via the communication bus, the method further includes: resetting the level signal to the first level position and clearing the timer value through the slave module that wins the competition, and waiting for a preset unit time slot to start the next round of data upload.
[0016] According to another aspect of the present invention, a data uploading device based on a level signal is provided, the device comprising:
[0017] The level signal monitoring module is used to monitor level signals through the host module and each slave module. When the level signal is detected to be in a specified state, the timing function is started to obtain the timer value.
[0018] The contention status determination module is used to determine the contention status of each slave module based on the timer value. The contention status includes successful contention, non-participation in contention, and abandonment of contention.
[0019] The data upload module is used by the slave module that wins the competition to upload data to the master module via the communication bus.
[0020] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:
[0021] At least one processor;
[0022] and a memory communicatively connected to the at least one processor;
[0023] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform a data uploading method based on a level signal as described in any embodiment of the present invention.
[0024] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement a data uploading method based on a level signal as described in any embodiment of the present invention.
[0025] The technical solution of this invention involves the master module and each slave module monitoring level signals and using timer values to determine the contention status of the slave modules. This allows each slave module to compete for bus access rights at different times, avoiding conflicts caused by multiple slaves uploading data simultaneously and ensuring orderly data uploading. Only the slave module that successfully competes can upload data to the master module, ensuring data transmission accuracy, reducing data transmission error rates, and improving the reliability of system data transmission. By monitoring level signals, upload contention arbitration is achieved, avoiding the need for complex protocols and expensive hardware circuits, effectively solving the bus upload contention problem.
[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 is a flowchart of a data uploading method based on a level signal according to Embodiment 1 of the present invention;
[0029] Figure 2 is a flowchart of another data upload method based on level signals according to Embodiment 1 of the present invention;
[0030] Figure 3 is a flowchart of another data upload method based on level signals according to Embodiment 2 of the present invention;
[0031] Figure 4 is a schematic diagram of a bus system according to Embodiment 2 of the present invention;
[0032] Figure 5 is a schematic diagram of a level signal according to Embodiment 2 of the present invention;
[0033] Figure 6 is a schematic diagram of a data uploading device based on a level signal according to Embodiment 3 of the present invention;
[0034] Figure 7 is a schematic diagram of the structure of an electronic device that implements a data uploading method based on level signals according to an embodiment of the present invention. Detailed Implementation
[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0037] Figure 1 is a flowchart of a data upload method based on level signals provided in Embodiment 1 of the present invention. This embodiment is applicable to a bus system, including a master module and a slave module. The method can be executed by a data upload device based on level signals, which can be implemented in hardware and / or software and can be configured in a computer controller. As shown in Figure 1, the method includes:
[0038] S110: Monitor the level signal through the master module and each slave module. When the level signal is detected to be in a specified state, start the timing function to obtain the timer value.
[0039] It's important to note that in a bus system, both the master and slave modules are connected to the communication bus. Level signals refer to signals generated on the transmission line (TXL), typically represented by high and low levels. The default level is high, indicating no slave module is requesting data upload. Both the master and slave modules have level signal monitoring circuits to detect the bus's level status in real time. When a level signal on the bus is in a specified state—for example, a change from high to low and then back to high—it indicates a potential data upload opportunity or the start of contention. At this point, both the master and slave modules initiate a timing function. This timing function is implemented using a timer circuit, which starts counting when the level signal is detected to be in the specified state, thus acquiring the timer value. It's worth noting that at the hardware level, the timers are integrated into both the master and slave modules. For the master module, the timer determines the start time of data reception, enabling it to enter data reception mode and ensuring that it receives data uploaded by the slave modules in the correct timing sequence, preventing data reception errors or loss. The slave module can use a timer to determine the state of the level signal within the slave upload time slot during the upload contention phase, thereby determining whether the communication bus is idle.
[0040] Specifically, the master module monitors the voltage level signal in real time. Upon detecting a pull-down signal and resetting, it starts timing and enters the data receiving state, receiving data uploaded by the slave module via the communication bus. The signal transceiver end has a buffer area for caching the data to be uploaded, and this buffer area is connected to the communication bus. The slave module monitors the voltage level signal in real time. Upon detecting a pull-down signal and resetting, it starts timing and enters the upload contention phase, deciding whether to upload data based on the contention result.
[0041] Optionally, the method further includes: when there is data in the buffer of the slave module, adjusting the level signal to a specified state through the control pin, wherein the specified state is adjusted from a first level position to a second level position, and then reset after a preset unit time slot.
[0042] It is known that when there is data in the slave module's buffer, it indicates that the slave module has a need to upload the data to the master module, which will trigger the operation of adjusting the level signal.
[0043] Specifically, the slave module adjusts the voltage level signal from a first level position to a second level position via a control pin. The first level position is high, and the second level position is low. Therefore, when the slave module has data to upload from its buffer, it pulls the TXL voltage level signal low. This change in voltage level signals the master module and other slave modules that data needs to be uploaded. Specifically, the slave module's GPIO pin is connected to the TXL pin, operating in open-drain mode, and the TXL voltage level is pulled low by grounding the TXL signal line. Furthermore, after pulling the TXL voltage level signal low, the slave module maintains this low state for a preset time slot. This preset time slot is a fixed duration pre-set by the system, ensuring that other modules have sufficient time to detect the voltage level change. The preset time slot is determined by the MCU performance of both the master and slave modules and the accuracy of the system clock; a preset time slot can be 50μs. During this time, both the master module and other slave modules will detect the change in the TXL voltage level signal and initiate corresponding timing and contention checks.
[0044] Furthermore, after continuously preset unit time slots, the slave module will reset the TXL level signal, that is, restore it to a high level state, so that the bus system returns to its initial state, so that other slave modules can also initiate data upload requests when needed.
[0045] S120. Determine the competition status of each slave module based on the timer value, where the competition status includes successful competition, not participating in competition, and giving up competition.
[0046] In this context, "successful contention" means that if a slave module's buffer contains data and no TXL level signal is detected being pulled down during its upload time slot, it indicates that the communication bus is idle. The slave module successfully competes for the data and can upload the buffer data to the master module via the communication bus by pulling the TXL level signal low through its control pin. "Participating in contention" means that if a slave module's buffer does not contain data, it does not participate in the contention and does not perform any upload operations. "Abandoning contention" means that if a slave module's buffer contains data, but a TXL level signal is detected being pulled down during its upload time slot, it indicates that the communication bus is occupied by another slave module. In this case, the slave module abandons the upload and waits for the next round of contention.
[0047] Figure 2 is a flowchart of a data uploading method based on a level signal provided in Embodiment 1 of the present invention. Step S120 mainly includes the following steps S121 to S127:
[0048] S121. Each slave module is designated as the target slave module.
[0049] Specifically, by treating each slave module as a target slave module, each slave module can be analyzed one by one. Based on the data in its buffer and the monitoring results of the current level signal, the specific situation of the slave module in the data upload contention can be determined.
[0050] S122. Determine if there is data in the buffer of the target slave module. If yes, execute S123-S124; otherwise, execute S127.
[0051] S123. Listen to the current level signal through the target slave module and determine the slave upload time slot of the target slave module.
[0052] Specifically, when data exists in the buffer of the target slave module, the module continuously monitors the current voltage level signal. After detecting that the voltage level signal changes from the first voltage level position to the second voltage level position and resets, the slave module starts timing and determines the corresponding slave upload time slot based on its own slave number. Within the slave upload time slot, it determines whether the communication bus is idle by monitoring the voltage level signal.
[0053] Optionally, determining the slave upload timeslot of the target slave module includes: obtaining the slave number of the target slave module; calculating the product of the slave number and the preset unit timeslot, and using the product as the slave upload timeslot of the target slave module.
[0054] Among them, the slave module number refers to the identification information of the slave module. Each slave module can be numbered sequentially according to its distance from the master module or its functional priority.
[0055] Specifically, the slave module's slave number is multiplied by a preset unit time slot; the product is the target slave module's upload time slot. This can be expressed as: ,in, Indicates the upload timeslot of the target slave module. Indicates the slave number of the target slave module. This indicates the preset unit time slot.
[0056] S124. Determine whether the current level signal has been adjusted from the first level position to the second level position within the slave upload time slot. If yes, execute S125; otherwise, execute S126.
[0057] S125. Determine the contention status of the target slave module and decide to abandon the competition.
[0058] Specifically, if, during the slave upload time slot of the target slave module, the level signal is detected to change from the first level position to the second level position (i.e., from high to low), it indicates that the communication bus has been occupied by another slave module. Other slave modules convey their intention to upload data by adjusting their level signals. At this point, it can be determined that the target slave module has given up the competition. After giving up, the target slave module will not upload data during this upload process but will wait for the next round of competition.
[0059] S126. Determine the contention status of the target slave module as a successful competition.
[0060] Specifically, if no change from high to low level is detected in the slave upload time slot of the target slave module, it indicates that the communication bus is idle. In this case, the contention by the target slave module can be considered successful. The successfully acquired slave module will readjust the level signal via its control pins to declare that it has obtained the right to upload data, and then upload the data in its buffer to the master module via the communication bus.
[0061] S127. Determine that the target slave module does not participate in the competition.
[0062] In one specific implementation, the system includes slave modules A, B, and C. The upload time slots of each slave module are arranged sequentially by number. If slave module A does not detect a low-level signal during its own upload time slot, it indicates the bus is idle, and slave module A's contention status is successful; it then uploads the data from its buffer to the master module. However, if slave module B detects a low-level signal at the beginning of its own upload time slot, it indicates the bus is already occupied by another module, and slave module B's contention status is to give up and wait for the next round. If slave module C's buffer has no data, then slave module C's contention status is not to participate in the contention.
[0063] In summary, the contention mechanism based on level signals and timer values effectively avoids conflicts caused by multiple slave modules uploading data simultaneously. This ensures that only one slave module can upload data at a time, guaranteeing the orderliness and reliability of data transmission in the bus system. Furthermore, the mechanism allowing slave modules to voluntarily relinquish contention further enhances system flexibility and efficiency, avoiding ineffective competition and resource waste.
[0064] S130. In the case of a successful competition, the slave module uploads data to the master module via the communication bus.
[0065] The communication bus is used for data transmission and interaction between the master module and the slave modules. The slave module that successfully competes for the data upload opportunity uploads its buffer data to the master module via the communication bus, serving as the physical carrier of the data transmission. In a competitive scenario, the slave module, after gaining the opportunity to upload data, will upload data to the master module via the communication bus. For example, the slave module encodes the data to be uploaded according to a specified data frame format and then sends it out through the bus. The master module listens for data on the bus; upon receiving the data uploaded by the slave module, it decodes and processes it according to the corresponding protocol, thereby realizing the data upload function.
[0066] Specifically, the communication bus can be an RS-422 bus system, or a full-duplex or half-duplex RS-485 bus system. In serial communication, especially in bus communication protocols like RS-485 and RS-422, data is typically transmitted in frames, with the start and end of a frame identified by start and stop bits. In this case, different slave modules do not share a globally synchronized clock signal, resulting in asynchronous communication. Furthermore, the different physical distances and cable lengths between the slave and master modules can lead to varying propagation delays.
[0067] It is known that clock differences caused by accumulated latency can prevent multiple devices from accurately synchronizing their operations during communication. Due to clock differences, devices may execute prematurely or delayedly, leading to data loss or errors. In scenarios involving multiple slave modules concurrently uploading data, if the clocks of the slave modules are inconsistent, they may miss the correct upload timing, causing multiple devices to send data at the same time, thus triggering data conflicts, increasing system response latency, and reducing system stability and reliability.
[0068] In summary, to address the synchronization issues caused by clock differences, this application employs a "hand-raising" mechanism to guide all slave modules to a unified zero-timeslot state. Specifically, before uploading data, each slave module performs a "hand-raising" action by pulling the TXL level signal low, indicating its readiness to upload data. Even if the clocks of individual slave modules differ, they coordinate using the same level signal, enabling all modules to determine their data upload permission within the same time slot without relying on their individual clocks for synchronization. Through this unified signal scheduling, their upload actions can be effectively ordered and coordinated, thus avoiding contention caused by clock differences.
[0069] The technical solution of this invention involves the master module and each slave module monitoring level signals and using timer values to determine the contention status of the slave modules. This allows each slave module to compete for bus access rights at different times, avoiding conflicts caused by multiple slaves uploading data simultaneously and ensuring orderly data uploading. Only the slave module that successfully competes can upload data to the master module, ensuring data transmission accuracy, reducing data transmission error rates, and improving the reliability of system data transmission. By monitoring level signals, upload contention arbitration is achieved, avoiding the need for complex protocols and expensive hardware circuits, effectively solving the bus upload contention problem.
[0070] Example 2
[0071] Figure 3 is a flowchart of a data upload method based on a level signal provided in Embodiment 2 of the present invention. This embodiment adds a specific process for the slave module, in the case of a successful contention, to upload data to the master module via the communication bus, based on Embodiment 1. The specific content of steps S210-S220 is largely the same as steps S110-S120 in Embodiment 1, and therefore will not be repeated in this embodiment. As shown in Figure 3, the method includes:
[0072] S210: Monitor the level signal through the master module and each slave module. When the level signal is detected to be in a specified state, start the timing function to obtain the timer value.
[0073] Optionally, the method further includes: when there is data in the buffer of the slave module, adjusting the level signal to a specified state through the control pin, wherein the specified state is adjusted from a first level position to a second level position, and then reset after a preset unit time slot.
[0074] S220. Determine the competition status of each slave module based on the timer value, where the competition status includes successful competition, not participating in competition, and giving up competition.
[0075] Optionally, the contention status of each slave module is determined based on the timer value, including: designating each slave module as a target slave module; determining whether there is data in the buffer of the target slave module; if so, listening to the current level signal through the target slave module and determining the contention status of the target slave module based on the current level signal; otherwise, determining that the target slave module does not participate in the contention.
[0076] Optionally, the contention status of the target slave module is determined based on the current level signal, including: determining the slave upload time slot of the target slave module; determining whether the current level signal is detected to be adjusted from the first level position to the second level position within the slave upload time slot; if so, the contention status of the target slave module is determined to be abandonment of contention; otherwise, the contention status of the target slave module is determined to be successful contention.
[0077] Optionally, determining the slave upload timeslot of the target slave module includes: obtaining the slave number of the target slave module; calculating the product of the slave number and the preset unit timeslot, and using the product as the slave upload timeslot of the target slave module.
[0078] S230. In the event of a contention, the slave module that wins the contention adjusts the level signal to the second level position through the control pin and uploads its own buffer data to the master module through the communication bus.
[0079] Specifically, the successfully contested slave module can adjust the signal level to a second low level position via a control pin. By pulling the signal low, it announces to the master module and other slave modules in the bus system that it has acquired the right to upload data and is about to begin uploading. When other modules detect this signal change, they know the bus is already occupied and will not attempt to upload data at this time, avoiding data conflicts. Upon detecting the signal being pulled low again, the master module prepares to receive data, ensuring accurate reception of the data uploaded by the slave module.
[0080] S240. The slave module that wins the competition resets the level signal to the first level position and clears the timer value, waiting for the preset unit time slot to start the next round of data upload.
[0081] As we know, in a bus system, slave modules compete for the right to use the communication bus and upload data to the master module. Once the data upload is complete, the system is restored to its initial contentionable state so that other slave modules with data upload needs can also compete for bus resources.
[0082] Specifically, after successfully uploading data, the slave module that wins the competition will reset the voltage level to the first level position (default state) via its control pin. This indicates that no slave module is currently using the bus for data upload, and the bus is idle and available for other slave modules to compete for. Simultaneously, it will clear the timer value to prepare for the next round of timing, ensuring that the timer restarts from 0 when a voltage level change is detected, accurately calculating the next upload time slot. After the preset time slot has elapsed, the entire system can begin the next round of data upload competition.
[0083] Specific application scenario: Figure 4 is a schematic diagram of a bus system provided in Embodiment 2 of the present invention, including: a master module 1, several slave modules 2, a level signal line TXL 3, and a communication bus 4; the signal transceiver end of the master module 1 is connected to the communication bus 4, and the signal transceiver end of the slave module 2 is provided with a buffer 5, which is connected to the communication bus 4; the level signal line TXL 3 exists in parallel with the communication bus 4 and is connected to the master module 1 and all slave modules 2, and is used to determine the timing and time slot of data upload; the communication bus 4 is used for data transmission and interaction between the master module 1 and the slave modules 2; the buffer 5 is used to buffer the data to be uploaded by the slave modules 2.
[0084] Specifically, Figure 5 is a schematic diagram of a level signal provided in Embodiment 2 of the present invention, showing a duration of 15 time slots. The chart shows the TXL level signal changes. The horizontal axis represents time slots (1 to 15 and subsequent slots omitted) to divide time segments. The vertical axis is divided into two states: H (high level) and L (low level). The arrows indicating the first and second "raise hand" actions signify that the slave module initiated a data upload request. That is, before uploading data, the slave module will pull the TXL level signal low to "raise hand," indicating its readiness to upload data. Time slots 1-3 represent the first stage, where the TXL level signal remains high for an extended period, indicating that no slave module is currently using the bus and no slave module has initiated a "raise hand" request. Time slot 4 marks the first "raise hand" action, after which the TXL level signal is pulled down and returns to its original level. The waiting time is one time slot. Subsequently, the TXL level signal was pulled down again in time slot 6, indicating that slot 1 occupied the communication bus and began uploading data to the host module, lasting for one unit time slot. The two consecutive pull-down signals indicate different actions: the first is a "hand-raising" action, and the second is an upload action, after which a new round of monitoring begins. A third pull-down occurs in time slot 8, indicating the second "hand-raising" action. Time slots 9-11 are the reporting waiting phase. The TXL level signal pulls down in time slots 12-13, indicating that slot 3 has occupied the communication bus and begun uploading data to the host module, lasting for two time slots. Afterwards, the TXL level signal returns to a high level, waiting for the next "raise hand". The slave module performs bus contention arbitration by monitoring the level signal and calculating the waiting time slot length.
[0085] The technical solution of this invention involves the master module and each slave module monitoring level signals and using timer values to determine the contention status of the slave modules. This allows each slave module to compete for bus access rights at different times, avoiding conflicts caused by multiple slaves uploading data simultaneously and ensuring orderly data uploading. Only the slave module that successfully competes can upload data to the master module, ensuring data transmission accuracy, reducing data transmission error rates, and improving the reliability of system data transmission. By monitoring level signals, upload contention arbitration is achieved, avoiding the need for complex protocols and expensive hardware circuits, effectively solving the bus upload contention problem.
[0086] Example 3
[0087] Figure 6 is a schematic diagram of a data upload device based on a level signal provided in Embodiment 3 of the present invention. As shown in Figure 6, the device includes: a level signal monitoring module 310, used to monitor level signals through a host module and each slave module, and to start a timing function to obtain a timer value when the level signal is detected to be in a specified state;
[0088] The contention status determination module 320 is used to determine the contention status of each slave module based on the timer value, wherein the contention status includes successful contention, not participating in contention, and giving up contention;
[0089] The data upload module 330 is used by the slave module that has won the competition to upload data to the master module through the communication bus.
[0090] Optionally, the device further includes: a level signal adjustment module, used to adjust the level signal to a specified state via a control pin when there is data in the buffer of the slave module, wherein the specified state is adjusted from a first level position to a second level position, and reset after a preset unit time slot.
[0091] Optionally, the contention situation determination module 320 is specifically used to: designate each slave module as a target slave module; determine whether there is data in the buffer of the target slave module; if so, listen to the current level signal through the target slave module and determine the contention situation of the target slave module based on the current level signal; otherwise, determine that the contention situation of the target slave module is not to participate in the contention.
[0092] Optionally, the contention situation determination module 320 specifically includes: a contention situation determination unit, used to: determine the slave upload time slot of the target slave module; determine whether the current level signal is detected to be adjusted from the first level position to the second level position within the slave upload time slot; if so, determine that the contention situation of the target slave module is to give up the contention; otherwise, determine that the contention situation of the target slave module is to succeed in the contention.
[0093] Optionally, the competition situation determination unit specifically includes a slave upload time slot determination subunit, used to: obtain the slave number of the target slave module; calculate the product of the slave number and the preset unit time slot, and use the product as the slave upload time slot of the target slave module.
[0094] Optionally, the data upload module 330 is specifically used for: in the event of a successful contention, the slave module adjusts the level signal to the second level position through the control pin and uploads its own buffer data to the master module through the communication bus.
[0095] Optionally, the device also includes a reset module, which, in the event of a contention, after the slave module that has won the contention uploads data to the master module via the communication bus, resets the level signal to the first level position and clears the timer value, and waits for a preset unit time slot to start the next round of data upload.
[0096] The technical solution of this invention involves the master module and each slave module monitoring level signals and using timer values to determine the contention status of the slave modules. This allows each slave module to compete for bus access rights at different times, avoiding conflicts caused by multiple slaves uploading data simultaneously and ensuring orderly data uploading. Only the slave module that successfully competes can upload data to the master module, ensuring data transmission accuracy, reducing data transmission error rates, and improving the reliability of system data transmission. By monitoring level signals, upload contention arbitration is achieved, avoiding the need for complex protocols and expensive hardware circuits, effectively solving the bus upload contention problem.
[0097] The data uploading device based on level signals provided in this embodiment of the invention can execute a data uploading method based on level signals provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the method.
[0098] Example 4
[0099] Figure 7 illustrates a schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.
[0100] As shown in Figure 7, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0101] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0102] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as a data upload method based on level signals.
[0103] In some embodiments, a level-signal-based data uploading method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the level-signal-based data uploading method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform a level-signal-based data uploading method by any other suitable means (e.g., by means of firmware).
[0104] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0105] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0106] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0107] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0108] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.
[0109] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.
[0110] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0111] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A method for uploading data based on a level signal, characterized by, Applied to bus systems, including master modules and slave modules, the methods include: The master module and each slave module monitor the level signal. When the level signal is detected to be in a specified state, the timing function is started to obtain the timer value. The competition status of each slave module is determined based on the timer value, wherein the competition status includes successful competition, not participating in competition, and giving up competition; In a competitive scenario, the slave module that wins the competition uploads data to the master module via the communication bus.
2. The method of claim 1, wherein, The method further includes: When there is data in the slave module's buffer, the level signal is adjusted to a specified state via the control pin. The specified state is adjusted from a first level position to a second level position, and then reset after a preset unit time slot.
3. The method of claim 1, wherein, The step of determining the contention status of each slave module based on the timer value includes: Each slave module is designated as the target slave module. Determine whether there is data in the buffer of the target slave module. If so, listen to the current level signal through the target slave module and determine the contention status of the target slave module based on the current level signal. Otherwise, the target slave module is determined to be not participating in the competition.
4. The method of claim 3, wherein, Determining the contention status of the target slave module based on the current level signal includes: Determine the slave upload time slot of the target slave module; Determine whether the current level signal is detected to have changed from the first level position to the second level position within the slave upload time slot. If so, determine that the target slave module has given up the competition. Otherwise, the competition status of the target slave module is considered a successful competition.
5. The method of claim 4, wherein, The determination of the slave upload time slot of the target slave module includes: Obtain the slave number of the target slave module; Calculate the product of the slave number and the preset unit time slot, and use the product as the slave upload time slot of the target slave module.
6. The method of claim 1, wherein, The competition scenario refers to the slave module that successfully competes for the data upload to the master module via the communication bus, including: In the event of a contention, the slave module that wins the contention adjusts the level signal to the second level position through the control pin and uploads its own buffer data to the master module through the communication bus.
7. The method of claim 6, wherein, After the slave module that wins the competition uploads data to the master module via the communication bus, the method further includes: The slave module that wins the competition resets the level signal to the first level position and clears the timer value, waiting for the preset unit time slot to start the next round of data upload.
8. A level signal based data upload apparatus, characterized by, include: The level signal monitoring module is used to monitor level signals through the host module and each slave module. When the level signal is detected to be in a specified state, the timing function is started to obtain the timer value. The competition status determination module is used to determine the competition status of each slave module based on the timer value, wherein the competition status includes successful competition, not participating in competition, and giving up competition; The data upload module is used by the slave module that wins the competition to upload data to the master module via the communication bus.
9. An electronic device, comprising: The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.
10. A computer storage medium, characterized in that The computer storage medium stores computer instructions that are used to cause a processor to execute the method of any one of claims 1-7.