Scaling analog-to-digital converter based on SAR-SDM hybrid architecture

Abstract

Disclosed in the present invention is a scaling analog-to-digital converter (ADC) based on an SAR-SDM hybrid architecture. The scaling ADC comprises an SAR ADC module, an SDM module, a scaling factor generation module, a five-bit adder, a five-bit subtracter and a data selector, wherein the SAR ADC module is configured to perform quantization and conversion processing on an analog input signal, so as to output a first digital output signal; the scaling factor generation module is configured to generate a five-bit scaling factor; the five-bit adder and the five-bit subtracter are configured to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor, so as to acquire a second digital output signal corresponding to a reference voltage; the SDM module is configured to output a one-bit digital bitstream; and the data selector is configured to perform a data selection and scaling operation on the second digital output signal on the basis of the one-bit digital bitstream, so as to output a final digital output signal. The present invention uses a hybrid architecture of an SAR ADC and an SDM, so as to simplify the design complexity of an ADC, thereby improving the conversion accuracy.

Description

A scaling analog-to-digital converter based on SAR-SDM hybrid structure Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a scaling analog-to-digital converter based on a SAR-SDM hybrid structure. Background Technology

[0002] In real-world physical systems, the efficient digital conversion of continuous analog signals such as temperature, pressure, acoustic vibrations, biometrics, and optical images is a key technological bottleneck for information processing in modern electronic systems. As the core interface between the analog and digital domains, the performance of an analog-to-digital converter (ADC) directly determines the accuracy and energy efficiency of a data acquisition system. In high-resolution applications such as wearable electronics and industrial inspection, traditional single-architecture ADCs face a trade-off between accuracy and power consumption: Sigma-Delta Modulator (SDM) ADCs can improve the signal-to-noise ratio through oversampling and noise shaping techniques, but their high-order architecture carries the risk of nonlinear oscillations; Successive Approximation Register (SAR) ADCs have the advantage of simple structure, but their quantization accuracy is limited by the matching accuracy of the capacitor array. Both of these traditional single-architecture ADCs have corresponding problems, resulting in unsatisfactory analog-to-digital conversion performance. Technical issues

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. Technical solutions

[0004] This invention provides a scaling analog-to-digital converter based on a SAR-SDM hybrid structure, which adopts a hybrid structure of SAR ADC and SDM modulator, simplifying the design of the analog-to-digital converter and improving the conversion accuracy. Beneficial effects

[0005] This invention provides a scaling analog-to-digital converter based on a SAR-SDM hybrid structure. The scaling analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector.

[0006] The input terminal of the SAR ADC module is connected to an analog input signal. The output terminal of the SAR ADC module and the output terminal of the scaling factor generation module are both connected to the input terminals of the five-bit adder and the five-bit subtractor. The output terminals of the five-bit adder and the five-bit subtractor are both connected to the data signal input terminal of the data selector. The output terminal of the SDM modulator module is connected to the control signal input terminal of the data selector. The output terminal of the data selector outputs the final digital output signal.

[0007] The SAR ADC module is used to perform quantization conversion processing on the analog input signal, output a first digital output signal, and transmit the first digital output signal to the first input terminal of the five-bit adder and the first input terminal of the five-bit subtractor.

[0008] The scaling factor generation module is used to generate a five-bit scaling factor and transmit the five-bit scaling factor to the second input terminal of the five-bit adder and the second input terminal of the five-bit subtractor;

[0009] The five-bit adder and five-bit subtractor are used to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor to obtain the second digital output signal corresponding to the reference voltage, and transmit the second digital output signal to the data signal input terminal of the data selector;

[0010] The SDM modulator module is used to output a one-bit digital code stream and transmit it to the control signal input terminal of the data selector;

[0011] The data selector is used to perform data selection scaling operation on the second digital output signal based on the one-bit digital code stream, and output the final digital output signal.

[0012] Furthermore, the SAR ADC module includes a differential capacitor DAC array, a Strong ARM comparator, and a SAR logic unit;

[0013] The input terminal of the differential capacitor DAC array is connected to an analog input signal, the output terminal of the differential capacitor DAC array is connected to the input terminal of the Strong ARM comparator, the output terminal of the Strong ARM comparator is connected to the input terminal of the SAR logic unit, and the output terminal of the SAR logic unit is connected to the differential capacitor DAC array based on a feedback circuit and outputs a first digital output signal.

[0014] Furthermore, the differential capacitor DAC array adopts a binary weighted capacitor array, including a first capacitor array and a second capacitor array. The first capacitor array and the second capacitor array respectively include capacitors C1, C2, C3, C4, C5, and C0, wherein the capacitance ratio of capacitors C1, C2, C3, C4, C5, and C0 is 1:2:4:8:16:1. The upper plate of each capacitor is connected to the input terminal of the Strong ARM comparator, and the lower plate of each capacitor is connected to a phase switch. Except for C0, the lower plate of each capacitor is also connected to an analog input signal and a reference voltage.

[0015] Furthermore, the phase switch is a CMOS switch, which is formed by NMOS and PMOS switches connected in parallel.

[0016] Furthermore, the Strong ARM comparator is a dynamic Strong ARM comparator with an RS latch.

[0017] Furthermore, the SAR logic unit includes an upper-layer D flip-flop group and a lower-layer D flip-flop group. The SAR logic unit performs shift register processing on the output signal of the Strong ARM. The upper-layer D flip-flop group performs shift processing on the comparison result based on the output signal of the Strong ARM comparator. The lower-layer D flip-flop group registers the shift processing result and outputs a first digital output signal of a five-bit digital signal.

[0018] Furthermore, the SAR logic unit performs shift register processing on the output signal of the Strong ARM using the DWA algorithm. The SAR logic unit extracts the 32-bit code generated based on the output signal of the Strong ARM and the 5-bit binary pointer generated based on the analog input signal to generate the DWA algorithm output code, and transmits the DWA algorithm output code to the differential capacitor DAC array through the feedback circuit.

[0019] Furthermore, the SDM modulator module includes a first-stage integrator circuit, a second-stage integrator circuit, and a chopper circuit;

[0020] The input terminal of the chopper circuit is connected to the input voltage, the output terminal of the chopper circuit is connected to the input terminal of the first-stage integrator circuit, the output terminal of the first-stage integrator circuit is connected to the input terminal of the second-stage integrator circuit, and the output terminal of the second-stage integrator circuit outputs a digital code stream to the control signal input terminal of the data selector.

[0021] The first-stage integrator circuit and the second-stage integrator circuit are also equipped with feedback circuits.

[0022] Furthermore, the first-stage integrator circuit includes a first operational amplifier, and the second-stage integrator circuit includes a second operational amplifier. The first and second operational amplifiers are CLADD A / AB fully differential two-stage operational amplifiers.

[0023] Furthermore, the chopper circuit includes a third operational amplifier, two operational amplifiers, a sampling capacitor, an integrating capacitor, and eight sampling switches, wherein four sampling switches are connected to the input terminal of the third operational amplifier, four sampling switches are connected to the output terminal of the third operational amplifier, and the two operational amplifiers, the sampling capacitor, and the integrating capacitor are connected in parallel with the third operational amplifier.

[0024] This invention provides a scaling analog-to-digital converter based on a SAR-SDM hybrid structure. It employs a five-bit SAR ADC and a third-order single-loop one-bit quantization SDM modulator, combining the advantages of high conversion accuracy of SAR ADC and simple structure of SDM modulator. This simplifies the design of the analog-to-digital converter and effectively improves conversion accuracy. The invention uses combinational logic circuits consisting of a five-bit adder, a five-bit subtractor, and a data selector to combine the SAR ADC and SDM modulator structures. This combines the fast conversion characteristics of SAR with the high precision characteristics of SDM, providing a new technical path for solving the synergistic optimization of high resolution and low power consumption. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 is an architecture diagram of a scaling analog-to-digital converter based on a SAR-SDM hybrid structure in an embodiment of the present invention;

[0027] Figure 2 is an architecture diagram of the combinational logic design in an embodiment of the present invention;

[0028] Figure 3 is an architecture diagram of the SAR ADC module in an embodiment of the present invention;

[0029] Figure 4 is an architecture diagram of the differential capacitor DAC array in an embodiment of the present invention;

[0030] Figure 5 is an architecture diagram of the CMOS switch in an embodiment of the present invention;

[0031] Figure 6 is an architecture diagram of the Strong ARM comparator in an embodiment of the present invention;

[0032] Figure 7 is an architecture diagram of the SAR logic unit in an embodiment of the present invention;

[0033] Figure 8 is an architecture diagram of the SDM modulator module in an embodiment of the present invention;

[0034] Figure 9 is an architectural diagram of the integrator circuit in an embodiment of the present invention;

[0035] Figure 10 is a schematic diagram of the architecture of the CLADD A / AB fully differential two-stage operational amplifier in an embodiment of the present invention;

[0036] Figure 11 is a schematic diagram of the switched capacitor common-mode feedback circuit in an embodiment of the present invention;

[0037] Figure 12 is a schematic diagram of the gate voltage bootstrap switch in an embodiment of the present invention;

[0038] Figure 13 is a schematic diagram of the chopper circuit in an embodiment of the present invention;

[0039] Figure 14 is a timing diagram of the chopper circuit in an embodiment of the present invention;

[0040] Figure 15 is an architectural diagram of a five-bit adder and a five-bit subtractor in an embodiment of the present invention;

[0041] Figure 16 is an architecture diagram of a one-bit full adder in an embodiment of the present invention;

[0042] Figure 17 is an architecture diagram of the data selector in Embodiment 1 of the present invention. The best embodiment of the present invention

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In this invention, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, portions or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, figures, steps, behaviors, components, portions or combinations thereof are present or added.

[0045] It should also be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] This invention provides a scaling analog-to-digital converter based on a SAR-SDM hybrid structure. The scaling analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector.

[0047] In an optional implementation of this embodiment, as shown in Figure 1, which illustrates the architecture of a scaling analog-to-digital converter based on a SAR-SDM hybrid structure according to an embodiment of the present invention, the scaling analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector. The input terminal of the SAR ADC module is connected to an analog input signal. The output terminals of the SAR ADC module and the scaling factor generation module are both connected to the input terminals of the five-bit adder and the five-bit subtractor, respectively. The output terminals of the five-bit adder and the five-bit subtractor are both connected to the data signal input terminal of the data selector. The output terminal of the SDM modulator module is connected to the control signal input terminal of the data selector. The output terminal of the data selector outputs the final digital output signal.

[0048] Specifically, the SAR ADC module is used to quantize and convert the analog input signal, output a first digital output signal, and transmit the first digital output signal to the first input terminal of the five-bit adder and the first input terminal of the five-bit subtractor; the scaling factor generation module is used to generate a five-bit scaling factor and transmit the five-bit scaling factor to the second input terminal of the five-bit adder and the second input terminal of the five-bit subtractor; the five-bit adder and the five-bit subtractor are used to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor to obtain a second digital output signal corresponding to the reference voltage, and transmit the second digital output signal to the data signal input terminal of the data selector; the SDM modulator module is used to output a one-bit digital code stream and transmit it to the control signal input terminal of the data selector; the data selector is used to perform data selection scaling operation on the second digital output signal based on the one-bit digital code stream, and output the final digital output signal.

[0049] In an optional implementation of this embodiment, the SAR ADC module, SDM modulator module, scaling factor generation module, five-bit adder, five-bit subtractor, and data selector are connected using a Combine combinational logic design.

[0050] Specifically, as shown in Figure 2, which illustrates the architecture of the combinational logic design in this embodiment of the invention, the first digital output signal SAR<5:1> of the five-bit structure output by the SAR ADC module is transmitted to the first input of the five-bit adder 5-bit ADD and the first input of the five-bit subtractor 5-bit MINUS, respectively. Simultaneously, the five-bit scaling factor M<5:1> generated by the scaling factor generation module is transmitted to the second input of the five-bit adder 5-bit ADD and the second input of the five-bit subtractor 5-bit MINUS. The second input of MINUS, after digital addition and subtraction operations by the five-bit adder and five-bit subtractor, obtains the second digital output signal corresponding to the reference voltage Vref, which is transmitted to the data signal input of the data selector DS. The one-bit digital code stream Select output by the SDM modulator module is transmitted to the control signal input of the data selector DS. The data selector uses the first digital output signal as the processing data. When the one-bit digital code stream Select is the high-bit code stream, it selects the second digital output signal of the five-bit adder. When the one-bit digital code stream Select is the low-bit code stream, it selects the second digital output signal of the five-bit subtractor. This completes the data scaling operation of the SDMF modulator module within the reference voltage Vref range. The data selector outputs the final digital output signal, which serves as the final digital output of the scaling analog-to-digital converter in this embodiment.

[0051] In an optional implementation of this embodiment, as shown in Figure 3, which illustrates the architecture of the SAR ADC module in this embodiment, the SAR ADC module includes a differential capacitor DAC array, a Strong ARM comparator, and a SAR logic unit. The input terminal of the differential capacitor DAC array is connected to an analog input signal, the output terminal of the differential capacitor DAC array is connected to the input terminal of the Strong ARM comparator, the output terminal of the Strong ARM comparator is connected to the input terminal of the SAR logic unit, and the output terminal of the SAR logic unit is connected to the differential capacitor DAC array based on a feedback circuit and outputs a first digital output signal.

[0052] In an optional implementation of this embodiment, the differential capacitor DAC array adopts a binary weighted capacitor array, including a first capacitor array and a second capacitor array. The first capacitor array and the second capacitor array respectively include capacitors C1, C2, C3, C4, C5, and C0, wherein the capacitance ratio of capacitors C1, C2, C3, C4, C5, and C0 is 1:2:4:8:16:1. The upper plate of each capacitor is connected to the input terminal of the Strong ARM comparator, and the lower plate of each capacitor is connected to a phase switch. Except for C0, the lower plate of each capacitor is also connected to an analog input signal and a reference voltage.

[0053] Specifically, as shown in Figure 4, which illustrates the architecture of the differential capacitor DAC array in this embodiment of the invention, the differential capacitor DAC array includes a first capacitor array and a second capacitor array that are symmetrically arranged vertically. The first capacitor array, from left to right, includes capacitors C0, C1, C2, C3, C4, and C5. The capacitance ratio of C0, C1, C2, C3, C4, and C5 is 1:1:2:4:8:16. C1, C2, C3, C4, and C5 are weighted capacitors, and C0 is a redundant capacitor to make up for the full weight. The capacitance values ​​of C0 and C1 are 49 fF, C2 is 49*2 fF, C3 is 49*4 fF, C4 is 49*8 fF, and C5 is 49*16 fF. The structure of the second capacitor array is completely symmetrical to that of the first capacitor array.

[0054] Furthermore, in the first capacitor array, the upper plates of capacitors C0, C1, C2, C3, C4, and C5 are all connected to the positive input terminal of the Strong ARM comparator (CMP). In the second capacitor array, the upper plates of capacitors C0, C1, C2, C3, C4, and C5 are all connected to the inverting input terminal of the Strong ARM comparator (CMP). In both the first and second capacitor arrays, the lower plates of capacitors C0, C1, C2, C3, C4, and C5 are connected to the corresponding phase switches PA and PB. The lower plate of redundant capacitor C0 is also connected to the analog input signal Vin or Vip and the reference voltage Vrefn. The lower plates of capacitors C1, C2, C3, C4, and C5 (excluding redundant capacitor C0) are also connected to the analog input signal Vin or Vip and the reference voltages Vrefn and Vrefp.

[0055] In an optional implementation of this embodiment, the working principle of the differential capacitor DAC array includes: during sampling, the phase is at the sampling phase, the clock signal controls the phase switch PA to close and the phase switch PB to open, and the lower plates of all capacitors are connected to the analog input signal for sampling; after sampling, a comparison operation is performed, the phase is at the comparison phase, the clock signal controls the phase switch PA to open and the phase switch PB to close, and the weighted capacitors other than the redundant capacitors are controlled by the five-bit digital output signal transmitted by the SAR logic unit through the feedback circuit to connect Vrefn or Vrefp respectively, transferring the charge stored in the capacitors to the input terminal of the comparator CMP, completing the conversion of the analog input signal to a level, wherein the redundant capacitors only participate in the sampling operation and do not participate in the comparison operation.

[0056] In an optional implementation of this embodiment, the phase switch is a CMOS switch, which is formed by NMOS and PMOS switches connected in parallel.

[0057] Specifically, as shown in Figure 5, which illustrates the architecture of the CMOS switch in this embodiment of the invention, the CMOS switch consists of an NMOS transistor and a PMOS transistor connected in parallel, sharing a source and drain to form a bidirectional conduction path. The substrate of the PMOS transistor is connected to the power supply, and the substrate of the NMOS transistor is grounded. The gates of the two transistors are connected by complementary signals. and Drive, when High level When the voltage is low, both transistors are conducting, forming a low-resistance path, allowing the signal to pass through; when... Low level, When the signal is high, both transistors are cut off, preventing the signal from passing through.

[0058] Setting a CMOS switch here allows for a wider signal transmission range from power supply to ground, as well as higher on-resistance linearity. Furthermore, since SAR ADC modules have relatively relaxed accuracy requirements, CMOS switches are suitable for use in SAR ADC modules.

[0059] In an optional implementation of this embodiment, the Strong ARM comparator is a dynamic Strong ARM comparator with an RS latch.

[0060] Specifically, in this embodiment, the SDM modulator module of the scaling analog-to-digital converter adopts a 1-bit (i.e., one-bit) quantization structure. Therefore, only one comparator is needed. Since the noise of the quantization comparator is introduced at the end of the ring structure and undergoes third-order shaping, a dynamic comparator is adopted. The circuit structure is simple, the chip area is small, and there is no static power consumption. In this embodiment, a dynamic Strong ARM comparator with an RS latch is adopted.

[0061] An optional implementation of this embodiment is shown in Figure 6, which illustrates the architecture of the Strong ARM comparator in this embodiment. It includes a differential pair: two parallel AND gates and NOT gates connected in series with the corresponding AND gates. Specifically, it includes NMOS devices M0, M1, M2, M3, and M4, and PMOS devices M5 and M6. Its working principle is as follows: when the signal ck is low, the comparator is in a reset state, the differential pair is turned off, and all nodes above the differential pair are pulled to VDD; when the signal ck rises, the current in the differential pair is pulled up and down through the p-node and q-node supports, activating NMOS devices M3 and M4, pulling them down. and At the node, the imbalance of pull-down current from the differential pair is amplified by the positive feedback provided by PMOS devices M5 and M6 until... and When the node goes low, the RS latch is then set to the comparison result, and the comparison result is output.

[0062] In an optional implementation of this embodiment, the SAR logic unit includes an upper-layer D flip-flop group and a lower-layer D flip-flop group. The SAR logic unit performs shift register processing on the output signal of the Strong ARM. The upper-layer D flip-flop group performs shift processing on the comparison result based on the output signal of the Strong ARM comparator. The lower-layer D flip-flop group registers the shift processing result and outputs a first digital output signal of a five-bit digital signal.

[0063] Specifically, as shown in Figure 7, which illustrates the architecture of the SAR logic unit in this embodiment of the invention, the SAR logic unit includes an upper-layer D flip-flop group and a lower-layer D flip-flop group. The D flip-flops with reset and set functions form a five-bit shift register to perform shift register processing on the digital signal output by the Strong ARM comparator. The upper-layer D flip-flop group implements the shift function, and the lower-layer D flip-flop group implements the register function and outputs five-bit digital results: D4, D3, D2, D1, and D0.

[0064] More specifically, its working principle includes: COMP is the output signal of the Strong ARM comparator, pb is the clock signal, and SET is the logic set / unset signal, active high. Outputs D4 to D0 serve as the five-bit digital signal output by the SAR ADC module. During the sampling phase of the SAR ADC module, SET is set to 1, the output of the upper-level most significant bit flip-flop is set to 1, controlling the lower-level most significant bit output D4 to be set to 1, while the remaining bits remain 0, resulting in an output of 10000. The logic circuit determines the final output of D4 based on the comparison result, and this value remains unchanged throughout the current comparison cycle. After the most significant bit comparison is completed, the shift function controls the second most significant bit to be set to 1, resulting in an output of 01000; the comparison result is stored in bit Dn-1. Similarly, the logic circuit controls the switching of the comparison bit length from high to low, completing the shift function.

[0065] In an optional implementation of this embodiment, the SAR logic unit performs shift register processing on the output signal of the Strong ARM using the DWA algorithm. The SAR logic unit extracts a 32-bit code generated based on the output signal of the Strong ARM and a 5-bit binary pointer generated based on the analog input signal to generate a DWA algorithm output code, and transmits the DWA algorithm output code to the differential capacitor DAC array through a feedback circuit.

[0066] Specifically, the SAR logic unit generates a 32-bit code by encoding the output signal of the Strong ARM through a quantizer. The analog input signal, which serves as the original input data, is passed through a modulo-5 adder to generate a 5-bit binary pointer. After being stored in a register, the DWA algorithm output code is generated and transmitted to the differential capacitor DAC array through a feedback circuit, thereby determining the selection of the corresponding capacitor array element.

[0067] The DWA algorithm is used here, which is simple to implement, has a small circuit area, low power consumption, and improves the working efficiency and accuracy of SAR ADC.

[0068] In an optional implementation of this embodiment, as shown in Figure 8, which illustrates the architecture of the SDM modulator module in this embodiment, the SDM modulator module includes a first-stage integrator circuit, a second-stage integrator circuit, and a chopper circuit. The input terminal of the chopper circuit is connected to an input voltage, and the output terminal of the chopper circuit is connected to the input terminal of the first-stage integrator circuit. The output terminal of the first-stage integrator circuit is connected to the input terminal of the second-stage integrator circuit, and the output terminal of the second-stage integrator circuit outputs a one-bit digital code stream to the control signal input terminal of the data selector. The first-stage integrator circuit and the second-stage integrator circuit are also provided with feedback circuits.

[0069] Specifically, the SDM modulator module adopts a third-order CIFF structure, which includes two-stage integrator circuits and chopper circuits, and introduces a feedforward path, i.e., a feedback circuit, which can optimize frequency response or suppress quantization noise.

[0070] In an optional implementation of this embodiment, as shown in Figure 9, which illustrates the architecture of the integrator circuit in this embodiment, the first-stage integrator circuit and the second-stage integrator circuit have the same structure, both being fully differential capacitor integrators. Taking the first-stage integrator circuit as an example, it includes a switch... capacitance And operational amplifiers, their connection relationship is shown in Figure 9.

[0071] Specifically, its working principle includes: all switches in Figure 9 operate under a two-phase non-overlapping clock. Assuming the period of the two-phase non-overlapping clock is T, at the nth cycle... High level yes The delayed signal, therefore and The control switches are all closed; and and If they are opposites, then... It must be a low level, that is The control switch is off. At this time, the integrator operates in the sampling phase, and the sampling capacitor... The total charge on is .exist time, , If it is low, then It must be a high level, therefore and The control switch is off. The control switch is closed. At this time, the integrator is operating in the integrating phase, and the capacitor... During discharge, the charge on the sampling capacitor is transferred to the integrating capacitor. The total charge on the capacitor becomes 0, and the integrating capacitor... The total charge on is In the During each cycle, the circuit operates in the sampling phase, at which time the output voltage becomes... During one period T, the total charge of the integrator is conserved, and the charge transfer equation on the integrator can be expressed as follows: By solving the simultaneous equations and performing a transformation in the z-domain, we can obtain:

[0072] The outputs of the first-stage integrator circuit and the second-stage integrator circuit can be obtained by calculating using the above formula.

[0073] In an optional implementation of this embodiment, the first-stage integrator circuit includes a first operational amplifier, and the second-stage integrator circuit includes a second operational amplifier. The first and second operational amplifiers are CLADD A / AB fully differential two-stage operational amplifiers.

[0074] Specifically, as shown in Figures 10 and 11, Figure 10 shows the architecture diagram of the CLADD A / AB fully differential two-stage operational amplifier in an embodiment of the present invention, and Figure 11 shows the architecture diagram of the switched capacitor common-mode feedback circuit in an embodiment of the present invention. The CLADD A / AB fully differential two-stage operational amplifier includes two stages of operational amplifiers, wherein the first stage is a Class A amplifier and the second stage is a push-pull output stage, and also includes switched capacitor common-mode feedback circuits (vop, vop1), (von, von1), etc. to realize the common-mode feedback function.

[0075] This design employs a CLADD A / AB fully differential two-stage operational amplifier, achieving high gain while maintaining a higher output swing. The push-pull output stage provides higher transconductance efficiency and saves power. The switched-capacitor common-mode feedback circuit offers the advantages of not introducing poles and having no quiescent power consumption.

[0076] In an optional implementation of this embodiment, the sampling switch at the input of the integrator circuit of the SDM modulator module is a gate voltage bootstrap switch.

[0077] Specifically, as shown in Figure 12, which illustrates the architecture of the gate voltage bootstrap switch in this embodiment of the invention, the working principle includes: when the clock signal clk is low (clkn is high), M1 and M7 are turned on, M2 and M9 are turned off, and the two ends of capacitor C1 are connected to VDD and ground respectively for pre-charging. The gate G of the switching transistor M10 is connected to ground through M3 and M4, and the switch is in the off state. Since the gate voltage of M10 will be higher than VDD (but less than twice VDD) during the sampling period, the discharge path needs to be composed of two transistors, M3 and M4. This ensures that during the charge discharge process at node G, the drain-source voltages Vds3 and Vds4 of both transistors will not exceed VDD, thus maintaining a safe operating state. When the clock signal clkn is high (clk is low), M1 and M7 are turned off. At this time, the source voltage of M10 is the input signal Vin, and the voltage at the gate G point is the source voltage plus the voltage VDD pre-stored by capacitor C1, i.e., Vin + VDD. Therefore, the gate-source voltage VGS of M10 is the stored voltage VDD of capacitor C1, which is a constant value. It should be noted that since the voltage on the upper plate of capacitor C1 will exceed VDD during sampling, the substrates of the two PMOS transistors M1 and M2 should be connected to the upper plate of CB, not VDD, to ensure that the circuit remains in a safe operating state.

[0078] Here, a gate-voltage bootstrap switch is used. The gate-voltage bootstrap switch is a common switching structure in high linearity applications. It uses charge pump boost technology to ensure that the gate-source voltage of the switch is constant, thereby ensuring the linearity of the on-resistance. At the sampling switch at the input of the SDM modulator module, high accuracy is required, but the accuracy of the CMOS complementary switch does not meet the requirements. Therefore, a gate-voltage bootstrap switch with better performance and higher accuracy is needed to ensure the accuracy of the sampling switch.

[0079] In an optional implementation of this embodiment, the chopper circuit includes a third operational amplifier, two operational amplifiers, a sampling capacitor, an integrating capacitor, and eight sampling switches. Four sampling switches are connected to the input terminal of the third operational amplifier, four sampling switches are connected to the output terminal of the third operational amplifier, and the two operational amplifiers, the sampling capacitor, and the integrating capacitor are connected in parallel with the third operational amplifier.

[0080] Specifically, as shown in Figure 13, which illustrates the architecture of the chopper circuit in an embodiment of the present invention, the chopper circuit includes a third operational amplifier and a sampling switch. Op-amp sampling integration capacitor The working principle includes: chopper switch Input signal Shifting to an odd frequency of the chopping frequency, and adding the op-amp's inherent 1 / f noise, results in... After being amplified by an operational amplifier, the signal is then switched at the same sampling frequency at the output of the operational amplifier. Chopping, thus turning the signal The original frequency is returned, and the 1 / f noise is chopped to an odd frequency of the chopping frequency. Since the 1 / f noise only goes through one chopping, it only appears at the odd frequency of the chopping frequency. It only needs to pass through a filter to be filtered out. Therefore, the switching chopping technique can effectively remove low-frequency noise.

[0081] Furthermore, as shown in Figure 14, which illustrates the timing diagram of the chopper circuit in this embodiment of the invention, P1 (P1D) represents the timing of the modulator sampling clock, and P2 (P2D) represents the complementary signal. To correspond to the timing of the chopper switch, the operating frequency of the chopper switch circuit is set to half of the system sampling frequency.

[0082] In practical manufacturing processes, the 1 / f noise amplitude introduced by the MOSFET decreases as the frequency increases, and it is a low-frequency noise. Therefore, in order to eliminate the influence of low-frequency 1 / f noise, a switching chopper technique is used at the input of the first-stage integrator of the modulator, which effectively optimizes noise and suppresses offset voltage.

[0083] In an optional implementation of this embodiment, the scaling factor generation module generates a five-bit scaling factor M and transmits it to the input terminals of the five-bit adder and the five-bit subtractor.

[0084] In an optional implementation of this embodiment, as shown in Figure 15, the five-bit adder and five-bit subtractor of this embodiment are composed of five one-bit full adders A1, A2, A3, A4, A5 and five XOR gates MB1, MB2, MB3, MB4, MB5. A and B are two input terminals, S is the output terminal, and M is the control terminal. Figure 16 shows the architecture of a one-bit full adder of this embodiment. When M is low, the overall circuit behaves as a five-bit adder; when M is high, the overall circuit behaves as a five-bit subtractor.

[0085] In an optional implementation of this embodiment, the data selector is a 2-to-1 data selector. Figure 17 shows the architecture diagram of the data selector in Embodiment 1 of the present invention, which consists of two AND gates, one NOT gate and one NOR gate. A is the output signal of the five-bit adder and the five-bit subtractor, B is the input of the five-bit scaling factor, Select is the output signal of the SDM modulator module, and Y is the final digital output signal, realizing the 2-to-1 data selection operation of the one-bit multiplexer.

[0086] In summary, this invention provides a scaling analog-to-digital converter based on a SAR-SDM hybrid structure. It employs a five-bit SAR ADC and a third-order single-loop one-bit quantization SDM modulator, combining the high conversion accuracy of the SAR ADC with the simple structure of the SDM modulator. This simplifies the design of the analog-to-digital converter and effectively improves conversion accuracy. Furthermore, it utilizes combinational logic circuits consisting of a five-bit adder, a five-bit subtractor, and a data selector to integrate the SAR ADC and SDM modulator structures. This combines the fast conversion characteristics of SAR with the high precision characteristics of SDM, providing a new technical path for achieving the synergistic optimization of high resolution and low power consumption.

[0087] The above provides a detailed description of a scaling analog-to-digital converter based on a SAR-SDM hybrid structure provided by the present invention. Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0088] Furthermore, the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A scaling analog-to-digital converter based on a SAR-SDM hybrid structure, characterized in that, The scaling analog-to-digital converter includes a SAR ADC module, an SDM modulator module, a scaling factor generation module, a five-bit adder, a five-bit subtractor, and a data selector. The input terminal of the SAR ADC module is connected to an analog input signal. The output terminal of the SAR ADC module and the output terminal of the scaling factor generation module are both connected to the input terminals of the five-bit adder and the five-bit subtractor. The output terminals of the five-bit adder and the five-bit subtractor are both connected to the data signal input terminal of the data selector. The output terminal of the SDM modulator module is connected to the control signal input terminal of the data selector. The output terminal of the data selector outputs the final digital output signal. The SAR ADC module is used to perform quantization conversion processing on the analog input signal, output a first digital output signal, and transmit the first digital output signal to the first input terminal of the five-bit adder and the first input terminal of the five-bit subtractor. The scaling factor generation module is used to generate a five-bit scaling factor and transmit the five-bit scaling factor to the second input terminal of the five-bit adder and the second input terminal of the five-bit subtractor; The five-bit adder and five-bit subtractor are used to perform digital addition and subtraction operations on the first digital output signal and the five-bit scaling factor to obtain the second digital output signal corresponding to the reference voltage, and transmit the second digital output signal to the data signal input terminal of the data selector; The SDM modulator module is used to output a one-bit digital code stream and transmit it to the control signal input terminal of the data selector; The data selector is used to perform data selection scaling operation on the second digital output signal based on the one-bit digital code stream, and output the final digital output signal.

2. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 1, characterized in that, The SAR ADC module includes a differential capacitor DAC array, a Strong ARM comparator, and a SAR logic unit; The input terminal of the differential capacitor DAC array is connected to an analog input signal, the output terminal of the differential capacitor DAC array is connected to the input terminal of the Strong ARM comparator, the output terminal of the Strong ARM comparator is connected to the input terminal of the SAR logic unit, and the output terminal of the SAR logic unit is connected to the differential capacitor DAC array based on a feedback circuit and outputs a first digital output signal.

3. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 2, characterized in that, The differential capacitor DAC array employs a binary weighted capacitor array, comprising a first capacitor array and a second capacitor array. The first and second capacitor arrays respectively include capacitors C1, C2, C3, C4, C5, and C0, wherein the capacitance ratio of capacitors C1, C2, C3, C4, C5, and C0 is 1:2:4:8:16:

1. The upper plate of each capacitor is connected to the input terminal of the Strong ARM comparator, and the lower plate of each capacitor is connected to a phase switch. Except for C0, the lower plate of each capacitor is also connected to an analog input signal and a reference voltage.

4. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 3, characterized in that, The phase switch is a CMOS switch, which is formed by NMOS and PMOS switches connected in parallel.

5. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 2, characterized in that, The Strong ARM comparator is a dynamic Strong ARM comparator with an RS latch.

6. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 2, characterized in that, The SAR logic unit includes an upper-level D flip-flop group and a lower-level D flip-flop group. The SAR logic unit performs shift register processing on the output signal of the Strong ARM. The upper-level D flip-flop group performs shift processing on the comparison result based on the output signal of the Strong ARM comparator. The lower-level D flip-flop group registers the shift processing result and outputs a first digital output signal of a five-bit digital signal.

7. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 6, characterized in that, The SAR logic unit performs shift register processing on the output signal of the Strong ARM using the DWA algorithm. The SAR logic unit extracts a 32-bit code generated based on the output signal of the Strong ARM and a 5-bit binary pointer generated based on the analog input signal to generate the DWA algorithm output code, and transmits the DWA algorithm output code to the differential capacitor DAC array through a feedback circuit.

8. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 1, characterized in that, The SDM modulator module includes a first-stage integrator circuit, a second-stage integrator circuit, and a chopper circuit. The input terminal of the chopper circuit is connected to the input voltage, the output terminal of the chopper circuit is connected to the input terminal of the first-stage integrator circuit, the output terminal of the first-stage integrator circuit is connected to the input terminal of the second-stage integrator circuit, and the output terminal of the second-stage integrator circuit outputs a digital code stream to the control signal input terminal of the data selector. The first-stage integrator circuit and the second-stage integrator circuit are also equipped with feedback circuits.

9. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 8, characterized in that, The first-stage integrator circuit includes a first operational amplifier, and the second-stage integrator circuit includes a second operational amplifier. The first and second operational amplifiers are CLADD A / AB fully differential two-stage operational amplifiers.

10. The scaling analog-to-digital converter based on a SAR-SDM hybrid structure as described in claim 8, characterized in that, The chopper circuit includes a third operational amplifier, two operational amplifiers, a sampling capacitor, an integrating capacitor, and eight sampling switches. Four sampling switches are connected to the input terminal of the third operational amplifier, four sampling switches are connected to the output terminal of the third operational amplifier, and the two operational amplifiers, the sampling capacitor, and the integrating capacitor are connected in parallel with the third operational amplifier.

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