Split-type physiological electrical signal measurement method and system, and medium

Abstract

Disclosed are a split-type physiological electrical signal measurement method and system. The method comprises the following steps: separately integrating a main hardware module and an accessory hardware module into a split-type device; the accessory hardware module collecting a first physiological electrical signal, and performing first amplification processing and first digital-to-analog conversion processing to obtain a first digital signal; performing first preliminary processing on the first digital signal to obtain first data, and storing same according to a collection sequence; generating a timestamp to mark a collection time of the first data; and transmitting the first data with the timestamp to the main hardware module, so as to trigger the main hardware module to execute the following steps: aligning the first data on the basis of the timestamp; collecting a second physiological electrical signal, and performing second amplification processing and second digital-to-analog conversion processing to obtain a second digital signal; performing second preliminary processing on the second digital signal to obtain second data, and using the second data as a reference signal; and performing synthesis and restoration on the second data and the first data.

Description

A split-type physiological electrical signal measurement method, system and medium Technical Field

[0001] This invention relates to the field of brain-computer interface technology, and in particular to a split-type physiological electrical signal measurement method, system, and medium. Background Technology

[0002] Physiological electrical signals, such as electrocardiogram (ECG), electromyography (EMS), and electroencephalography (EEG), play an important role in health monitoring and disease diagnosis. Traditional physiological electrical signal measurement devices are usually integrated designs, which have problems such as large size, inconvenience in wearing, and limited signal acquisition range, making it difficult to meet users' needs for portability and multi-scenario applications.

[0003] In existing technologies, the design of split-type devices is gradually gaining attention, such as the combination of split charging cases with earphones, head-mounted devices, etc. However, these devices still have limitations in the measurement of physiological electrical signals. Existing technologies usually rely on a single device for signal acquisition and lack an effective distributed measurement mechanism for reference potential electrodes and data potential electrodes, resulting in insufficient accuracy and completeness of signal acquisition.

[0004] In other words, existing methods for measuring physiological electrical signals have the problem of poor user experience. Summary of the Invention

[0005] The main objective of this invention is to provide a split-type physiological electrical signal measurement method, system, and medium, aiming to solve the technical problem of poor user experience in existing physiological electrical signal measurement methods.

[0006] To achieve the above objectives, the present invention provides a split-type physiological electrical signal measurement method, which includes the following steps:

[0007] The main hardware module is connected to the auxiliary hardware module via wired or wireless means, and is connected to an external data processing terminal via wireless communication; the main hardware module and the auxiliary hardware module are respectively integrated into a split device;

[0008] The auxiliary hardware module performs the following steps:

[0009] The first physiological electrical signal is acquired and subjected to the first amplification process and the first digital-to-analog conversion process to obtain the first digital signal;

[0010] The first digital signal undergoes preliminary processing to obtain the first data, which is then stored according to the acquisition sequence.

[0011] Generate a timestamp to mark the time when the first data was collected;

[0012] The first data, with a timestamp, is transmitted to the main hardware module to trigger the main hardware module to perform the following steps:

[0013] Align the first data based on the timestamp;

[0014] The second physiological electrical signal is acquired and subjected to a second amplification and a second digital-to-analog conversion to obtain a second digital signal;

[0015] The second digital signal undergoes a second preliminary processing to obtain second data, which is then used as a reference signal.

[0016] The second data is synthesized and restored with the first data to obtain a complete physiological electrical signal data sequence, which is then transmitted to an external data processing terminal.

[0017] Optionally, after the main hardware module is connected to the auxiliary hardware module via wired or wireless means, the main hardware module calibrates and synchronizes the clock of the auxiliary hardware module, which includes at least the following steps:

[0018] The main hardware module sends multiple RTC sub-second time data packets to the auxiliary hardware module;

[0019] The auxiliary hardware module calculates the average latency difference based on the difference between the reception time and the transmission time of each data packet;

[0020] The auxiliary hardware module calibrates its local clock based on the difference between the current clock time of the main hardware module and the link delay.

[0021] Optionally, during the process of synthesizing and restoring the second data with the first data, if there are data errors or omissions in the physiological electrical signal sequence, data is inserted according to the zero-padding principle.

[0022] Optionally, the connection status between the main hardware module and the auxiliary hardware module can be monitored through one or more detection methods, such as data, electrical interface, or mechanical triggering mechanism.

[0023] Optionally, the data detection method specifically involves heartbeat packet detection or serial port interrupt detection via a wired interface to monitor the connection status between the main hardware module and the auxiliary hardware module.

[0024] Electrical interface detection methods include monitoring the connection status between the main hardware module and the auxiliary hardware module through one of the following: voltage detection circuit, current detection circuit, or power management circuit.

[0025] The specific detection method of the trigger mechanism is to monitor the connection status between the main hardware module and the auxiliary hardware module through mechanical switches, Hall sensor groups or specific optoelectronic transceiver modules.

[0026] Optionally, when the main hardware module is connected to the auxiliary hardware module via a wired connection, the auxiliary hardware module and the main hardware module do not need to communicate during the physiological electrical signal acquisition process. After the first physiological electrical signal acquisition is completed and reconnected, the auxiliary hardware module transmits the first data with a timestamp to the main hardware module.

[0027] When the main hardware module connects to the auxiliary hardware module wirelessly, data is transmitted in real time.

[0028] Optionally, during real-time data transmission, the first data transmitted by the auxiliary hardware module has an ID sequence;

[0029] When the sequence is not misaligned, the main hardware module directly inputs the first data received to the digital-to-analog converter for digital-to-analog conversion, and then inputs the digital-to-analog conversion result into the operational amplifier to sum with the reference signal before inputting it into the analog-to-digital converter for analog-to-digital conversion.

[0030] When a sequence error or packet loss occurs, subsequent incoming data packets are stored in a buffer and wait for a preset time. If the expected sequence packet is received during the waiting period, it is directly input into a digital-to-analog converter for digital-to-analog conversion. The digital-to-analog conversion result is then input into an operational amplifier and summed with a reference signal before being input into an analog-to-digital converter for analog-to-digital conversion. Otherwise, the data packet with the smallest sequence number in the buffer is input into a digital-to-analog converter for digital-to-analog conversion. The digital-to-analog conversion result is then input into an operational amplifier and summed with a reference signal before being input into an analog-to-digital converter for analog-to-digital conversion.

[0031] Optionally, during real-time data transmission, the first data transmitted by the auxiliary hardware module has an ID sequence and is aligned with a timestamp;

[0032] When the sequence is not misaligned, the main hardware module directly inputs the first data received at the moment and the reference signal aligned with the corresponding timestamp into the digital-to-analog converter for digital-to-analog conversion. Then, the digital-to-analog conversion result is input into the operational amplifier for summation and then input into the analog-to-digital converter for analog-to-digital conversion.

[0033] When a sequence error or packet loss occurs, subsequent incoming data packets are stored in a buffer and wait for a preset time. If the expected sequence packet is received during the waiting period, the reference signal aligned with its corresponding timestamp is directly input into the digital-to-analog converter for digital-to-analog conversion. The digital-to-analog conversion result is then input into an operational amplifier for summation and finally input into an analog-to-digital converter for analog-to-digital conversion. Otherwise, the data packet with the smallest sequence number in the buffer is directly input into the digital-to-analog converter for digital-to-analog conversion along with its corresponding timestamp. The digital-to-analog conversion result is then input into an operational amplifier for summation and finally input into an analog-to-digital converter for analog-to-digital conversion.

[0034] Corresponding to the aforementioned split-type physiological electrical signal measurement method, the present invention provides a split-type physiological electrical signal measurement system, which includes:

[0035] The device includes a main hardware module and at least one auxiliary hardware module; wherein the main hardware module and the auxiliary hardware module are respectively integrated in a split device, the main hardware module is connected to the auxiliary hardware module via wired or wireless means, and is connected to an external data processing terminal via wireless communication.

[0036] The auxiliary hardware module is used to acquire a first physiological electrical signal, perform a first amplification process and a first digital-to-analog conversion process to obtain a first digital signal; perform a first preliminary processing on the first digital signal to obtain first data, and store it according to the acquisition order; generate a timestamp to mark the acquisition time of the first data; and transmit the first data with the timestamp to the main hardware module.

[0037] The main hardware module is used to align the first data based on the timestamp; acquire the second physiological electrical signal, and perform the second amplification and second digital-to-analog conversion to obtain the second digital signal; perform the second preliminary processing on the second digital signal to obtain the second data as a reference signal; synthesize and restore the second data with the first data to obtain a complete physiological electrical signal data sequence and transmit it to an external data processing terminal.

[0038] In addition, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a split-type physiological electrical signal measurement program, which, when executed by a processor, implements the steps of the split-type physiological electrical signal measurement method as described above.

[0039] The beneficial effects of this invention are:

[0040] (1) Compared with the prior art, the present invention realizes the distributed acquisition and synthesis restoration of physiological electrical signals through the design of a split hardware module. Through distributed measurement and signal synchronization processing, it can be flexibly applied to various split devices, such as TWS earphones and wearable devices, which improves the versatility and applicability of physiological electrical signal measurement devices. At the same time, through timestamp alignment and synthesis restoration of reference signals, the accuracy and reliability of physiological electrical signal measurement are improved, which effectively improves the user experience.

[0041] (2) Compared with the prior art, the present invention ensures time synchronization between the main hardware module and the auxiliary hardware module by calibrating the clock of the auxiliary hardware module through the main hardware module, thereby improving the accuracy of data alignment, reducing measurement errors caused by time deviation, and further improving the accuracy of physiological electrical signal measurement.

[0042] (3) Compared with the prior art, the present invention adopts the zero-padding principle to handle data errors and omissions when synthesizing and restoring physiological electrical signal data sequences. This can effectively avoid the impact of missing data on measurement results, ensure the integrity and continuity of physiological electrical signal data, and improve the availability of data.

[0043] (4) Compared with the prior art, the present invention monitors the connection status of the main hardware module and the auxiliary hardware module through multiple detection methods, which can determine the connection status of the two in a timely and accurate manner, thereby triggering the corresponding data acquisition and processing process, avoiding unnecessary power consumption in the non-acquisition state, and improving the energy utilization efficiency of the system.

[0044] (5) Compared with the prior art, the present invention reconnects the auxiliary hardware module after data acquisition and then transmits the data in the wired connection mode, and transmits the data in real time in the wireless connection mode. This flexible data transmission mode can meet the needs of different application scenarios and improve the flexibility and applicability of the system.

[0045] (6) Compared with the prior art, the present invention manages and processes data packets through ID sequence during real-time data transmission. When errors or missing packets occur in the sequence, a buffering and waiting mechanism is adopted to ensure the order and integrity of data transmission, improve the reliability of data transmission, and further guarantee the accuracy of physiological electrical signal measurement.

[0046] (7) Compared with the prior art, the present invention further considers timestamp alignment when processing data packets, so that the data can maintain time consistency better during transmission and processing, further improving the accuracy and reliability of physiological electrical signal data, and providing a higher quality data foundation for subsequent data analysis and processing. Attached Figure Description

[0047] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0048] Figure 1 is a simplified flowchart of an embodiment of the split-type physiological electrical signal measurement method of the present invention;

[0049] Figure 2 is a schematic diagram of two embodiments of the present invention in which the main hardware module and the auxiliary hardware module are respectively integrated in a split device;

[0050] Figure 3 is a schematic diagram of an embodiment of the hardware module of the present invention;

[0051] Figure 4 is a schematic diagram of an embodiment of the main hardware module of the present invention;

[0052] Figure 5 is a schematic diagram of another embodiment of the main hardware module of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] As shown in Figure 1, a split-type physiological electrical signal measurement method of the present invention includes the following steps:

[0055] The main hardware module is connected to the auxiliary hardware module via wired or wireless means, and is connected to an external data processing terminal via wireless communication; the main hardware module and the auxiliary hardware module are respectively integrated into a split device;

[0056] The auxiliary hardware module performs the following steps:

[0057] The first physiological electrical signal is acquired and subjected to the first amplification process and the first digital-to-analog conversion process to obtain the first digital signal;

[0058] The first digital signal undergoes preliminary processing to obtain the first data, which is then stored according to the acquisition sequence.

[0059] Generate a timestamp to mark the time when the first data was collected;

[0060] The first data, with a timestamp, is transmitted to the main hardware module to trigger the main hardware module to perform the following steps:

[0061] Align the first data based on the timestamp;

[0062] The second physiological electrical signal is acquired and subjected to a second amplification and a second digital-to-analog conversion to obtain a second digital signal;

[0063] The second digital signal undergoes a second preliminary processing to obtain second data, which is then used as a reference signal.

[0064] The second data is synthesized and restored with the first data to obtain a complete physiological electrical signal data sequence, which is then transmitted to an external data processing terminal.

[0065] In this embodiment, when the main hardware module is connected to the auxiliary hardware module via a wired connection, the synthesis and restoration of the second data and the first data is specifically a distributed data restoration and synthesis. When the main hardware module is connected to the auxiliary hardware module via a wireless connection, the synthesis and restoration of the second data and the first data is specifically a near-real-time data restoration and synthesis. Near-real-time data restoration and synthesis refers to real-time data acquisition during use, where the two modules transmit data, synthesize the data in the main hardware module, and then transmit the complete physiological electrophysiological signal data sequence to an external data processing terminal (such as a mobile phone) and display the waveform within a certain time delay. Distributed data restoration and synthesis reduces the data transmission between the two hardware modules during use. Data synthesis can be performed after the two hardware modules are assembled together. In this case, the synthesized data is transmitted and applied only after the external data processing terminal establishes a connection with the hardware module.

[0066] This invention achieves distributed acquisition and synthesis of physiological electrical signals through a split hardware module design. Distributed measurement and synchronous signal processing enable flexible application in various split devices, such as TWS earphones and wearable devices (see Figure 2 for a schematic diagram of two embodiments where the main hardware module and auxiliary hardware module are integrated into a split device). This improves the versatility and applicability of the physiological electrical signal measurement device. Furthermore, through timestamp alignment and reference signal synthesis, the accuracy and reliability of physiological electrical signal measurement are enhanced, effectively improving the user experience.

[0067] In this embodiment, after the main hardware module is connected to the auxiliary hardware module via wired or wireless means, the main hardware module calibrates and synchronizes the clock of the auxiliary hardware module, which includes at least the following steps:

[0068] The main hardware module sends multiple RTC sub-second time data packets to the auxiliary hardware module;

[0069] The auxiliary hardware module calculates the average latency difference based on the difference between the reception time and the transmission time of each data packet;

[0070] The auxiliary hardware module calibrates its local clock based on the difference between the current clock time of the main hardware module and the link delay.

[0071] In this embodiment, the auxiliary hardware module calibrates its local clock based on the difference between the current clock time of the main hardware module and the link delay. Specifically, the auxiliary hardware module T... Si Set the clock to: Among them, T Si This represents the i-th auxiliary hardware module. Indicates the current clock time of the main hardware module. This represents the average latency difference, and σ is the system time error compensation coefficient of the auxiliary hardware module itself.

[0072] Furthermore, it is also possible to determine whether to re-perform the time calibration process by calculating the standard deviation between the difference between the reception time and the transmission time of each data packet and the fixed parameter, as well as the degree of deviation between the current standard error and the historical standard error records.

[0073] Preferably, during periods when the physiological electrical signal acquisition function is inactive (e.g., after the auxiliary hardware module has just completed its acquisition work and is physically connected to the main hardware module), the two communicate directly via a wired serial port to calibrate and synchronize the clock of the auxiliary hardware module through the main hardware module (if the main hardware module requires an external data processing terminal to synchronize its clock, this clock synchronization is asynchronous with the synchronization clock operations of the main and auxiliary hardware modules and has no sequential relationship).

[0074] When the clock synchronization function is triggered, the main hardware module and all auxiliary hardware modules record the clock time at the trigger moment as the trigger moment point, and the difference between the two is ΔTP = TP. S -TP P It can be used to correct the difference between the main hardware module and the auxiliary hardware module, where TP S For the trigger point of the auxiliary hardware module, TP P This is the trigger point for the main hardware module.

[0075] One example is in the scenario where the electrical interface monitors the connection status of the main hardware module and the auxiliary hardware module. The main hardware module adds an offset of |ΔTP| to the first data received by the auxiliary hardware module or the second physiological electrical signal acquired locally, or truncates the first ΔTP part of the corresponding data before synchronously inputting it into the digital-to-analog converter, based on the sign of ΔTP.

[0076] Another example involves performing first-level digital signal pattern recognition on the synthesized physiological electrical signal data sequence to determine its peaks, troughs, and other time-frequency domain features and statistical characteristics. The identified signal features are then compared with a general model (a physiological electrical signal feature model applicable to most people, representing the physiological electrical signal characteristics of the general population) or a personalized model (a physiological electrical signal feature model for a specific individual, considering individual differences). If the synthesized data deviates significantly from the general model or the personalized model corresponding to the object being collected, such as a statistical deviation where the standard deviation / mean of the peak sequence extreme values ​​differs from the general model by more than a threshold, or a deviation from the personal model by more than a threshold, or a visual detection model having less effective data than a threshold, the data is deemed to need reprocessing. In this case, the offset reference value to be applied is ΔTP.

[0077] Another example is based on no offset, ΔTP, each time. or multiple times After calculating the offset based on the derived migration probability, multiple sets of data are generated through the circuit, and then the best data is selected as the offset based on the data quality.

[0078] This invention ensures time synchronization between the main hardware module and the auxiliary hardware module by calibrating the clock of the main hardware module, thereby improving the accuracy of data alignment, reducing measurement errors caused by time deviation, and further improving the accuracy of physiological electrical signal measurement.

[0079] In this embodiment, the auxiliary hardware module generates timestamps as follows: when the auxiliary hardware module and the main hardware module are determined to be in a separated state, the separation time is used as the origin time, and physiological electrical signals are collected separately. The physiological electrical signals entering the analog-to-digital converter (ADC) from the analog circuit are timestamped and sorted according to the sampling frequency and data order. In this embodiment, after the auxiliary hardware module and the main hardware module reconnect, the first data point of the two data strings is the origin for aligning the two sets of data.

[0080] In another embodiment, the auxiliary hardware module generates timestamps by: after the auxiliary hardware module and the main hardware module determine separation, they begin collecting physiological electrical signals according to local real-time times, and timestamp and sort the physiological electrical signals entering the analog-to-digital converter from the analog circuit according to the data order based on the sampling frequency. In this embodiment, after the auxiliary hardware module and the main hardware module reconnect, the alignment point of the two data strings is the sequential data with the same specific timestamp.

[0081] In this embodiment, during the process of synthesizing and restoring the second data with the first data, if there are data errors or omissions in the physiological electrical signal sequence, data is inserted according to the zero-padding principle.

[0082] This invention employs a zero-padding principle to handle data errors and omissions when synthesizing and restoring physiological electrical signal data sequences. This effectively avoids the impact of missing data on measurement results, ensures the integrity and continuity of physiological electrical signal data, and improves data usability.

[0083] In this embodiment, the connection status between the main hardware module and the auxiliary hardware module is monitored through one or more detection methods, including data, electrical interface, or mechanical triggering mechanism.

[0084] In this embodiment, the data detection method specifically involves monitoring the connection status between the main hardware module and the auxiliary hardware module via heartbeat packet detection or serial port interrupt detection through a wired interface. Specifically, heartbeat packet detection is performed via a wired interface such as pogopin, with the main hardware module and the auxiliary hardware module periodically sending heartbeat packets (low data volume). After the main hardware module or the auxiliary hardware module sends a heartbeat packet, the auxiliary hardware module or the main hardware module (if the heartbeat packet was sent by the main hardware module, then the auxiliary hardware module replies with an acknowledgment packet; if the heartbeat packet was sent by the auxiliary hardware module, then the main hardware module replies with an acknowledgment packet) should reply with an acknowledgment packet within a specified time. If the module sending the heartbeat packet does not receive an acknowledgment packet after multiple attempts, the connection is considered to be broken.

[0085] Alternatively, in another embodiment, another instance of wired connection interrupt detection specifically involves configuring a serial port interrupt in the MCU, which is triggered when data is received. If no interrupt is triggered within a certain period and there is no other communication activity, the connection may be considered broken.

[0086] In this embodiment, the electrical interface detection method includes monitoring the connection status between the main hardware module and the auxiliary hardware module through one of a voltage detection circuit, a current detection circuit, or a power management circuit.

[0087] Voltage detection circuit: When the connection is normal, the voltage across the pogo pin should remain within a certain normal range; when the connection is broken, the voltage will change significantly (e.g., become 0V or approach the power supply voltage). Therefore, this voltage value can be periodically read using an ADC (analog-to-digital converter) module in the MCU. Once an abnormal voltage change is detected, it can be determined that the connection has been broken.

[0088] Current detection circuit: If current flows between the main hardware module and the auxiliary hardware module, a small resistor can be connected in series on the connection line. The presence of current can be determined by detecting the voltage drop across the resistor. When the connection is broken, the current will suddenly drop to 0, and the MCU can determine the connection status by detecting the change in voltage drop.

[0089] Power management circuit: If there is a charging relationship between the main hardware module and the auxiliary hardware module, the MCU can monitor the voltage changes of the power management circuit or IC to confirm the on / off state.

[0090] In this embodiment, the specific detection method of the mechanism triggering mechanism is to monitor the connection status between the main hardware module and the auxiliary hardware module through a mechanical switch, a Hall sensor group, or a specific optoelectronic transceiver module.

[0091] Mechanical switches: These switches trigger the on / off state of the corresponding circuits through actions such as pressing and popping, thereby determining the on / off status of the main hardware module and the auxiliary hardware module.

[0092] Hall sensor array: Detects whether the main hardware module and the auxiliary hardware module are in the predetermined relative position. If they are not in the predetermined relative position, it is determined that the main hardware module and the auxiliary hardware module are in a separate state, thereby triggering the next state change judgment of the main hardware module or the auxiliary hardware module.

[0093] Specific optoelectronic transceiver module: The receiver group deployed on the main hardware module transmitter and receiver, as well as the auxiliary hardware module, determines the next state change of the main hardware module or auxiliary hardware module by the change of light intake at a specific frequency.

[0094] This invention monitors the connection status between the main hardware module and the auxiliary hardware module through multiple detection methods, which can determine the connection status in a timely and accurate manner, thereby triggering the corresponding data acquisition and processing flow, avoiding unnecessary power consumption in the non-acquisition state, and improving the energy utilization efficiency of the system.

[0095] In this embodiment, when the main hardware module is connected to the auxiliary hardware module via a wired connection, the auxiliary hardware module and the main hardware module do not need to communicate during the physiological electrical signal acquisition process. After the first physiological electrical signal acquisition is completed and reconnected, the auxiliary hardware module transmits the first data with a timestamp to the main hardware module.

[0096] When the main hardware module connects to the auxiliary hardware module wirelessly, data is transmitted in real time.

[0097] In this embodiment, when the main hardware module and the auxiliary hardware module communicate wirelessly (such as via Bluetooth), during periods when the physiological electrical signal acquisition function is inactive (e.g., after the auxiliary hardware module has just finished working and is physically connected to the main hardware module), the main hardware module and the auxiliary hardware module are generally in a power-saving mode. The connection status between the two is monitored through one or more detection methods, such as data, electrical interface, or mechanical triggering mechanism.

[0098] In power-saving mode, the synchronization between the main hardware module and the auxiliary hardware module can further reduce power consumption by reducing the frequency of energy saving features.

[0099] Preferably, the energy-saving features include at least one or more of the following: increasing the connection interval, setting the slave latency to 0-499, increasing the supervision timeout, modifying the advertising interval, performing LE power control (TX power level), using a lazy timer to reduce the number of MCU wake-ups, and the device stack entering deep sleep modes (such as EM2 mode). Specifically, the connection interval can be increased from 7.5ms to 4s.

[0100] This invention allows for flexible data transmission by using a wired connection where the auxiliary hardware module reconnects and transmits data after data acquisition, and a wireless connection where data is transmitted in real time. This flexible data transmission method can meet the needs of different application scenarios and improve the system's flexibility and applicability.

[0101] In this embodiment, during real-time data transmission, the first data transmitted by the auxiliary hardware module has an ID sequence. When the sequence is not misaligned, the main hardware module directly inputs the currently received first data into the digital-to-analog converter for digital-to-analog conversion, and then inputs the digital-to-analog conversion result into the operational amplifier to sum with the reference signal before inputting it into the analog-to-digital converter for analog-to-digital conversion.

[0102] When a sequence error or packet loss occurs (e.g., k+1 is expected, but k+2, k+3, etc., arrive before the expected sequence), subsequent data packets are stored in a buffer and wait for a preset time. If the expected sequence packet is received during the waiting period, it is directly input into a digital-to-analog converter for digital-to-analog conversion. The result of the digital-to-analog conversion is then input into an operational amplifier and summed with a reference signal before being input into an analog-to-digital converter for analog-to-digital conversion. Otherwise, the data packet with the smallest sequence number in the buffer is input into the digital-to-analog converter for digital-to-analog conversion. The result of the digital-to-analog conversion is then input into an operational amplifier and summed with a reference signal before being input into an analog-to-digital converter for analog-to-digital conversion.

[0103] This invention manages and processes data packets using ID sequences during real-time data transmission. When errors or missing packets occur in the sequence, a buffering and waiting mechanism is employed to ensure the order and integrity of data transmission, thereby improving the reliability of data transmission and further guaranteeing the accuracy of physiological electrical signal measurements.

[0104] Preferably, the preset duration T wait= n * T, where n is the difference between the smallest sequence number in the buffer and the currently expected sequence number. If the sequence number of a newly arriving packet in the buffer is less than the current smallest sequence number, then n is updated and T is recalculated. wait TT is the waiting time constant.

[0105] In this embodiment, during real-time data transmission, the first data transmitted by the auxiliary hardware module has an ID sequence and is aligned with a timestamp.

[0106] When the sequence is not misaligned, the main hardware module directly inputs the first data received at the moment and the reference signal aligned with the corresponding timestamp into the digital-to-analog converter for digital-to-analog conversion. Then, the digital-to-analog conversion result is input into the operational amplifier for summation and then input into the analog-to-digital converter for analog-to-digital conversion.

[0107] When a sequence error or missing packet occurs (e.g., k+1 is expected, but k+2, k+3, etc., arrive before the expected sequence), the subsequent arriving data packets are stored in the buffer and wait for a preset time. If the expected sequence packet is received during this period, the reference signal aligned with its corresponding timestamp is directly input into the digital-to-analog converter for digital-to-analog conversion. The result of the digital-to-analog conversion is then input into the operational amplifier for summation and then into the analog-to-digital converter for analog-to-digital conversion. Otherwise, the data packet with the smallest sequence number in the buffer is directly input into the digital-to-analog converter for digital-to-analog conversion along with the reference signal aligned with its corresponding timestamp. The result of the digital-to-analog conversion is then input into the operational amplifier for summation and then into the analog-to-digital converter for analog-to-digital conversion.

[0108] This invention further considers timestamp alignment when processing data packets, enabling data to maintain better time consistency during transmission and processing, thereby improving the accuracy and reliability of physiological electrical signal data and providing a higher quality data foundation for subsequent data analysis and processing.

[0109] As shown in Figure 2, the present invention also provides a split-type physiological electrical signal measurement method, which includes:

[0110] The device includes a main hardware module and at least one auxiliary hardware module; wherein the main hardware module and the auxiliary hardware module are respectively integrated in a split device, the main hardware module is connected to the auxiliary hardware module via wired or wireless means, and is connected to an external data processing terminal via wireless communication.

[0111] The auxiliary hardware module is used to acquire a first physiological electrical signal, perform a first amplification process and a first digital-to-analog conversion process to obtain a first digital signal; perform a first preliminary processing on the first digital signal to obtain first data, and store it according to the acquisition order; generate a timestamp to mark the acquisition time of the first data; and transmit the first data with the timestamp to the main hardware module.

[0112] The main hardware module is used to align the first data based on the timestamp; acquire the second physiological electrical signal, and perform the second amplification and second digital-to-analog conversion to obtain the second digital signal; perform the second preliminary processing on the second digital signal to obtain the second data as a reference signal; synthesize and restore the second data with the first data to obtain a complete physiological electrical signal data sequence and transmit it to an external data processing terminal.

[0113] In this embodiment, the data flow mainly flows from the auxiliary hardware module (internal structure can be referred to in Figure 3) to the main hardware (internal structure can be referred to in Figures 4 and 5) which has better performance and can communicate directly with more devices, so as to improve the overall system uptime.

[0114] The auxiliary hardware module and the main hardware module each have independent electrode modules, amplifier modules, digital-to-analog conversion modules, signal processing modules (including filtering, noise reduction and feature extraction modules), storage modules, clock modules, communication modules and power modules.

[0115] Specifically, the auxiliary hardware modules include at least:

[0116] The first electrode module is used to directly contact the organism and collect the first physiological electrical signal (such as data from one of the electrodes of electrical signals such as electrocardiogram, electromyography, and electroencephalogram).

[0117] The first amplifier module is used to perform a first amplification process on the first physiological electrical signal;

[0118] The first digital-to-analog conversion module is used to perform first analog-to-digital conversion processing on the amplified first physiological electrical signal and convert it into a first digital signal.

[0119] A first signal processing module is used to perform a first preliminary processing on a first digital signal to obtain first data. The first preliminary processing includes at least a first filtering process, a first noise reduction process, and a first feature extraction process.

[0120] The first clock module is used to generate a timestamp to mark the acquisition time of the first data.

[0121] The first communication module is used to transmit the first data with a timestamp to the main hardware module; it can be a wireless communication module (such as Bluetooth, Wi-Fi) or a wired communication module (such as USB, serial port);

[0122] The first energy module is used to provide the necessary electrical energy to each module;

[0123] The first storage module is used to store the first physiological electrical signal collected, the intermediate results of the first preliminary processing, the first data, and the first data with a timestamp.

[0124] The main hardware module includes at least:

[0125] The second electrode module is used to directly contact the organism and collect second physiological electrical signals (such as data from one of the electrodes of electrical signals such as electrocardiogram, electromyography, and electroencephalogram).

[0126] The second amplifier module is used to amplify the second physiological electrical signal.

[0127] The second analog-to-digital conversion module is used to perform a second analog-to-digital conversion on the amplified analog signal and convert it into a second digital signal.

[0128] The second signal processing module is used to perform a second preliminary processing on the second digital signal to obtain second data and use it as a reference signal. The second preliminary processing includes at least a second filtering process, a second noise reduction process and a second feature extraction process.

[0129] The second clock module is used to generate timestamps to mark the acquisition time of the second data; align the first data based on the timestamps; and calibrate the time of the first clock module.

[0130] The synthesis and restoration module is used to synthesize and restore the complete signal from the second data and the first data to obtain a complete physiological electrical signal data sequence.

[0131] The second communication module is used to receive the first data with a timestamp; and to transmit the complete physiological electrical signal data sequence to an external data processing terminal. It can be a wireless communication module (such as Bluetooth or Wi-Fi) or a wired communication module (such as USB or serial port).

[0132] The second energy module is used to provide the necessary electrical energy to each module;

[0133] The second storage module is used to store the acquired second physiological electrical signal, as well as the intermediate results and physiological electrical signal data sequence after the second preliminary processing.

[0134] This invention also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the memory described in the above embodiments; or it may be a standalone computer-readable storage medium not assembled into a device. The computer-readable storage medium stores at least one instruction, which is loaded and executed by a processor to implement the split-type physiological electrosignal measurement method shown in FIG1. ​​The computer-readable storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0135] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system and medium embodiments, since they are basically similar to method embodiments, the descriptions are relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0136] Furthermore, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0137] The foregoing description illustrates and describes preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept by means of the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A split-type physiological electrical signal measurement method, characterized in that, At least the following steps are included: The main hardware module is connected to the auxiliary hardware module via wired or wireless means, and is connected to an external data processing terminal via wireless communication; the main hardware module and the auxiliary hardware module are integrated into separate devices. The auxiliary hardware module performs the following steps: The first physiological electrical signal is acquired and subjected to the first amplification process and the first digital-to-analog conversion process to obtain the first digital signal; The first digital signal undergoes preliminary processing to obtain the first data, which is then stored according to the acquisition sequence. Generate a timestamp to mark the time when the first data was collected; The first data, with a timestamp, is transmitted to the main hardware module to trigger the main hardware module to perform the following steps: Align the first data based on the timestamp; The second physiological electrical signal is acquired and subjected to a second amplification and a second digital-to-analog conversion to obtain a second digital signal; The second digital signal undergoes a second preliminary processing to obtain second data, which is then used as a reference signal. The second data is synthesized and restored with the first data to obtain a complete physiological electrical signal data sequence, which is then transmitted to an external data processing terminal.

2. The split-type physiological electrical signal measurement method according to claim 1, characterized in that: After the main hardware module is connected to the auxiliary hardware module via wired or wireless means, the main hardware module calibrates and synchronizes the clock of the auxiliary hardware module, which includes at least the following steps: The main hardware module sends multiple RTC sub-second time data packets to the auxiliary hardware module; The auxiliary hardware module calculates the average latency difference based on the difference between the reception time and the transmission time of each data packet; The auxiliary hardware module calibrates its local clock based on the difference between the current clock time of the main hardware module and the link delay.

3. The split-type physiological electrical signal measurement method according to claim 1, characterized in that: During the process of synthesizing and restoring the second data with the first data, if there are data errors or omissions in the physiological electrical signal sequence, data is inserted according to the zero-padding principle.

4. The split-type physiological electrical signal measurement method according to claim 1, characterized in that: The connection status between the main hardware module and the auxiliary hardware module is monitored through one or more detection methods, including data, electrical interface, or mechanical triggering mechanism.

5. The split-type physiological electrical signal measurement method according to claim 4, characterized in that: The data detection method specifically involves detecting heartbeat packets or serial port interrupts via a wired interface to monitor the connection status between the main hardware module and the auxiliary hardware module. Electrical interface detection methods include monitoring the connection status between the main hardware module and the auxiliary hardware module through one of the following: voltage detection circuit, current detection circuit, or power management circuit. The specific detection method of the trigger mechanism is to monitor the connection status between the main hardware module and the auxiliary hardware module through mechanical switches, Hall sensor groups or specific optoelectronic transceiver modules.

6. The split-type physiological electrical signal measurement method according to claim 1, characterized in that: When the main hardware module is connected to the auxiliary hardware module via a wired connection, the auxiliary hardware module and the main hardware module do not need to communicate during the physiological electrical signal acquisition process. After the first physiological electrical signal acquisition is completed and reconnection is completed, the auxiliary hardware module transmits the first data with a timestamp to the main hardware module. When the main hardware module connects to the auxiliary hardware module wirelessly, data is transmitted in real time.

7. The split-type physiological electrical signal measurement method according to claim 6, characterized in that: During real-time data transmission, the first data transmitted by the auxiliary hardware module has an ID sequence. When the sequence is not misaligned, the main hardware module directly inputs the first data received to the digital-to-analog converter for digital-to-analog conversion, and then inputs the digital-to-analog conversion result into the operational amplifier to sum with the reference signal before inputting it into the analog-to-digital converter for analog-to-digital conversion. When a sequence error or packet loss occurs, the subsequent incoming data packets are stored in the buffer and wait for a preset time. If the expected sequence packet is received during the waiting period, it is directly input into the digital-to-analog converter for digital-to-analog conversion. The digital-to-analog conversion result is then input into the operational amplifier and summed with the reference signal before being input into the analog-to-digital converter for analog-to-digital conversion. Otherwise, the data packet with the smallest sequence number in the buffer will be input into the digital-to-analog converter for digital-to-analog conversion, and then the digital-to-analog conversion result will be input into the operational amplifier and summed with the reference signal before being input into the analog-to-digital converter for analog-to-digital conversion.

8. The split-type physiological electrical signal measurement method according to claim 6, characterized in that: During real-time data transmission, the first data transmitted by the auxiliary hardware module has an ID sequence and is aligned with a timestamp. When the sequence is not misaligned, the main hardware module directly inputs the first data received at the moment and the reference signal aligned with the corresponding timestamp into the digital-to-analog converter for digital-to-analog conversion, and then inputs the digital-to-analog conversion result into the operational amplifier for summation before inputting it into the analog-to-digital converter for analog-to-digital conversion. When a sequence error or packet loss occurs, the subsequent incoming data packets are stored in the buffer and wait for a preset time. If the expected sequence packet is received during the waiting period, the reference signal aligned with the corresponding timestamp is directly input into the digital-to-analog converter for digital-to-analog conversion. The digital-to-analog conversion result is then input into the operational amplifier for summation and then input into the analog-to-digital converter for analog-to-digital conversion. Otherwise, the data packet with the smallest sequence number in the buffer and the reference signal aligned with the corresponding timestamp will be directly input into the digital-to-analog converter for digital-to-analog conversion. The digital-to-analog conversion result will then be input into the operational amplifier for summation and then input into the analog-to-digital converter for analog-to-digital conversion.

9. A split-type physiological electrical signal measurement system, characterized in that, include: The device includes a main hardware module and at least one auxiliary hardware module; wherein the main hardware module and the auxiliary hardware module are respectively integrated in a split device, the main hardware module is connected to the auxiliary hardware module via wired or wireless means, and is connected to an external data processing terminal via wireless communication. The auxiliary hardware module is used to acquire a first physiological electrical signal, perform a first amplification process and a first digital-to-analog conversion process to obtain a first digital signal; perform a first preliminary processing on the first digital signal to obtain first data, and store it according to the acquisition order; generate a timestamp to mark the acquisition time of the first data; and transmit the first data with the timestamp to the main hardware module. The main hardware module is used to align the first data based on the timestamp; acquire the second physiological electrical signal, and perform the second amplification and second digital-to-analog conversion to obtain the second digital signal; perform the second preliminary processing on the second digital signal to obtain the second data as a reference signal; synthesize and restore the second data with the first data to obtain a complete physiological electrical signal data sequence and transmit it to an external data processing terminal.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a split-type physiological electrical signal measurement program, which, when executed by a processor, implements the steps of the split-type physiological electrical signal measurement method as described in any one of claims 1 to 8.

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