Non-volatile two-terminal memory cell, manufacturing method, and related product

Abstract

A non-volatile two-terminal memory cell, a manufacturing method, and a related product. The non-volatile two-terminal memory cell comprises a lower electrode (10), an upper electrode (20), and a conversion layer (30); the conversion layer (30) is arranged between the lower electrode (10) and the upper electrode (20); and the conversion layer (30) at least comprises a first region (31), a second region (32), and a first transition region which is separately in contact with the first region (31) and the second region (32). The conversion layer (30) has a local high electric field region; the local high electric field region is located in the first transition region; and the thickness of the first transition region is less than the thickness of the first region (31) and the thickness of the second region (32). In a direction from the upper electrode (20) to the lower electrode (10), the projection of the first region (31) at least overlaps the projection of the second region (32). By means of the non-volatile two-terminal memory cell, the positions at which conductive filaments are formed have certain regularity, thereby reducing the differences between the memory cells of a memory.

Description

Non-volatile dual-ended storage, manufacturing method and related products Cross-references to related applications

[0001] This application claims priority to Chinese patent application filed on March 24, 2025, with application number 2025103545728 and entitled "Non-volatile dual-end storage unit, manufacturing method and related products". Technical Field

[0002] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a non-volatile two-terminal memory module, a method of manufacturing it, and related products. Background Technology

[0003] Non-volatile two-terminal memory retains data even after power loss. Structurally, it can consist of two electrodes sandwiching a layer of functional material, forming a "sandwich" structure. It utilizes the physical properties of the material (such as resistance changes, phase transitions, or ferroelectric polarization) to store data. Common types of non-volatile two-terminal memory include resistive random access memory (RRAM), a type of non-volatile memory based on resistance changes. It stores data by utilizing the characteristic that the resistance state of the storage medium changes under different voltages. The basic principle of RRAM is to switch between a high-resistance state (HRS) and a low-resistance state (LRS) by applying different voltages to the memory cells, thereby enabling data storage and retrieval.

[0004] The basic structure of an RRAM typically consists of two electrodes and a resistive switching layer (storage medium) sandwiched in between, a typical "metal-insulator-metal" (MIM) structure. Specifically, the electrodes in an RRAM primarily provide electrical signals to the resistive switching layer, enabling read and write operations on the memory cells. Electrode materials are generally metals with good conductivity, such as platinum (Pt), titanium (Ti), tungsten (W), and copper (Cu). The interface characteristics between different electrode materials and the resistive switching layer affect the performance of the RRAM. For example, the work function and surface roughness of the electrode materials influence electron injection and transport, thus affecting the resistance switching characteristics, operating voltage, and durability of the RRAM. The resistive switching layer is the core component that enables the resistance switching function. It is typically made of metal oxides (such as TiO2, ZnOT), perovskite structures, or other materials with resistive switching properties. Under the influence of an external electric field, physical or chemical changes occur within the resistive switching layer, causing its resistance to reversibly switch between high and low resistance states, thereby enabling data storage.

[0005] Understandably, the relevant conversion layer is integrated between the upper and lower electrodes. Because the conversion layer has a planar structure and is relatively thin (e.g., only 1-20 nm), the locations of the thinnest and thickest parts of each memory cell are random. This not only leads to unstable operating voltages in the memory cells but also causes the conductive filament formation regions to be randomly distributed at the thinnest locations of the conversion layer. Consequently, this results in significant differences between memory cells.

[0006] In view of this, there is an urgent need to provide a non-volatile two-terminal storage unit, a manufacturing method, and related product solutions, so as to be able to determine the location area where the conductive filaments are formed. Summary of the Invention

[0007] In order to at least solve one or more of the technical problems mentioned above, this disclosure proposes a solution for a non-volatile end-to-end storage unit, a manufacturing method, and related products in several aspects.

[0008] In a first aspect, this application provides a non-volatile two-terminal storage unit, the non-volatile two-terminal storage unit including a lower electrode, an upper electrode, and a transition layer, the transition layer being disposed between the lower electrode and the upper electrode, the transition layer including at least a first region, a second region, and a first transition region respectively contacting the first region and the second region; wherein, the transition layer has a locally high electric field region located in the first transition region, the thickness of the first transition region being less than the thickness of the first region and the thickness of the second region; wherein, along the direction from the upper electrode to the lower electrode, the projection of the first region and the projection of the second region have at least an overlapping region.

[0009] In some embodiments, the conversion layer further includes a third region having a third inner surface and a third outer surface, and the second region having a second inner surface and a second outer surface, wherein the third inner surface and the second inner surface form a first conversion angle, and the third outer surface and the second outer surface form a second conversion angle, wherein the first conversion angle is less than or equal to the second conversion angle.

[0010] In some embodiments, along the direction from the upper electrode to the lower electrode, the projection of the third region overlaps with the projection of the second region by at least a certain area.

[0011] In some embodiments, the non-volatile dual-terminal storage portion further includes a dielectric layer disposed between the lower electrode and the upper electrode, wherein the dielectric layer has a first through-hole, and the surface of the first through-hole contacts the first outer surface of the first region.

[0012] In some embodiments, the lower electrode has a first concave structure formed on the side facing the conversion layer. The first concave structure has a first concave sidewall and a first concave bottom surface. The first concave sidewall is engaged with the surface of the first through hole and contacts at least a portion of the first outer surface. The first concave bottom surface contacts the second outer surface of the second region, such that the conversion layer is at least partially disposed within the first concave structure.

[0013] In some embodiments, when there is a potential difference between the lower electrode and the upper electrode, the conversion layer can form conductive filaments in the first transition region.

[0014] In some embodiments, the first region has a first outer surface, the second region has a second outer surface, and the angle formed by the first outer surface and the second outer surface is in the range of 30°-90°.

[0015] In a second aspect, this application provides a method for manufacturing a non-volatile dual-ended storage portion, the method comprising: forming a dielectric layer on a lower electrode; forming a first via in the dielectric layer, wherein the bottom diameter of the first via is larger than the top diameter of the first via; and forming a transition layer and an upper electrode in the first via, such that the transition layer includes a first transition region having a locally high electric field region.

[0016] In some embodiments, forming a first via in the dielectric layer includes etching the dielectric layer in an inclined direction such that the bottom diameter of the first via is larger than the top diameter of the first via.

[0017] In some embodiments, after forming a first via in the dielectric layer, the method further includes etching the lower electrode to obtain a first concave structure.

[0018] In some embodiments, forming a conversion layer and an upper electrode in a first via includes: depositing the conversion layer on the surface of a dielectric layer and on the lower electrode, wherein the surface of the dielectric layer includes the surface of the first via; and forming the upper electrode on the conversion layer.

[0019] In some embodiments, forming an upper electrode on the conversion layer includes: removing the conversion layer located on the dielectric layer using a planarization process; and depositing the upper electrode on the dielectric layer where the conversion layer has been removed and on the conversion layer.

[0020] In some embodiments, depositing the conversion layer on the surface of the dielectric layer and the lower electrode includes: depositing the conversion layer on the surface of the dielectric layer and the lower electrode using a physical vapor deposition method or a chemical vapor deposition method.

[0021] In a third aspect, this application provides a memory comprising: one or more non-volatile dual-ended storage units according to any one of the first aspects.

[0022] In a fourth aspect, this application provides an electronic device comprising: one or more non-volatile dual-ended storage units according to any one of the first aspects.

[0023] Through the non-volatile two-terminal storage section, manufacturing method and related products provided above, the solution disclosed herein enables the formation of conductive filaments in the conversion layer within the first transition region by making the thickness of the first transition region smaller than the thickness of the first region and the thickness of the second region. This allows the formation of conductive filaments to have a certain regularity, avoiding the randomness and uncontrollability of conductive filaments in traditional resistive switching memories, thereby reducing the differences between memory cells. Attached Figure Description

[0024] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0025] Figure 1a shows an exemplary cross-sectional view of a memory cell of a conventional resistive random access memory (RRAM);

[0026] Figure 1b shows an exemplary cross-sectional view of the conductive filament formation of a memory cell in a conventional resistive switching memory.

[0027] Figure 2 shows an exemplary cross-sectional view of a non-volatile end-to-end storage unit according to some embodiments of this disclosure;

[0028] Figure 3 shows an exemplary cross-sectional view of a non-volatile end-to-end storage unit according to other embodiments of this disclosure;

[0029] Figure 4a shows an exemplary cross-sectional view of a non-volatile end-point storage unit according to other embodiments of this disclosure;

[0030] Figure 4b shows an exemplary cross-sectional view of a non-volatile end-point storage unit according to other embodiments of this disclosure;

[0031] Figure 5 shows an exemplary block diagram of a method for manufacturing a non-volatile two-terminal storage unit according to some embodiments of this disclosure;

[0032] Figure 6a shows an exemplary structural diagram of the dielectric layer after etching along an inclined direction according to some embodiments of this disclosure;

[0033] Figure 6b illustrates an exemplary structural diagram of etching a dielectric layer along multiple directions according to other embodiments of this disclosure;

[0034] Figure 6c shows an exemplary structural diagram of etching a dielectric layer along multiple directions according to some embodiments of this disclosure;

[0035] Figure 7 shows an exemplary block diagram of a method for forming a conversion layer and an upper electrode in a first via according to some embodiments of this disclosure.

[0036] Tag Name

[0037] 10-Lower electrode, 20-Upper electrode, 30-Conversion layer, 31-First region, 32-Second region, 321-Second inner surface, 322-Second outer surface, 33-Third region, 331-Third inner surface, 332-Third outer surface, 40-Dielectric layer, 41-First via. Detailed Implementation

[0038] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0040] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0041] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0042] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0043] Figure 1a shows an exemplary cross-sectional view of a conventional resistive switching memory (RSM) cell; Figure 1b shows an exemplary cross-sectional view of the formation of conductive filaments in a conventional RSM cell. As shown in Figures 1a and 1b, the cross-sections of the upper electrode 20, lower electrode 10, and conversion layer 30 of a conventional RSM can be rectangular, and the distance between the upper electrode 20 and the lower electrode 10 can be equal. However, during manufacturing, due to the thinness of the conversion layer (e.g., 1-20 nm) and issues with the manufacturing process of the conversion layer, it is difficult to guarantee the uniformity of the conversion layer thickness, and the location of the minimum conversion layer thickness is undetermined. This makes the area where the conductive filaments are formed random, resulting in significant differences between memory cells.

[0044] Figure 2 shows an exemplary cross-sectional view of a non-volatile two-terminal storage unit according to some embodiments of this disclosure. As shown in Figure 2, the non-volatile two-terminal storage unit includes a lower electrode 10, an upper electrode 20, and a conversion layer 30. The conversion layer 30 is disposed between the lower electrode 10 and the upper electrode 20. The conversion layer 30 includes at least a first region 31, a second region 32, and a first transition region (not shown) that contacts the first region 31 and the second region 32, respectively. The conversion layer has a locally high electric field region located within the first transition region. The thickness of the first transition region is less than the thickness of the first region and the thickness of the second region. Along the direction from the upper electrode to the lower electrode, the projections of the first region and the second region at least overlap. In some embodiments, when a potential difference exists between the lower electrode 10 and the upper electrode 20, the conversion layer 30 can form conductive filaments within the first transition region.

[0045] In some embodiments, the aforementioned non-volatile end-to-end storage may include resistive memory, phase-change memory, ferroelectric memory, and magnetoresistive memory, as well as other memories with similar structures, which are not limited here.

[0046] In some embodiments, the aforementioned lower electrode 10 may be located at the bottom of the non-volatile end-to-end storage portion, the upper electrode 20 may be located at the top of the non-volatile end-to-end storage portion, and the conversion layer may be located between the lower electrode 10 and the upper electrode 20. Further, the material of the lower electrode 10 may be an active metal, such as Ag, Cu, etc. Preferably, the material of the lower electrode 10 may be copper, whose main advantages compared to other metals are high electrical and thermal conductivity, corrosion resistance, suitable strength, and ease of processing and forming. In the embodiments of this application, the lower electrode 10 of the first region may also be made of other metals as needed, and is not limited thereto. Further still, the material of the upper electrode 20 may be an inert metal, such as Pt, TiN, etc. The material of the conversion layer may be a metal oxide, such as HfO2, TaO, etc. x Metal oxides such as TiO2 can be used, and the conversion layer material can also be a chalcogenide compound, such as GeS2.

[0047] In some embodiments, the upper electrode 20 may have a convex structure on the side facing the lower electrode 10, which may include a convex sidewall and a convex bottom. In some embodiments, the first region 31 may have a first inner surface and a first outer surface, and the second region 32 may have a second inner surface and a second outer surface. Specifically, the first inner surface may be the side facing the convex sidewall of the upper electrode 20, and the first outer surface may be the side facing away from the convex sidewall of the upper electrode 20. The second outer surface may be the side facing the lower electrode 10, and the second inner surface may be the side facing away from the lower electrode 10.

[0048] It should be understood that in existing memories, when a voltage is applied between the upper electrode 20 and the lower electrode 10, metal ions can migrate under the influence of an electric field and form a conductive channel, which can be a conductive filament. When the voltage between the upper electrode 20 and the lower electrode 10 is removed, the conductive filament can dissipate. In this embodiment, by controlling the thickness of the first region, the thickness of the second region, or the thickness of the first transition region to the minimum value of the conversion layer thickness, metal ions can form conductive channels in the first region 31, the second region 32, or the first transition region, thereby forming a local high electric field region, allowing the conductive filament to form within this local high electric field. The aforementioned first transition region can be the portion in the conversion layer connecting the first region 31 and the second region 32, and the composition of the first transition region can be the same as or different from the composition of the first region and the second region.

[0049] In some embodiments, the thickness of the first transition region can be less than the thickness of the first region 31 and the thickness of the second region 32. That is, there is a minimum thickness portion within the first transition region, and a local high electric field region can be located within the first transition region. Specifically, after applying a voltage between the lower electrode 10 and the upper electrode 20, in the conversion layer, since the thickness of the first transition region is less than the thickness of the first region 31, the electric field intensity within the first transition region can be greater than the electric field intensity within the first region 31. Similarly, since the thickness of the first transition region is less than the thickness of the second region 32, the electric field intensity within the first transition region can also be greater than the electric field intensity within the second region 32. Therefore, the voltage in the first transition region of the conversion layer can be greater than the voltage in the first region 31 and the voltage in the second region 32, thereby forming a local high electric field region.

[0050] When using the non-volatile two-terminal storage unit for the first time, an initialization operation can be performed. Specifically, taking the thickness of the first transition region as less than the thickness of the first region and the thickness of the second region as an example, a relatively high voltage (e.g., 3-5V) can be applied between the lower electrode 10 and the upper electrode 20 of the non-volatile two-terminal storage unit, so that the metal cations (e.g., Ag) in the conversion layer... + Cu 2+ Alternatively, oxygen vacancies may migrate under the influence of an electric field. Understandably, since the electric field strength in the first transition region is greater than that in the first region 31 and the second region 32, cations or oxygen vacancies can form nanoscale conductive channels within the first transition region. These conductive channels can be conductive filaments. The conductive filaments can connect the lower electrode 10 and the upper electrode 20, allowing the storage cells of the non-volatile end-to-end storage units to enter a low-resistance state.

[0051] Furthermore, when writing to a memory cell in the non-volatile storage region, a positive voltage (e.g., +1V) can be applied to maintain or strengthen the conductive filament, allowing the memory cell to remain in a low-resistance state. When erasing a memory cell in the non-volatile storage region, a reverse voltage (e.g., -1V) can be applied to partially or completely destroy the conductive filament, allowing the memory cell to return to a high-resistance state.

[0052] Furthermore, when it is necessary to read a memory cell from the non-volatile end-to-end storage section, a low voltage (e.g., 0.1-0.5V) can be applied, and the state of the memory cell can be determined by detecting the current magnitude. For example, when the current is large, the memory cell can be in a low-impedance state; when the current is small, it can be in a high-impedance state. It should be understood that the magnitude of the aforementioned low voltage is insufficient to change the state of the memory cell.

[0053] In some embodiments, the projections of the first region 31 and the second region 32 may have at least an overlapping region along the direction from the upper electrode 20 to the lower electrode 10. Specifically, the second outer surface of the second region 32 may be arranged parallel to the surface of the lower electrode 10. The thickness of the second region 32 may be fixed or variable. Similarly, the distance between the first outer surface and the first inner surface may also be fixed or variable.

[0054] In a cross-sectional view of the storage cell of the non-volatile end-to-end storage section, along the direction from the upper electrode 20 to the lower electrode 10, the projection of the first region 31 can be a first line segment, and the projection of the second region 32 can be a second line segment, wherein the length of the first line segment can be less than the length of the second line segment, and the first line segment can be located inside the second line segment.

[0055] In a top view of the storage cell of the non-volatile dual-end storage section, along the direction from the upper electrode 20 to the lower electrode 10, the projection of the first region 31 can be presented as an annular shape, the projection of the second region 32 can be presented as a circular shape, and the aforementioned annular shape can be located inside the circle, having an overlapping area.

[0056] In some embodiments, the angle between the first inner surface and the second inner surface can be a third transformation angle, and the angle between the first outer surface and the second outer surface can be a fourth transformation angle. It is understood that when the projections of the first region and the second region at least overlap, the third transformation angle can be less than or equal to the fourth transformation angle. Further, the aforementioned third transformation angle can be an acute angle.

[0057] In some embodiments, the transition layer may further include a third region 33 and a second transition region (not shown) that contacts the second region 32 and the third region 33 respectively. It is understood that the second transition region may be the connection portion between the second region 32 and the third region 33. The third region may have a third inner surface and a third outer surface.

[0058] In some embodiments, the projection of the third region along the direction from the upper electrode to the lower electrode may overlap with the projection of the second region. It is understood that the angle between the third inner surface and the second inner surface can be an acute angle in this case.

[0059] In other embodiments, along the direction from the upper electrode to the lower electrode, the projection of the third region may be connected to the projection of the second region, but they do not overlap. It is understood that the angle between the third inner surface and the second inner surface can be a right angle (as shown in Figure 2) or an obtuse angle.

[0060] The scheme disclosed herein helps to suppress the formation of conductive filaments in other areas of the conversion layer when conductive filaments are formed in the first transition region. This allows the formation of conductive filaments to have a certain regularity, avoiding the randomness and uncontrollability of conductive filaments in traditional resistive switching memory, thereby reducing the differences between memory cells.

[0061] Figure 3 shows an exemplary cross-sectional view of a non-volatile end-to-end storage unit according to other embodiments of this disclosure. As shown in Figure 3, the conversion layer further includes a third region 33 having a third inner surface 331 and a third outer surface 332, and a second region 32 having a second inner surface 321 and a second outer surface 322, wherein the third inner surface 331 and the second inner surface 321 form a first conversion angle, and the third outer surface 332 and the second outer surface 322 form a second conversion angle, wherein the first conversion angle is less than or equal to the second conversion angle.

[0062] In some embodiments, the transition layer may include a first region 31, a second region 32, a third region 33, a first transition region, and a second transition region, wherein the first transition region may contact the first region 31 and the second region 32, and the second transition region may contact the second region 32 and the third region 33.

[0063] In some embodiments, the second inner surface and the third inner surface may be surfaces facing the upper electrode, and the second outer surface and the third outer surface may be surfaces facing away from the upper electrode.

[0064] Understandably, when the first transition angle is less than the second transition angle, within the second region 32, the distance between the second outer surface and the second inner surface can gradually increase along the direction from the third region 33 to the first region 31; similarly, within the third region 33, the distance between the third outer surface and the third inner surface can gradually increase along the direction from the lower electrode to the upper electrode. Therefore, the thickness of the second transition region can be less than the thickness of the second region 32 and the thickness of the third region 33. In this case, when a voltage is applied between the lower electrode and the upper electrode, the voltage of the transition layer in the second transition region can be greater than the voltage in the second region 32 and the voltage in the third region 33. Understandably, the thickness of the first transition region can be less than, equal to, or greater than the thickness of the second transition region, thus allowing conductive filaments to be formed within the first transition region and / or the second transition region. Furthermore, when the distance between the first and second transition angles is the minimum thickness of the second transition region, conductive filaments can be formed between the first and second transition angles.

[0065] When the first transition angle equals the second transition angle, it can be understood that the distance between the second inner surface and the second outer surface of the second region 32 can remain unchanged, and the distance between the third inner surface and the third inner surface of the third region 33 can also remain unchanged. It should be understood that since the thickness of the first transition region can be less than the thickness of the second region, conductive filaments can also be formed within the first transition region.

[0066] By setting the first transition angle to be less than or equal to the second transition angle, conductive filaments can be formed in the second transition region or the first transition region. This allows the formation of conductive filaments to have a certain regularity, thereby reducing the differences between memory cells.

[0067] In some embodiments, along the direction from the upper electrode to the lower electrode, the projection of the third region 33 and the projection of the second region 32 have at least an overlapping area.

[0068] In some embodiments, the second outer surface of the second region 32 may be arranged parallel to the surface of the lower electrode. The thickness of the second region 32 may be fixed or variable. Specifically, when the thickness of the second region 32 is fixed, the distance between the second outer surface and the second inner surface may be fixed. When the thickness of the second region 32 is variable, the distance between the second outer surface and the second inner surface is also variable. For the same reason, the distance between the first outer surface and the first inner surface may also be fixed or variable.

[0069] In a cross-sectional view of the storage cell in the non-volatile end-to-end storage section, along the direction from the upper electrode 20 to the lower electrode 10, the projection of the third region 33 can be a third line segment, and the projection of the second region 32 can be a second line segment. The length of the third line segment can be less than the length of the second line segment, and the third line segment can be located inside the second line segment.

[0070] In a top view of the storage cell of the non-volatile end-to-end storage section, along the direction from the upper electrode 20 to the lower electrode 10, the projection of the third region 33 can be an annular shape, and the projection of the second region 32 can be a circle. The aforementioned annular part can be located inside the circle and have an overlapping area.

[0071] Figure 4a shows an exemplary cross-sectional view of a non-volatile two-ended storage unit according to other embodiments of this disclosure. Figure 4b shows an exemplary cross-sectional view of a non-volatile two-ended storage unit according to other embodiments of this disclosure. As shown in Figures 4a and 4b, the non-volatile two-ended storage unit further includes a dielectric layer 40 disposed between the lower electrode 10 and the upper electrode 20, wherein the dielectric layer 40 is provided with a first through-hole 41, the surface of the first through-hole contacting a first outer surface of the first region. In some embodiments, a first concave structure is formed on the side of the lower electrode facing the conversion layer, the first concave structure having a first concave sidewall and a first concave bottom surface; the first concave sidewall is engaged with the surface of the first through-hole, and the first concave sidewall is in contact with at least a portion of the first outer surface; the first concave bottom surface is in contact with a second outer surface of the second region, such that the conversion layer is at least partially disposed within the first concave structure.

[0072] In some embodiments, the first region has a first outer surface, the second region has a second outer surface, and the angle formed by the first outer surface and the second outer surface is in the range of 30°-90°.

[0073] In some embodiments, the non-volatile end-to-end storage portion may include a lower electrode 10, an upper electrode 20, a conversion layer 30, and a dielectric layer 40. Specifically, the dielectric layer may be composed of an insulating material, such as a high dielectric constant material (e.g., Al2O3, SiO2, HfO2, etc.) or a nitride (e.g., SiN). x This dielectric layer can restrict the migration paths of ions / vacancies, thereby improving the controllability of conductive filament formation.

[0074] In some embodiments, the dielectric layer 40 may be provided with a first through-hole 41. Further, the bottom diameter of the first through-hole may be larger than the top diameter of the first through-hole. In this case, the surface of the first through-hole may be inclined, and the surface of the first through-hole and the plane containing the lower electrode may form an acute angle. It is understood that after the first through-hole 41 is formed, when the conversion layer 30 is formed within the first through-hole 41, since the surface of the first through-hole is inclined, the first region of the conversion layer may also be formed inclined on the surface of the first through-hole, and the first outer surface may contact the surface of the first through-hole.

[0075] In other embodiments, the surface of the first through-hole may include a first surface and a second surface, wherein the first surface may be inclined and form an acute angle with the plane containing the lower electrode; the second surface may be vertical and form a right angle with the plane containing the lower electrode. In some embodiments, the projection of the aforementioned first concave structure in the direction from the upper electrode to the lower electrode may be an annulus.

[0076] By setting the first concave structure, when the upper and lower electrodes are energized, the electric field can be concentrated in a smaller area, thereby reducing the voltage required to form the conductive filament.

[0077] In some embodiments, the first region has a first outer surface, the second region has a second outer surface, and the angle formed by the first outer surface and the second outer surface is in the range of 30°-90°.

[0078] In some embodiments, the included angle formed by the aforementioned first outer surface and second outer surface can be a fourth conversion angle, which can be 30°, 60°, or 90°, etc. It is understood that the conversion layer can be grown on the surface of the first via of the dielectric layer, therefore the fourth conversion angle can be the same as the second dielectric angle of the first via. Therefore, the angle range of the second dielectric angle can also be 30°-90°.

[0079] It is important to understand that when a conversion layer is formed on the surface of the dielectric layer, the angle of arrival of that surface and the deposition rate of the conversion layer can be positively correlated. That is, the smaller the angle of arrival, the slower the deposition rate; and the larger the angle of arrival, the faster the deposition rate of the conversion layer. On the dielectric layer, the angle of arrival in the region surrounding the second dielectric angle can reach its minimum value, meaning the deposition rate in the first transition zone can be the slowest, thus allowing for precise control of the conversion layer thickness in this region. The angle of arrival of the dielectric layer will be described in detail later with reference to Figure 5.

[0080] The solution disclosed herein allows for more precise control of the thickness of the conversion layer within the first conversion zone, ensuring better consistency in the thickness of this region.

[0081] Figure 5 shows an exemplary block diagram of a method 500 for manufacturing a non-volatile two-terminal storage unit according to some embodiments of this disclosure. As shown in Figure 5, the method includes: S501 forming a dielectric layer on a lower electrode; S502 forming a first via in the dielectric layer, wherein the bottom diameter of the first via is larger than the top diameter of the first via; and S503 forming a transition layer and an upper electrode in the first via, such that the transition layer includes a first transition region having a locally high electric field region.

[0082] In some embodiments, prior to step S501, a substrate may be provided, which may include a silicon-based substrate, a glass substrate, or a metal substrate, etc., and the specific substrate selection can be made according to the application scenario. Further, electrode material can be deposited on the substrate to form a first electrode.

[0083] In step S501, forming a dielectric layer on the lower electrode may include depositing a dielectric layer on the lower electrode. The lower electrode may be a metallic material, including titanium, tungsten, ruthenium, iridium, nickel, platinum, copper, silver, gold, and aluminum. The aforementioned dielectric layer may be a metal oxide with resistive switching properties, including aluminum, magnesium, yttrium, lanthanum, titanium, zirconium, hafnium, niobium, tantalum, cerium, chromium, molybdenum, tungsten, manganese, iron, cobalt, nickel, copper, gadolinium, zinc, germanium, tin, ytterbium, and lutetium.

[0084] Furthermore, the deposition of a dielectric layer on the lower electrode can be achieved by using physical methods such as physical vapor deposition (PVD) or chemical methods such as chemical vapor deposition (CVD).

[0085] In step S502, forming the first via in the dielectric layer may include etching the dielectric layer to form the first via. It is understood that etching can be performed along an inclined direction in the dielectric layer, such that the bottom diameter of the first via is larger than the top diameter. In some embodiments, the dielectric layer can be etched in a vacuum reaction chamber to form the first via, exposing the lower electrode portion that was originally covered by the dielectric layer. The direction from the lower electrode layer to the upper electrode layer can be a first direction, and the inclined direction can be a direction inclined to the first direction. In some embodiments, the angle formed between the top layer of the dielectric layer and the surface of the first via can be a first dielectric angle; the angle formed between the surface of the first via and the exposed surface of the lower electrode can be a second dielectric angle. Further, since the top radius of the first via can be smaller than the bottom radius, the first dielectric angle can be greater than 270°, and the second dielectric angle can be less than 90°.

[0086] In step S503, a conversion layer and an upper electrode are formed in the first via, such that the conversion layer includes a first transition region having a locally high electric field region. In some embodiments, the conversion layer may be formed in the first via, and the upper electrode may be formed on the conversion layer after the conversion layer is obtained.

[0087] In some embodiments, the aforementioned conversion layer may have a local high electric field region, which may be located within a first transition region. The thickness of the first transition region may be less than the thickness of the first region and the thickness of the second region. In this embodiment, the projections of the first region and the second region may have at least an overlapping region along the direction from the upper electrode to the lower electrode.

[0088] In some embodiments, forming a conversion layer in a first via may include deposition on top of a dielectric layer and on the surface of the first via of the dielectric layer, wherein deposition may be performed using methods such as PVD or CVD.

[0089] It's important to understand that during deposition, the angle formed by the surface to which the deposition is being performed can be called the angle of arrival. For example, when depositing on a plane, the angle of arrival can be 180°; when depositing on a surface forming an acute angle, the angle of arrival can be an acute angle; and when depositing on a surface forming a right angle, the angle of arrival can be a right angle. Furthermore, the deposition rate can be related to the angle of arrival; the smaller the angle of arrival, the slower the deposition rate; and the larger the angle of arrival, the faster the deposition rate can be.

[0090] In some embodiments, when deposition is performed on top of the dielectric layer, the angle of arrival can remain constant at 180°, thus maintaining a constant deposition rate. When deposition is performed on the region where the top of the dielectric layer meets the first via (i.e., the region near the first dielectric angle), the angle of arrival can be greater than 270°, allowing for a faster deposition rate.

[0091] Furthermore, when depositing on the surface of the first via, the angle of arrival can remain constant at 180°, allowing the deposition rate to remain constant. After deposition on the surface of the first via, a first region of the conversion layer can be formed. Even further, when depositing into the region where the first via and the top of the lower electrode contact (i.e., near the second dielectric angle), the angle of arrival can be acute, thus allowing for a slower deposition rate. After deposition in the region containing the second dielectric angle, a first transition region of the conversion layer can be formed. When depositing on the exposed lower electrode, the angle of arrival can also remain constant at 180°, allowing the deposition rate to remain constant. After deposition on the lower electrode, a second region of the conversion layer can be formed.

[0092] It is understandable that during the above deposition process, the deposition rate is slowest in the first transition zone, so its thickness has better uniformity, and the thickness of the first transition zone can be less than the thickness of the first region and the thickness of the second region.

[0093] After the deposition is completed, an upper electrode can be deposited on the conversion layer obtained by deposition. At this time, the thickness of the transition region can be less than the thickness of the first region and the thickness of the second region.

[0094] In some embodiments, after the conversion layer deposition is completed, the first region, the conversion layer, and / or the second region of the conversion layer can be etched as needed to change the thickness of the first region, the conversion layer, and / or the second region, thereby minimizing the thickness of the first region, the conversion region, or the second region to control the formation position of the conductive filaments. In other embodiments, when depositing the conversion layer on the dielectric layer, the deposition thickness can be controlled by controlling the deposition time. For example, when the deposition time of the first region is less than the deposition time of the first transition region and the second region, the thickness of the first region can be minimized. When the deposition time of the first transition region is less than the deposition time of the first region and the second region, the thickness of the first transition region can be minimized. When the deposition time of the second region is less than the deposition time of the first region and the first transition region, the thickness of the second region can be minimized. It is understood that when the thickness of the first region or the second region is less than that of the first transition region, the corresponding process is more complex and more difficult to control.

[0095] Preferably, the thickness of the first transition zone can be made smaller than the thickness of the first region and the thickness of the second region through the above deposition process, which can enable the conductive filaments to form in the first transition zone. This helps to suppress the formation of conductive filaments in other regions of the conversion layer and makes the formation of conductive filaments more regular.

[0096] The scheme disclosed herein, during the formation of the transition layer, results in the slowest deposition rate in the region where the second dielectric angle of the dielectric layer is located due to the acute angle. This leads to a more uniform thickness of the deposited first transition region, and the thickness of the first transition region can be smaller than that of both the first and second transition regions. This allows for control over the formation location of conductive filaments within the first transition region, reducing variability between different memory cells. Furthermore, by controlling the thickness of the first, second, and third regions of the transition layer, the area where conductive filaments form can be controlled, reducing the likelihood of filaments forming at random locations and further minimizing variability between different memory cells.

[0097] Figure 6a shows an exemplary structural diagram of the dielectric layer after etching along an inclined direction according to some embodiments of the present disclosure; Figure 6b shows an exemplary structural diagram of the dielectric layer after etching along multiple directions according to other embodiments of the present disclosure; Figure 6c shows an exemplary structural diagram of the dielectric layer after etching along multiple directions according to some embodiments of the present disclosure.

[0098] In some embodiments, forming a first via in the dielectric layer includes etching the dielectric layer in an inclined direction such that the bottom diameter of the first via is larger than the top diameter of the first via.

[0099] In some embodiments, before etching the dielectric layer, photoresist can be formed on the upper surface of the dielectric layer. The photoresist is selectively exposed using an exposure machine, and development removes the exposed or unexposed portions of the photoresist to form a patterned photomask layer. Further, a first via can be formed by etching the dielectric layer not covered by the patterned photomask layer, thus obtaining an exposed lower electrode. After forming the first via, the patterned photomask layer is removed.

[0100] As shown in Figure 6a, in some embodiments, when etching the dielectric layer, the sidewall of the first via can be tilted by adjusting the substrate tilt angle or the incident direction of the ion beam. In this case, the bottom diameter of the first via can be larger than the top diameter of the first channel, and the first via can form a frustum-shaped structure with a smaller top and a larger bottom. In this case, the cross-sectional shape of the first via can be a trapezoid without right angles.

[0101] In other embodiments, forming a first via in the dielectric layer may include etching the dielectric layer along multiple directions. Specifically, the dielectric layer may be etched along inclined and vertical directions. This can result in a first via as shown in Figure 6b or 6c. In this case, the first via can form a trapezoidal structure with a smaller upper end and a larger lower end, and its cross-sectional shape can be a right trapezoid.

[0102] The via is etched along an inclined direction to create an acute angle between the surface of the first via and the exposed surface of the lower electrode. Subsequent deposition in this acute-angle region can reduce the deposition rate, which helps maintain the thickness of the conversion layer in that area.

[0103] In some embodiments, after forming a first via in the dielectric layer, the method further includes etching the lower electrode to obtain a first concave structure.

[0104] In some embodiments, before etching the dielectric layer, photoresist can be formed on the upper surface of the dielectric layer. The photoresist is selectively exposed using an exposure machine, and development removes portions of the photoresist, either the exposed or unexposed portions, to form a patterned photomask layer. Further, a first via can be formed by etching the dielectric layer not covered by the patterned photomask layer. This first via can then contact the lower electrode, resulting in an exposed lower electrode. Further etching can continue on the exposed lower electrode to obtain a first concave structure. After obtaining the first concave structure, the patterned photomask layer can be removed.

[0105] By etching the lower electrode, an edge structure can be formed, allowing an electric field to be generated in a local area. When the conductive filament is formed in the first transition region, the voltage required for the formation of the conductive filament can be reduced.

[0106] Figure 7 shows an exemplary block diagram of a method 700 for forming a conversion layer and an upper electrode in a first via according to some embodiments of this disclosure. As shown in Figure 7, forming the conversion layer and the upper electrode in the first via includes: S701 depositing the conversion layer on the surface of a dielectric layer and on the lower electrode, wherein the surface of the dielectric layer includes the surface of the first via; and S702 forming the upper electrode on the conversion layer.

[0107] In some embodiments, forming an upper electrode on the conversion layer includes: removing the conversion layer located on the dielectric layer using a planarization process; and depositing the upper electrode on the dielectric layer where the conversion layer has been removed and on the conversion layer.

[0108] In some embodiments, during the deposition of the conversion layer, the deposited conversion layer must at least cover the exposed first electrode and the surface of the first via of the dielectric layer. This deposition can be performed using methods such as PVD or CVD. After deposition on the surface of the first via of the dielectric layer, a first region can be formed. Since the surface of the first via can remain constant at 180°, the angle of arrival of the first via can also remain constant at 180°, resulting in a constant deposition rate on the surface of the first via. After deposition on the lower electrode, a second region is obtained, whose angle of arrival can also remain constant at 180°, resulting in a constant deposition rate on the surface of the lower electrode. After deposition on the region containing the second dielectric angle, a first transition region can be formed. Since its angle of arrival can be acute, the deposition rate in this region can be lower than the deposition rate on the surface of the first via and the deposition rate on the surface of the lower electrode, thus allowing for better consistency in the thickness of the deposition in the first transition region.

[0109] It is understood that after obtaining the conversion layer, the conversion layer can cover the upper surface of the dielectric layer, the surface of the first via, and the surface of the exposed lower electrode. In some embodiments, the upper electrode can be deposited directly on the aforementioned conversion layer. In other embodiments, the upper electrode can be obtained by deposition after removing the conversion layer located on the dielectric layer. In some embodiments, a planarization method can be used when removing the conversion layer located on the dielectric layer, which may include chemical mechanical polishing (CMP).

[0110] The scheme disclosed herein allows for a slower formation of the first transition region, resulting in better consistency in its thickness. Furthermore, by removing the transition layer located on the dielectric layer, direct contact between the upper electrode and the dielectric layer is achieved, reducing surface unevenness and defects. This helps improve the interface quality between the upper electrode and the dielectric layer, thereby enhancing the reliability and performance of the device.

[0111] In some embodiments, depositing the conversion layer on the surface of the dielectric layer and the lower electrode includes: depositing the conversion layer on the surface of the dielectric layer and the lower electrode using a physical vapor deposition method or a chemical vapor deposition method.

[0112] This disclosure also provides a memory comprising one or more non-volatile dual-ended storage units according to any of the foregoing embodiments. These non-volatile dual-ended storage units can be used to store instructions or data.

[0113] This disclosure also provides an electronic device that may include one or more volatile end-to-end storage units of any of the foregoing embodiments.

[0114] In summary, the scheme disclosed herein helps to suppress the formation of conductive filaments in other areas of the conversion layer when they are formed in the first transition region. This allows the formation of conductive filaments to have a certain regularity, avoiding the randomness and uncontrollability of conductive filaments in traditional resistive switching memory, thereby reducing the differences between memory cells.

[0115] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A non-volatile two-terminal storage unit, characterized in that, The non-volatile two-terminal storage unit includes a lower electrode (10), an upper electrode (20), and a conversion layer (30). The conversion layer (30) is disposed between the lower electrode (10) and the upper electrode (20). The conversion layer (30) includes at least a first region (31), a second region (32), and a first transition region that contacts the first region (31) and the second region (32) respectively. The conversion layer (30) has a local high electric field region located in the first transition region. The thickness of the first transition region is less than the thickness of the first region (31) and the thickness of the second region (32). Wherein, along the direction from the upper electrode (20) to the lower electrode (10), the projection of the first region (31) and the projection of the second region (32) have at least an overlapping area.

2. The non-volatile dual-ended storage unit according to claim 1, characterized in that, The conversion layer (30) further includes a third region having a third inner surface (331) and a third outer surface (332), and the second region (32) having a second inner surface (321) and a second outer surface (322), wherein the third inner surface (331) and the second inner surface (321) form a first conversion angle, and the third outer surface (332) and the second outer surface (322) form a second conversion angle, wherein the first conversion angle is less than or equal to the second conversion angle.

3. The non-volatile dual-ended storage unit according to claim 2, characterized in that, Along the direction from the upper electrode (20) to the lower electrode (10), the projection of the third region overlaps with the projection of the second region (32) at least in one region.

4. The non-volatile dual-ended storage unit according to claim 1, characterized in that, The non-volatile end-to-end storage section further includes a dielectric layer (40) disposed between the lower electrode (10) and the upper electrode (20), wherein the dielectric layer (40) is provided with a first through hole (41), and the surface of the first through hole (41) is in contact with the first outer surface of the first region (31).

5. The non-volatile dual-ended storage unit according to claim 4, characterized in that, The lower electrode (10) has a first concave structure on the side facing the conversion layer (30), the first concave structure having a first concave sidewall and a first concave bottom surface; The first concave sidewall is connected to the surface of the first through hole (41), and the first concave sidewall is in contact with at least a portion of the first outer surface; The first concave bottom surface contacts the second outer surface (322) of the second region (32), such that the conversion layer (30) is at least partially disposed within the first concave structure.

6. The non-volatile dual-ended storage unit according to claim 1, characterized in that, When there is a potential difference between the lower electrode (10) and the upper electrode (20), the conversion layer (30) can form conductive filaments in the first transition region.

7. The non-volatile dual-ended storage unit according to claim 1, characterized in that, The first region (31) has a first outer surface, and the second region (32) has a second outer surface (322). The angle between the first outer surface and the second outer surface (322) is in the range of 30°-90°.

8. A method for manufacturing a non-volatile dual-ended storage unit, characterized in that, The method includes: A dielectric layer is formed on the lower electrode; A first through-hole is formed in the dielectric layer, wherein the bottom diameter of the first through-hole is larger than the top diameter of the first through-hole; and A conversion layer and an upper electrode are formed in the first via, such that the conversion layer includes a first transition region having a local high electric field region.

9. The method according to claim 8, characterized in that, The step of forming a first via in the dielectric layer includes etching the dielectric layer along an inclined direction such that the bottom diameter of the first via is larger than the top diameter of the first via.

10. The method according to claim 8, characterized in that, After forming the first via in the dielectric layer, the method further includes etching the lower electrode to obtain a first concave structure.

11. The method according to claim 8, characterized in that, The formation of the conversion layer and the upper electrode in the first through-hole includes: The conversion layer is deposited on the surface of the dielectric layer and on the lower electrode, wherein the surface of the dielectric layer includes the surface of the first via; and An upper electrode is formed on the conversion layer.

12. The method according to claim 11, characterized in that, Forming an upper electrode on the conversion layer includes: The conversion layer located on the dielectric layer is removed using a planarization process; and The upper electrode is formed by depositing a dielectric layer on which the conversion layer has been removed and the conversion layer.

13. The method according to claim 11, characterized in that, Depositing the conversion layer on the surface of the dielectric layer and on the lower electrode includes depositing the conversion layer on the surface of the dielectric layer and on the lower electrode using a physical vapor deposition method or a chemical vapor deposition method.

14. A memory, characterized in that, include: One or more non-volatile dual-ended storage units according to any one of claims 1-7.

15. An electronic device, characterized in that, include: One or more non-volatile dual-ended storage units according to any one of claims 1-7.

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