Correction circuit, memory device, computing-in-memory system, and electronic apparatus

Abstract

Disclosed are a correction circuit, a memory device, a computing-in-memory system, and an electronic apparatus, relating to the technical field of semiconductors. The correction circuit is configured to correct a first semiconductor device of a memory circuit; the first semiconductor device comprises a first terminal, a second terminal, and a first control terminal, wherein a first channel is formed between the first terminal and the second terminal, and the first control terminal is configured to control the conduction capability of the first channel. The correction circuit comprises: a second semiconductor device matching the first semiconductor device, and comprising a third terminal, a fourth terminal, and a second control terminal, wherein a second channel is formed between the third terminal and the fourth terminal, the second control terminal is configured to control the conduction capability of the second channel, and the third terminal is coupled to a constant current; and a feedback control branch connected to the third terminal, and outputting a correction voltage on the basis of the voltage of the third terminal, the second control terminal being coupled to the correction voltage, the correction voltage being used for stabilizing the channel current of the second channel, and the correction voltage being applied to the first control terminal. The correction circuit can reduce precision reduction caused by environmental factors.

Description

Correction circuits, storage devices, in-memory computing systems and electronic devices Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a correction circuit, a storage device, a memory computing system, and an electronic device. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architecture physically merges storage and computation, enabling computation through storage devices or storing data within computing devices. This reduces data transfer requirements, lowers latency and energy consumption, and significantly improves data processing efficiency. However, IMC architecture still faces challenges; for example, its computational accuracy needs further improvement. Summary of the Invention

[0004] This application provides a correction circuit, a storage device, a memory computing system, and an electronic device to improve the computing accuracy of a memory computing architecture.

[0005] In a first aspect, a calibration circuit is provided for calibrating a first semiconductor device in a storage circuit. The first semiconductor device includes a first terminal, a second terminal, and a first control terminal. A first channel is formed between the first terminal and the second terminal. The first control terminal is used to control the conduction capability of the first channel. The calibration circuit includes: a second semiconductor device matched with the first semiconductor device, and including a third terminal, a fourth terminal, and a second control terminal. A second channel is formed between the third terminal and the fourth terminal. The second control terminal is used to control the conduction capability of the second channel. The third terminal is coupled to a constant current. A feedback control branch is connected to the third terminal and outputs a calibration voltage based on the voltage of the third terminal. The second control terminal is coupled to the calibration voltage. The calibration voltage is used to stabilize the channel current of the second channel and is used at the first control terminal.

[0006] The second semiconductor device is matched with the first semiconductor device. The channel current or channel conduction capability of the two are affected by environmental factors in the same or similar ways. The correction voltage generated by the second semiconductor device can be used to reduce or offset the influence of environmental factors on the channel current or channel conduction capability of the first semiconductor device, thereby reducing the reduction in read accuracy or calculation accuracy of the storage device and the memory system caused by changes in environmental factors.

[0007] In some implementations of the first aspect, the feedback control branch includes: a feedback control circuit coupled to a reference voltage and connected to a third terminal, the feedback control circuit being used to adjust and output a correction voltage based on the voltage at the third terminal and the reference voltage.

[0008] In some implementations of the first aspect, the feedback control circuit includes an operational amplifier with a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a reference voltage, the second input terminal is connected to a third terminal, and the output terminal is used to output a correction voltage.

[0009] In some implementations of the first aspect, the first semiconductor device further includes a third control terminal for coupling to an input signal and controlling the conduction capability of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal for coupling to a first voltage.

[0010] In some implementations of the first aspect, the first voltage is determined based on the input signal.

[0011] In some implementations of the first aspect, the second semiconductor device includes a transistor; the second control terminal includes a substrate, and the fourth control terminal includes a gate; or, the second control terminal includes a first gate, and the fourth control terminal includes a second gate.

[0012] In some implementations of the first aspect, the storage circuit further includes a third semiconductor device, which shares or interconnects with the channel of the first semiconductor device, and a correction voltage is used to correct the third semiconductor device through the first semiconductor device.

[0013] In some implementations of the first aspect, the storage circuit further includes a fourth semiconductor device connected to the third semiconductor device for coupling the input signal of the third semiconductor device and inputting the input signal to the third semiconductor device.

[0014] In some implementations of the first aspect, the correction circuit further includes a fifth semiconductor device, which shares or interconnects with the channel of the second semiconductor device.

[0015] In some implementations of the first aspect, the correction circuit further includes a sixth semiconductor device connected to the second and fifth semiconductor devices for coupling a second voltage.

[0016] In some implementations of the first aspect, the correction circuit includes a plurality of second semiconductor devices, the second control terminals of the plurality of second semiconductor devices being connected together, and the third terminals of the plurality of second semiconductor devices being connected together.

[0017] In some implementations of the first aspect, the correction circuit further includes a driving circuit connected between the second control terminal of the second semiconductor device and the first control terminal of the first semiconductor device, for increasing the output power of the correction voltage output by the feedback control branch.

[0018] In a second aspect, a storage device is provided, comprising: a storage circuit including a first semiconductor device, the first semiconductor device including a first terminal, a second terminal, and a first control terminal, a first channel being formed between the first terminal and the second terminal, the first control terminal being used to control the conduction capability of the first channel; and a correction circuit as described in the first aspect or any possible implementation thereof.

[0019] In some implementations of the second aspect, the first semiconductor device further includes a third control terminal for coupling to an input signal and controlling the conduction capability of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal for coupling to a first voltage.

[0020] In some implementations of the second aspect, the storage circuit includes a storage cell group, which includes a plurality of first semiconductor devices. In the first semiconductor devices within the storage cell group, a third control terminal is coupled to a plurality of input signals respectively. The third terminals are connected to each other and connected to the same output line. The storage cell group is configured to convert the plurality of input signals into a plurality of output signals based on the weight data stored in each of the first semiconductor devices within the storage cell group, and to output an accumulated signal of the plurality of output signals on the same output line.

[0021] In some implementations of the second aspect, the storage circuit further includes a third semiconductor device, which shares or interconnects with the channel of the first semiconductor device, and a correction voltage is used to correct the third semiconductor device through the first semiconductor device.

[0022] In some implementations of the second aspect, the storage circuit further includes a fourth semiconductor device connected to the third semiconductor device for coupling the input signal of the third semiconductor device and inputting the input signal to the third semiconductor device.

[0023] Thirdly, a storage computing system is provided, comprising: a storage device as described in the second aspect or any possible implementation of the second aspect; and a control circuit for controlling the storage circuit of the storage device.

[0024] Fourthly, an electronic device is provided, including a storage device as described in the second aspect or any possible implementation of the second aspect, or a storage computing system as described in the third aspect or any possible implementation of the third aspect. Attached Figure Description

[0025] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0026] Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0027] Figure 3 shows a schematic diagram of a storage device according to an exemplary embodiment of this application.

[0028] Figure 4 shows a schematic diagram of yet another storage device according to an exemplary embodiment of this application.

[0029] Figure 5 shows a schematic diagram of yet another storage device according to an exemplary embodiment of this application.

[0030] Figure 6 shows a schematic diagram of yet another storage device according to an exemplary embodiment of this application.

[0031] Figure 7 shows a schematic diagram of a correction circuit according to an exemplary embodiment of this application.

[0032] Figure 8 shows a schematic diagram of yet another storage device according to an exemplary embodiment of this application.

[0033] Figure 9 shows a schematic diagram of yet another storage device according to an exemplary embodiment of this application.

[0034] Figure 10 shows a schematic diagram of yet another storage device according to an exemplary embodiment of this application.

[0035] Figures 11 to 13 show schematic diagrams of various semiconductor devices according to exemplary embodiments of this application.

[0036] Figures 14 to 17 show schematic diagrams of various correction circuits according to exemplary embodiments of this application.

[0037] Figure 18 shows a schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application.

[0038] Figure 19 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application.

[0039] Figure 20 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application.

[0040] Figure 21 shows a schematic diagram of yet another correction circuit according to an exemplary embodiment of this application.

[0041] Figure 22 shows a schematic diagram of yet another correction circuit according to an exemplary embodiment of this application. Detailed Implementation

[0042] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0043] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0044] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0045] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0046] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0047] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0048] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.

[0049] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0050] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0051] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0052] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0053] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0054] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0055] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0056] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in the example of Figure 2, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0057] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly along columns, and the output terminals can be connected collinearly along rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, a memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0058] The performance of semiconductor devices in memory cells can change with environmental variations. This performance variation can lead to changes in the memory cell's output, resulting in different read or calculation results from the in-memory computing system even with the same input signal and weighted data, thus affecting the system's read or calculation accuracy. For example, a transistor can control its channel current using gate voltage or substrate voltage. The gate voltage or substrate voltage serves as the input voltage of the memory cell, and the channel current serves as its output. The channel current is related to the input voltage and the threshold voltage, i.e., Id = f(Vg, Vth), where Id represents the channel current, Vg represents the gate voltage, Vth represents the threshold voltage, and f() represents the relationship function between the channel current and the input and threshold voltages. However, the threshold voltage Vth may vary with temperature, i.e., Vth = g(T), where T represents the temperature, and g() represents the relationship function between the threshold voltage and temperature; in other words, temperature affects the transistor's channel conduction capability. Therefore, at different temperatures, the channel current of a semiconductor device will be different, and the memory cell or memory cell group will generate different output currents, resulting in different read or calculation results, which leads to a decrease in the read accuracy or calculation accuracy of the memory device and the memory computing system.

[0059] In view of this, embodiments of this application propose a correction circuit, a storage device, a memory computing system, and an electronic device. The correction circuit uses a feedback control branch to correct the influence of environmental factors such as temperature on the conduction capability or channel current of the semiconductor device, stabilizes the output of the storage cell at different temperatures, thereby improving the read accuracy or calculation accuracy of the storage device and the memory computing system, and expanding the operating temperature range and application scenarios of the memory computing system.

[0060] Figure 3 shows a schematic diagram of a storage device according to an exemplary embodiment of the present application. As shown in Figure 3, the storage device 300 may include a storage circuit 310 and a correction circuit 320.

[0061] The storage circuit 310 may include a semiconductor device 311. The semiconductor device 311 may be used as a storage cell or part of a storage cell. The semiconductor device 311 may include a first terminal t1, a second terminal t2, and a first control terminal c1, with a first channel formed between the first terminal t1 and the second terminal t2. The first control terminal c1 can control the conduction capability of the first channel. The first control terminal c1 may be coupled to a correction voltage VT, which may be provided by a correction circuit 320. This correction circuit 320 adaptively obtains the correction voltage VT using a semiconductor device 321 matched to the semiconductor device 311, allowing the correction voltage VT to adapt to environmental factors (e.g., temperature). The influence of the correction voltage VT on the channel current or channel conduction capability of the semiconductor device 311 can reduce or offset the influence of environmental factors on the channel current or channel conduction capability of the semiconductor device 311. Thus, the reduction in read accuracy or calculation accuracy of the storage device and the memory system caused by changes in environmental factors can be reduced.

[0062] The correction circuit 320 may include a semiconductor device 321 and a feedback control branch 322. The semiconductor device 321 may include a third terminal t3, a fourth terminal t4, and a second control terminal c2. A second channel is formed between the third terminal t3 and the fourth terminal t4. The second control terminal c2 can control the conduction capability of the second channel. The third terminal t3 is coupled to a constant current I0. The feedback control branch 322 may be connected to the third terminal t3 and outputs a correction voltage VT based on the voltage at the third terminal t3. The second control terminal c2 is coupled to the correction voltage VT, which can be used to stabilize the channel current of the second channel. The semiconductor device 321 may be matched with the semiconductor device 311, and the correction voltage VT can be used at the first control terminal c1.

[0063] This application does not restrict the direction of the constant current I0. For example, it can flow from the third terminal t3 to the fourth terminal t4, or from the fourth terminal t4 to the third terminal t3. The arrows in Figure 3 are for illustrative purposes only.

[0064] According to some embodiments, the fourth terminal t4 can be coupled to the voltage V2 of the channel of the semiconductor device 321. This application does not limit the magnitude of the voltage V2; for example, it can include a positive supply voltage (VDD) or a negative supply voltage / ground voltage (VSS). For instance, voltage V2 can include a ground voltage. The feedback control branch 322 adaptively outputs a correction voltage VT based on the voltage of the third terminal t3. By controlling the channel conduction capability of the semiconductor device 321, it stabilizes the channel current of the semiconductor device 321 to, for example, a constant current I0, thereby reducing or offsetting the influence of environmental factors (e.g., temperature) on the channel current or channel conduction capability of the semiconductor device 321. Semiconductor device 321 is matched with semiconductor device 311. The channel current or channel conduction capability of the two are affected by environmental factors in the same or similar way. The correction voltage VT generated by semiconductor device 321 can be used to reduce or offset the influence of environmental factors on the channel current or channel conduction capability of semiconductor device 311, thereby reducing the reduction in read accuracy or calculation accuracy of storage devices and memory computing systems caused by changes in environmental factors.

[0065] According to some embodiments, the feedback control branch 322 may include a circuit from the third terminal t3 to the second control terminal c2. The constant current I0 may include a first component flowing through the semiconductor device 321 and a second component flowing through the feedback control branch 322. The first component corresponds to the channel current of the semiconductor device 321, and the second component tends to be 0. The second component is less than or equal to a first current threshold. The first current threshold is an error-tolerant current, and its value is not limited in this embodiment, as long as the second component can be considered equal to or approximately equal to 0 within the error tolerance range. Thus, the first component or channel current can tend to the constant current I0. The difference between the first component or channel current and the constant current I0 is less than or equal to the second current threshold. The second current threshold is an error-tolerant current, and its value is not limited in this embodiment, as long as the first component or channel current can be considered equal to or approximately equal to the constant current I0 within the error tolerance range. The second current threshold can be equal to the first current threshold. In addition, the feedback control branch 322 may include an output terminal, which may be connected to the second control terminal c2.

[0066] This application does not limit the manner in which the constant current I0 is provided. The constant current I0 can be generated by a current source or provided by a conversion circuit that converts voltage into current. For example, the current source can generate the constant current I0 based on a voltage V1. For example, the voltage V1 can include a voltage provided by a bandgap reference circuit. Furthermore, the current source can include a zero-temperature-coefficient (ZTC) current source, and the conversion circuit can include a current-mode DAC, etc. The constant current I0 is less affected by environmental factors. For example, the constant current I0 may be unaffected by temperature, or the effect of temperature on the constant current I0 may be negligible. The temperature coefficient of the constant current I0 can be low, for example, below the current temperature coefficient threshold. The effect of temperature on the constant current I0 is less than the effect of temperature on the threshold voltage of the semiconductor device. For example, both the effect of temperature on the constant current I0 and the effect of temperature on the threshold voltage of the semiconductor device affect the channel current, but the effect of temperature through the constant current I0 on the channel current is less than the effect of temperature through the threshold voltage of the semiconductor device on the channel current.

[0067] According to some embodiments, semiconductor device 321 may be matched with semiconductor device 311. Device parameters of semiconductor device 321 may be matched with device parameters of semiconductor device 311. For example, semiconductor device 321 and semiconductor device 311 may have at least one of the following parameters that are nearly identical or the same: threshold voltage, temperature coefficient of threshold voltage, channel conductance, temperature coefficient of channel conductance, transconductance, dimensional parameters, thermal parameters, or noise parameters, etc. Differences in device parameters between semiconductor devices 311 and 321 may include differences within permissible limits due to errors. Semiconductor devices 311 and 321 may be fabricated using the same or identical processes. For example, semiconductor devices 311 and 321 may be formed on the same substrate. Semiconductor devices 311 and 321 may include transistors. Semiconductor devices 311 and 321 may include transistors of the same type. For example, semiconductor devices 311 and 321 may include n-type transistors, or semiconductor devices 311 and 321 may include p-type transistors. Thus, the correction voltage of semiconductor device 321 can be used as the correction voltage of semiconductor device 311, and control terminals C1 and C2 can be used as correction terminals.

[0068] Figure 4 shows a schematic diagram of another storage device according to an exemplary embodiment of this application. As shown in Figure 4, according to some embodiments, the third terminal t3 and the second control terminal c2 can be directly connected, for example, by wiring. The correction voltage VT can be directly determined based on the voltage of the third terminal t3. The second control terminal c2 may include a voltage control terminal, through which no current or a current less than a threshold will flow. The threshold is an error-tolerant current value, and the embodiments of this application do not limit its value, as long as the current can be considered equal to or approximately equal to 0 within the error tolerance range. In this way, the feedback control branch can have a simple structure and control method, and the design, manufacturing, and control of the circuit are simplified.

[0069] Figure 5 shows a schematic diagram of another storage device according to an exemplary embodiment of this application. As shown in Figure 5, according to some embodiments, the feedback control branch 322 may include a voltage adjustment circuit 3222. The voltage adjustment circuit 3222 may be connected between the constant current and the third terminal t3. A voltage drop may be generated across the voltage adjustment circuit 3222. Thus, the voltage at the third terminal t3 and the voltage fed back to the second control terminal c2 may be different. The voltage at the third terminal t3 can be controlled to be different from the correction voltage coupled to the second control terminal c2, so that changes in the correction voltage caused by environmental factors (e.g., temperature) will not affect the third terminal t3 in the same way. This prevents a simple correlation between the correction voltage and the voltage at the third terminal from limiting the voltage value of the third terminal. In this way, it can prevent the voltage at the third terminal t3 of the semiconductor device 321 from differing too much from the voltage at the first terminal t1 of the semiconductor device 311, which would affect the correction effect of the correction voltage. According to some embodiments, the voltage adjustment circuit 3222 may include a transistor or a resistor; for example, the transistor may include a P-type transistor or an N-type transistor, and the source or drain of the transistor may be coupled to a constant current, the drain or source may be connected to a third terminal t3, and the gate may be coupled to a voltage V3 to drive the transistor to operate.

[0070] Figure 6 shows a schematic diagram of another storage device according to an exemplary embodiment of this application. As shown in Figure 6, according to some embodiments, the feedback control branch 322 may include a feedback control circuit 3221. The feedback control circuit 3221 may be coupled to a reference voltage Vr and connected to a third terminal t3. The feedback control circuit 3221 may adjust and output a correction voltage VT based on the voltage at the third terminal t3 and the reference voltage Vr. The introduction of the feedback control circuit 3221 and the reference voltage can prevent a simple correlation between the correction voltage and the voltage at the third terminal from limiting the voltage value at the third terminal. In this way, it can prevent the voltage at the third terminal t3 of the semiconductor device 321 from differing too much from the voltage at the first terminal t1 of the semiconductor device 311, thus preventing the correction effect of the correction voltage from being affected.

[0071] According to some embodiments of this application, the feedback control circuit 3221 may include an operational amplifier. For example, FIG7 shows a schematic diagram of a correction circuit according to an exemplary embodiment of this application. As shown in FIG7, the correction circuit 700 may include a semiconductor device 710 and a feedback control circuit 720, and the feedback control circuit 720 may include an operational amplifier 721. The operational amplifier 721 may include input terminals in1 and in2 and an output terminal out1. Input terminal in1 may be coupled to a reference voltage Vr, input terminal in2 may be connected to the third terminal t3 of the semiconductor device 710, and output terminal out1 may be connected to the second control terminal c2 of the semiconductor device 710. Output terminal out1 may output a correction voltage VT. Input terminal in1 may include an inverting input terminal, and input terminal in2 may include a non-inverting input terminal; or, input terminal in1 may include a non-inverting input terminal, and input terminal in2 may include an inverting input terminal.

[0072] Based on the characteristics of the operational amplifier, such as virtual short, the voltage value at input terminal in2 can be determined based on the voltage at input terminal in1, for example, based on a reference voltage Vr. The temperature coefficient of the reference voltage Vr can be low, for example, below the voltage temperature coefficient threshold. The voltage at input terminal in2 can be equal to or close to the voltage at input terminal in1. The voltage difference between input terminals in1 and in2 can be less than or equal to a first voltage threshold, which is an error tolerance voltage. This application embodiment does not limit its value; as long as the first voltage threshold can be considered equal to or approximately equal to 0 within the error tolerance range, it is acceptable. Furthermore, based on the characteristics of the operational amplifier, such as virtual open, current less than the threshold or no current will flow through input terminal in2. The channel current of semiconductor device 321 can be equal to or close to the constant current I0. The channel current of semiconductor device 321 can be determined based on the constant current I0. The description of the threshold is the same as in the above embodiments and will not be repeated here.

[0073] Referring again to Figure 3, according to some embodiments, the semiconductor device 311 may further include a third control terminal c3. The third control terminal c3 can be used as a signal input terminal. The third control terminal c3 can be coupled to an input signal Vin and control the conduction capability of the first channel of the semiconductor device 311 based on the input signal Vin. During reading, the semiconductor device 311 can output the stored weight data in the form of channel current under the drive of the input signal. During calculation, the semiconductor device 311 can perform calculations based on the stored weight data and the input signal received through the third control terminal c3. The calculation result is output in the form of channel current through the combined control of the channel conduction capability by the weight data and the input signal.

[0074] The storage circuit may include multiple semiconductor devices 311. The input signals Vin of different semiconductor devices 311 may be the same or different. This application does not impose any restrictions. The specific input signals are related to the service performed by the storage circuit.

[0075] According to some embodiments, semiconductor device 321 may further include a fourth control terminal c4. The fourth control terminal c4 corresponds to the third control terminal c3. The fourth control terminal c4 may be coupled to a voltage Vinr. The voltage Vinr may be referred to as an input reference voltage, and the fourth control terminal c4 may be referred to as an input reference terminal. The voltage Vinr may be determined based on the voltage of the input signal Vin. The storage circuit includes a plurality of semiconductor devices 311, and some or all of the input signals Vin of the plurality of semiconductor devices may be used to determine the voltage Vinr. For example, the voltage Vinr may be determined based on the maximum voltage, minimum voltage, or average of the maximum and minimum voltages of the input signals Vin of the plurality of semiconductor devices. Alternatively, the voltage Vinr may be determined based on the average or mode of the input signals Vin of the plurality of semiconductor devices. For example, the voltage Vinr may be equal to or approximately equal to the maximum voltage, minimum voltage, or average of the maximum and minimum voltages of the input signals Vin of the plurality of semiconductor devices, or it may be equal to or approximately equal to the average or mode of the input signals Vin of the plurality of semiconductor devices.

[0076] According to some embodiments, semiconductor devices 311 and 321 may further include more control terminals. For example, please refer to FIG8, which shows a schematic diagram of another memory device according to an exemplary embodiment of this application. As shown in FIG8, semiconductor device 311 may include control terminals c1, c3, ..., c2m-1, where m is a positive integer. Semiconductor device 321 may include control terminals c2, c4, ..., c2n, where n is a positive integer. Control terminals other than c1 to c4 may be referred to as reference control terminals. The reference control terminals c2p-1 and c2q can be coupled to reference voltages V2p-1 and V2q, respectively, where p∈(2,m] and q∈(2,n). The reference voltages V2p-1 and V2q can include fixed bias voltages. During calculation or reading, the reference control terminals of semiconductor device 311 can control the conduction capability of the channel of semiconductor device 311 with a stable reference voltage, preventing the reference voltage at the reference control terminals from affecting the output result. Similarly, when the correction circuit generates the correction voltage, the reference control terminals of semiconductor device 321 can control the conduction capability of the channel of semiconductor device 321 with a stable reference voltage, ensuring that the output correction voltage is not affected by the reference voltage. The influence of the reference voltage at the control terminal. The reference control terminals and reference voltages of semiconductor devices 311 and 321 can correspond to each other. For example, when p = q, reference control terminals c2p-1 and c2q can correspond, and reference control terminals c2p-1 and c2q can include ports of the same type. For example, when p = q, reference voltages V2p-1 and V2q can correspond, and the difference between reference voltages V2p-1 and V2q can be less than a second voltage threshold. The second voltage threshold is an error tolerance voltage, and the embodiments of this application do not limit its value, as long as the second voltage threshold can be considered equal to or approximately equal to 0 within the error tolerance range.

[0077] According to some embodiments, n can be equal to m, so that semiconductor device 311 and semiconductor device 321 are matched and can include devices of the same type.

[0078] According to some embodiments, n may not be equal to m, thus semiconductor device 311 and semiconductor device 321 may include different numbers of reference control terminals. When one of semiconductor device 311 and semiconductor device 321 includes one or more reference control terminals that do not correspond to the reference control terminals of the other semiconductor device 311 and semiconductor device 321, by controlling the coupling of the one or more reference control terminals to their corresponding reference voltages, it is possible to prevent the one or more reference control terminals from affecting calibration, reading, or calculation. Thus, semiconductor device 311 and semiconductor device 321 can be referred to as controlled matching. In the case of controlled matching, the calibration circuit 320 can still generate a calibration voltage for semiconductor device 311. Matching semiconductor device 321 with semiconductor device 311 can include controlled matching of semiconductor device 321 with semiconductor device 311.

[0079] According to some embodiments, the storage circuit 310 may include an array of semiconductor devices 311. The third control terminal c3 of the semiconductor device 311 can be used as a signal input terminal (e.g., input IN in FIG. 2), and the first terminal t1 or the second terminal t2 of the semiconductor device 311 can be used as a signal output terminal (e.g., output OUT in FIG. 2). The first control terminal c1 of the semiconductor device 311 can be used as a correction terminal. The horizontal and vertical directions represent the directions in the figures. The horizontal direction may include the row direction, and the vertical direction may include the column direction, or vice versa. The signal input terminals of the semiconductor devices 311 arranged in the horizontal direction can be connected to the same input line, and the signal output terminals of the semiconductor devices 311 arranged in the vertical direction can be connected to the same output line, or vice versa. Semiconductors 311 connected to the same input line can be coupled to the same input signal Vin. Semiconductor devices 311 connected to different input lines can be coupled to different input signals Vin. Different input signals Vin can include the same or different signal values, such as the same or different voltage values. The signal input terminals of semiconductor devices 311 within the memory cell group can be coupled to multiple input signals respectively. During computation, the memory cell group converts multiple input signals into multiple output signals based on the weight data stored in each semiconductor device 311 within the memory cell group, and outputs a cumulative signal of the multiple output signals on the same output line.

[0080] The first control terminals c1 of semiconductor devices 311 arranged in the horizontal direction can be connected to the same trace, or the first control terminals c1 of semiconductor devices 311 arranged in the vertical direction can be connected to the same trace, or the first control terminals c1 of semiconductor devices 311 arranged in a two-dimensional array in both the horizontal and vertical directions can be connected to the same trace. The first control terminals connected to the same trace can receive correction voltages through that same trace, simplifying the method of applying correction voltages to multiple semiconductor devices.

[0081] According to some embodiments, in addition to being used as a calibration terminal, the first control terminal c1 may also have other uses. For example, the first control terminal c1 may also be used as an erasure terminal. The wiring method of the first control terminal c1 can be determined according to this other use. In this way, the wiring method of the first control terminal can enable the first control terminal to perform multiple functions.

[0082] Figure 9 shows a schematic diagram of another storage device according to an exemplary embodiment of this application. As shown in Figure 9, the storage device 300 may include a storage circuit 310 and a correction circuit 320. The correction circuit 320 may include a plurality of semiconductor devices 321. The plurality of semiconductor devices 321 may be connected in parallel. The second control terminals c2 of the plurality of semiconductor devices 321 may be connected, and the third terminals t3 of the plurality of semiconductor devices 321 may be connected. The correction circuit including a plurality of semiconductor devices can reduce the impact of semiconductor device process errors and improve the driving capability of the correction voltage to subsequent circuits. In addition, the correction circuit including a plurality of semiconductor devices can improve reliability. Even if the plurality of semiconductor devices includes a semiconductor device that is not working properly, the remaining working semiconductor devices can still ensure that the correction circuit works properly.

[0083] According to some embodiments, multiple fourth terminals t4 can be connected. Multiple reference control terminals c2q can be connected, where q∈(2,n). Connecting corresponding ports can help simplify wiring and the application of control signals (e.g., reference voltage). However, the embodiments are not limited to this; the multiple fourth terminals t4 may not be connected. The multiple reference control terminals c2q may not be connected. Not connecting corresponding ports allows for flexible control of different ports of the semiconductor device. In addition, whether corresponding ports are connected can be consistent with the connection relationship of each port of the semiconductor device 311 that matches the semiconductor device 321 in the storage circuit. In this way, the same or similar wiring methods can be used in the storage circuit and the correction circuit, and the circuit design can be reused.

[0084] Figure 10 shows a schematic diagram of another storage device according to an exemplary embodiment of this application. As shown in Figure 10, the storage device 300 may include a storage circuit 310 and a correction circuit 320. The correction circuit 320 may further include a drive circuit 323. The drive circuit 323 may be connected between the second control terminal c2 of the semiconductor device 321 and the first control terminal c1 of the semiconductor device 311, for boosting the output power of the correction voltage VT output by the feedback control branch 322. The output power of the correction voltage VT output by the feedback control branch 322 via the drive circuit 323 is higher than the output power of the correction voltage VT directly output by the feedback control branch 322. The drive circuit 323 can boost the power of the input signal before outputting it without changing the voltage of the input signal, i.e., without changing the correction voltage VT. The output voltage of the drive circuit 323 may be the same as the input voltage of the drive circuit 323. The output voltage being the same as the input voltage may include: the difference between the input voltage and the output voltage being less than a threshold value, which is an error tolerance voltage value. This embodiment of the application does not limit its value, as long as it can be considered equal to or approximately equal to 0 within the error tolerance range. In this way, the correction voltage can stably correct the effects of environmental factors (e.g., temperature) on the memory circuit, and can correct a larger number of semiconductor devices / memory cells in the memory circuit.

[0085] According to some embodiments, the correction circuit 320 may include a plurality of semiconductor devices 321, which can improve the driving capability and driving stability of the correction voltage on the driving circuit 323, thereby enabling the driving circuit 323 to more stably increase the driving power of the correction voltage.

[0086] Semiconductor devices 311, 321, and 710 may include flash memory devices, ferroelectric devices, DRAM devices, transistor devices (e.g., thin-film transistor devices), etc. Thus, semiconductor devices 311, 321, and 710 may include a gate and a substrate. The gate or substrate can control the conduction capability of the channel and can be used as a control terminal for semiconductor devices 311, 321, and 710.

[0087] For example, Figures 11 to 13 show schematic diagrams of various semiconductor devices according to exemplary embodiments of this application.

[0088] Referring to FIG11, semiconductor device 1100 may include non-control electrodes 1101 and 1102 and control electrodes 1103, 1104, and 1105. Semiconductor device 1100 may include a split-gate floating-gate transistor, such as a tri-gate floating-gate transistor. Semiconductor device 1100 may be used as a memory cell. Control electrode 1103 may include a control gate (CG), control electrode 1104 may include a select gate (SG) or a word line (WL), and control electrode 1105 may include an erase gate (EG). According to some embodiments, semiconductor device 1100 may also include a back control electrode, which may include a substrate or a back gate. Non-control electrodes 1101 and 1102 may each include a source and a drain, respectively. Non-control electrode 1101 may include a source, and non-control electrode 1102 may include a drain; alternatively, non-control electrode 1102 may include a source, and non-control electrode 1101 may include a drain.

[0089] Semiconductor device 1100 can be used in semiconductor devices 311, 321, and 710. According to some example embodiments, non-control electrode 1101 can be used as the first terminal t1 and the third terminal t3, and non-control electrode 1102 can be used as the second terminal t2 and the fourth terminal t4; alternatively, non-control electrode 1101 can be used as the second terminal t2 and the fourth terminal t4, and non-control electrode 1102 can be used as the first terminal t1 and the third terminal t3. According to some example embodiments, control electrode 1103 can be used as control terminals c3 and c4, and control electrode 1104 or 1105 can be used as control terminals c1 and c2. Thus, the control electrode 1103 (e.g., CG) of semiconductor device 1100 serves as the signal input terminal of the semiconductor device, allowing for precise control of the input signal. According to some example embodiments, control electrode 1103 can be used as control terminals c1 and c2, and control electrode 1104 or 1105 can be used as control terminals c3 and c4. Control electrodes or back control electrodes not used as control terminals c1 to c4 can be used as reference control terminals, such as control terminals c2p-1 and c2q, where p∈(2,m] and q∈(2,n). Thus, the control electrode 1103 (e.g., CG) of the semiconductor device 1100 can be used as a correction terminal to accurately correct the influence of environmental factors (e.g., temperature) on the channel's conductivity.

[0090] Referring to FIG12, semiconductor device 1200 may include uncontrolled electrodes 1201 and 1202 and controlled electrodes 1203 and 1204. Semiconductor device 1200 may include a split-gate floating-gate transistor, such as a dual-gate floating-gate transistor. Semiconductor device 1200 may be used as a memory cell. For example, controlled electrode 1203 may include a control gate (CG), and controlled electrode 1204 may include a select gate (SG) or a word line (WL). According to some embodiments, semiconductor device 1200 may also include a back controlled electrode, which may include a substrate or a back gate. Uncontrolled electrodes 1201 and 1202 may each include a source and a drain, respectively. Uncontrolled electrode 1201 may include a source, and uncontrolled electrode 1202 may include a drain; alternatively, uncontrolled electrode 1202 may include a source, and uncontrolled electrode 1201 may include a drain.

[0091] Semiconductor device 1200 can be used with semiconductor devices 311, 321, and 710. According to some example embodiments, non-control electrode 1201 can be used as the first terminal t1 and the third terminal t3, and non-control electrode 1202 can be used as the second terminal t2 and the fourth terminal t4; alternatively, non-control electrode 1201 can be used as the second terminal t2 and the fourth terminal t4, and non-control electrode 1202 can be used as the first terminal t1 and the third terminal t3. According to some example embodiments, control electrode 1203 can be used as control terminals c3 and c4, and control electrode 1204 can be used as control terminals c1 and c2. Thus, the control electrode 1203 (e.g., CG) of semiconductor device 1200 serves as the signal input terminal of the semiconductor device, allowing for precise control of the input signal. According to some example embodiments, control electrode 1203 can be used as control terminals c1 and c2, and control electrode 1204 can be used as control terminals c3 and c4. Control electrodes or back control electrodes not used as control terminals c1 to c4 can be used as reference control terminals, such as control terminals c2p-1 and c2q, where p∈(2,m] and q∈(2,n). Thus, the control electrode 1203 (e.g., CG) of the semiconductor device 1200 can be used as a correction terminal to more accurately correct the effects of environmental factors (e.g., temperature) on the channel's conductivity.

[0092] Referring to Figure 13, semiconductor device 1300 may include non-control electrodes 1301 and 1302 and control electrode 1303. Although Figure 13 shows semiconductor device 1300 including a non-floating gate transistor, the embodiment is not limited thereto, and semiconductor device 1300 may include a floating gate transistor, a ferroelectric field-effect transistor, a thin-film transistor (e.g., IGZO, MoS2, etc.), etc. Semiconductor device 1300 may be used as a memory cell or part of a memory cell (e.g., as a read tube). Control electrode 1303 may include a gate. Semiconductor device 1300 may also include a back control electrode 1304, which may include a substrate or a back gate. Non-control electrodes 1301 and 1302 may each include a source and a drain, respectively. Non-control electrode 1301 may include a source, and non-control electrode 1302 may include a drain, or non-control electrode 1302 may include a source, and non-control electrode 1301 may include a drain.

[0093] Semiconductor device 1300 can be used in semiconductor devices 311, 321, and 710. According to some example embodiments, non-control electrode 1301 can be used as the first terminal t1 and the third terminal t3, and non-control electrode 1302 can be used as the second terminal t2 and the fourth terminal t4; alternatively, non-control electrode 1301 can be used as the second terminal t2 and the fourth terminal t4, and non-control electrode 1302 can be used as the first terminal t1 and the third terminal t3. According to some example embodiments, back control electrode 1304 can be used as control terminals c1 and c2, and control electrode 1303 can be used as control terminals c2 and c4. Thus, control electrode 1303 of semiconductor device 1300 serves as the signal input terminal of the semiconductor device, allowing for precise control of the input signal. According to some example embodiments, back control electrode 1304 can be used as control terminals c3 and c4, and control electrode 1303 can be used as control terminals c1 and c2. Thus, the control electrode 1303 of the semiconductor device 1300 is used as a calibration terminal, which can more accurately correct for the effects of environmental factors (e.g., temperature).

[0094] Referring to Figures 3 and 11 to 13, according to some embodiments, the first control terminal c1 may have other uses besides serving as a calibration terminal. For example, when the first control terminal c1 includes control poles 1104 or 1105, it can also be used as, for example, WL or EG. For example, when it can also be used as EG, the first control terminal c1 can be used as a calibration terminal during reading or calculation, and as an erasing terminal during erasure. The wiring method of the first control terminal c1 can be determined according to these other uses. In this way, the wiring method of the first control terminal can enable it to perform multiple functions.

[0095] According to some embodiments, the second control terminal c2 may include a substrate, and the fourth control terminal c4 may include a gate, such as a control electrode. Correspondingly, the first control terminal c1 may include a substrate, and the third control terminal c3 may include a gate. In this way, using the substrate instead of the gate as the calibration terminal can avoid the design limitations caused by the versatility of the gate, and allow for more flexible selection of the control terminal connection method.

[0096] According to some embodiments, control terminals c2 and c4 may each include a first gate and a second gate, such as control electrodes 1103 and 1104. Correspondingly, control terminals c1 and c3 include different gates. In this way, the first control terminal c1 can perform multiple functions, improving its utilization rate, while avoiding the need for substrate dicing and reducing process complexity.

[0097] According to some embodiments, the storage circuit may include multiple semiconductor devices with shared or interconnected channels, and the correction circuit may utilize at least one of these semiconductor devices to correct other conductor devices. For example, the storage circuit may include a first semiconductor device and a third semiconductor device, the third semiconductor device sharing or interconnecting with the first semiconductor device's channel, and a correction voltage used to correct the third semiconductor device through the first semiconductor device. As described above, the correction voltage can be used to reduce or offset the influence of environmental factors on the channel current or channel conduction capability of the first semiconductor device. Because the third semiconductor device shares or interconnects with the first semiconductor device's channel, the channel of the first semiconductor device, after correction by the first correction voltage, can reduce or offset the influence of environmental factors on the output of the third semiconductor device. The storage circuit may include multiple third semiconductor devices that may be connected in series and share or interconnected channels.

[0098] The above embodiments can be used to correct three-dimensional storage circuits, such as NAND flash memory.

[0099] According to some embodiments, multiple semiconductor devices with shared or interconnected channels can be uniformly controlled by a single semiconductor device; and the currently activated semiconductor device can be selected by signals from the control terminals of the multiple semiconductor devices. For example, the above storage circuit may further include a fourth semiconductor device connected to the third semiconductor device for coupling the input signal of the third semiconductor device and inputting the input signal to the third semiconductor device.

[0100] Figure 20 shows a schematic diagram of a memory circuit according to an exemplary embodiment of this application. Referring to Figure 20, the memory circuit 2000 includes semiconductor devices 2010, 2020, and 2040. Semiconductor devices 2010, 2020, and 2030 may include transistors. Semiconductor device 2010 may serve as a first semiconductor device, and its control terminal may be coupled to a correction voltage VT for correcting the channel current or channel conduction capability of semiconductor device 2030 that shares a channel with it or is interconnected with it. Semiconductor device 2030 may serve as a third semiconductor device, acting as a memory cell in the memory circuit for storing data. Multiple memory cells sharing a channel or interconnected with it may be included; for example, the memory circuit 2000 may include multiple semiconductor devices 2030 connected in series. Semiconductor device 2040 can serve as the fourth semiconductor device described above, used to input input signals to the connected memory cell. For example, the control terminal of semiconductor device 2040 can be coupled to the input signal and input the input signal to the selected semiconductor device 2030. Optionally, the input signal can turn on semiconductor device 2040, and when semiconductor device 2040 is turned on, the input signal is input to the selected semiconductor device 2030. Alternatively, the non-control terminal of semiconductor device 2040 can be coupled to the input signal, and the control terminal can turn on semiconductor device 2040, causing the input signal to be input to the selected semiconductor device 2030. For multiple semiconductor devices 2030, the currently active semiconductor device can be selected by a control terminal signal (e.g., a signal coupled to a word line). The data stored in the currently active semiconductor device can be read or calculations can be performed based on its stored data.

[0101] According to some embodiments, semiconductor device 2040 and semiconductor device 2030 may be of the same or different types. For example, semiconductor device 2030 may include a floating-gate transistor, and semiconductor device 2040 may include a floating-gate transistor or a non-floating-gate transistor. Semiconductor device 2010 and semiconductor device 2030 may be of the same type, for example, they may include a floating-gate transistor or other transistors with storage functions. Semiconductor device 2010 and semiconductor device 2030 may be of different types; for example, semiconductor device 2030 may include a floating-gate transistor, and semiconductor device 2010 may include a non-floating-gate transistor.

[0102] According to some embodiments, the semiconductor device 2010 may include any layer of semiconductor devices in the stacking direction of the three-dimensional memory circuit. This application does not limit the number of semiconductor devices 2010; for example, one semiconductor device in a series-connected string may be selected for temperature correction, or more than one semiconductor device in a series-connected string may be selected for temperature correction. The control terminal of the semiconductor device 2010 may be coupled to a correction voltage to correct the effects of environmental factors (e.g., temperature) on the reading or computation of the memory cell.

[0103] This application does not limit the location and number of semiconductor devices 2010. For example, a series of semiconductor devices sharing a common channel or interconnected channels can be calibrated using a single semiconductor device, or multiple semiconductor devices can be used for calibration. The semiconductor device used for calibration can be located near both ends or near the middle. According to some embodiments, the memory circuit may include multiple semiconductor devices 2010, which can be uniformly or non-uniformly arranged among multiple semiconductor devices 2030 connected in series. By arranging multiple semiconductor devices 2010, the impact of semiconductor device process errors can be further reduced, allowing the calibration voltage to more accurately reduce or offset the influence of environmental factors on the channel current or channel conductivity of the semiconductor devices.

[0104] According to some embodiments, the correction circuit may include more than one semiconductor device to more accurately reduce or counteract the effects of environmental factors on the channel current or channel conduction capability of the semiconductor device. For example, the correction circuit may further include a fifth semiconductor device that shares or interconnects with the channel of the second semiconductor device. Thus, the correction circuit may include a structure similar to that of the memory circuit, enabling a correction voltage generated based on this similar structure to better correct the semiconductor device of the memory circuit.

[0105] Figure 21 shows a schematic diagram of another correction circuit according to an exemplary embodiment of this application. Referring to Figure 21, the correction circuit 2100 includes a semiconductor device 2110, a semiconductor device 2120, and a feedback control branch 322. The semiconductor device 2110 can serve as the second semiconductor device described above, and its control terminal 2111 can serve as the second control terminal c2. One end of the non-control terminal of the semiconductor device 2110 can be connected to the feedback control branch 322 via the semiconductor device 2120, and the other end can be coupled to a voltage. This application does not limit the magnitude of the voltage; for example, the voltage can include a positive supply voltage (VDD), a negative supply voltage (VSS), or a ground voltage. The coupled voltage is related to the type of transistor, and the voltage can be used to form the bias voltage of the conducting transistor. The semiconductor device 2120 can serve as the fifth semiconductor device described above. The correction circuit 2100 may also include a driving circuit 323. The description of the second semiconductor device, the feedback control branch, and the driving circuit can be found in the foregoing embodiments.

[0106] This application does not limit the number of fifth semiconductor devices. For example, the correction circuit may include one or more fifth semiconductor devices. For example, FIG21 shows one semiconductor device 2120, and FIG22 shows more than one semiconductor device 2220, which can serve as the fifth semiconductor device. This application also does not limit the location of the fifth semiconductor device. For example, although FIG21 shows that semiconductor device 2120 is disposed between feedback control branch 322 and semiconductor device 2110, the embodiment is not limited thereto, and semiconductor device 2110 may be disposed between semiconductor device 2120 and feedback control branch 322. The semiconductor devices of the correction circuit 2100 can be connected in series in any manner.

[0107] According to some embodiments, the second semiconductor device may include a floating-gate transistor or a non-floating-gate transistor. The fifth semiconductor device may include a floating-gate transistor or other transistors with storage functionality. The fifth semiconductor device may use the same or similar transistors as the fourth semiconductor device, for example, it may be fabricated using the same or the same process.

[0108] According to some embodiments, the correction circuit 2100 may include a plurality of second semiconductor devices connected in series. This can further reduce the impact of semiconductor device process errors, allowing the correction voltage to more accurately reduce or offset the effects of environmental factors on the channel current or channel conduction capability of the semiconductor devices. According to some embodiments, the number of second semiconductor devices connected in series may be the same as the number of first semiconductor devices connected in series.

[0109] According to some embodiments, the fifth semiconductor device can be configured to store non-zero data, such as data "1". When the fourth semiconductor device stores data "0", its output will be a signal representing "0" during reading or calculation by the storage circuit, and it is less affected by environmental factors. Even if the fifth semiconductor device stores non-zero data, its correction result has little impact on the output signal representing "0". When the fourth semiconductor device stores non-zero data (e.g., data "1"), its output is more affected by environmental factors during reading or calculation by the storage circuit compared to the case where the output is "0". Configuring the fifth semiconductor device of the correction circuit to store non-zero data (e.g., data "1") allows for a higher degree of matching between the fifth and fourth semiconductor devices when they are more affected by environmental factors. This allows the correction voltage generated by the correction circuit to more effectively reduce or offset the impact of environmental factors on the channel current or channel conduction capability of the semiconductor devices in the storage circuit.

[0110] According to some embodiments, the control terminal of the fifth semiconductor device (e.g., control terminal 2121) can be coupled with a voltage that is the same as or similar to the voltage coupled to the control terminal of the fourth semiconductor device in the read or compute state. This allows for a higher degree of matching between the fifth and fourth semiconductor devices, thereby enabling the correction voltage generated by the correction circuit to more accurately reduce or offset the influence of environmental factors on the channel current or channel conduction capability of the semiconductor devices in the memory circuit in the operating state.

[0111] According to some embodiments, the correction circuit may include multiple fifth semiconductor devices connected in series, matched with multiple fourth semiconductor devices connected in series. For example, the number of fifth semiconductor devices connected in series may be the same as the number of fourth semiconductor devices connected in series. This allows the correction circuit and the portion of the memory circuit to be corrected to have the same or similar structure, resulting in a higher degree of matching between the multiple fifth semiconductor devices and the multiple fourth semiconductor devices. Consequently, the correction voltage generated by the correction circuit can more accurately reduce or offset the influence of environmental factors on the channel current or channel conduction capability of the semiconductor devices in the memory circuit. Optionally, the semiconductor devices in the correction circuit may reuse some of the structure in the memory circuit, reducing design complexity.

[0112] According to some embodiments, when the correction circuit includes multiple fifth semiconductor devices, all or some of these fifth semiconductor devices can store non-zero data. For example, one fifth semiconductor device can store non-zero data. The control terminal of the fifth semiconductor device storing zero data is coupled to the voltage that turns on the fifth semiconductor device. This improves the matching degree between the multiple fifth semiconductor devices and the multiple fourth semiconductor devices used in reading or calculation, thereby allowing the correction voltage generated by the correction circuit to more accurately reduce or offset the influence of environmental factors on the channel current or channel conduction capability of the semiconductor devices in the storage circuit.

[0113] According to some embodiments, the data stored in the fifth semiconductor device is not limited; for example, it can store "0" or "1". The fifth semiconductor device can be coupled with a voltage used to turn on the fifth semiconductor device.

[0114] According to some embodiments, the correction circuit may further include a sixth semiconductor device connected to the second and fifth semiconductor devices for coupling a second voltage. Thus, the correction circuit may include a structure matching the third semiconductor device, thereby enabling the correction voltage generated by a correction circuit based on a similar memory circuit structure to more accurately correct the semiconductor devices of the memory circuit.

[0115] Figure 22 shows a schematic diagram of another correction circuit according to an exemplary embodiment of this application. Referring to Figure 22, the correction circuit 2200 includes semiconductor device 2210, semiconductor device 2220, semiconductor device 2230, and feedback control branch 322. Semiconductor device 2210 can serve as a second semiconductor device, and its control terminal 2211 can serve as a second control terminal c2. One end of the non-control terminal of semiconductor device 2210 can be connected to feedback control branch 322 via semiconductor devices 2220 and 2230, and the other end can be coupled to a voltage. This application does not limit the magnitude of the voltage. For example, the voltage can include a positive supply voltage (VDD), a negative supply voltage (VSS), or a ground voltage. The coupled voltage is related to the type of transistor, and the voltage can be used to form a bias voltage for the conducting transistor. Semiconductor device 2220 can serve as the fifth semiconductor device mentioned above. The control terminal of the fifth semiconductor device (e.g., control terminal 2221) can be coupled to a voltage that is the same as or similar to the voltage coupled to the control terminal of the fourth semiconductor device in the read or calculate state. The correction circuit 2200 may further include a drive circuit 323. Descriptions of the second semiconductor device, the fifth semiconductor device, the feedback control branch, and the drive circuit can be found in the foregoing embodiments. Although FIG22 shows semiconductor device 2220 disposed between semiconductor device 2210 and semiconductor device 2230, the embodiments are not limited thereto, and the semiconductor devices of the correction circuit 2200 may be connected in series in any manner.

[0116] According to some embodiments, the sixth semiconductor device 2230 may include a floating-gate transistor or a non-floating-gate transistor. The second voltage may include a voltage that turns on the sixth semiconductor device. For example, the semiconductor device 2230 may include a control terminal 2231 for coupling to the second voltage.

[0117] In the embodiments of this application, serial connection refers to the connection of different non-control terminals of semiconductor devices to each other, such as the connection of the source of one semiconductor device to the drain of another semiconductor device connected in series with it.

[0118] Figures 14 to 17 show schematic diagrams of various correction circuits according to exemplary embodiments of this application.

[0119] Figure 14 illustrates a correction circuit 1400. Referring to Figure 14, the correction circuit 1400 may include a semiconductor device 1410 and a feedback control circuit 1420. The semiconductor device 1410 may include non-control terminals 1411 and 1412 and control terminals 1413, 1414, and 1415. The semiconductor device 1410 may include a split-gate floating-gate transistor, such as a tri-gate floating-gate transistor. Control terminal 1413 may include a control gate (CG), control terminal 1414 may include a select gate (SG) or a word line (WL), and control terminal 1415 may include an erase gate (EG). According to some embodiments, the semiconductor device 1410 may also include a back control terminal. The feedback control circuit 1420 may include an operational amplifier 1421. Input in2 of the operational amplifier 1421 is coupled to a reference voltage Vr, and input in1 is connected to the non-control terminal 1411 of the semiconductor device 1410. The control terminal 1413 of semiconductor device 1410 can be used as an input reference terminal, the control terminal 1414 can be used as a reference control terminal, the control terminal 1415 can be used as a correction terminal, and the non-control terminal 1412 can be coupled to, for example, voltage V2. The output voltage of the operational amplifier 1421 can be used as a correction voltage for use with a semiconductor device matched to semiconductor device 1410 in the storage circuit, such as semiconductor device 311. The output of operational amplifier 1421 can be connected, for example, directly to the correction terminal of a semiconductor device, such as the first control terminal c1 of semiconductor device 311.

[0120] According to some embodiments, the correction circuit 1400 may further include a drive circuit 1430. The drive circuit 1430 may receive the output of the operational amplifier 1421. The drive circuit 1430 may boost the power of the input signal before outputting it without changing the voltage of the input signal, i.e., without changing the correction voltage VT. The output voltage of the drive circuit 1430 may be the same as the input voltage of the drive circuit 1430. The output voltage being the same as the input voltage may include: the difference between the input voltage and the output voltage being less than a threshold value, which is an error tolerance voltage value. This embodiment does not limit its value, as long as it can be considered equal to or approximately equal to 0 within the error tolerance range. In this way, the correction voltage can stably correct the effects of environmental factors (e.g., temperature) on the storage circuit and can correct a larger number of semiconductor devices / storage cells in the storage circuit. The output terminal of the drive circuit 323 may be connected to the correction terminal of a semiconductor device, such as the first control terminal c1 of the semiconductor device 311. The drive circuit 1430 may include an operational amplifier.

[0121] According to some embodiments, referring to FIG14, the correction circuit 1400 may include a plurality of semiconductor devices 1410. The plurality of semiconductor devices 1410 may be connected in parallel. The non-control terminals 1411 of the plurality of semiconductor devices 1410 may be connected to each other and connected to the input terminal of operational amplifier 1421. Additionally, the non-control terminals 1411 of the plurality of semiconductor devices 1410 may be coupled to a constant current I0. The control terminals 1415 of the plurality of semiconductor devices 1410 may be connected to each other and connected to the output terminal of operational amplifier 1421. Thus, by including a plurality of semiconductor devices, the correction circuit can reduce the impact of semiconductor device process errors and improve the driving capability of the correction voltage to subsequent circuits. Furthermore, including a plurality of semiconductor devices improves reliability; even if a malfunctioning semiconductor device is included among the plurality of semiconductor devices, the remaining malfunctioning semiconductor devices can still ensure the normal operation of the correction circuit.

[0122] According to some embodiments, multiple non-control electrodes 1412 can be connected to each other. Multiple control electrodes 1413 can be connected to each other. Multiple control electrodes 1414 can be connected to each other. Connecting corresponding control electrodes or non-control electrodes to each other can help simplify wiring and the way control signals (e.g., reference voltage) are applied. However, the embodiments are not limited to this; multiple non-control electrodes 1412 can be unconnected to each other. Multiple control electrodes 1413 can be unconnected to each other. Multiple control electrodes 1414 can be unconnected to each other. Unconnecting corresponding control electrodes or non-control electrodes to each other allows for flexible control of different electrodes of the semiconductor device. In addition, whether corresponding control electrodes or non-control electrodes are connected to each other can be consistent with the connection relationship of each electrode of the semiconductor device used as a memory cell in the memory circuit. In this way, the same or similar wiring methods can be used in the memory circuit and the correction circuit, and the circuit design can be reused.

[0123] Additionally, the semiconductor device 1410, feedback control circuit 1420, and drive circuit 1430 can be described with reference to the corresponding devices or circuits in other embodiments.

[0124] Figure 15 illustrates a correction circuit 1500. The correction circuit 1500 may include a semiconductor device 1510 and a feedback control circuit 1520. The semiconductor device 1510 may include non-control electrodes 1511 and 1512 and control electrodes 1513, 1514, and 1515. The semiconductor device 1510 may include a split-gate floating-gate transistor, such as a tri-gate floating-gate transistor. Control electrode 1513 may include a control gate (CG), control electrode 1514 may include a select gate (SG) or a word line (WL), and control electrode 1515 may include an erase gate (EG). The feedback control circuit 1520 may include an operational amplifier 1521. According to some embodiments, the correction circuit 1500 may also include a driver circuit 1530. The semiconductor device 1510, the feedback control circuit 1520, and the driver circuit 1530 can be referred to the description of corresponding devices or circuits in other embodiments.

[0125] The similarities or similarities between the calibration circuit 1500 and the calibration circuit 1400 in Figure 14 can be found in their respective descriptions, and will not be repeated here. The differences between the calibration circuit 1500 and the calibration circuit 1400 in Figure 14 include that the control electrode 1514 of the semiconductor device 1510 is used as the calibration terminal, and the control electrode 1515 is used as the reference control terminal.

[0126] Figure 16 illustrates a correction circuit 1600. The correction circuit 1600 may include a semiconductor device 1610 and a voltage adjustment circuit 1620. Semiconductor device 1610 may include non-control electrodes 1611 and 1612 and control electrodes 1613 and 1614. Semiconductor device 1610 may include a split-gate floating-gate transistor, such as a dual-gate floating-gate transistor. Control electrode 1613 may include a control gate (CG), and control electrode 1614 may include a select gate (SG) or a word line (WL). Voltage adjustment circuit 1620 may include a transistor or a resistor. Voltage adjustment circuit 1620 may be connected between a constant current I0 and the non-control electrode 1611. The constant current I0 may also be connected to control electrode 1614. According to some embodiments, correction circuit 1600 may also include a drive circuit 1630. Semiconductor device 1610, voltage adjustment circuit 1620, and drive circuit 1630 may be described with reference to the corresponding devices or circuits in other embodiments.

[0127] Figure 17 illustrates a correction circuit 1700. The correction circuit 1700 may include a semiconductor device 1710 and a feedback control circuit 1720. The semiconductor device 1710 may include non-control electrodes 1711 and 1712, a control electrode 1713, and a back control electrode 1714. The back control electrode 1714 may include a substrate or a back gate. The feedback control circuit 1720 may include an operational amplifier 1721. According to some embodiments, the correction circuit 1700 may also include a drive circuit 1730. The semiconductor device 1710, the feedback control circuit 1720, and the drive circuit 1730 can be referred to the description of corresponding devices or circuits in other embodiments.

[0128] Figure 18 shows a schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application.

[0129] The in-memory computing system 1800 may include any of the above-mentioned storage devices 1810 for storing data or performing calculations on data. The in-memory computing system 1800 may also include a control circuit 1820 for controlling the operating state of the storage device. The operating state may include, for example, a programming state, a reading state, a calculation state, and an erasing state. The control circuit 1820 may also be used to control the correction circuit of the storage device 1810 to generate a correction voltage, thereby correcting for the reduction in reading accuracy and calculation accuracy of the storage device 1810 or the in-memory computing system 1800 caused by temperature changes.

[0130] Figure 19 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application.

[0131] The electronic device 1900 may include any of the above-mentioned in-memory computing systems 1910 for processing data from the electronic device. The electronic device 1900 may also include an input / output device 1920 for receiving user input or outputting processing results. This application does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input. The output may include text output, voice output, image output, or video output. The electronic device may also include a processor 1930, which can process data provided to the in-memory computing system 1910 or process the output data of the in-memory computing system 1910. The output of the input / output device 1920 may be based on the output of the processor 1930 or the output of the in-memory computing system 1910.

[0132] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0133] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A correction circuit, characterized in that, A first semiconductor device for calibrating a storage circuit, the first semiconductor device including a first terminal, a second terminal, and a first control terminal, a first channel formed between the first terminal and the second terminal, the first control terminal being used to control the conduction capability of the first channel, the calibration circuit including: A second semiconductor device, matched with the first semiconductor device, includes a third terminal, a fourth terminal, and a second control terminal. A second channel is formed between the third terminal and the fourth terminal. The second control terminal is used to control the conduction capability of the second channel. The third terminal is coupled to a constant current. A feedback control branch is connected to the third terminal and outputs a correction voltage based on the voltage of the third terminal. The second control terminal is coupled to the correction voltage, which is used to stabilize the channel current of the second channel and is used at the first control terminal.

2. The correction circuit according to claim 1, characterized in that, The feedback control branch includes: A feedback control circuit, coupled to a reference voltage and connected to the third terminal, is used to adjust and output the correction voltage based on the voltage at the third terminal and the reference voltage.

3. The correction circuit according to claim 2, wherein the feedback control circuit comprises: An operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the reference voltage, the second input terminal is connected to the third terminal, and the output terminal is used to output the correction voltage.

4. The correction circuit as described in any one of claims 1 to 3, characterized in that, The first semiconductor device further includes a third control terminal, which is used to couple an input signal and control the conduction capability of the first channel based on the input signal; the second semiconductor device further includes a fourth control terminal, which is used to couple a first voltage.

5. The correction circuit as described in claim 4, characterized in that, The first voltage is determined based on the input signal.

6. The correction circuit as described in claim 4 or 5, characterized in that, The second semiconductor device includes a transistor; The second control terminal includes a substrate, and the fourth control terminal includes a gate; or, the second control terminal includes a first gate, and the fourth control terminal includes a second gate.

7. The correction circuit as described in any one of claims 1 to 3, characterized in that, The storage circuit further includes a third semiconductor device, which shares or interconnects with the channel of the first semiconductor device, and the correction voltage is used to correct the third semiconductor device through the first semiconductor device.

8. The correction circuit as described in claim 7, characterized in that, The storage circuit further includes a fourth semiconductor device, which is connected to the third semiconductor device and is used to couple the input signal of the third semiconductor device and input the input signal to the third semiconductor device.

9. The correction circuit as described in claim 7 or 8, characterized in that, The correction circuit also includes: A fifth semiconductor device, wherein the fifth semiconductor device shares or interconnects with the channel of the second semiconductor device.

10. The correction circuit as described in claim 9, characterized in that, The correction circuit also includes: A sixth semiconductor device, which is connected to the second semiconductor device and the fifth semiconductor device, for coupling a second voltage.

11. The correction circuit according to any one of claims 1 to 10, characterized in that, It includes multiple second semiconductor devices, the second control terminals of the multiple second semiconductor devices are connected, and the third terminals of the multiple second semiconductor devices are connected.

12. The correction circuit as described in any one of claims 1 to 11, characterized in that, Also includes: A driving circuit is connected between the second control terminal of the second semiconductor device and the first control terminal of the first semiconductor device, and is used to increase the output power of the correction voltage output by the feedback control branch.

13. A storage device, characterized in that, include: A storage circuit includes a first semiconductor device, the first semiconductor device including a first terminal, a second terminal and a first control terminal, a first channel being formed between the first terminal and the second terminal, and the first control terminal being used to control the conduction capability of the first channel; The correction circuit as described in any one of claims 1 to 12.

14. The storage device of claim 13, wherein the first semiconductor device further comprises a third control terminal for coupling to an input signal and controlling the conduction capability of the first channel based on the input signal; and the second semiconductor device further comprises a fourth control terminal for coupling to a first voltage.

15. The storage device as claimed in claim 14, characterized in that, The storage circuit includes a group of storage cells, and the group of storage cells includes a plurality of the first semiconductor devices. In the first semiconductor device within the memory cell group, a third control terminal is coupled to multiple input signals, and the third terminals are connected to each other and connected to the same output line. The storage cell group is configured to convert the plurality of input signals into a plurality of output signals based on the weight data stored in the respective first semiconductor devices within the storage cell group, and to output a cumulative signal of the plurality of output signals on the same output line.

16. The storage device as claimed in claim 13, characterized in that, The storage circuit further includes a third semiconductor device, which shares or interconnects with the channel of the first semiconductor device, and the correction voltage is used to correct the third semiconductor device through the first semiconductor device.

17. The storage device as claimed in claim 16, characterized in that, The storage circuit further includes a fourth semiconductor device, which is connected to the third semiconductor device and is used to couple the input signal of the third semiconductor device and input the input signal to the third semiconductor device.

18. An in-memory computing system, characterized in that, include: The storage device as claimed in any one of claims 13 to 17; A control circuit for controlling the storage circuit of the storage device.

19. An electronic device, characterized in that, Includes the storage device as described in any one of claims 13 to 17 or the storage system as described in claim 18.

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