Preparation method for non-volatile two-terminal memory cell, and product

Abstract

The present application discloses a preparation method for a non-volatile two-terminal memory cell, and a product. The preparation method comprises: stacking a first dielectric layer (130) on the upper surfaces of lower electrode metal connection layers (111, 112); forming a first-region lower electrode interconnection via (141) and a second-region lower electrode interconnection via (142) on the basis of a first patterned photomask layer (391); forming a first-region first stack layer (250A) filling the first-region lower electrode interconnection via, or forming a memory cell stack layer (350) on the first-region lower electrode interconnection via; and forming a first-region upper electrode interconnection via (181) and a second-region upper electrode interconnection via (182) on the basis of the first patterned photomask layer (391). By using a patterned photomask layer, preparation of a non-volatile two-terminal memory cell is achieved, thereby shortening the preparation process for the non-volatile two-terminal memory cell, and improving the accuracy of alignment of the lower electrode interconnection vias (141, 142) and the upper electrode interconnection vias (181, 182).

Description

Fabrication method and products of non-volatile two-terminal memory cells Cross-references to related applications

[0001] This application claims priority to Chinese patent application No. 202510363324.X, filed on March 25, 2025, entitled "Method for fabricating non-volatile two-terminal memory cells and products thereof", and Chinese patent application No. 202510363395.X, filed on March 25, 2025, entitled "Method for fabricating non-volatile two-terminal memory cells and products thereof". Technical Field

[0002] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a method for fabricating a non-volatile two-terminal memory cell and the product thereof. Background Technology

[0003] Resistive Random Access Memory (RRAM) is a non-volatile two-terminal memory cell that stores information based on changes in the resistance of a material. It typically consists of a lower electrode, a switching layer, and a upper electrode. In existing technologies, the fabrication of RRAM requires two separate photolithography steps to fabricate the lower and upper electrodes. Due to the manufacturing process, the fabrication of the lower and upper electrodes usually requires a different patterned photomask layer, significantly increasing production costs and complicating the fabrication process. Furthermore, this method involves aligning the lower and upper electrodes during fabrication, further complicating the fabrication of RRAM.

[0004] In view of this, there is an urgent need to provide a method for fabricating non-volatile two-sided memory cells. This method can fabricate the lower and upper electrodes of the non-volatile two-sided memory cells while reducing the number of patterned photomask layers used, thereby reducing the production cost of non-volatile two-sided memory cells, simplifying the fabrication process, and avoiding the problem of mutual alignment between the lower and upper electrodes, thus reducing the fabrication difficulty of non-volatile two-sided memory cells. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, this disclosure proposes a method for fabricating non-volatile two-ended memory cells and a solution for their products in several aspects.

[0006] In a first aspect, this disclosure provides a method for fabricating a non-volatile two-terminal memory cell, the method comprising:

[0007] A first dielectric layer 130 is stacked on the upper surface of the first region lower electrode metal interconnect layer 111 located in the first region and on the upper surface of the second region lower electrode metal interconnect layer 112 located in the second region. Based on the first patterned photomask layer 391, a first region lower electrode interconnect via 141 that contacts the upper surface of the first region lower electrode metal interconnect layer 111 and a second region lower electrode interconnect via 142 that contacts the upper surface of the second region lower electrode metal interconnect layer 112 are formed in the first dielectric layer 130. A first region first stacked layer 250A is formed to fill the first region lower electrode interconnect via 141. The first region first stacked layer 250A is electrically connected to the first region lower electrode metal interconnect layer 111, or a memory cell stacked layer 350 is formed above the first region lower electrode interconnect via 141. 350 contacts the upper surface of the first region lower electrode interconnect via 141; a second dielectric layer 170 is formed in the first region and the second region; based on the first patterned photomask layer 391, a first region upper electrode interconnect via 181 and a second region upper electrode interconnect via 182 are formed in the second dielectric layer 170; a first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnect via 181, and a second region upper electrode metal connection layer 192 is formed in the second region upper electrode interconnect via 182, wherein the first region upper electrode metal connection layer 191 is electrically connected to the first region first stacked layer 250A or the first region lower electrode metal connection layer 111, and the second region upper electrode metal connection layer 192 is electrically connected to the second region lower electrode metal connection layer 112.

[0008] In a second aspect, this disclosure provides a non-volatile two-terminal memory cell, the non-volatile two-terminal memory cell including a first dielectric layer 130, the first dielectric layer 130 being stacked on the upper surface of a first region lower electrode metal interconnect layer 111 in a first region and the upper surface of a second region lower electrode metal interconnect layer 112 in a second region; a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142, based on a first patterned photomask layer 391, formed in the first dielectric layer 130; a first region first stacked layer 250A, filling the first region lower electrode interconnect via 141, and electrically connected to the first region lower electrode metal interconnect layer 111, or a memory cell stacked layer 350, connected to the first region lower electrode metal interconnect layer 111. The upper surface of the first region lower electrode interconnect via 141 is in contact; a second dielectric layer 170 is formed in the first region and the second region; a first region upper electrode interconnect via 181 and a second region upper electrode interconnect via 182 are formed in the second dielectric layer 170 based on the first patterned photomask layer 391; a first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnect via 181 and is electrically connected to the first region first stacked layer 250A or the first region lower electrode metal connection layer 111; a second region upper electrode metal connection layer 192 is formed in the second region upper electrode interconnect via 182 and is electrically connected to the second region lower electrode metal connection layer 112.

[0009] In a third aspect, this disclosure provides a memory comprising one or more non-volatile end-to-end memory cells according to any embodiment of this disclosure.

[0010] In a fourth aspect, this disclosure provides an electronic device, wherein the electronic device includes the memory described in the embodiments of this disclosure.

[0011] Using the fabrication scheme of the non-volatile two-sided memory cell provided above, the embodiments disclosed herein simultaneously etch a first lower electrode interconnect via 141 located in the memory cell array region 80 and a second lower electrode interconnect via 142 located in the peripheral circuit region 90 based on the first patterned photomask layer 391. Furthermore, based on the first patterned photomask layer 391, a first upper electrode interconnect via 181 located in the memory cell array region 80 and a second upper electrode interconnect via 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. This allows the fabrication of the non-volatile two-sided memory cell to be achieved using only one patterned photomask layer, thereby shortening the fabrication process of the non-volatile two-sided memory cell and reducing the fabrication cost. Furthermore, by using the same patterned photomask layer (i.e., the first patterned photomask layer 391) as the etched lower electrode interconnect via (i.e., the first lower electrode interconnect via 141 located in the memory cell array region 80 and the second lower electrode interconnect via 142 located in the peripheral circuit region 90) as a mask, the upper electrode interconnect via (i.e., the first upper electrode interconnect via 181 located in the memory cell array region 80 and the second upper electrode interconnect via 182 located in the peripheral circuit region 90) can be etched. This can improve the alignment accuracy of the lower electrode interconnect via and the upper electrode interconnect via, avoid problems such as contact resistance changes caused by poor alignment, and improve the stability and reliability of the formed non-volatile two-terminal memory cells. Attached Figure Description

[0012] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0013] Figures 1A-1K show schematic diagrams of semiconductor cross-sectional structures fabricated using existing techniques for non-volatile two-terminal memory cells;

[0014] Figure 2 shows an exemplary structural block diagram of a method for fabricating a non-volatile two-ended memory cell according to some embodiments of this application;

[0015] Figures 3A-3J show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to some embodiments of this disclosure;

[0016] Figure 4 shows an exemplary structural block diagram of a method for fabricating a non-volatile two-ended memory cell according to some other embodiments of this application;

[0017] Figures 5A-5I show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to further embodiments of this disclosure;

[0018] Figures 6A-6I show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to other embodiments of this disclosure.

[0019] Appendix Symbols:

[0020] 110-Lower electrode metal connection layer, 111-First region lower electrode metal connection layer, 112-Second region lower electrode metal connection layer, 120-Lower dielectric layer, 130-First dielectric layer, 141-First region lower electrode interconnect via, 142-Second region lower electrode interconnect via, 151-Second lower electrode metal layer, 1511-Second lower electrode metal layer 1, 15111-First region second lower electrode metal layer 1, 15112-Second region second lower electrode metal layer 1, 1512-Second lower electrode metal layer 2, 152-Second switching layer, 153-Second upper electrode metal layer, 154-Upper electrode hard mask layer, 159-Sidewall, 170-Second dielectric layer, 181-First region upper electrode interconnect via, 182-Second region upper electrode interconnect via, 191-First region upper electrode metal connection layer, 192-Second region upper electrode metal connection layer;

[0021] 250A - First stacked layer of the first region, 250B - First stacked layer of the second region, 251 - First lower electrode metal layer, 252 - First switching layer, 253 - First upper electrode metal layer;

[0022] 342 - Second functional layer, 350 - Storage cell stacking layer, 380 - Lower electrode hard mask layer, 381 - Lower electrode hard mask layer 1, 382 - Lower electrode hard mask layer 2, 391 - First patterned photomask layer, 393 - Third patterned photomask layer, 394 - Fourth patterned photomask layer.

[0023] 50 - Stop line, 80 - Memory cell array area, 90 - Peripheral circuit area. Detailed Implementation

[0024] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0027] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0028] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0029] Figures 1A-1K show schematic diagrams of semiconductor cross-sectional structures for fabricating non-volatile two-terminal memory cells using existing technology.

[0030] Figure 1A shows a schematic diagram of the semiconductor cross-sectional structure in the prior art for forming a third patterned photomask layer 393.

[0031] As shown in Figure 1A, a multilayer semiconductor structure is provided, and a third patterned photomask layer 393 is formed on top of the semiconductor structure. Specifically, the pattern of the third patterned photomask layer 393 can be used to define the pattern of the subsequently formed lower electrode interconnect via 141 in the first region of the memory cell array region 80.

[0032] Specifically, the semiconductor structure is processed to form the following structure in sequence: a lower electrode metal connection layer 110 surrounded by a lower dielectric layer 120, a first dielectric layer 130, a lower electrode hard mask layer 380, and a third patterned photomask layer 393.

[0033] The lower electrode metal connection layer 110 includes a first lower electrode metal connection layer 111 located in the memory cell array region 80 and a second lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are separated by a lower dielectric layer 120 to prevent short circuits from forming between the two first lower electrode metal connection layers 111, between the two second lower electrode metal connection layers 112, or between the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112. Simultaneously, the upper surfaces of the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first lower electrode metal connection layer 111, the second lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0034] A first dielectric layer 130 is deposited on the upper surface of the lower electrode metal interconnect layer 110, which is surrounded by a lower dielectric layer 120, using a thin film deposition process. The first dielectric layer 130 may consist of multiple layers.

[0035] A lower electrode hard mask layer 380 is deposited on the upper surface of the first dielectric layer 130 using a thin film deposition process. The lower electrode hard mask layer 380 may consist of multiple layers. In this embodiment, the lower electrode hard mask layer 380 may include a lower electrode hard mask first layer 381 and a lower electrode hard mask second layer 382.

[0036] A third patterned photomask layer 393 is formed above the two-layer lower electrode hard mask 382, ​​the pattern of which can be used to define the pattern of the subsequently formed lower electrode interconnect via 141 in the first region of the memory cell array region 80.

[0037] Figure 1B shows a schematic diagram of the semiconductor cross-sectional structure in the prior art for forming the first region lower electrode interconnect via 141.

[0038] As shown in Figure 1B, based on the third patterned photomask layer 393, the exposed lower electrode hard mask layer 380 is etched until the corresponding position of the first dielectric layer 130 is exposed. The remaining lower electrode hard mask layer 380 forms a patterned lower electrode hard mask layer, and the aforementioned third patterned photomask layer 393 is removed. Next, using the patterned lower electrode hard mask layer as a mask, the exposed first dielectric layer 130 is etched to form a first region lower electrode interconnect via 141 in the first dielectric layer 130, and the remaining lower electrode hard mask layer 380 is removed.

[0039] Specifically, the first region lower electrode interconnect via 141 is located in the memory cell array region 80, and its bottom contacts the upper surface of the first region lower electrode metal connection layer 111. The cross-sectional shape and size of the first region lower electrode interconnect via 141 are not limited. Preferably, the cross-sectional shape of the first region lower electrode interconnect via 141 is an inverted trapezoid, where the width of the upper base of the inverted trapezoid is greater than the width of the lower base, and the width of the upper base is greater than... The width of the lower base of the inverted trapezoid is greater than The angle between the legs and the lower base of the inverted trapezoid is greater than 105 degrees.

[0040] Figure 1C shows a schematic diagram of a semiconductor cross-sectional structure of a layer 1511 with a second lower electrode metal deposited in the prior art.

[0041] As shown in Figure 1C, a second lower electrode metal layer 1511 is deposited in the lower electrode interconnect via 141 of the first region and on the upper surface of the first dielectric layer 130 by a thin film deposition process, so that the second lower electrode metal layer 1511 at least fills the lower electrode interconnect via 141 of the first region.

[0042] Figure 1D shows a schematic diagram of a semiconductor cross-sectional structure of a second lower electrode metal with a layered 1511 planarization process in the prior art.

[0043] As shown in Figure 1D, the second lower electrode metal layer 1511 is planarized to form the first region of the second lower electrode metal layer 15111. Specifically, the first region of the second lower electrode metal layer 15111 fills the first region of the lower electrode interconnect via 141, and the upper surface of the first region of the second lower electrode metal layer 15111 is flush with the upper surface of the first dielectric layer 130.

[0044] Figure 1E shows a schematic diagram of a semiconductor cross-sectional structure in the prior art in which a second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154 are deposited sequentially.

[0045] As shown in Figure 1E, a second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154 are sequentially deposited on the upper surface of the first dielectric layer 130 and the upper surface of the first region second lower electrode metal layer 15111.

[0046] Figure 1F shows a schematic diagram of a semiconductor cross-sectional structure forming a memory cell stack layer 350 in the prior art.

[0047] As shown in Figure 1F, photolithography and etching processes are used to etch the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154, so that the remaining portions of the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 form a memory cell stack layer 350, and the bottom of the memory cell stack layer 350 is in contact with the upper surface of the second lower electrode metal layer 15111 in the first region.

[0048] Figure 1G shows a schematic diagram of a semiconductor cross-sectional structure forming sidewalls 159 in the prior art.

[0049] As shown in Figure 1G, sidewalls 159 are deposited in the exposed areas of the storage cell stack layer 350 and the first dielectric layer 130. Then, the deposited sidewalls 159 are etched so that the etching process stops on the upper surface of the first dielectric layer 130, so that the etched sidewalls 159 can wrap around the storage cell stack layer 350 from the side.

[0050] Figure 1H shows a schematic diagram of the semiconductor cross-sectional structure of the deposited second dielectric layer 170 in the prior art.

[0051] As shown in Figure 1H, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the surface of the exposed memory cell stack layer 350, and the surface of the exposed sidewall 159.

[0052] Figure 1I shows a schematic diagram of the semiconductor cross-sectional structure in the prior art for forming the fourth patterned photomask layer 394.

[0053] As shown in Figure 1I, a fourth patterned photomask layer 394 is formed in the structure described above, and the fourth patterned photomask layer 394 is located above the second dielectric layer 170. The pattern of the fourth patterned photomask layer 394 is different from the pattern of the third patterned photomask layer 393. Specifically, the pattern of the fourth patterned photomask layer 394 can be used to define the patterns of the subsequently formed upper electrode interconnect vias 181 in the first region of the memory cell array region 80 and the upper electrode interconnect vias 182 in the second region of the peripheral circuit region 90.

[0054] Figure 1J shows a schematic diagram of the semiconductor cross-sectional structure in the prior art for forming the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182.

[0055] As shown in Figure 1J, based on the fourth patterned photomask layer 394, a first region upper electrode interconnect via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154 through photolithography and etching processes, and a second region upper electrode interconnect via 182 is formed in the second dielectric layer 170 and the first dielectric layer 130. The first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112. Then, the fourth patterned photomask layer 394 is removed.

[0056] Figure 1K shows a schematic diagram of the semiconductor cross-sectional structure in the prior art for forming a first region upper electrode metal interconnect layer 191 and a second region upper electrode metal interconnect layer 192.

[0057] As shown in Figure 1K, a first-region upper electrode metal interconnect layer 191 is filled in the first region upper electrode interconnect via 181, and a second-region upper electrode metal interconnect layer 192 is filled in the second region upper electrode interconnect via 182. The first-region upper electrode metal interconnect layer 191 is located in the memory cell array region 80, and its bottom is in contact with the memory cell stack layer 350; the second-region upper electrode metal interconnect layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the second-region lower electrode metal interconnect layer 112.

[0058] In the prior art, during the fabrication of the lower and upper electrodes of a non-volatile two-sided memory cell, one patterned photomask layer (the third patterned photomask layer 393) is required during the etching of the first dielectric layer 130 to form the lower electrode interconnect via (i.e., the first region lower electrode interconnect via 141 mentioned above), and another patterned photomask layer (the fourth patterned photomask layer 394 mentioned above) is required during the etching of the second dielectric layer 170 to form the upper electrode interconnect via (i.e., the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182 mentioned above). Therefore, the prior art requires at least two different patterned photomask layers to fabricate the non-volatile two-sided memory cell. This significantly increases production costs and makes the fabrication process more complex. Furthermore, this fabrication method involves aligning the lower and upper electrodes during fabrication, which makes the fabrication of the non-volatile two-sided memory cell difficult.

[0059] In view of this, the present disclosure provides a fabrication scheme for a non-volatile two-sided memory cell. Based on a patterned photomask layer (i.e., the first patterned photomask layer 391 hereinafter), a lower electrode interconnect via (i.e., the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 hereinafter) is etched. Then, based on the same patterned photomask layer (i.e., the first patterned photomask layer 391 hereinafter), an upper electrode interconnect via (i.e., the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182 hereinafter) is etched. This achieves the formation of the lower and upper electrode interconnect vias of the non-volatile two-sided memory cell using only one patterned photomask layer, for the fabrication of the lower and upper electrodes, reducing fabrication costs, shortening the fabrication process of the non-volatile two-sided memory cell, and reducing fabrication difficulty.

[0060] Figure 2 shows an exemplary structural block diagram of a method for fabricating a non-volatile two-ended memory cell according to some embodiments of this application.

[0061] As shown in Figure 2, the fabrication method 200 of the non-volatile two-terminal memory cell includes the following steps:

[0062] In step S210, a first dielectric layer 130 is stacked on the upper surface of the first region lower electrode metal connection layer 111 located in the first region and on the upper surface of the second region lower electrode metal connection layer 112 located in the second region.

[0063] In step S220, based on the first patterned photomask layer 391, a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142 are formed in the first dielectric layer 130.

[0064] In step S230, a first stacked layer 250A is formed to fill the first region lower electrode interconnect via 141, and the first stacked layer 250A is electrically connected to the first region lower electrode metal connection layer 111.

[0065] In step S240, a second dielectric layer 170 is formed in the first region and the second region;

[0066] In step S250, based on the first patterned photomask layer 391, a first region upper electrode interconnect via 181 and a second region upper electrode interconnect via 182 are formed in the second dielectric layer 170.

[0067] In step S260, a first upper electrode metal connection layer 191 is formed in the first upper electrode interconnect via 181, and a second upper electrode metal connection layer 192 is formed in the second upper electrode interconnect via 182. The first upper electrode metal connection layer 191 is electrically connected to the first stacked layer 250A of the first region, and the second upper electrode metal connection layer 192 is electrically connected to the second lower electrode metal connection layer 112.

[0068] Based on the fabrication process of the non-volatile two-ended memory cell in Figure 2, the exemplary process flow of the fabrication method 200 of the non-volatile two-ended memory cell using some embodiments of this application will be described in detail below with reference to the semiconductor cross-sectional structure schematic diagrams shown in Figures 3A-3J.

[0069] Figures 3A-3J show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to some embodiments of this disclosure.

[0070] Figure 3A shows a schematic diagram of the semiconductor cross-sectional structure for forming the first patterned photomask layer 391 according to an embodiment of this application.

[0071] As shown in Figure 3A, a multilayer semiconductor structure is provided, and a first patterned photomask layer 391 is formed on top of the semiconductor structure. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed lower electrode interconnect vias 141 in the first region of the memory cell array region 80 and the lower electrode interconnect vias 142 in the second region of the peripheral circuit region 90.

[0072] Specifically, the semiconductor structure is processed to form the following structure in sequence: a lower electrode metal connection layer 110 surrounded by a lower dielectric layer 120, a first dielectric layer 130, and a first patterned photomask layer 391.

[0073] The lower electrode metal connection layer 110 includes a first lower electrode metal connection layer 111 located in the memory cell array region 80 and a second lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are separated by a lower dielectric layer 120 to prevent short circuits from forming between the two first lower electrode metal connection layers 111, between the two second lower electrode metal connection layers 112, or between the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112. Simultaneously, the upper surfaces of the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first lower electrode metal connection layer 111, the second lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0074] The number of lower electrode metal connection layers 111 in the first region can be one or more. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be the same or different. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be copper. The main advantages of copper compared to other metals are its high electrical conductivity, high thermal conductivity, corrosion resistance, suitable strength, and ease of processing and forming. In the embodiments of this application, other metals can also be used for the lower electrode metal connection layers 111 and 112 in the first region as needed, and this is not limited here.

[0075] Specifically, the material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, or a low-k dielectric material. More specifically, the low-k dielectric material can be porous silicon dioxide, silicon fluoride glass, etc. In the embodiments of this application, the lower dielectric layer 120 can also be selected from other materials according to the actual application scenario and process requirements, and no limitation is made here.

[0076] Specifically, various known processes can be used to fabricate the lower dielectric layer 120 around the lower electrode metal interconnect layer 110, and the embodiments of this application are not limited in this respect.

[0077] For example, a lower dielectric layer 120 is made to surround a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, exposing the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112. This part of the process includes: first, providing a lower dielectric layer 120, forming a patterned photomask layer on the lower dielectric layer 120, selectively exposing photoresist using an exposure machine, developing to remove exposed or unexposed portions of the photoresist, etching or depositing patterns in the exposed areas, removing remaining photoresist, and continuing to form the desired first groove located in the memory cell array region 80 and the second groove located in the peripheral circuit region 90 by dry etching or wet etching, wherein the number of first grooves can be single or multiple. Then, metal material is deposited in the first groove and the second groove. Finally, the metal material is planarized to form a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, such that the upper surfaces of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush. Thus, a lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 is obtained, and the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112 are exposed.

[0078] Specifically, the lower electrode metal connection layer 110, surrounded by the lower dielectric layer 120, can isolate the first region lower electrode metal connection layer 111 from other unrelated parts; it can also isolate the second region lower electrode metal connection layer 112 from other unrelated parts. This prevents current from flowing along unwanted paths, avoiding short circuits and leakage. For example, it prevents direct connections between the two first region lower electrode metal connection layers 111, between the two second region lower electrode metal connection layers 112, or between the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112, thus avoiding short circuits.

[0079] Specifically, the first dielectric layer 130 is formed on the upper surface of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the exposed lower dielectric layer 120. The first dielectric layer 130 can be formed by a thin film deposition process. The first dielectric layer 130 can be a single layer or multiple layers. For example, the first dielectric layer 130 can include a first dielectric layer and a first dielectric layer stacked sequentially. The first dielectric layer can be a silicon nitride (SiN) thin film or a nitro-doped silicon carbide (NDC) thin film, and the first dielectric layer can be a low-temperature oxide (LTO), a silicon dioxide layer (SiO2), or a silicon-rich oxide (SRO), etc. In the embodiments of this application, the first dielectric layer and the first dielectric layer can also be made of other materials according to the actual application scenario and process requirements, which are not limited here.

[0080] The first dielectric layer 130 can protect the first stacked layer 250A in the first region and the functional layer 342 in the second region (including the first stacked layer 250B in the second region) from external damage.

[0081] Specifically, a first patterned photomask layer 391 is formed above the first dielectric layer 130. The first patterned photomask layer 391 can be made using either positive or negative photoresist. The first patterned photomask layer 391 can be formed using various known processes, and this application embodiment is not limited in this respect. For example, a photomask layer is coated above the first dielectric layer 130, and the photomask layer is exposed to form exposed and unexposed areas. Then, the exposed photomask layer is developed to remove the photomask layer in the exposed or unexposed areas, forming the first patterned photomask layer 391. When a positive photoresist is used, the photomask layer in the exposed areas changes from being insoluble in the developer to being soluble in the developer and is removed during development. When a negative photoresist is used, the photomask layer in the exposed areas changes from being soluble in the developer to being insoluble in the developer and is not removed during development. Thus, when a negative photoresist is used, the photomask layer in the unexposed areas is removed.

[0082] Figure 3B shows a schematic cross-sectional view of the semiconductor structure forming the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 according to an embodiment of this application.

[0083] As shown in Figure 3B, based on the first patterned photomask layer 391, the exposed first dielectric layer 130 is etched to form a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142 in the first dielectric layer 130, and the first patterned photomask layer 391 is removed.

[0084] Specifically, the first region lower electrode interconnect via 141 is located in the memory cell array region 80, and its bottom contacts the upper surface of the first region lower electrode metal connection layer 111. The second region lower electrode interconnect via 142 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112. Both the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum-shaped structure or a trapezoidal structure. In the embodiments of this application, the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can also be selected with other structural shapes according to the actual application scenario and process requirements, which are not limited here.

[0085] In this embodiment, the cross-sectional shape of the lower electrode interconnect via 141 in the first region is an inverted trapezoid, with the width of the upper base of the inverted trapezoid greater than the width of the lower base. The width of the lower base of the inverted trapezoid is greater than The angle between the legs and the lower base of the inverted trapezoid is greater than 105 degrees.

[0086] Specifically, since the first lower electrode interconnect via 141 located in the memory cell array region 80 corresponds to the subsequently formed first upper electrode interconnect via 181 located in the memory cell array region 80, and the second lower electrode interconnect via 142 located in the peripheral circuit region 90 corresponds to the subsequently formed second upper electrode interconnect via 182 located in the peripheral circuit region 90, the first lower electrode interconnect via 141 and the second lower electrode interconnect via 142, as well as the first upper electrode interconnect via 181 and the second upper electrode interconnect via 182, can be etched based on the first patterned photomask layer 391.

[0087] Figure 3C shows a schematic diagram of the semiconductor cross-sectional structure of the first lower electrode metal layer 251, the first switching layer 252 and the first upper electrode metal layer 253 deposited sequentially according to an embodiment of this application.

[0088] As shown in Figure 3C, a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 are sequentially deposited in the first region lower electrode interconnect via 141, the second region lower electrode interconnect via 142, and on the upper surface of the first dielectric layer 130 through a thin film deposition process, so that the deposited first lower electrode metal layer 251, first switching layer 252, and first upper electrode metal layer 253 at least fill the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0089] In the embodiments of this application, during the deposition of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in sequence, the material may be deposited only on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, or deposited on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, as well as on a portion of the upper surface of the first dielectric layer 130. However, the deposited material must at least fill the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, and ensure that the first switching layer 252 is located between the first lower electrode metal layer 251 and the first upper electrode metal layer 253, separating the two.

[0090] In the embodiments of this application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure, and the material used may be one of TiN (titanium nitride), Ti (titanium), Ta (tantalum), W (tungsten), etc. Alternatively, the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 may use the same metal material, thereby ensuring close contact between the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 and avoiding the formation of voids.

[0091] When the first lower electrode metal layer 251 adopts a two-layer structure, it may include a first lower electrode metal layer 1 and a first lower electrode metal layer 2 covering the upper surface of the first lower electrode metal layer 1. In this case, the first lower electrode metal layer 1 can be made of TiN (titanium nitride), and the first lower electrode metal layer 2 can be made of W (tungsten). The first lower electrode metal layer 2 can serve as a connecting layer between the first lower electrode metal layer 1 and the first switching layer. Furthermore, by using W (tungsten) as the material for the first lower electrode metal layer 2, not only can the thermal conductivity and resistance of the first lower electrode metal layer 2 be ensured, but heat can also be conducted quickly, promoting heat dissipation and reducing heat generation, thereby minimizing thermal damage to the fabricated non-volatile two-sided memory cell. Using W (tungsten) as the material for the first lower electrode metal layer 2 also ensures that the first lower electrode metal layer 2 has higher inertness, thus preventing chemical reactions between the first lower electrode metal layer 2 and the first switching layer, and ensuring the thermal stability of the fabricated non-volatile two-sided memory cell.

[0092] In the embodiments of this application, the material of the first switching layer 252 may be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), or tantalum oxide (TaO), which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 may also be selected from other materials according to the actual application scenario and process requirements, which are not limited here.

[0093] In the embodiments of this application, the first upper electrode metal layer 253 may be a single-layer or multi-layer structure.

[0094] When the first upper electrode metal layer 253 adopts a two-layer structure, the first upper electrode metal layer 253 may include a first upper electrode metal layer one and a first upper electrode metal layer two covering the surface of the first upper electrode metal layer one. In this case, the material used in the first upper electrode metal layer one is more easily oxidized than the material used in the first upper electrode metal layer two. The material used in the first upper electrode metal layer one may be AlN (aluminum nitride), and the material used in the first upper electrode metal layer two may be TiN (titanium nitride).

[0095] The material used in the first upper electrode metal layer is more easily oxidized than the material used in the second upper electrode metal layer. The purpose is that, as the upper electrode of the non-volatile two-sided memory cell, the first upper electrode metal layer provides metal ions to the first switching layer 252, but also prevents the first upper electrode metal layer from being oxidized and causing adverse effects, such as reduced conductivity. Therefore, the second upper electrode metal layer, which is less prone to oxidation than the first upper electrode metal layer, needs to cover the first upper electrode metal layer, thereby reducing the possibility of the first upper electrode metal layer being oxidized and ensuring that the characteristics of the non-volatile two-sided memory cell are not affected.

[0096] Other materials can also be used for the first upper electrode metal layer one and the first upper electrode metal layer two.

[0097] Figure 3D shows a schematic diagram of the semiconductor cross-sectional structure before planarization in an embodiment of this application.

[0098] As shown in Figure 3D, a stop line 50 is set before planarization. When the semiconductor structure reaches the height of the stop line 50 during planarization, the planarization process stops. The height of the stop line 50 is not higher than the upper surface of the first dielectric layer 130, so that after planarization, the semiconductor structure forms a first stacked layer that fills the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0099] Figure 3E shows a schematic diagram of the semiconductor cross-sectional structure after planarization in an embodiment of this application.

[0100] As shown in Figure 3E, a planarization process is used to expose the upper surface of the first dielectric layer 130, forming a first stacked layer 250A in the first region and a first stacked layer 250B in the second region. Specifically, the first stacked layer 250A in the first region fills the lower electrode interconnect via 141 in the first region, and the first stacked layer 250B in the second region fills the lower electrode interconnect via 142 in the second region. The upper surfaces of the first stacked layer 250A in the first region, the upper surfaces of the first stacked layer 250B in the second region, and the upper surface of the first dielectric layer 130 are flush.

[0101] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0102] Specifically, the first stacked layer 250A in the first region is electrically connected to the lower electrode metal connection layer 111 in the first region, and the first stacked layer 250B in the second region is electrically connected to the lower electrode metal connection layer 112 in the second region.

[0103] In this embodiment, the bottom of the first stacked layer 250A in the first region is in contact with the upper surface of the lower electrode metal connection layer 111 in the first region, and the bottom of the first stacked layer 250B in the second region is in contact with the upper surface of the lower electrode metal connection layer 112 in the second region.

[0104] Figure 3F shows a schematic diagram of the semiconductor cross-sectional structure of the second functional layer 342 in an embodiment of this application.

[0105] As shown in Figure 3F, after planarization, the first stacked layer 250B of the second region is etched, and the etching consumes part or all of the first stacked layer 250B of the second region.

[0106] In an embodiment of this application, based on a specific patterned photomask layer, the first stacked layer 250B of the second region is etched, and the etching process is stopped at the upper surface of the first lower electrode metal layer 251 of the first stacked layer 250B of the second region, with the remaining portion forming the second region functional layer 342. Then the patterned photomask layer is removed.

[0107] The pattern of the patterned photomask can be used to etch the first stacked layer 250B in the second region, and its material and the specific method of formation are not limited.

[0108] At this time, the materials of the first lower electrode metal layer 251 and the second functional layer 342 are the same, and the thickness of the first lower electrode metal layer 251 is not less than the thickness of the second functional layer 342.

[0109] The functions of the second functional layer 342 include at least the following two aspects. Taking the lower electrode metal connection layer 112 of the second region as a copper conductor as an example.

[0110] First, the second functional layer 342 is used as a barrier layer here. The second functional layer 342 covers the copper conductor. After the upper surface of the second lower electrode metal connection layer 112 is exposed to copper (i.e. after the second lower electrode interconnect via 142 is formed), by covering the second functional layer 342, the copper on the upper surface of the second lower electrode metal connection layer 112 can be prevented from being oxidized or the oxidation diffusion can be slowed down. At the same time, it can increase the QTime (Queue Time or process time interval) of the fabrication process.

[0111] Secondly, the second functional layer 342 can be used as an etching stop layer. When etching is performed on the top of the second functional layer 342, it serves as a stop layer for the etching process, thereby effectively controlling the accuracy of etching stop and preventing the copper wire (i.e., the second lower electrode metal connection layer 112) from being etched and thus causing damage to the copper wire.

[0112] Preferably, the thickness of the second functional layer 342 ranges from [specific range missing]. Between. When the thickness is less than If the thickness is too small, the second functional layer 342 may be etched through, leading to its failure. Furthermore, an excessively thin second functional layer 342 would be too costly to manufacture in actual production. When the thickness is greater than... At this time, the second functional layer 342 will significantly increase the resistivity of the conductive metal interconnects in the peripheral circuit region 90. Therefore, the thickness of the second functional layer 342 is located at... This arrangement avoids a significant increase in resistivity, prevents etching penetration that could render the function ineffective, and facilitates preparation in actual production.

[0113] Figure 3G shows a schematic diagram of the semiconductor cross-sectional structure of the second dielectric layer 170 according to an embodiment of this application.

[0114] As shown in Figure 3G, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the upper surface of the first stacked layer 250A in the first region, and the upper surface of the functional layer 342 in the second region. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the first stacked layer 250A in the first region and fills the remaining space of the lower electrode interconnect via 142 in the second region.

[0115] Figure 3H shows a schematic diagram of the semiconductor cross-sectional structure for forming the first patterned photomask layer 391 according to an embodiment of this application.

[0116] As shown in Figure 3H, a first patterned photomask layer 391 is formed above the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed upper electrode interconnect vias 181 in the first region of the memory cell array region 80 and the upper electrode interconnect vias 182 in the second region of the peripheral circuit region 90.

[0117] Figure 3I shows a schematic diagram of the semiconductor cross-sectional structure of the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182 according to an embodiment of this application.

[0118] As shown in Figure 3I, based on the first patterned photomask layer 391, the exposed second dielectric layer 170 is etched until the corresponding positions of the first stacked layer 250A in the first region are exposed, and the exposed second dielectric layer 170 is etched until the corresponding positions of the functional layer 342 in the second region are exposed. First region upper electrode interconnect vias 181 and 182 are formed in the second dielectric layer 170. The first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the first stacked layer 250A in the first region; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the functional layer 342 in the second region. Then, the first patterned photomask layer 391 is removed.

[0119] Specifically, the bottom of the first upper electrode interconnect via 181 is in contact with the first upper electrode metal layer 253, and the bottom of the second upper electrode interconnect via 182 is in contact with the second functional layer 342.

[0120] Figure 3J shows a schematic cross-sectional view of the semiconductor structure in an embodiment of this application, illustrating the formation of the first region upper electrode metal interconnect layer 191 and the second region upper electrode metal interconnect layer 192.

[0121] As shown in Figure 3J, a first-region upper electrode metal interconnect layer 191 is filled in the first region upper electrode interconnect via 181, and a second-region upper electrode metal interconnect layer 192 is filled in the second region upper electrode interconnect via 182. The first-region upper electrode metal interconnect layer 191 is located in the memory cell array region 80, and its bottom is in contact with the first stacked layer 250A of the first region; the second-region upper electrode metal interconnect layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the functional layer 342 of the second region. The entire lower surface of the bottom of the first-region upper electrode metal interconnect layer 191 is in contact with the upper surface of the first upper electrode metal layer 253, so that the first-region upper electrode metal interconnect layer 191 and the first upper electrode metal layer 253 are in full contact, and short circuits are prevented from occurring due to partial contact between the bottom of the first-region upper electrode metal interconnect layer 191 and the upper surface of the first lower electrode metal layer 251.

[0122] Specifically, the first upper electrode metal layer 253 is electrically connected to the first region upper electrode metal connection layer 191, and the second region functional layer 342 is electrically connected to the second region upper electrode metal connection layer 192.

[0123] Specifically, the material used for the second dielectric layer 170 may be silicon nitride (Si3N4). In the embodiments of this application, the second dielectric layer 170 may also be selected from other materials according to the actual application scenario and process requirements, and no limitation is made here.

[0124] Specifically, the second dielectric layer 170 can isolate the first region upper electrode metal connection layer 191 and the second region upper electrode metal connection layer 192 from the non-connection area, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0125] Specifically, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can be made of conductive materials such as copper. In the embodiments of this application, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can also be made of other metals as needed, and are not limited here.

[0126] In summary, by utilizing the fabrication scheme for non-volatile two-sided memory cells provided above, this disclosed embodiment simultaneously etches a first lower electrode interconnect via 141 located in the memory cell array region 80 and a second lower electrode interconnect via 142 located in the peripheral circuit region 90 based on a first patterned photomask layer 391. Furthermore, based on the first patterned photomask layer 391, a first upper electrode interconnect via 181 located in the memory cell array region 80 and a second upper electrode interconnect via 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. This allows for the fabrication of non-volatile two-sided memory cells using only one patterned photomask layer, thereby shortening the fabrication process of non-volatile two-sided memory cells and reducing fabrication costs. Furthermore, by using the same patterned photomask layer (i.e., the first patterned photomask layer 391) as the etched lower electrode interconnect via (i.e., the first lower electrode interconnect via 141 located in the memory cell array region 80 and the second lower electrode interconnect via 142 located in the peripheral circuit region 90) as a mask, the upper electrode interconnect via (i.e., the first upper electrode interconnect via 181 located in the memory cell array region 80 and the second upper electrode interconnect via 182 located in the peripheral circuit region 90) can be etched. This can improve the alignment accuracy of the lower electrode interconnect via and the upper electrode interconnect via, avoid problems such as contact resistance changes caused by poor alignment, and improve the stability and reliability of the formed non-volatile two-terminal memory cells.

[0127] In one embodiment of this application, a non-volatile two-terminal memory cell is also provided. The non-volatile two-terminal memory cell includes a first dielectric layer 130, which is stacked on the upper surface of a first region lower electrode metal interconnect layer 111 in a first region and the upper surface of a second region lower electrode metal interconnect layer 112 in a second region. A first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142 are formed in the first dielectric layer 130 based on a first patterned photomask layer 391. A first region first stacked layer 250A fills the first region lower electrode interconnect via 141 and connects with the first region lower electrode metal interconnect layer 112 in the second region. The lower electrode metal connection layer 111 of the first region is electrically connected; the second dielectric layer 170 is formed in the first region and the second region; the upper electrode interconnect via 181 of the first region and the upper electrode interconnect via 182 of the second region are formed in the second dielectric layer 170 based on the first patterned photomask layer 391; the upper electrode metal connection layer 191 of the first region is formed in the upper electrode interconnect via 181 of the first region and is electrically connected to the first stacked layer 250A of the first region; the upper electrode metal connection layer 192 of the second region is formed in the upper electrode interconnect via 182 of the second region and is electrically connected to the lower electrode metal connection layer 112 of the second region.

[0128] In this case, the upper surface of the first stacked layer 250A in the first region is flush with the upper surface of the first dielectric layer 130.

[0129] The cross-sectional shape and size of the lower electrode interconnect via 141 in the first region are not limited. Preferably, the cross-sectional shape of the lower electrode interconnect via 141 in the first region is an inverted trapezoid, wherein the width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid. The width of the lower base of the inverted trapezoid is greater than The angle between the legs and the lower base of the inverted trapezoid is greater than 105 degrees.

[0130] In one embodiment of this application, the non-volatile two-terminal storage cell further includes a second functional layer 342, which partially fills the second lower electrode interconnect via 142 and is electrically connected to the second lower electrode metal connection layer 112 and the second upper electrode metal connection layer 192.

[0131] In one embodiment of this application, the first stacked layer 250A in the first region includes a first lower electrode metal layer 251, a first switching layer 252 and a first upper electrode metal layer 253 stacked sequentially.

[0132] In the embodiments of this application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure, and the material used may be one of TiN (titanium nitride), Ti (titanium), Ta (tantalum), W (tungsten), etc. Alternatively, the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 may use the same metal material, thereby ensuring close contact between the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 and avoiding the formation of voids.

[0133] When the first lower electrode metal layer 251 adopts a two-layer structure, it may include a first lower electrode metal layer 1 and a first lower electrode metal layer 2 covering the upper surface of the first lower electrode metal layer 1. In this case, the first lower electrode metal layer 1 can be made of TiN (titanium nitride), and the first lower electrode metal layer 2 can be made of W (tungsten). The first lower electrode metal layer 2 can serve as a connecting layer between the first lower electrode metal layer 1 and the first switching layer. Furthermore, by using W (tungsten) as the material for the first lower electrode metal layer 2, not only can the thermal conductivity and resistance of the first lower electrode metal layer 2 be ensured, but heat can also be conducted quickly, promoting heat dissipation and reducing heat generation, thereby minimizing thermal damage to the fabricated non-volatile two-sided memory cell. Using W (tungsten) as the material for the first lower electrode metal layer 2 also ensures that the first lower electrode metal layer 2 has higher inertness, thus preventing chemical reactions between the first lower electrode metal layer 2 and the first switching layer, and ensuring the thermal stability of the fabricated non-volatile two-sided memory cell.

[0134] In the embodiments of this application, the material of the first switching layer 252 may be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), or tantalum oxide (TaO), which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 may also be selected from other materials according to the actual application scenario and process requirements, which are not limited here.

[0135] In the embodiments of this application, the first upper electrode metal layer 253 may be a single-layer or multi-layer structure.

[0136] When the first upper electrode metal layer 253 adopts a two-layer structure, the first upper electrode metal layer 253 may include a first upper electrode metal layer one and a first upper electrode metal layer two covering the surface of the first upper electrode metal layer one. In this case, the material used in the first upper electrode metal layer one is more easily oxidized than the material used in the first upper electrode metal layer two. The material used in the first upper electrode metal layer one may be AlN (aluminum nitride), and the material used in the first upper electrode metal layer two may be TiN (titanium nitride).

[0137] The material used in the first upper electrode metal layer is more easily oxidized than the material used in the second upper electrode metal layer. The purpose is that, as the upper electrode of the non-volatile two-sided memory cell, the first upper electrode metal layer provides metal ions to the first switching layer 252, but also prevents the first upper electrode metal layer from being oxidized and causing adverse effects, such as reduced conductivity. Therefore, the second upper electrode metal layer, which is less prone to oxidation than the first upper electrode metal layer, needs to cover the first upper electrode metal layer, thereby reducing the possibility of the first upper electrode metal layer being oxidized and ensuring that the characteristics of the non-volatile two-sided memory cell are not affected.

[0138] Other materials can also be used for the first upper electrode metal layer one and the first upper electrode metal layer two.

[0139] In one embodiment of this application, the first lower electrode metal layer 251 and the second functional layer 342 are made of the same material, and the thickness of the first lower electrode metal layer 251 is not less than the thickness of the second functional layer 342.

[0140] In one embodiment of this application, the bottom of the first stacked layer 250A in the first region is in contact with the upper surface of the lower electrode metal connection layer 111 in the first region, and the bottom of the upper electrode metal connection layer 191 in the first region is in contact with the upper surface of the first stacked layer 250A in the first region.

[0141] In one embodiment of this application, the bottom of the second functional layer 342 is in contact with the upper surface of the second lower electrode metal connection layer 112, and the bottom of the second upper electrode metal connection layer 192 is in contact with the upper surface of the second functional layer 342.

[0142] In one embodiment of this application, the bottom of the first lower electrode metal layer 251 contacts the upper surface of the first region lower electrode metal connection layer 111, and the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253. The entire lower surface of the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, ensuring sufficient contact between the first region upper electrode metal connection layer 191 and the first upper electrode metal layer 253, and preventing a short circuit caused by partial contact between the bottom of the first region upper electrode metal connection layer 191 and the upper surface of the first lower electrode metal layer 251.

[0143] The aforementioned non-volatile two-ended memory cell saves on patterned photomask layers, and the manufacturing method facilitates the formation and alignment of the lower electrode interconnect vias and upper electrode interconnect vias of the non-volatile two-ended memory cell. Therefore, it can shorten the fabrication process of the non-volatile two-ended memory cell, reduce the fabrication difficulty, and thus reduce the fabrication cost.

[0144] In one embodiment of this application, a memory is also provided, which includes one or more non-volatile dual-ended memory cells as described in the embodiments of this application. This memory employs the aforementioned non-volatile dual-ended memory cells, thereby improving the yield rate of the memory and reducing its manufacturing cost.

[0145] In one embodiment of this application, an electronic device is also provided, which includes the memory described in the embodiments of this application. This electronic device uses the aforementioned memory, thus reducing the possibility of quality problems with the memory in the electronic device and lowering the hardware cost of the electronic device.

[0146] Figure 4 shows an exemplary structural block diagram of a method for fabricating a non-volatile two-ended memory cell according to further embodiments of this application.

[0147] As shown in Figure 4, the fabrication method 400 of the non-volatile two-terminal memory cell includes the following steps: In step S410, a first dielectric layer 130 is stacked on the upper surface of the first region lower electrode metal interconnect layer 111 located in the first region and the upper surface of the second region lower electrode metal interconnect layer 112 located in the second region; In step S420, based on the first patterned photomask layer 391, a first region lower electrode interconnect via 141 contacting the upper surface of the first region lower electrode metal interconnect layer 111 and a second region lower electrode interconnect via 142 contacting the upper surface of the second region lower electrode metal interconnect layer 112 are formed in the first dielectric layer 130; In step S430, a memory cell stacking layer 350 is formed above the first region lower electrode interconnect via 141. 50 contacts the upper surface of the first region lower electrode interconnect via 141; in step S440, a second dielectric layer 170 is formed in the first region and the second region; in step S450, based on the first patterned photomask layer 391, a first region upper electrode interconnect via 181 and a second region upper electrode interconnect via 182 are formed in the second dielectric layer 170; in step S460, a first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnect via 181, and a second region upper electrode metal connection layer 192 is formed in the second region upper electrode interconnect via 182, wherein the first region upper electrode metal connection layer 191 is electrically connected to the first region lower electrode metal connection layer 111, and the second region upper electrode metal connection layer 192 is electrically connected to the second region lower electrode metal connection layer 112.

[0148] Based on the fabrication process of the non-volatile two-ended memory cell in Figure 4, the exemplary process flow of the fabrication method 400 of the non-volatile two-ended memory cell using some embodiments of this application will be described in detail below with reference to the semiconductor cross-sectional structure schematic diagrams shown in Figures 5A-5I.

[0149] Figures 5A-5I show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to further embodiments of this disclosure.

[0150] Figure 5A shows a schematic diagram of the semiconductor cross-sectional structure for forming the first patterned photomask layer 391 according to an embodiment of this application.

[0151] As shown in Figure 5A, a multilayer semiconductor structure is provided, and a first patterned photomask layer 391 is formed on top of the semiconductor structure. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed lower electrode interconnect vias 141 in the first region of the memory cell array region 80 and the lower electrode interconnect vias 142 in the second region of the peripheral circuit region 90.

[0152] Specifically, the semiconductor structure is processed to form the following structure in sequence: a lower electrode metal connection layer 110 surrounded by a lower dielectric layer 120, a first dielectric layer 130, a lower electrode hard mask layer 380, and a first patterned photomask layer 391.

[0153] The lower electrode metal connection layer 110 includes a first lower electrode metal connection layer 111 located in the memory cell array region 80 and a second lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are separated by a lower dielectric layer 120 to prevent short circuits from forming between the two first lower electrode metal connection layers 111, between the two second lower electrode metal connection layers 112, or between the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112. Simultaneously, the upper surfaces of the first lower electrode metal connection layer 111 and the second lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first lower electrode metal connection layer 111, the second lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0154] Similarly, the number of lower electrode metal connection layers 111 in the first region can be one or more. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be the same or different. The materials used for the lower electrode metal connection layers 111 and 112 in the first region can be copper. The main advantages of copper compared to other metals are its high electrical conductivity, high thermal conductivity, corrosion resistance, suitable strength, and ease of processing and forming. In the embodiments of this application, other metals can also be used for the lower electrode metal connection layers 111 and 112 in the first region as needed, and this is not limited here.

[0155] Specifically, similarly, the material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, low-k dielectric constant (Low-k) materials, etc. More specifically, the low-k dielectric constant (Low-k) material can be porous silicon dioxide, silicon fluoride glass, etc. In the embodiments of this application, the lower dielectric layer 120 can also be selected from other materials according to the actual application scenario and process requirements, and is not limited here.

[0156] Specifically, various known processes can be used to fabricate the lower dielectric layer 120 around the lower electrode metal interconnect layer 110, and the embodiments of this application are not limited in this respect.

[0157] For example, a lower dielectric layer 120 is made to surround a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, exposing the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112. This part of the process includes: first, providing a lower dielectric layer 120, forming a patterned photomask layer on the lower dielectric layer 120, selectively exposing photoresist using an exposure machine, developing to remove exposed or unexposed portions of the photoresist, etching or depositing patterns in the exposed areas, removing remaining photoresist, and continuing to form the desired first groove located in the memory cell array region 80 and the second groove located in the peripheral circuit region 90 by dry etching or wet etching, wherein the number of first grooves can be single or multiple. Then, metal material is deposited in the first groove and the second groove. Finally, the metal material is planarized to form a first region lower electrode metal connection layer 111 and a second region lower electrode metal connection layer 112, such that the upper surfaces of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush. Thus, a lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 is obtained, and the upper surfaces of the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112 are exposed.

[0158] Specifically, the lower electrode metal connection layer 110, surrounded by the lower dielectric layer 120, can isolate the first region lower electrode metal connection layer 111 from other unrelated parts; it can also isolate the second region lower electrode metal connection layer 112 from other unrelated parts. This prevents current from flowing along unwanted paths, avoiding short circuits and leakage. For example, it prevents direct connections between the two first region lower electrode metal connection layers 111, between the two second region lower electrode metal connection layers 112, or between the first region lower electrode metal connection layer 111 and the second region lower electrode metal connection layer 112, thus avoiding short circuits.

[0159] Specifically, the first dielectric layer 130 is formed on the upper surface of the first region lower electrode metal connection layer 111, the second region lower electrode metal connection layer 112, and the exposed lower dielectric layer 120. The first dielectric layer 130 can be formed by a thin film deposition process. The first dielectric layer 130 can be a single layer or multiple layers. For example, the first dielectric layer 130 can include a first dielectric layer and a first dielectric layer stacked sequentially. The first dielectric layer can be a silicon nitride (SiN) thin film or a nitro-doped silicon carbide (NDC) thin film, and the first dielectric layer can be a low-temperature oxide (LTO), a silicon dioxide layer (SiO2), or a silicon-rich oxide (SRO), etc. In the embodiments of this application, the first dielectric layer and the first dielectric layer can also be made of other materials according to the actual application scenario and process requirements, which are not limited here.

[0160] The first dielectric layer 130 can protect the first region second lower electrode metal layer 15111 and the second region functional layer 342 (including the second region second lower electrode metal layer 15112) from external damage.

[0161] Specifically, a lower electrode hard mask layer 380 is formed above the first dielectric layer 130. The lower electrode hard mask layer 380 can be formed by a thin film deposition process. The lower electrode hard mask layer 380 may include a lower electrode hard mask first layer 381 and a lower electrode hard mask second layer 382. The lower electrode hard mask first layer 381 and the lower electrode hard mask second layer 382 may be made of the same material or different materials. The lower electrode hard mask first layer 381 and the lower electrode hard mask second layer 382 may be made of at least one material selected from amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonoxynitride, and silicon carbonitride.

[0162] Specifically, the first patterned photomask layer 391 can be made of positive or negative photoresist. The first patterned photomask layer 391 is formed using various known processes, and this application embodiment is not limited in this respect. For example, a photomask layer is coated above the lower electrode hard mask layer 380, and the photomask layer is exposed to form exposed and unexposed areas. Then, the exposed photomask layer is developed to remove the photomask layer in the exposed or unexposed areas, forming the first patterned photomask layer 391. When a positive photoresist is used, the photomask layer in the exposed areas changes from being insoluble in the developer to being soluble in the developer and is removed during development. When a negative photoresist is used, the photomask layer in the exposed areas changes from being soluble in the developer to being insoluble in the developer and is not removed during development. Thus, when a negative photoresist is used, the photomask layer in the unexposed areas is removed.

[0163] Figure 5B shows a schematic cross-sectional view of the semiconductor structure forming the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 according to an embodiment of this application.

[0164] As shown in Figure 5B, based on the first patterned photomask layer 391, the exposed lower electrode hard mask layer 380 is etched until the corresponding position of the first dielectric layer 130 is exposed. The remaining lower electrode hard mask layer 380 forms a patterned lower electrode hard mask layer, and the aforementioned first patterned photomask layer 391 is removed. Next, using the patterned lower electrode hard mask layer as a mask, the exposed first dielectric layer 130 is etched to form a first region lower electrode interconnect via 141 and a second region lower electrode interconnect via 142 in the first dielectric layer 130, and the remaining lower electrode hard mask layer 380 is removed.

[0165] Specifically, the first region lower electrode interconnect via 141 is located in the memory cell array region 80, and its bottom contacts the upper surface of the first region lower electrode metal connection layer 111. The second region lower electrode interconnect via 142 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112. Both the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum-shaped structure or a trapezoidal structure. In the embodiments of this application, the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142 can also be selected with other structural shapes according to the actual application scenario and process requirements, which are not limited here.

[0166] In this embodiment, the cross-sectional shape of the lower electrode interconnect via 141 in the first region is an inverted trapezoid, with the width of the upper base of the inverted trapezoid greater than the width of the lower base. The width of the lower base of the inverted trapezoid is greater than The angle between the legs and the lower base of the inverted trapezoid is greater than 105 degrees.

[0167] Specifically, since the first lower electrode interconnect via 141 located in the memory cell array region 80 corresponds to the subsequently formed first upper electrode interconnect via 181 located in the memory cell array region 80, and the second lower electrode interconnect via 142 located in the peripheral circuit region 90 corresponds to the subsequently formed second upper electrode interconnect via 182 located in the peripheral circuit region 90, the first lower electrode interconnect via 141 and the second lower electrode interconnect via 142, as well as the first upper electrode interconnect via 181 and the second upper electrode interconnect via 182, can be etched based on the first patterned photomask layer 391.

[0168] Figure 5C shows a schematic diagram of the semiconductor cross-sectional structure of the deposited second lower electrode metal layer 1511 according to an embodiment of this application.

[0169] As shown in Figure 5C, a second lower electrode metal layer 1511 is deposited in the first region lower electrode interconnect via 141, the second region lower electrode interconnect via 142, and on the upper surface of the first dielectric layer 130 through a thin film deposition process, so that the second lower electrode metal layer 1511 fills the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0170] In the embodiments of this application, during the deposition of the second lower electrode metal layer 1511, the second lower electrode metal layer 1511 may be deposited only on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, or the second lower electrode metal layer 1511 may be deposited on the inner walls and bottom of the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142, as well as on a portion of the upper surface of the first dielectric layer 130. However, the deposited second lower electrode metal layer 1511 must at least completely fill the first region lower electrode interconnect via 141 and the second region lower electrode interconnect via 142.

[0171] Figure 5D shows a schematic diagram of the semiconductor cross-sectional structure of the second lower electrode metal after planarization treatment of layer 1511 according to an embodiment of this application.

[0172] As shown in Figure 5D, the second lower electrode metal layer 1511 is planarized to form a first region second lower electrode metal layer 15111 and a second region second lower electrode metal layer 15112. Specifically, the first region second lower electrode metal layer 15111 fills the first region lower electrode interconnect via 141, and the second region second lower electrode metal layer 15112 fills the second region lower electrode interconnect via 142. The upper surfaces of the first region second lower electrode metal layer 15111, the second region second lower electrode metal layer 15112, and the upper surface of the first dielectric layer 130 are flush.

[0173] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0174] Specifically, the first lower electrode metal layer 15111 of the first region is electrically connected to the first lower electrode metal connecting layer 111, and the second lower electrode metal layer 15112 of the second region is electrically connected to the second lower electrode metal connecting layer 112.

[0175] In this embodiment, the bottom of the second lower electrode metal layer 15111 in the first region is in contact with the upper surface of the lower electrode metal connecting layer 111 in the first region, and the bottom of the second lower electrode metal layer 15112 in the second region is in contact with the upper surface of the lower electrode metal connecting layer 112 in the second region.

[0176] Specifically, the first lower electrode metal layer 15111 and the second lower electrode metal layer 15112 in the first region can be a single layer or multiple layers. The first lower electrode metal layer 15111 and the second lower electrode metal layer 15112 in the first region can be one or more of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), etc. In the embodiments of this application, the first region second lower electrode metal layer 15111 and the first region lower electrode metal connecting layer 111 can be made of the same metal material, and the second region second lower electrode metal layer 15112 and the second region lower electrode metal connecting layer 112 can be made of the same metal material, so that the first region second lower electrode metal layer 15111 and the first region lower electrode metal connecting layer 111 are in close contact, and the second region second lower electrode metal layer 15112 and the second region lower electrode metal connecting layer 112 are in close contact, avoiding the formation of holes between the two materials due to the different coefficients of thermal expansion caused by thermal expansion and contraction.

[0177] Figure 5E shows a schematic diagram of the semiconductor cross-sectional structure of the memory cell stack layer 350 and sidewall 159 in an embodiment of this application.

[0178] As shown in Figure 5E, a memory cell stack layer 350 is deposited on the upper surface of the exposed first dielectric layer 130, the upper surface of the second lower electrode metal layer 15111 in the first region, and the upper surface of the second lower electrode metal layer 15112 in the second region. The memory cell stack layer 350 includes the second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154. Next, photolithography and etching processes are used to etch the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Then, sidewalls 159 are deposited in the etched areas of the second switching layer 152, the second upper electrode metal layer 153, the upper electrode hard mask layer 154, and the exposed areas of the first dielectric layer 130. The deposited sidewalls 159 and the second lower electrode metal layer 1512 are etched to stop the etching process on the upper surface of the first dielectric layer 130, so that the etched sidewalls 159 can wrap the memory cell stack layer 350 from the side.

[0179] In the embodiments of this application, during the etching process of the deposited sidewall 159 and the second lower electrode metal layer 1512, some or all of the second lower electrode metal layer 15112 in the second region may be consumed due to over-etching. In this embodiment, a portion of the second lower electrode metal layer 15112 in the second region is consumed, and the remaining portion forms the second functional layer 342.

[0180] At this time, the materials of the second lower electrode metal layer 15111 in the first region and the functional layer 342 in the second region are the same, and the thickness of the second lower electrode metal layer 15111 in the first region is not less than the thickness of the functional layer 342 in the second region.

[0181] The functions of the second functional layer 342 include at least the following two aspects. Taking the lower electrode metal connection layer 112 of the second region as a copper conductor as an example.

[0182] First, the second functional layer 342 is used as a barrier layer here. The second functional layer 342 covers the copper conductor. After the upper surface of the second lower electrode metal connection layer 112 is exposed to copper (i.e. after the second lower electrode interconnect via 142 is formed), by covering the second functional layer 342, the copper on the upper surface of the second lower electrode metal connection layer 112 can be prevented from being oxidized or the oxidation diffusion can be slowed down. At the same time, it can increase the QTime (Queue Time or process time interval) of the fabrication process.

[0183] Secondly, the second functional layer 342 can be used as an etching stop layer. When etching is performed on the top of the second functional layer 342, it serves as a stop layer for the etching process, thereby effectively controlling the accuracy of etching stop and preventing the copper wire (i.e., the second lower electrode metal connection layer 112) from being etched and thus causing damage to the copper wire.

[0184] Preferably, the thickness of the second functional layer 342 ranges from [specific range missing]. Between. When the thickness is less than If the thickness is too small, the second functional layer 342 may be etched through, leading to its failure. Furthermore, an excessively thin second functional layer 342 would be too costly to manufacture in actual production. When the thickness is greater than... At this time, the second functional layer 342 will significantly increase the resistivity of the conductive metal interconnects in the peripheral circuit region 90. Therefore, the thickness of the second functional layer 342 is located at... This arrangement avoids a significant increase in resistivity, prevents etching penetration that could render the function ineffective, and facilitates preparation in actual production.

[0185] Specifically, the second lower electrode metal layer 1512 can be made of the same material or a different material from the aforementioned second lower electrode metal layer 15111 in the first region. The material used for the second lower electrode metal layer 1512 may include one or more of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and aluminum (Al).

[0186] Specifically, the material of the second switching layer 152 may include metal oxides such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), and tantalum oxide (TaO), which are used to change the resistance between the second lower electrode metal layer 1512 and the second upper electrode metal layer 153. In the embodiments of this application, the second switching layer 152 may also be selected from other materials according to the actual application scenario and process requirements, which is not limited here.

[0187] Specifically, the material used for the second upper electrode metal layer 153 may include one or more of gold (Au), platinum (Pt), copper (Cu), and aluminum (Al). In the embodiments of this application, the second upper electrode metal layer 153 may also be selected from other materials according to the actual application scenario and process requirements, which is not limited here.

[0188] Specifically, the upper electrode hard mask layer 154 may be made of at least one material selected from amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonoxylate, and silicon carbonitride. The upper electrode hard mask layer 154 is used to protect the underlying second upper electrode metal layer 153 during subsequent fabrication processes. The upper electrode hard mask layer 154 may be a non-conductive layer.

[0189] Figure 5F shows a schematic diagram of the semiconductor cross-sectional structure for forming the second dielectric layer 170 according to an embodiment of this application.

[0190] As shown in Figure 5F, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the surface of the exposed memory cell stack 350, the surface of the exposed sidewall 159, and the upper surface of the second region functional layer 342. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the memory cell stack 350 and fills the remaining space of the second region lower electrode interconnect via 142.

[0191] Figure 5G shows a schematic diagram of the semiconductor cross-sectional structure of forming the first patterned photomask layer 391 according to an embodiment of this application.

[0192] As shown in Figure 5G, a first patterned photomask layer 391 is formed above the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed upper electrode interconnect vias 181 in the first region of the memory cell array region 80 and the upper electrode interconnect vias 182 in the second region of the peripheral circuit region 90.

[0193] Figure 5H shows a schematic cross-sectional view of the semiconductor structure forming the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182 according to an embodiment of this application.

[0194] As shown in Figure 5H, based on the first patterned photomask layer 391, the exposed second dielectric layer 170 and the upper electrode hard mask layer 154 are etched up to the corresponding positions of the second upper electrode metal layer 153, and the exposed second dielectric layer 170 up to the corresponding positions of the second functional layer 342. A first region upper electrode interconnect via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154, and a second region upper electrode interconnect via 182 is formed in the second dielectric layer 170. The first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second functional layer 342. Then, the first patterned photomask layer 391 is removed.

[0195] Specifically, the bottom of the first region upper electrode interconnect via 181 is in contact with the second upper electrode metal layer 153, and the bottom of the second region upper electrode interconnect via 182 is in contact with the second region functional layer 342.

[0196] Figure 5I shows a schematic diagram of the semiconductor cross-sectional structure of the first region upper electrode metal interconnect layer 191 and the second region upper electrode metal interconnect layer 192 according to an embodiment of this application.

[0197] As shown in Figure 5I, a first-region upper electrode metal connection layer 191 is filled in the first region upper electrode interconnect via 181, and a second-region upper electrode metal connection layer 192 is filled in the second region upper electrode interconnect via 182. The first-region upper electrode metal connection layer 191 is located in the memory cell array region 80, and its bottom is in contact with the memory cell stack layer 350; the second-region upper electrode metal connection layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the second region functional layer 342.

[0198] Specifically, the second upper electrode metal layer 153 is electrically connected to the first region upper electrode metal connection layer 191, and the second region functional layer 342 is electrically connected to the second region upper electrode metal connection layer 192.

[0199] Specifically, the material used for the second dielectric layer 170 may be silicon nitride (Si3N4). In the embodiments of this application, the second dielectric layer 170 may also be selected from other materials according to the actual application scenario and process requirements, and no limitation is made here.

[0200] Specifically, the second dielectric layer 170 can isolate the second upper electrode metal layer 153 and the first region upper electrode metal connection layer 191 from the non-connection area, and isolate the second region upper electrode metal connection layer 192 from the non-connection area, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0201] Specifically, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can be made of conductive materials such as copper. In the embodiments of this application, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can also be made of other metals as needed, and are not limited here.

[0202] In summary, by utilizing the fabrication scheme for non-volatile two-sided memory cells provided above, this disclosed embodiment simultaneously etches a first lower electrode interconnect via 141 located in the memory cell array region 80 and a second lower electrode interconnect via 142 located in the peripheral circuit region 90 based on a first patterned photomask layer 391. Furthermore, based on the first patterned photomask layer 391, a first upper electrode interconnect via 181 located in the memory cell array region 80 and a second upper electrode interconnect via 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. This allows for the fabrication of non-volatile two-sided memory cells using only one patterned photomask layer, thereby shortening the fabrication process of non-volatile two-sided memory cells and reducing fabrication costs. Furthermore, by using the same patterned photomask layer (i.e., the first patterned photomask layer 391) as the etched lower electrode interconnect via (i.e., the first lower electrode interconnect via 141 located in the memory cell array region 80 and the second lower electrode interconnect via 142 located in the peripheral circuit region 90) as a mask, the upper electrode interconnect via (i.e., the first upper electrode interconnect via 181 located in the memory cell array region 80 and the second upper electrode interconnect via 182 located in the peripheral circuit region 90) can be etched. This can improve the alignment accuracy of the lower electrode interconnect via and the upper electrode interconnect via, avoid problems such as contact resistance changes caused by poor alignment, and improve the stability and reliability of the formed non-volatile two-terminal memory cells.

[0203] Next, based on the fabrication process of the non-volatile two-ended memory cell in FIG4, and in conjunction with the semiconductor cross-sectional structure schematic diagrams shown in FIG6A-FIG6I, an exemplary process flow of the fabrication method 400 of the non-volatile two-ended memory cell using other embodiments of this application will be described in detail.

[0204] The fabrication steps of the non-volatile two-terminal memory cell shown in Figures 6A-6D are the same as those shown in Figures 5A-5D, so they will not be described in detail here.

[0205] Figure 6E shows a schematic diagram of the semiconductor cross-sectional structure of the memory cell stack layer 350 and sidewall 159 according to an embodiment of this application.

[0206] As shown in Figure 6E, a memory cell stack layer 350 is deposited on the upper surface of the exposed first dielectric layer 130, the upper surface of the second lower electrode metal layer 15111 in the first region, and the upper surface of the second lower electrode metal layer 15112 in the second region. The memory cell stack layer 350 includes the second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154. Next, photolithography and etching processes are used to etch the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Then, sidewalls 159 are deposited in the etched areas of the second switching layer 152, the second upper electrode metal layer 153, the upper electrode hard mask layer 154, and the exposed areas of the first dielectric layer 130. The deposited sidewalls 159 and the second lower electrode metal layer 1512 are etched to stop the etching process on the upper surface of the first dielectric layer 130, so that the etched sidewalls 159 can wrap the memory cell stack layer 350 from the side.

[0207] In the embodiments of this application, during the etching process of the deposited sidewall 159 and the second lower electrode metal layer 1512, some or all of the second lower electrode metal layer 15112 in the second region may be consumed due to over-etching. Unlike FIG5E, in this embodiment, all of the second lower electrode metal layer 15112 in the second region is consumed, exposing the upper surface of the lower electrode metal bonding layer 112 in the second region.

[0208] Compared to the technical solution in Figure 5E, this technical solution does not require specific equipment to control the thickness of the remaining portion of the second lower electrode metal layer 15112 in the second region, and the manufacturing process is relatively simple and the cost is lower.

[0209] Specifically, the second lower electrode metal layer 1512 can be made of the same material or a different material from the aforementioned second lower electrode metal layer 15111 in the first region. The material used for the second lower electrode metal layer 1512 may include one or more of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and aluminum (Al).

[0210] Specifically, the material of the second switching layer 152 may include metal oxides such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), and tantalum oxide (TaO), which are used to change the resistance between the second lower electrode metal layer 1512 and the second upper electrode metal layer 153. In the embodiments of this application, the second switching layer 152 may also be selected from other materials according to the actual application scenario and process requirements, which is not limited here.

[0211] Specifically, the material used for the second upper electrode metal layer 153 may include one or more of gold (Au), platinum (Pt), copper (Cu), and aluminum (Al). In the embodiments of this application, the second upper electrode metal layer 153 may also be selected from other materials according to the actual application scenario and process requirements, which is not limited here.

[0212] Specifically, the upper electrode hard mask layer 154 may be made of at least one material selected from amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonoxylate, and silicon carbonitride. The upper electrode hard mask layer 154 is used to protect the underlying second upper electrode metal layer 153 during subsequent fabrication processes. The upper electrode hard mask layer 154 may be a non-conductive layer.

[0213] Figure 6F shows a schematic diagram of the semiconductor cross-sectional structure for forming the second dielectric layer 170 according to an embodiment of this application.

[0214] As shown in Figure 6F, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the surface of the exposed memory cell stack 350, and the upper surface of the exposed sidewall 159. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the memory cell stack 350 and fills the remaining space of the second region lower electrode interconnect via 142.

[0215] Figure 6G shows a schematic diagram of the semiconductor cross-sectional structure forming the first patterned photomask layer 391 according to an embodiment of this application.

[0216] As shown in Figure 6G, a first patterned photomask layer 391 is formed above the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the subsequently formed upper electrode interconnect vias 181 in the first region of the memory cell array region 80 and the upper electrode interconnect vias 182 in the second region of the peripheral circuit region 90.

[0217] Figure 6H shows a schematic diagram of the semiconductor cross-sectional structure of the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182 according to an embodiment of this application.

[0218] As shown in Figure 6H, based on the first patterned photomask layer 391, the exposed second dielectric layer 170 and the upper electrode hard mask layer 154 are etched until the corresponding positions of the second upper electrode metal layer 153 are exposed, and the exposed second dielectric layer 170 is etched until the corresponding positions of the second region lower electrode metal interconnect layer 112 are exposed. A first region upper electrode interconnect via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154, and a second region upper electrode interconnect via 182 is formed in the second dielectric layer 170. The first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90, and unlike the technical solution in Figure 5H, its bottom contacts the upper surface of the second region lower electrode metal interconnect layer 112. Then, the first patterned photomask layer 391 is removed.

[0219] Specifically, the bottom of the upper electrode interconnect via 181 in the first region is in contact with the second upper electrode metal layer 153, and the bottom of the upper electrode interconnect via 182 in the second region is in direct contact with the lower electrode metal connection layer 112 in the second region.

[0220] Figure 6I shows a schematic cross-sectional view of the semiconductor structure in which the first region upper electrode metal interconnect layer 191 and the second region upper electrode metal interconnect layer 192 are formed according to an embodiment of this application.

[0221] As shown in Figure 6I, the first region upper electrode interconnect via 181 is filled with a first region upper electrode metal connection layer 191, and the second region upper electrode interconnect via 182 is filled with a second region upper electrode metal connection layer 192. The first region upper electrode metal connection layer 191 is located in the memory cell array region 80, and its bottom is in contact with the memory cell stack layer 350; the second region upper electrode metal connection layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the second region lower electrode metal connection layer 112.

[0222] Specifically, the second upper electrode metal layer 153 is electrically connected to the first region upper electrode metal connection layer 191, and the second region lower electrode metal connection layer 112 is electrically connected to the second region upper electrode metal connection layer 192.

[0223] Specifically, the material used for the second dielectric layer 170 may be silicon nitride (Si3N4). In the embodiments of this application, the second dielectric layer 170 may also be selected from other materials according to the actual application scenario and process requirements, and no limitation is made here.

[0224] Specifically, the second dielectric layer 170 can isolate the second upper electrode metal layer 153 and the first region upper electrode metal connection layer 191 from the non-connection area, and isolate the second region upper electrode metal connection layer 192 from the non-connection area, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0225] Specifically, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can be made of conductive materials such as copper. In the embodiments of this application, the first upper electrode metal connection layer 191 and the second upper electrode metal connection layer 192 can also be made of other metals as needed, and are not limited here.

[0226] In summary, by utilizing the fabrication scheme for non-volatile two-sided memory cells provided above, this disclosed embodiment simultaneously etches a first lower electrode interconnect via 141 located in the memory cell array region 80 and a second lower electrode interconnect via 142 located in the peripheral circuit region 90 based on a first patterned photomask layer 391. Furthermore, based on the first patterned photomask layer 391, a first upper electrode interconnect via 181 located in the memory cell array region 80 and a second upper electrode interconnect via 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. This allows for the fabrication of non-volatile two-sided memory cells using only one patterned photomask layer, thereby shortening the fabrication process of non-volatile two-sided memory cells and reducing fabrication costs. Furthermore, by using the same patterned photomask layer (i.e., the first patterned photomask layer 391) as the etched lower electrode interconnect via (i.e., the first lower electrode interconnect via 141 located in the memory cell array region 80 and the second lower electrode interconnect via 142 located in the peripheral circuit region 90) as a mask, the upper electrode interconnect via (i.e., the first upper electrode interconnect via 181 located in the memory cell array region 80 and the second upper electrode interconnect via 182 located in the peripheral circuit region 90) can be etched. This can improve the alignment accuracy of the lower electrode interconnect via and the upper electrode interconnect via, avoid problems such as contact resistance changes caused by poor alignment, and improve the stability and reliability of the formed non-volatile two-terminal memory cells.

[0227] In one embodiment of this application, a non-volatile dual-ended memory cell is also provided. The non-volatile dual-ended memory cell includes a first dielectric layer 130 stacked on the upper surface of a first region lower electrode metal interconnect layer 111 in a first region and on the upper surface of a second region lower electrode metal interconnect layer 112 in a second region; a first region lower electrode interconnect via 141 formed in the first dielectric layer 130 based on a first patterned photomask layer 391, and in contact with the upper surface of the first region lower electrode metal interconnect layer 111; and a second region lower electrode interconnect via 142 formed in the first dielectric layer 130 based on the first patterned photomask layer 391, and in contact with the upper surface of the second region lower electrode metal interconnect layer 112. The storage cell stack layer 350 is in contact with the upper surface of the first region lower electrode interconnect via 141; the second dielectric layer 170 is formed in the first region and the second region; the first region upper electrode interconnect via 181 and the second region upper electrode interconnect via 182 are formed in the second dielectric layer 170 based on the first patterned photomask layer 391 and penetrate the second dielectric layer 170; the first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnect via 181 and is electrically connected to the first region lower electrode metal connection layer 111; the second region upper electrode metal connection layer 192 is formed in the second region upper electrode interconnect via 182 and is electrically connected to the second region lower electrode metal connection layer 112.

[0228] The cross-sectional shape and size of the lower electrode interconnect via 141 in the first region are not limited. Preferably, the cross-sectional shape of the lower electrode interconnect via 141 in the first region is an inverted trapezoid, wherein the width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid. The width of the lower base of the inverted trapezoid is greater than The angle between the legs and the lower base of the inverted trapezoid is greater than 105 degrees.

[0229] In one embodiment of this application, the non-volatile end-to-end storage cell further includes a second functional layer 342. The second functional layer 342 is formed in the second lower electrode interconnect via 142. The upper surface of the second functional layer 342 is lower than the upper surface of the first dielectric layer 130. The second functional layer 342 is electrically connected to the second lower electrode metal connection layer 112, and the second upper electrode metal connection layer 192 is electrically connected to the second functional layer 342.

[0230] In one embodiment of this application, the non-volatile dual-ended storage cell further includes a first region second lower electrode metal layer 15111, the upper surface of the first region second lower electrode metal layer 15111 is flush with the upper surface of the first dielectric layer 130, the first region second lower electrode metal layer 15111 is electrically connected to the first region lower electrode metal connection layer 111, and the first region upper electrode metal connection layer 191 is electrically connected to the first region second lower electrode metal layer 15111.

[0231] In one embodiment of this application, the memory cell stack layer 350 includes a second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154 stacked sequentially. The non-volatile two-terminal memory cell may also include a sidewall 159, which can wrap the memory cell stack layer 350 from the side.

[0232] In one embodiment of this application, the bottom of the upper electrode metal connection layer 192 of the second region is in contact with the upper surface of the functional layer 342 of the second region, and the bottom of the functional layer 342 of the second region is in contact with the upper surface of the lower electrode metal connection layer 112 of the second region, so that the lower electrode metal connection layer 112 of the second region and the upper electrode metal connection layer 192 of the second region are indirectly connected through the functional layer 342 of the second region.

[0233] In one embodiment of this application, the second functional layer 342 may not exist in the second lower electrode interconnect via 142, and the second lower electrode metal connection layer 112 is directly connected to the second upper electrode metal connection layer 192, that is, the bottom of the second lower electrode metal connection layer 112 is in contact with the upper surface of the second upper electrode metal connection layer 192.

[0234] The aforementioned non-volatile two-ended memory cell saves on patterned photomask layers, and the manufacturing method facilitates the formation and alignment of the lower electrode interconnect vias and upper electrode interconnect vias of the non-volatile two-ended memory cell. Therefore, it can shorten the fabrication process of the non-volatile two-ended memory cell, reduce the fabrication difficulty, and thus reduce the fabrication cost.

[0235] In one embodiment of this application, a memory is also provided, which includes one or more non-volatile dual-ended memory cells as described in the embodiments of this application. This memory employs the aforementioned non-volatile dual-ended memory cells, thereby improving the yield rate of the memory and reducing its manufacturing cost.

[0236] In one embodiment of this application, an electronic device is also provided, which includes the memory described in the embodiments of this application. This electronic device uses the aforementioned memory, thus reducing the possibility of quality problems with the memory in the electronic device and lowering the hardware cost of the electronic device.

[0237] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for fabricating a non-volatile two-terminal storage cell, characterized in that, The preparation method includes: A first dielectric layer (130) is stacked on the upper surface of the first region lower electrode metal connection layer (111) located in the first region and on the upper surface of the second region lower electrode metal connection layer (112) located in the second region. Based on the first patterned photomask layer (391), a first region lower electrode interconnect via (141) that contacts the upper surface of the first region lower electrode metal connection layer (111) and a second region lower electrode interconnect via (142) that contacts the upper surface of the second region lower electrode metal connection layer (112) are formed in the first dielectric layer (130). A first stacked layer (250A) is formed to fill the first region lower electrode interconnect via (141), and the first region first stacked layer (250A) is electrically connected to the first region lower electrode metal connection layer (111); or a memory cell stacked layer (350) is formed above the first region lower electrode interconnect via (141), and the memory cell stacked layer (350) is in contact with the upper surface of the first region lower electrode interconnect via (141); A second dielectric layer (170) is formed in the first region and the second region; Based on the first patterned photomask layer (391), a first region upper electrode interconnect via (181) and a second region upper electrode interconnect via (182) are formed in the second dielectric layer (170); A first upper electrode metal connection layer (191) is formed in the first upper electrode interconnect via (181), and a second upper electrode metal connection layer (192) is formed in the second upper electrode interconnect via (182). The first upper electrode metal connection layer (191) is electrically connected to the first stacked layer (250A) of the first region or the lower electrode metal connection layer (111) of the first region, and the second upper electrode metal connection layer (192) is electrically connected to the lower electrode metal connection layer (112) of the second region.

2. The preparation method according to claim 1, characterized in that, A second upper electrode metal connection layer (192) is formed in the second upper electrode interconnect via (182), and the second upper electrode metal connection layer (192) is electrically connected to the second lower electrode metal connection layer (112), including: After forming the second region lower electrode interconnect via (142), a second region functional layer (342) is formed that partially fills the second region lower electrode interconnect via (142), and the second region functional layer (342) is electrically connected to the second region lower electrode metal connection layer (112). After forming the second region upper electrode interconnect via (182), a second region upper electrode metal connection layer (192) is formed in the second region upper electrode interconnect via (182), and the second region upper electrode metal connection layer (192) is electrically connected to the second region functional layer (342).

3. The preparation method according to claim 2, characterized in that, The upper surface of the second functional layer (342) is lower than the upper surface of the first dielectric layer (130).

4. The preparation method according to claim 3, characterized in that, A second functional layer (342) is formed that partially fills the second region lower electrode interconnect via (142), and the upper surface of the second functional layer (342) is lower than the upper surface of the first dielectric layer (130), including: After forming the second region lower electrode interconnect via (142), a second region first stacked layer (250B) filling the second region lower electrode interconnect via (142) is formed, or before forming the memory cell stacked layer (350), a second region second lower electrode metal layer (15112) filling the second region lower electrode interconnect via (142) is formed, and the upper surface of the second region first stacked layer (250B) or the second region second lower electrode metal layer (15112) is flush with the upper surface of the first dielectric layer (130); In the second region, a portion of the second region first stacked layer (250B) is removed from the second region lower electrode interconnect via (142), or in the process of forming the memory cell stacked layer (350), a second region second lower electrode metal layer (15112) in the second region lower electrode interconnect via (142) is partially removed to form the second region functional layer (342).

5. The preparation method according to claim 4, characterized in that, The second region first stacked layer (250B) includes a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) stacked sequentially; Specifically, a portion of the first stacked layer (250B) of the second region is removed from the lower electrode interconnect via (142) of the second region to form a functional layer (342) of the second region, including: At least the first switching layer (252) and the first upper electrode metal layer (253) in the first stacked layer (250B) of the second region are removed.

6. The preparation method according to claim 4, characterized in that, Forming a second dielectric layer (170) in the second region includes: After forming the second region functional layer (342) in the second region lower electrode interconnect via (142), the second dielectric layer (170) is formed in the second region, the second dielectric layer (170) covering the upper surface of the second region functional layer (342) and at least filling the remaining space of the second region lower electrode interconnect via (142).

7. The preparation method according to claim 4, characterized in that, The bottom of the upper electrode metal connection layer (191) of the first region is in contact with the first stacked layer (250A) of the first region.

8. The preparation method according to claim 7, characterized in that, A method for forming a first stacked layer (250A) in the first region filling the lower electrode interconnect via (141) in the first region and a first stacked layer (250B) in the second region filling the lower electrode interconnect via (142) in the second region, comprising: After forming the first region lower electrode interconnect via (141) and the second region lower electrode interconnect via (142), a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) are sequentially stacked at least in the region of the first region lower electrode interconnect via (141) and the region of the second region lower electrode interconnect via (142). Remove the first lower electrode metal layer (251), the first switching layer (252), and the first upper electrode metal layer (253) outside the regions of the first lower electrode interconnect via (141) and the second lower electrode interconnect via (142). Form a first stacked layer (250A) in the first region lower electrode interconnect via (141) and a first stacked layer (250B) in the second region lower electrode interconnect via (142). The upper surfaces of the first stacked layer (250A) and the second stacked layer (250B) are flush with the upper surface of the first dielectric layer (130).

9. The preparation method according to claim 8, characterized in that, The first lower electrode metal layer (251), the first switching layer (252), and the first upper electrode metal layer (253), excluding the regions outside the first region lower electrode interconnect via (141) and the second region lower electrode interconnect via (142), include: Remove the first lower electrode metal layer (251), the first switching layer (252), the first upper electrode metal layer (253), and the first dielectric layer (130) above the stop line 50, wherein the height of the stop line (50) is not higher than the upper surface of the first dielectric layer (130).

10. The preparation method according to claim 8, characterized in that, During the removal of the first lower electrode metal layer (251), the first switching layer (252), and the first upper electrode metal layer (253) outside the region of the first lower electrode interconnect via (141) and the region of the second lower electrode interconnect via (142), an etching process or a CMP process is used.

11. The production method according to claim 1 or 4, characterized by, A first region upper electrode metal connection layer (191) is formed in the first region upper electrode interconnect via (181), and the first region upper electrode metal connection layer (191) is electrically connected to the first region lower electrode metal connection layer (111), including: After forming the first region lower electrode interconnect via (141), a first region second lower electrode metal layer (15111) is formed to fill the first region lower electrode interconnect via (141). The upper surface of the first region second lower electrode metal layer (15111) is flush with the upper surface of the first dielectric layer (130). The first region second lower electrode metal layer (15111) is electrically connected to the first region lower electrode metal connection layer (111). After forming the first region upper electrode interconnect via (181), a first region upper electrode metal connection layer (191) is formed in the first region upper electrode interconnect via (181). The first region upper electrode metal connection layer (191) is in contact with the memory cell stack layer (350), and the first region upper electrode metal connection layer (191) is electrically connected to the first region second lower electrode metal layer (15111).

12. The preparation method according to claim 11, characterized in that, A method for forming a first region second lower electrode metal layer (15111) filling the first region lower electrode interconnect via (141) and a second region second lower electrode metal layer (15112) filling the second region lower electrode interconnect via (142), comprising: After forming the first region lower electrode interconnect via (141) and the second region lower electrode interconnect via (142), a second lower electrode metal layer (1511) is formed at least in the region of the first region lower electrode interconnect via (141) and the region of the second region lower electrode interconnect via (142); Remove the second lower electrode metal layer (1511) outside the region of the first lower electrode interconnect via (141) and the region of the second lower electrode interconnect via (142), so that the remaining portion in the first lower electrode interconnect via (141) forms the first region second lower electrode metal layer (15111), and the remaining portion in the second lower electrode interconnect via (142) forms the second region second lower electrode metal layer (15112). The upper surface of the first region second lower electrode metal layer (15111) and the upper surface of the second region second lower electrode metal layer (15112) are flush with the upper surface of the first dielectric layer (130).

13. The preparation method according to claim 12, characterized in that, During the removal of the second lower electrode metal layer (1511) outside the region of the first lower electrode interconnect via (141) and outside the region of the second lower electrode interconnect via (142), an etching process or a CMP process is used.

14. The preparation method according to claim 11, characterized in that, The first region's second lower electrode metal layer (15111) and the second region's functional layer (342) are made of the same material.

15. The preparation method according to claim 11, characterized in that, The thickness of the first region's second lower electrode metal layer (15111) is not less than the thickness of the second region's functional layer (342).

16. The preparation method according to claim 2, characterized in that, The first stacked layer (250A) of the first region includes a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) stacked in sequence, and the memory cell stacked layer (350) includes a second lower electrode metal layer (1512), a second switching layer (152), a second upper electrode metal layer (153) and an upper electrode hard mask layer (154) stacked in sequence.

17. The preparation method according to claim 16, characterized in that, The bottom of the first region upper electrode metal connection layer (191) is in contact with the upper surface of the first upper electrode metal layer (253), or the bottom of the first region upper electrode metal connection layer (191) penetrates the upper electrode hard mask layer (154) and is in contact with the upper surface of the second upper electrode metal layer (153).

18. The method of claim 16, wherein, The first lower electrode metal layer (251) and the second functional layer (342) are made of the same material.

19. The method of claim 16, wherein, The thickness of the first lower electrode metal layer (251) is not less than the thickness of the second functional layer (342).

20. The preparation method according to claim 1, characterized in that, The bottom of the first stacked layer (250A) in the first region is in contact with the upper surface of the lower electrode metal connection layer (111) in the first region.

21. The preparation method according to claim 2, characterized in that, The bottom of the second functional layer (342) is in contact with the upper surface of the second lower electrode metal connection layer (112), and the bottom of the second upper electrode metal connection layer (192) is in contact with the upper surface of the second functional layer (342).

22. The preparation method according to claim 1, characterized in that, The first region includes a memory cell array region (80), and the second region includes a peripheral circuit region (90).

23. The preparation method according to claim 1, characterized in that, The cross-sectional shape of the lower electrode interconnect via (141) in the first region is an inverted trapezoid.

24. The preparation method according to claim 23, characterized in that, The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than... The width of the lower base of the inverted trapezoid is greater than 25. The preparation method according to claim 23, characterized in that, The angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

26. A non-volatile two-terminal storage unit, characterized in that, The non-volatile two-end storage unit includes: A first dielectric layer (130) is stacked on the upper surface of the first region lower electrode metal connection layer (111) of the first region and the upper surface of the second region lower electrode metal connection layer (112) of the second region. The first region lower electrode interconnect via (141) and the second region lower electrode interconnect via (142) are formed in the first dielectric layer (130) based on the first patterned photomask layer (391); The first stacked layer (250A) of the first region fills the first region lower electrode interconnect via (141) and is electrically connected to the first region lower electrode metal connection layer (111); or the memory cell stacked layer (350) contacts the upper surface of the first region lower electrode interconnect via (141). A second dielectric layer (170) is formed in the first region and the second region; The first region upper electrode interconnect via (181) and the second region upper electrode interconnect via (182) are formed in the second dielectric layer (170) based on the first patterned photomask layer (391); The first region upper electrode metal connection layer (191) is formed in the first region upper electrode interconnect via (181) and is electrically connected to the first region first stack layer (250A) or the first region lower electrode metal connection layer (111). The second region upper electrode metal connection layer (192) is formed in the second region upper electrode interconnect via (182) and is electrically connected to the second region lower electrode metal connection layer (112).

27. The non-volatile two-terminal storage cell according to claim 26, characterized in that, The non-volatile two-ended storage unit also includes: The second functional layer (342) partially fills the second lower electrode interconnect via (142) and is electrically connected to the second lower electrode metal connection layer (112) and the second upper electrode metal connection layer (192).

28. The non-volatile two-terminal storage cell according to claim 27, characterized in that, The first stacked layer (250A) of the first region includes a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) stacked in sequence, and the memory cell stacked layer (350) includes a second lower electrode metal layer (1512), a second switching layer (152), a second upper electrode metal layer (153) and an upper electrode hard mask layer (154) stacked in sequence.

29. The non-volatile two-terminal storage unit according to claim 28, characterized in that, The first lower electrode metal layer (251) and the second functional layer (342) are made of the same material.

30. The non-volatile two-ended storage cell according to claim 28, characterized in that, The thickness of the first lower electrode metal layer (251) is not less than the thickness of the second functional layer (342).

31. The non-volatile two-terminal storage unit according to claim 26, characterized in that, The bottom of the first stacked layer (250A) in the first region is in contact with the upper surface of the lower electrode metal connection layer (111) in the first region, and the bottom of the upper electrode metal connection layer (191) in the first region is in contact with the upper surface of the first stacked layer (250A) in the first region.

32. The non-volatile two-terminal storage unit according to claim 27, characterized in that, The bottom of the second functional layer (342) is in contact with the upper surface of the second lower electrode metal connection layer (112), and the bottom of the second upper electrode metal connection layer (192) is in contact with the upper surface of the second functional layer (342).

33. The non-volatile two-ended storage cell according to claim 28, characterized in that, The bottom of the first lower electrode metal layer (251) is in contact with the upper surface of the first region lower electrode metal connection layer (111), and the bottom of the first region upper electrode metal connection layer (191) is in contact with the upper surface of the first upper electrode metal layer (253).

34. The non-volatile two-ended storage cell according to claim 26, characterized in that, The non-volatile two-ended storage unit also includes: The first region has a second lower electrode metal layer (15111), the upper surface of which is flush with the upper surface of the first dielectric layer (130), the first region has a second lower electrode metal layer (15111) electrically connected to the first region lower electrode metal connecting layer (111), and the first region upper electrode metal connecting layer (191) electrically connected to the first region's second lower electrode metal layer (15111).

35. The non-volatile two-terminal storage cell according to claim 26, characterized in that, The bottom of the upper electrode metal connection layer (192) of the second region is in contact with the upper surface of the lower electrode metal connection layer (112) of the second region.

36. A memory, characterized in that, The memory includes one or more non-volatile two-ended memory cells according to any one of claims 26-35.

37. An electronic device, characterized in that, The electronic device includes the memory as described in claim 36.

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