Device structure and manufacturing method for an n-type silicon PERT bifacial solar cell

Abstract

The present invention relates to the technical field of solar cells, and more particularly to a device structure and manufacturing method for an N-type silicon PERT bifacial solar cell. The device structure comprises a front electrode, a front-side anti-reflection layer, a passivation layer, a p+ emitter, an N-type monocrystalline silicon wafer, an n+ back surface field, a rear-side anti-reflection layer, and a rear electrode. The n+ back surface field is a composite thin-film structure consisting of an amorphous silicon layer, a microcrystalline silicon layer, and a polycrystalline silicon layer. The design replaces the conventional thermally diffused back field with doped microcrystalline and polycrystalline silicon thin films, effectively avoiding bulk defects in the silicon wafer such as dislocations and lattice distortion caused by phosphorus impurities. This structure forms a graded back surface field and a refractive-index-graded optical composite film, thereby achieving dual optimization of electrical and optical performance. As a result, the open-circuit voltage and short-circuit current are improved, which leads to an increase in the overall conversion efficiency of the solar cell.

Description

Device Structure and Manufacturing Method for an N-Type Silicon PERT Bifacial Solar CellDescription

[0001] The present invention relates to the technical field of solar cells, and more particularly to a device structure and manufacturing method for an N-type silicon PERT bifacial solar cell.

[0002] In recent years, with the increasing demand in the photovoltaic industry for high-efficiency and low-cost solar cells, N-type bifacial PERT (Passivated Emitter and Rear Totally-diffused) solar cells have attracted considerable attention due to their low light-induced degradation characteristics. FIG. 1 illustrates a schematic diagram of the conventional PERT cell structure.

[0003] In FIG. 1, the device structure of a conventional PERT cell includes:an Ag front electrode 11, a front-side Si₃N₄ anti-reflection layer 12, an Al₂O₃ passivation layer 13, a p+ emitter 14, an N-type silicon wafer 15, an n+ back surface field 16, a rear-side Si₃N₄ anti-reflection layer 17, and an Ag rear electrode 18.

[0004] However, traditional PERT cells face a dual dilemma in large-scale mass production. Firstly, the conversion efficiency in mass production has stagnated at around 24%, reaching the performance limit of the existing structure, offering only a marginal improvement of about 0.5 percentage points over PERC (Passivated Emitter and Rear Cell) technology. Secondly, the non-silicon cost exceeds 0.20 RMB / W, which is more than 30% higher than that of PERC cells, resulting in significant economic disadvantages. Due to the limited open-circuit voltage and cell efficiency, coupled with its cost disadvantage, PERT cells have become marginalized in the mainstream photovoltaic market.

[0005] Therefore, there is a need for an improved device structure and corresponding manufacturing method for PERT solar cells that can achieve higher efficiency and lower cost.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a schematic structural diagram of a conventional N-type silicon PERT bifacial solar cell.

[0007] FIG. 2 is a schematic structural diagram of the N-type silicon PERT bifacial solar cell provided by the present invention.

[0008] FIG. 3 is a flowchart illustrating the manufacturing process of the N-type silicon PERT bifacial solar cell according to the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0009] The technical solutions of the embodiments of the present invention will now be clearly and completely described in conjunction with the accompanying drawings. It should be understood that the described embodiments are merely a portion of all possible embodiments of the invention and are not intended to limit the scope thereof. Based on the embodiments of the present invention, all other embodiments that can be derived by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0010] The present invention provides a technical solution: a device structure of an N-type silicon PERT bifacial solar cell, comprising a front electrode 1, a front-side anti-reflection layer 2, a passivation layer 3, a p+ emitter 4, an N-type monocrystalline silicon wafer 5, an n+ back surface field 6, a rear-side anti-reflection layer 7, and a rear electrode 8. The n+ back surface field 6 is a composite thin-film layer consisting of amorphous silicon, microcrystalline silicon, and polycrystalline silicon, specifically comprising an amorphous silicon layer 61, a microcrystalline silicon layer 62, and a polycrystalline silicon layer 63.

[0011] The front electrode 1 is an Ag front electrode or an Ag / Al front electrode; the front-side anti-reflection layer 2 is a Si₃N₄ anti-reflection layer; the passivation layer 3 is an Al₂O₃ passivation layer; the rear-side anti-reflection layer 7 is a Si₃N₄ anti-reflection layer; and the rear electrode 8 is an Ag rear electrode.

[0012] The present invention also provides a technical solution: a method for manufacturing an N-type silicon PERT bifacial solar cell, comprising the following steps:

[0013] Step 1: Texturing

[0014] Form pyramid structures on both the front and rear surfaces to reduce light reflectance and enhance light trapping capability, thereby improving photoelectric conversion efficiency.

[0015] Step 2: Boron Diffusion

[0016] Form a p+ emitter 4 (inversion layer) on the front side through boron diffusion to establish a PN junction with the N-type monocrystalline silicon wafer 5, enabling the separation of photogenerated charge carriers. On the rear side, a doped silicon thin-film composite layer is used to form the back surface field, utilizing the built-in electric field to suppress minority carrier (hole) recombination at the rear surface.

[0017] Step 3: Cleaning and Alkaline Polishing

[0018] Remove surface impurities via cleaning, eliminate excess edge doping, and polish the rear surface using alkaline etching to improve the passivation effect.

[0019] Step 4: PECVD Growth of Composite n+ Back Surface Field Layer 6

[0020] Using plasma-enhanced chemical vapor deposition (PECVD), sequentially deposit an intrinsic hydrogenated amorphous silicon layer, a lightly doped microcrystalline silicon layer, and a heavily doped polycrystalline silicon layer to form the n+ back surface field 6.

[0021] Specifically, by adjusting process parameters, deposit:

[0022] a 2–5 nm intrinsic hydrogenated amorphous silicon layer 61,

[0023] a 5–15 nm lightly doped microcrystalline silicon layer 62 with an impurity concentration of 1–5×1019 / cm³,

[0024] and a 15–50 nm heavily doped polycrystalline silicon layer 63 with an impurity concentration of 1–5×1020 / cm³.

[0025] This forms a graded amorphous–microcrystalline–polycrystalline silicon thin-film stack, establishing a composite back surface field structure with both graded crystallinity and graded doping concentration. On one hand, the variation in doping concentration enhances the back surface field effect; on the other hand, the refractive index gradient reduces optical loss on the rear side. The resulting structure is a graded back surface field and optical composite thin film with refractive index grading, achieving simultaneous optimization of electrical and optical performance.

[0026] The specific PECVD process parameters are shown in Table 1.

[0027]

[0028] Step 5: ALD Deposition of Front-Side Passivation Layer

[0029] Deposit the passivation layer 3 on the front surface using atomic layer deposition ALD. The passivation layer is an Al₂O₃ layer.

[0030] Step 6: PECVD Deposition of Front-Side Anti-Reflection Layer

[0031] Deposit the front-side anti-reflection layer 2 using plasma-enhanced chemical vapor deposition PECVD. The anti-reflection layer is composed of Si₃N₄.

[0032] Step 7: PECVD Deposition of Rear-Side Anti-Reflection Layer

[0033] Deposit the rear-side anti-reflection layer 7, also composed of Si₃N₄, using PECVD.

[0034] Step 8: Screen Printing and Sintering:

[0035] Print silver paste on both the front and rear sides of the cell to form the front electrode 1 (Ag or Ag / Al electrode) and the rear electrode 8 (Ag electrode).

[0036] High-temperature sintering at 750–950 °C enables the front silver or silver-aluminum paste to form ohmic contact with the front surface of the silicon wafer, and the rear silver paste to form ohmic contact with the silicon thin-film composite layer, while removing organic binders.

[0037] Step 9: Laser Scanning Treatment of Front and Rear Electrodes

[0038] Laser scanning is applied to both the front electrode 1 and the rear electrode 8 to improve the metal–semiconductor contact between silver and silicon. During laser irradiation, a reverse bias voltage of more than 20 V is applied across the front and rear electrodes of the cell to enhance carrier mobility and promote the diffusion of silver ions into the silicon wafer or silicon thin film, thereby improving the contact between silver and silicon and further optimizing contact quality. This process reduces series resistance and increases the fill factor.

[0039] The rear electrode 8 forms an ohmic contact directly with the microcrystalline or polycrystalline silicon layer, avoiding direct contact with the N-type monocrystalline silicon wafer 5 bulk. This configuration minimizes the accumulation of locally high carrier concentrations, thereby significantly reducing Auger recombination and other non-radiative recombination processes, leading to an increase in open-circuit voltage and overall cell conversion efficiency.

[0040] The laser scanning is performed using a nanosecond or picosecond laser source with a wavelength of 500–1400 nm, laser power of 8–24 W, energy density of 0.5–2.5 J / cm², pulse frequency of 50–200 kHz, scanning speed of 5–20 m / s, and a spot diameter of 20–50 μm. The applied reverse bias voltage during scanning is 12–16 V.

[0041] Step 10: Testing, Sorting, and Packaging

[0042] The finished solar cells undergo testing, sorting, and packaging. Testing includes electrical performance testing and optical inspection. Electrical testing comprises IV (current–voltage) characteristic testing and EL (electroluminescence) inspection. Optical inspection includes appearance checking and reflectance / transmittance measurement. Cells are then sorted and graded before final packaging.

[0043] The conventional fabrication process for N-type PERT bifacial solar cells involves twelve steps, including:

[0044] S1: Wafer cleaning and double-sided texturing;

[0045] S2: Boron diffusion (formation of P+ emitter);

[0046] S3: Boron silicate glass (BSG) removal;

[0047] S4: Phosphorus diffusion (formation of N+ back surface field);

[0048] S5: Phosphosilicate glass (PSG) removal;

[0049] S6: Edge isolation etching;

[0050] S7: Front-side passivation and anti-reflection layer deposition;

[0051] S8: Rear-side passivation and structure optimization;

[0052] S9: Rear-side laser contact opening;

[0053] S10: Double-sided electrode printing and metallization;

[0054] S11: High-temperature sintering;

[0055] S12: Performance testing, sorting, and packaging.

[0056] In contrast, the novel N-type PERT bifacial solar cell provided by the present invention requires only ten fabrication steps, reducing two steps compared to the traditional process. This simplification contributes to a significant reduction in non-silicon cost.

[0057] Example 1:

[0058] Step 1: Texturing.

[0059] Step 2: Boron diffusion.

[0060] Step 3: Cleaning and alkaline polishing.

[0061] Step 4: PECVD deposition of a 5 nm amorphous silicon layer 61;

[0062] PECVD deposition of a 15 nm microcrystalline silicon layer 62 with a doping concentration of 1×1019 cm-3;

[0063] PECVD deposition of a 50 nm polycrystalline silicon layer 63 with a doping concentration of 5×1020 cm-3.

[0064] The PECVD process parameters used in Example 1 are shown in Table 2.

[0065] Step 5: ALD Deposition of Front-Side Passivation Layer

[0066] Deposit the passivation layer 3 on the front surface using atomic layer deposition ALD. The passivation layer is an Al₂O₃ layer.

[0067] Step 6: PECVD Deposition of Front-Side Anti-Reflection Layer

[0068] Deposit the front-side anti-reflection layer 2 using plasma-enhanced chemical vapor deposition PECVD. The anti-reflection layer is composed of Si₃N₄.

[0069] Step 7: PECVD Deposition of Rear-Side Anti-Reflection Layer

[0070] Deposit the rear-side anti-reflection layer 7, also composed of Si₃N₄, using PECVD.

[0071] Step 8: Screen Printing and Sintering:

[0072] Print silver paste on both the front and rear sides of the cell to form the front electrode 1 (Ag or Ag / Al electrode) and the rear electrode 8 (Ag electrode).

[0073] High-temperature sintering at 750–950 °C enables the front silver or silver-aluminum paste to form ohmic contact with the front surface of the silicon wafer, and the rear silver paste to form ohmic contact with the silicon thin-film composite layer, while removing organic binders.

[0074] Step 9: Laser Scanning Treatment of Front and Rear Electrodes

[0075] Laser scanning is applied to both the front electrode 1 and the rear electrode 8 to improve the metal–semiconductor contact between silver and silicon. During laser irradiation, a reverse bias voltage of more than 20 V is applied across the front and rear electrodes of the cell to enhance carrier mobility and promote the diffusion of silver ions into the silicon wafer or silicon thin film, thereby improving the contact between silver and silicon and further optimizing contact quality. This process reduces series resistance and increases the fill factor.

[0076] The rear electrode 8 forms an ohmic contact directly with the microcrystalline or polycrystalline silicon layer, avoiding direct contact with the N-type monocrystalline silicon wafer 5 bulk. This configuration minimizes the accumulation of locally high carrier concentrations, thereby significantly reducing Auger recombination and other non-radiative recombination processes, leading to an increase in open-circuit voltage and overall cell conversion efficiency.

[0077] The laser scanning is performed using a nanosecond or picosecond laser source with a wavelength of 500–1400 nm, laser power of 8–24 W, energy density of 0.5–2.5 J / cm², pulse frequency of 50–200 kHz, scanning speed of 5–20 m / s, and a spot diameter of 20–50 μm. The applied reverse bias voltage during scanning is 12–16 V.

[0078] Step 10: Testing, Sorting, and Packaging

[0079] The finished solar cells undergo testing, sorting, and packaging. Testing includes electrical performance testing and optical inspection. Electrical testing comprises IV (current–voltage) characteristic testing and EL (electroluminescence) inspection. Optical inspection includes appearance checking and reflectance / transmittance measurement. Cells are then sorted and graded before final packaging.

[0080] The conventional manufacturing process for N-type silicon PERT bifacial solar cells involves twelve steps, including:

[0081] S1: Wafer cleaning and double-sided texturing;

[0082] S2: Boron diffusion (formation of P+ emitter);

[0083] S3: Boron silicate glass (BSG) removal;

[0084] S4: Phosphorus diffusion (formation of N+ back surface field);

[0085] S5: Phosphosilicate glass (PSG) removal;

[0086] S6: Edge isolation etching;

[0087] S7: Front-side passivation and anti-reflection layer deposition;

[0088] S8: Rear-side passivation and structure optimization;

[0089] S9: Rear-side laser contact opening;

[0090] S10: Double-sided electrode printing and metallization;

[0091] S11: High-temperature sintering;

[0092] S12: Performance testing, sorting, and packaging.

[0093] In contrast, the novel N-type silicon PERT bifacial solar cell provided by the present invention requires only ten manufacturing steps, reducing two steps compared to the traditional process. This simplification contributes to a significant reduction in non-silicon cost.

[0094] Example 1:

[0095] Step 1: Texturing.

[0096] Step 2: Boron diffusion.

[0097] Step 3: Cleaning and alkaline polishing.

[0098] Step 4: PECVD deposition of a 5 nm amorphous silicon layer 61;

[0099] PECVD deposition of a 15 nm microcrystalline silicon layer 62 with a doping concentration of 1×1019 cm-3;

[0100] PECVD deposition of a 50 nm polycrystalline silicon layer 63 with a doping concentration of 5×1020 cm-3.

[0101] The PECVD process parameters used in Example 1 are shown in Table 2.

[0102]

[0103] Step 5: ALD deposition of the front-side passivation layer.

[0104] Step 6: PECVD deposition of the front-side anti-reflection layer.

[0105] Step 7: PECVD deposition of the rear-side anti-reflection layer.

[0106] Step 8: Screen printing and sintering.

[0107] Step 9: Laser scanning treatment of front and rear electrodes.

[0108] The specific laser scanning parameters are as follows:

[0109] Wavelength: 1064 nm,

[0110] Laser power: 20 W,

[0111] Energy density: 2.3 J / cm²,

[0112] Pulse frequency: 100 kHz,

[0113] Scanning speed: 15 m / s,

[0114] Spot diameter: 40 μm,

[0115] Reverse bias voltage: 14 V.

[0116] Step 10: Performance testing, sorting, and packaging.

[0117] The N-type silicon PERT bifacial solar cell manufactured through the above process exhibits the following performance parameters:

[0118] Open-circuit voltage (Voc): 718 mV

[0119] Short-circuit current density (Jsc): 41.2 mA / cm²

[0120] Fill factor (FF): 82.5%

[0121] Conversion efficiency (η): 24.4%

[0122] Example 1 adopts a high deposition rate process, which is suitable for mass production. Although the performance is slightly lower, the cost remains controllable.

[0123] Example 2:

[0124] Example 2 differs from Example 1 in that the thicknesses of the individual layers deposited via PECVD in Step 4, as well as the PECVD process parameters, are different.

[0125] Specifically, in Step 4, the following layers are deposited using PECVD:

[0126] A 3 nm amorphous silicon layer 61;

[0127] A 12 nm microcrystalline silicon layer 62 with a doping concentration of 3×1019 cm-3;

[0128] A 40 nm polycrystalline silicon layer 63 with a doping concentration of 2×1020 cm-3.

[0129] The PECVD process parameters used in Example 2 are shown in Table 3.

[0130]

[0131] The N-type silicon PERT bifacial solar cell manufactured through the above process exhibits the following performance parameters:

[0132] Open-circuit voltage (Voc): 722 mV

[0133] Short-circuit current density (Jsc): 41.7 mA / cm²

[0134] Fill factor (FF): 84.1%

[0135] Conversion efficiency (η): 25.3%

[0136] Example 2 adopts a balanced parameter design, making it suitable for stable and high-efficiency production lines.

[0137] Example 3:

[0138] Example 3 differs from Example 1 in that the thicknesses of the individual layers deposited via PECVD in Step 4, as well as the PECVD process parameters, are different.

[0139] Specifically, in Step 4, the following layers are deposited using PECVD:

[0140] A 2 nm amorphous silicon layer 61;

[0141] An 8 nm microcrystalline silicon layer 62 with a doping concentration of 5×1019 cm-3;

[0142] A 30 nm polycrystalline silicon layer 63 with a doping concentration of 4×1020 cm-3.

[0143] The PECVD process parameters used in Example 3 are shown in Table 4.

[0144]

[0145] The N-type silicon PERT bifacial solar cell manufactured through the above process exhibits the following performance parameters:

[0146] Open-circuit voltage (Voc): 728 mV

[0147] Short-circuit current density (Jsc): 42.0 mA / cm²

[0148] Fill factor (FF): 83.6%

[0149] Conversion efficiency (η): 25.6%

[0150] Example 3 employs high hydrogen dilution to enhance the crystallinity of the deposited films, enabling near-limit efficiency performance under laboratory conditions.

[0151] All three examples (Examples 1–3) were subjected to performance testing using a solar cell I–V tester, from which the above performance parameters were obtained.

[0152] Comparative Example:

[0153] The comparative example adopts the n-PERT bifacial solar cell jointly developed by IMEC and Jolywood, with the following publicly disclosed electrical performance parameters:

[0154] Open-circuit voltage (Voc): 690 mV

[0155] Short-circuit current density (Jsc): 40.5 mA / cm²

[0156] Fill factor (FF): 83%

[0157] Conversion efficiency (η): 23.2%

[0158] The Table 5 below compares the performance parameters of various N-type PERT cells.

[0159]

[0160] Compared to the comparative example, Example 1 shows an increase of 28 mV in open-circuit voltage, an increase of 0.7 mA / cm² in short-circuit current density, a decrease of 0.5% in fill factor, and an improvement of 1.2% in solar cell conversion efficiency η.

[0161] Compared to the comparative example, Example 2 shows an increase of 32 mV in open-circuit voltage, an increase of 1.2 mA / cm² in short-circuit current density, an increase of 1.1% in fill factor, and an improvement of 2.1% in solar cell conversion efficiency η.

[0162] Compared to the comparative example, Example 3 shows an increase of 38 mV in open-circuit voltage, an increase of 1.5 mA / cm² in short-circuit current density, an increase of 0.6% in fill factor, and an improvement of 2.4% in solar cell conversion efficiency η.

[0163] In summary, the N-type silicon PERT bifacial solar cell manufactured using the method provided by the present invention represents an upgraded version of conventional N-PERT cells. It achieves dual optimization of both electrical and optical performance. The resulting device exhibits an open-circuit voltage (Voc) of ≥718 mV, a short-circuit current density (Jsc) of ≥41.2 mA / cm², a fill factor (FF) of ≥82.5%, and a conversion efficiency η of ≥24.4%. This reflects an improvement of at least 1.2% in efficiency compared to conventional cells, along with increased Voc and FF. Furthermore, the non-silicon cost is reduced by at least 0.04 RMB / W, ultimately lowering the levelized cost of electricity  for photovoltaic power systems.

[0164] It is apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, the embodiments disclosed herein are to be considered illustrative and not restrictive. The scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications and equivalents that fall within the meaning and scope of the claims are intended to be embraced within the invention.Any reference signs in the claims shall not be construed as limiting the scope of the claims.

[0165] Although embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the invention. The scope of the invention is defined by the appended claims and their equivalents.

[0166] The objective of the present invention is to provide a device structure and manufacturing method for an N-type silicon PERT bifacial solar cell, so as to address the problems mentioned in the background section.

[0167] To achieve the above objective, the present invention provides the following technical solution:

[0168] An N-type silicon PERT bifacial solar cell device structure, comprising:

[0169] a front electrode, a front-side anti-reflection layer, a passivation layer, a p+ emitter, an N-type monocrystalline silicon wafer, an n+ back surface field, a rear-side anti-reflection layer, and a rear electrode;

[0170] wherein the n+ back surface field is an amorphous–microcrystalline–polycrystalline silicon composite thin-film stack, consisting of an amorphous silicon layer, a microcrystalline silicon layer, and a polycrystalline silicon layer.

[0171] The present invention also provides a method for manufacturing the N-type silicon PERT bifacial solar cell described above, comprising the following steps:

[0172] S1: Texturing, wherein both the front and rear surfaces of the wafer are textured with a pyramidal structure;

[0173] S2: Performing boron diffusion;

[0174] S3: Cleaning and alkaline polishing;

[0175] S4: Sequential deposition of an intrinsic amorphous silicon film, a microcrystalline silicon film, and a polycrystalline silicon film using PECVD to form the n+ back surface field;

[0176] S5: depositing a front-side passivation layer (3) using atomic layer deposition (ALD);

[0177] S6: depositing a front-side film using PECVD;

[0178] S7: depositing a rear-side film using PECVD;

[0179] S8: Screen printing and sintering of front and rear electrodes;

[0180] S9: Laser scanning treatment of the front and rear electrodes.

[0181] Preferably, in Step 2, a p+ emitter is formed on the front surface by boron diffusion to constitute a PN junction with the N-type monocrystalline silicon wafer,and a back surface field is formed on the rear side via a doped silicon thin-film composite layer..

[0182] Preferably, in Step 4, a PECVD process is employed to sequentially deposit a 2–5 nm amorphous silicon layer, a 5–15 nm microcrystalline silicon layer, and a 15–50 nm polycrystalline silicon layer, thereby forming a graded amorphous–microcrystalline–polycrystalline silicon thin-film stack. This structure builds a composite back surface field with a gradient in both crystallinity and doping concentration.

[0183] Preferably, the amorphous silicon layer is an intrinsic hydrogenated amorphous silicon film; the microcrystalline silicon layer has a doping concentration of 1–5×1019 cm-3; and the polycrystalline silicon layer has a doping concentration of 1–5×1020 cm-3.

[0184] Preferably, the PECVD process parameters are as follows: deposition temperature ranging from 100 °C to 350 °C, RF frequency from 13.56 MHz to 60 MHz, RF power density greater than 0.1 W / cm², deposition pressure from 0.1 to 3 Torr, H₂ / SiH₄ gas flow ratio from 2 to 90, PH₃ volume concentration from 1 to 4 vol%, and a deposition rate ranging from 0.1 to 8 nm / min.

[0185] Preferably, the PECVD process parameters for depositing each silicon layer are as follows:

[0186] For the amorphous silicon layer:

[0187] Temperature: 100–180 °C,

[0188] RF frequency: 13.56 MHz,

[0189] RF power density: 0.1–0.3 W / cm²,

[0190] Deposition pressure: 0.1–1 Torr,

[0191] H₂ / SiH₄ flow ratio: 2–5,

[0192] Deposition rate: 0.1–0.5 nm / min.

[0193] For the microcrystalline silicon layer:

[0194] Temperature: 180–250 °C,

[0195] RF frequency: 13.56–27.12 MHz,

[0196] RF power density: 0.5–1 W / cm²,

[0197] Deposition pressure: 1–3 Torr,

[0198] H₂ / SiH₄ flow ratio: 20–30,

[0199] PH₃ volume concentration: 1–2 vol%,

[0200] Deposition rate: 0.5–4 nm / min.

[0201] For the polycrystalline silicon layer:

[0202] Temperature: 250–350 °C,

[0203] RF frequency: 40–60 MHz,

[0204] RF power density:>2 W / cm²,

[0205] Deposition pressure: 0.5–1.5 Torr,

[0206] H₂ / SiH₄ flow ratio: 50–90,

[0207] PH₃ volume concentration: 3–4 vol%,

[0208] Deposition rate: 1–8 nm / min.

[0209] Preferably, in Step 6, the film deposited by PECVD is a front-side anti-reflection layer,and in Step 7, the film deposited by PECVD is a rear-side anti-reflection layer.

[0210] Preferably, in Step 8, the printing process comprises printing silver paste on both the front and rear surfaces of the cell to form the front electrode and the rear electrode,and the sintering process comprises sintering the front silver paste or silver-aluminum paste to form an ohmic contact with the front surface of the silicon wafer, and sintering the rear silver paste to form an ohmic contact with the silicon thin-film composite layer, while removing organic binders.

[0211] Preferably, in Step 9, both the front electrode and the rear electrode undergo laser scanning treatment to improve the metal–semiconductor contact between silver and silicon, with a reverse bias voltage applied during laser irradiation,and the rear electrode forms direct ohmic contact with the microcrystalline silicon layer or the polycrystalline silicon layer, avoiding contact with the bulk of the N-type monocrystalline silicon wafer.

[0212] In summary, the present disclosure has the following advantages:

[0213] 1.The invention replaces the conventional thermally diffused back surface field with a doped thin-film stack comprising microcrystalline and polycrystalline silicon layers. This design avoids silicon bulk defects (such as dislocations and lattice distortion) typically caused by phosphorus diffusion. By tuning PECVD process parameters, a graded composite thin-film structure is formed by sequential deposition:

[0214] a 2–5 nm intrinsic hydrogenated amorphous silicon ultra-thin layer, a 5–15 nm lightly doped microcrystalline silicon layer, and a 15–50 nm heavily doped polycrystalline silicon layer.

[0215] This multilayer stack improves the back surface field effect via graded doping concentration, while simultaneously forming a refractive index gradient layer that reduces rear-side optical losses. The resulting structure optimizes both electrical and optical performance, thereby increasing open-circuit voltage (Voc), fill factor (FF), and short-circuit current density (Jsc), ultimately leading to a significant enhancement in conversion efficiency.

[0216] 2.The rear surface of the silicon wafer is polished flat using alkaline polishing, removing the pyramid texturing and allowing it to serve as an efficient infrared emitter. This treatment also improves the film density and continuity of the amorphous–microcrystalline–polycrystalline silicon composite layer, enhancing surface passivation and further increasing Voc.

[0217] 3.After firing through the rear-side anti-reflection layer, the rear electrode forms direct ohmic contact with the microcrystalline or polycrystalline silicon layer, avoiding direct contact with the silicon wafer bulk. This prevents the accumulation of high local carrier concentrations, significantly reduces Auger and other non-radiative recombination, and thereby improves both open-circuit voltage and conversion efficiency.

[0218] 4.Laser scanning is applied to both the front and rear electrodes under a reverse bias, improving the metal–semiconductor contact between silver and silicon. This reduces series resistance and increases the fill factor.

[0219] 5.With the optimized device structure, the manufacturing process eliminates two steps compared to conventional N-type PERT bifacial cells. This not only improves conversion efficiency but also reduces non-silicon manufacturing costs, enabling scalable mass production.

Claims

1.An N-type silicon PERT bifacial solar cell device structure, comprising:a front electrode (1), a front-side anti-reflection layer (2), a passivation layer (3), a p+ emitter (4), an N-type monocrystalline silicon wafer (5), an n+ back surface field (6), a rear-side anti-reflection layer (7), and a rear electrode (8),wherein the n+ back surface field (6) is an amorphous–microcrystalline–polycrystalline silicon composite thin-film stack, consisting of an amorphous silicon layer (61), a microcrystalline silicon layer (62), and a polycrystalline silicon layer (63).2.A method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 1, comprising the following steps:Step 1: texturing, wherein both the front and rear surfaces of the wafer are textured with a pyramidal structure,Step 2: boron diffusion,Step 3: cleaning and alkaline polishing,Step 4: sequentially depositing, using PECVD, an intrinsic amorphous silicon film, a microcrystalline silicon film, and a polycrystalline silicon film to form the n+ back surface field (6),Step 5: depositing a front-side passivation layer (3) using ALD,Step 6: depositing a front-side film using PECVD,Step 7: depositing a rear-side film using PECVD,Step 8: screen printing and sintering,Step 9: performing laser scanning treatment on both the front and rear electrodes.3.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 2,wherein in Step 2, a p+ emitter (4) is formed on the front surface by boron diffusion to constitute a PN junction with the N-type monocrystalline silicon wafer (5),and a back surface field is formed on the rear side via a doped silicon thin-film composite layer.4.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 2,wherein in Step 4, a PECVD process is employed to sequentially deposit:a 2–5 nm amorphous silicon layer (61),a 5–15 nm microcrystalline silicon layer (62),and a 15–50 nm polycrystalline silicon layer (63),thereby forming a graded amorphous–microcrystalline–polycrystalline silicon thin-film structure that establishes a composite back surface field with gradients in both crystallinity and doping concentration.5.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 4,wherein the amorphous silicon layer (61) is an intrinsic hydrogenated amorphous silicon film,the microcrystalline silicon layer (62) has a doping concentration of 1–5×1019 cm-3,and the polycrystalline silicon layer (63) has a doping concentration of 1–5×1020 cm-3.6.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 5,wherein the PECVD process parameters are as follows:a deposition temperature of 100–350 °C,an RF frequency of 13.56–60 MHz,an RF power density greater than 0.1 W / cm²,a deposition pressure of 0.1–3 Torr,H₂ / SiH₄ gas flow ratio of 2–90,PH₃ volume concentration of 1–4 vol%,and a deposition rate of 0.1–8 nm / min.7.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 6,wherein the PECVD process parameters for depositing each silicon layer are as follows:For the amorphous silicon layer (61):deposition temperature 100–180 °C,RF frequency 13.56 MHz,RF power density 0.1–0.3 W / cm²,deposition pressure 0.1–1 Torr,H₂ / SiH₄ flow ratio 2–5,and deposition rate 0.1–0.5 nm / min,For the microcrystalline silicon layer (62):deposition temperature 180–250 °C,RF frequency 13.56–27.12 MHz,RF power density 0.5–1 W / cm²,deposition pressure 1–3 Torr,H₂ / SiH₄ flow ratio of 20–30,PH₃ volume concentration 1–2 vol%,and deposition rate 0.5–4 nm / min,For the polycrystalline silicon layer (63):deposition temperature 250–350 °C,RF frequency 40–60 MHz,RF power density > 2 W / cm²,deposition pressure 0.5–1.5 Torr,H₂ / SiH₄ flow ratio 50–90,PH₃ volume concentration 3–4 vol%,and deposition rate 1–8 nm / min.8.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 2,wherein in Step 6, the film deposited by PECVD is a front-side anti-reflection layer (2),and in Step 7, the film deposited by PECVD is a rear-side anti-reflection layer (7).9.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 2,wherein in Step 8, the printing process comprises printing silver paste on both the front and rear surfaces of the cell to form the front electrode (1) and the rear electrode (8),and the sintering process comprises sintering the front silver paste or silver-aluminum paste to form an ohmic contact with the front surface of the silicon wafer, and sintering the rear silver paste to form an ohmic contact with the silicon thin-film composite layer, while removing organic binders.10.The method for manufacturing the N-type silicon PERT bifacial solar cell according to claim 2,wherein in Step 9, both the front electrode (1) and the rear electrode (8) undergo laser scanning treatment to improve the metal–semiconductor contact between silver and silicon, with a reverse bias voltage applied during laser irradiation,and the rear electrode (8) forms direct ohmic contact with the microcrystalline silicon layer (62) or the polycrystalline silicon layer (63), avoiding contact with the bulk of the N-type monocrystalline silicon wafer (5).

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