Pixel driving circuit and driving method
Patent Information
- Application Number
- PCT/CN2025/117208
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2025-08-27
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025117208_01102026_PF_FP_ABST
Abstract
Description
Pixel driving circuit and driving method Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a pixel driving circuit and driving method. Background Technology
[0002] OLED (Organic Light Emitting Diode) display panels offer advantages such as faster response times, superior color purity and brightness, higher contrast, and wider viewing angles, thus attracting increasing attention from display technology developers. As display technology advances, the demands on the display quality of OLED panels are also rising.
[0003] The pixel unit in an OLED display panel mainly includes an organic light-emitting diode and a pixel driving circuit for driving the organic light-emitting diode. The pixel driving circuit includes a driving transistor. How to optimize the structure of the pixel driving circuit to achieve high refresh rate, high uniformity and high image quality in OLED display panels has become an urgent problem to be solved in the field of display technology.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] To address the problems in the prior art, the present invention aims to provide a pixel driving circuit and driving method. This pixel driving circuit solves the problems of insufficient compensation time for the threshold voltage Vth of the driving transistor and hysteresis caused by long-term operation of the driving transistor under high refresh rate and high resolution.
[0006] A first aspect of the present invention provides a pixel driving circuit, comprising:
[0007] The driving sub-circuit is configured to transmit the voltage of the first node N1 and its own threshold voltage to the third node N3 in response to the second node N2;
[0008] The light-emitting control unit is configured to control the coupling between the positive power supply signal ELVDD and the first node N1 and the coupling between the third node N3 and the fourth node N4 under the control of the first enable signal En_a. The fourth node N4 is used to couple the anode of a light-emitting diode.
[0009] The data writing unit is configured to transmit the data signal Data to the sixth node N6 in response to the first scan signal Sn;
[0010] The first storage capacitor C1 and the second storage capacitor C2 are coupled through the fifth node N5. The first storage capacitor C1 is coupled to the fifth node N5 and the second node N2, and the second storage capacitor C2 is coupled to the sixth node N6 and the fifth node N5.
[0011] The initialization unit is configured to transmit a third initialization signal Vint3 to a first node N1 in response to a second scan signal Sn+1, transmit a first initialization signal Vint1 to a second node N2 in response to a second latch signal Sc-1, transmit a second initialization signal Vint2 to a fourth node N4 in response to a second scan signal Sn+1, transmit a power supply positive signal ELVDD to a fifth node N5 in response to a first latch signal Sc, and transmit a fourth initialization signal Vint4 to a sixth node N6 in response to a second enable signal En_b.
[0012] The first compensation unit is configured to write the power supply positive signal ELVDD and the threshold voltage of the driving transistor into the second node N2 in response to the first latch signal Sc.
[0013] According to a first aspect of the present invention, the light-emitting control unit includes a fourth switching transistor T4 and a fifth switching transistor T5;
[0014] The fourth switching transistor T4 is coupled to the positive power supply signal ELVDD, the first enable signal En_a and the first node N1. Under the control of the first enable signal En_a, the fourth switching transistor T4 controls the coupling between the positive power supply signal ELVDD and the first node N1.
[0015] The fifth switching transistor T5 is coupled to the third node N3, the first enable signal En_a and the fourth node N4. The fifth switching transistor T5 is configured to control the coupling between the third node N3 and the fourth node N4 under the control of the first enable signal En_a.
[0016] According to a first aspect of the present invention, the initialization unit includes a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, a ninth switching transistor T9, and a tenth switching transistor T10;
[0017] The sixth switching transistor T6 is coupled to the second latch signal Sc-1, the second node N2 and the first initialization signal Vint1;
[0018] The seventh switching transistor T7 is coupled to the second scan signal Sn+1, the fourth node N4 and the second initialization signal Vint2;
[0019] The eighth switching transistor T8 is coupled to the second scan signal Sn+1, the first node N1 and the third initialization signal Vint3;
[0020] The ninth switching transistor T9 is coupled to the second enable signal En_b, the sixth node N6 and the fourth initialization signal Vint4;
[0021] The tenth switching transistor T10 is coupled to the first latch signal Sc, the fifth node N5, and the positive power supply signal ELVDD.
[0022] According to a first aspect of the present invention, the data writing unit includes a first switching transistor T1, wherein the first switching transistor T1 is a single-gate transistor or a multi-gate transistor.
[0023] According to a first aspect of the invention, the first switching transistor T1 and the ninth switching transistor T9 are transistors of different channel types;
[0024] The second enable signal En_b is connected to the first scan signal Sn.
[0025] According to a first aspect of the present invention, the sixth switching transistor T6, the ninth switching transistor T9 and / or the tenth switching transistor T10 are dual-gate transistors, and a storage capacitor is provided between the control terminal and the intermediate terminal of the dual-gate transistor.
[0026] According to a first aspect of the invention, the pixel driving circuit further includes a second supplementary unit configured to write a power supply positive signal ELVDD to the first node N1 in response to a first latch signal Sc.
[0027] According to a first aspect of the present invention, the first switching transistor T1 is a dual-gate transistor, and a storage capacitor is provided between the control terminal and the intermediate terminal of the first switching transistor T1.
[0028] According to a first aspect of the present invention, the first compensation unit includes a third switching transistor T3, wherein the third switching transistor T3 is a single-gate transistor or a multi-gate transistor.
[0029] A second aspect of the present invention provides a driving method applied to the aforementioned pixel driving circuit, comprising:
[0030] In phase B, the first latch signal Sc and the second latch signal Sc-1 include at least one on potential, and the first latch signal Sc is at a different potential than the second latch signal Sc-1. The first enable signal En_a, the first scan signal Sn and the second scan signal Sn+1 are all off potentials, and the second enable signal En_b is an on point.
[0031] In stage C, the first latch signal Sc and the second enable signal En_b are both on potentials, and the first enable signal En_a, the second latch signal Sc-1, the first scan signal Sn and the second scan signal Sn+1 are all off potentials.
[0032] In stage D, the first latch signal Sc and the first scan signal Sn are both on potentials, and the first enable signal En_a, the second enable signal En_b, the second latch signal Sc-1 and the second scan signal Sn+1 are all off potentials.
[0033] In phase E, the second enable signal En_b, the first scan signal Sn, and the second scan signal Sn+1 are all on-state potentials, while the first enable signal En_a, the second latch signal Sc-1, the first latch signal Sc, and the first scan signal Sn are all off-state potentials; and
[0034] In phase A, the first enable signal En_a and the second enable signal En_b are both on-potentials, and the second latch signal Sc-1, the first latch signal Sc, the first scan signal Sn and the second scan signal Sn+1 are all off-potentials.
[0035] The pixel driving circuit of this invention includes multiple initialization nodes, which can solve the problems of insufficient compensation time for the threshold voltage Vth of the driving transistor and hysteresis caused by long-term operation of the driving transistor under high refresh rate and high resolution. At the same time, in order to increase the uniformity of low brightness display, a voltage reset function of the light-emitting control unit is added to realize that En_a is in multiple power-off potential pulses within one frame to turn off the switching transistor of the light-emitting control unit. In addition, compared with the prior art, in order to avoid the switching transistor of the initialization unit being affected by En_a and switching on and off multiple times, thereby causing large changes in the potential of the second node N2 within one frame and causing uneven display brightness of the display panel, the switching transistor of the initialization unit is set with a separate enable signal. Attached Figure Description
[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without inventive effort. Furthermore, the drawings are merely illustrative diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.
[0037] Figure 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention;
[0038] Figure 2 is a schematic diagram of a pixel driving circuit according to another embodiment of the present invention;
[0039] Figure 3 is a timing diagram of a pixel driving circuit according to an embodiment of the present invention;
[0040] Figures 4 to 8 are state diagrams of the pixel driving circuit in the first embodiment of the present invention at various stages;
[0041] Figure 9 is a timing diagram of the pixel driving circuit according to another embodiment of the present invention;
[0042] Figure 10 is a timing diagram of the pixel driving circuit in one frame according to an embodiment of the present invention.
[0043] Figure 11 is a simulated voltage diagram of the second node N2 in the pixel driving circuit of the prior art; and
[0044] Figure 12 is a simulated voltage diagram of the second node N2 of a pixel driving circuit according to an embodiment of the present invention. Detailed Implementation
[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present invention can be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.
[0046] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.
[0047] In the representation of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate different embodiments or examples represented in this invention, as well as features of different embodiments or examples, without contradiction.
[0048] To clearly illustrate the present invention, components unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.
[0049] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.
[0050] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.
[0051] Although the terms first, second, etc., are used in some instances herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.
[0052] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the invention. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.
[0053] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with relevant technical literature and the content of this present instruction, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.
[0054] The pixel driving circuit and driving method of the present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention. In the pixel driving circuit provided by the embodiments of the present invention, each node does not represent an actual existing component, but rather represents a junction point of related electrical connections in the circuit diagram. That is to say, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.
[0055] Figure 1 is a schematic diagram of a pixel driving circuit according to a first embodiment of the present invention. Specifically, the pixel driving circuit includes:
[0056] A driving sub-circuit, coupled to a first node N1, a second node N2, and a third node N3, is configured to transmit the voltage of the first node N1 and its own threshold voltage to the third node N3 in response to the second node N2. In a first embodiment, the driving sub-circuit includes a second driving transistor T2, the control electrode of which is coupled to the second node N2, the first electrode of which is coupled to the first node N1, and the second electrode of which is coupled to the third node N3. In this case, the voltage of the third node N3 is the sum of the threshold voltage Vth of the second driving transistor T2 and the voltage of the first node N1. It should be noted that in the pixel driving circuit of the present invention, the control electrode of each thin-film transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor.
[0057] The light-emitting control unit is configured to control the coupling between the positive power supply signal ELVDD and the first node N1, and the coupling between the third node N3 and the fourth node N4, under the control of the first enable signal En_a. The fourth node N4 is used to couple the anode of a light-emitting diode, and the cathode of the light-emitting diode is coupled to a negative power supply signal ELVSS. In a first embodiment, the light-emitting control unit includes a fourth switching transistor T4 and a fifth switching transistor T5; wherein, the fourth switching transistor T4 is coupled to the positive power supply signal ELVDD, the first enable signal En_a, and the first node N1, that is, the control electrode of the fourth switching transistor T4 is coupled to the first enable signal En_a, the first electrode of the fourth switching transistor T4 is coupled to the positive power supply signal ELVDD, and the second electrode of the fourth switching transistor T4 is coupled to the first node N1. At this time, the fourth switching transistor T4 controls the coupling between the positive power supply signal ELVDD and the first node N1 under the control of the first enable signal En_a. The fifth switching transistor T5 is coupled to the third node N3, the first enable signal En_a, and the fourth node N4. That is, the control electrode of the fifth switching transistor T5 is coupled to the first enable signal En_a, the first electrode of the fifth switching transistor T5 is coupled to the third node N3, and the second electrode of the fifth switching transistor T5 is coupled to the fourth node N4. At this time, the fifth switching transistor T5 is configured to control the coupling between the third node N3 and the fourth node N4 under the control of the first enable signal En_a.
[0058] A data writing unit is configured to transmit a data signal Data to a sixth node N6 in response to a first scan signal Sn. In a first embodiment, the data writing unit includes a first switching transistor T1, the control electrode of which is coupled to the first scan signal Sn, and its first and second electrodes are coupled to the data signal Data and the sixth node N6, respectively. A first storage capacitor C1 and a second storage capacitor C2 are coupled through a fifth node N5, with the first storage capacitor C1 coupled to both the fifth node N5 and the second node N2, and the second storage capacitor C2 coupled to both the sixth node N6 and the fifth node N5.
[0059] The initialization unit is configured to transmit a third initialization signal Vint3 to a first node N1 in response to a second scan signal Sn+1, transmit a first initialization signal Vint1 to a second node N2 in response to a second latch signal Sc-1, transmit a second initialization signal Vint2 to a fourth node N4 in response to a second scan signal Sn+1, transmit a power supply positive signal ELVDD to a fifth node N5 in response to a first latch signal Sc, and transmit a fourth initialization signal Vint4 to a sixth node N6 in response to a second enable signal En_b. In the above embodiments, the initialization unit includes a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, a ninth switching transistor T9, and a tenth switching transistor T10; the sixth switching transistor T6 is coupled to a second latch signal Sc-1, a second node N2, and a first initialization signal Vint1; the seventh switching transistor T7 is coupled to a second scan signal Sn+1, a fourth node N4, and a second initialization signal Vint2; the eighth switching transistor T8 is coupled to the second scan signal Sn+1, a first node N1, and a third initialization signal Vint3; the ninth switching transistor T9 is coupled to a second enable signal En_b, a sixth node N6, and a fourth initialization signal Vint4; and the tenth switching transistor T10 is coupled to the first latch signal Sc, a fifth node N5, and a positive power supply signal ELVDD. It should be noted that the voltage reset function of the fourth node N4 is implemented through the first enable signal En_a, which adds the voltage reset function of the light-emitting control unit. This enables the first enable signal En_a to be in multiple power-off potential pulses within one frame to turn off the switching transistor of the light-emitting control unit. However, in order to avoid the ninth switching transistor T9 of the initialization unit switching multiple times, which would cause the potential of the second node N2 to change significantly within one frame and result in uneven display brightness, the ninth switching transistor T9 of the initialization unit is set with a separate second enable signal En_b. The effect of this improvement will be discussed in the driving method section of the pixel driving circuit.
[0060] A first compensation unit is configured to write a power supply positive signal ELVDD and a threshold voltage of a driving transistor into a second node N2 in response to a first latch signal Sc. In a first embodiment, the first compensation unit includes a third switching transistor T3, the control electrode of which is coupled to the first latch signal Sc, and its first and second electrodes are coupled to the second node N2 and the third node N3, respectively.
[0061] Furthermore, the pixel driving circuit also includes a second supplementary unit configured to write the positive power supply signal ELVDD into the first node N1 in response to the first latch signal Sc. The second supplementary unit includes an eleventh switching transistor T11, the control terminal of which is coupled to the first latch signal Sc, and its first and second terminals are coupled to the positive power supply signal ELVDD and the first node N1, respectively.
[0062] The pixel driving circuit of the present invention can solve the problems of insufficient compensation time of threshold voltage Vth of driving transistor under high refresh rate and high resolution and hysteresis caused by long-term operation of driving transistor. At the same time, it adds the voltage reset function of the fourth node N4 to reset the capacitance of the light-emitting diode device itself, thereby reducing the brightness in dark state and the uniformity of light emission.
[0063] Each switching transistor in the pixel driving circuit of the present invention can be a single-gate transistor or a dual-gate transistor. Since the voltages of the second node N2, the fifth node N5, and the sixth node N6 need to be maintained for one frame time, it is necessary to reduce the leakage current of the first switching transistor T1 of the data writing unit, the third switching transistor T3 of the first compensation unit, the sixth switching transistor T6, the ninth switching transistor T9, and the tenth switching transistor T10. In addition to changing the leakage current (Ioff) characteristics of the switching transistors in the manufacturing process, preferably, all of the above-mentioned switching transistors can be multi-gate structures with a number of gates greater than or equal to 2. For example, the first switching transistor T1 of the data writing unit, the third switching transistor T3 of the first compensation unit, the sixth switching transistor T6, the ninth switching transistor T9, and the tenth switching transistor T10 are all dual-gate transistors. The above structure can effectively reduce the leakage current of the switching transistors, thereby increasing the uniformity of the light emission of the display panel.
[0064] In other embodiments, the first switching transistor T1, the third switching transistor T3, the sixth switching transistor T6, the ninth switching transistor T9, and the tenth switching transistor T10 are all dual-gate transistors, and a storage capacitor is provided between the control terminal and the intermediate terminal of each dual-gate transistor. Specifically, the two ends of the storage capacitor Ca are respectively coupled to the control terminal (first scan signal Sn) and the intermediate terminal of the first switching transistor T1; the two ends of the storage capacitor Cb are respectively coupled to the control terminal (first latch signal Sc) and the intermediate terminal of the tenth switching transistor T10; the two ends of the storage capacitor Cc are respectively coupled to the control terminal (first latch signal Sc) and the intermediate terminal of the third switching transistor T3; the two ends of the storage capacitor Cd are respectively coupled to the control terminal (second latch signal Sc-1) and the intermediate terminal of the sixth switching transistor T6; and the two ends of the storage capacitor Ce are respectively coupled to the control terminal (fourth initialization signal Vint4) and the intermediate terminal of the ninth switching transistor T9. Adding storage capacitors between the multi-gate transistors can further reduce the leakage current of the switching transistors, thereby further increasing the uniformity of the light emission of the display panel. It should be noted that one end of each of the above-mentioned storage capacitors is coupled to the middle terminal of the multi-gate transistor, and the other end can be coupled to a fixed voltage potential, such as ELVDD, ELVSS, Vint1, Vint2, Vint3, Vint4, etc., or they can be interchanged.
[0065] The present invention also provides a driving method applied to a pixel driving circuit, wherein the driving transistor and each switching transistor of the driving circuit can be P-type transistors, such as PMOS transistors, or N-type transistors, such as NMOS transistors.
[0066] Figure 2 is a schematic diagram of a pixel driving circuit according to another embodiment of the present invention, wherein the first switching transistor T1 and the ninth switching transistor T9 are transistors of different channel types. For example, the first switching transistor T1 is a P-type transistor (PMOS) and the ninth switching transistor T9 is an N-type transistor (NMOS). In this case, the first scan signal Sn can be retained, and the second enable signal En_b can be connected to the first scan signal Sn. If the first switching transistor T1 is an N-type transistor and the ninth switching transistor T9 is an N-type transistor, the second enable signal En_b can be retained, and the first scan signal Sn can be connected to the second enable signal En_b. The above structure can reduce the number of input signals, which is beneficial for narrowing the bezel of the display panel.
[0067] Taking the embodiment in Figure 1, which uses PMOS transistors, as an example, the transistor's control terminal is at a high potential when it is off, and at a low potential when it is on. Figure 3 is a timing diagram of the pixel driving circuit according to an embodiment of the present invention. Specifically, the driving method includes the following time periods:
[0068] In stage B, at least one of the first latch signal Sc and the second latch signal Sc-1 includes a conduction potential, and the first latch signal Sc is at a different potential than the second latch signal Sc-1. The first enable signal En_a, the first scan signal Sn, and the second scan signal Sn+1 are all off potentials (high potential), and the second enable signal En_b is a conduction point (low potential). In the embodiment shown in Figure 3, the second latch signal Sc-1 and the second enable signal En_b are on potentials (low potential), and the first enable signal En_a, the first latch signal Sc, the first scan signal Sn, and the second scan signal Sn+1 are all off potentials. When the voltage is high, the first switching transistor T1, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the seventh switching transistor T7, the eighth switching transistor T8, the tenth switching transistor T10, and the eleventh switching transistor T11 are all turned off, as shown in Figure 4; the second latch signal Sc-1 is low, the sixth switching transistor T6 is turned on, the second node N2 is reset to low by writing the first initialization signal Vint1, the second enable signal En_b is low, the ninth switching transistor T9 is turned on, and the sixth node N6 is reset to low by writing the fourth initialization signal Vint4. As shown in Figure 3, the second latch signal Sc-1 includes a low-level signal (conduction potential). In practical applications, to eliminate the display problem caused by the influence of the previous frame's data signal Data potential on the final write potential of the second node N2, the second latch signal Sc-1 in stage B includes multiple low-level signals. Since the first latch signal Sc is at a different potential than the second latch signal Sc-1, the first latch signal Sc in stage B also includes multiple low-level signals. As shown in the driving timing diagram of another embodiment in Figure 9, the second latch signal Sc-1 includes two low-level signals, i.e., stage B includes stages B1, B2, and B3. The inclusion of multiple low-level signals in the second latch signal Sc-1 can make the second node N2 closer to the potential of the first initialization signal Vint1. It should be noted that the total duration of stages B1, B2, and B3 must be greater than or equal to the duration of stage B in the embodiment of Figure 3.
[0069] In phase C, both the first latch signal Sc and the second enable signal En_b are on, while the first enable signal En_a, the second latch signal Sc-1, the first scan signal Sn, and the second scan signal Sn+1 are all off (high potential). At this time, the first switching transistor T1, the fourth switching transistor T4, the fifth switching transistor T5, the seventh switching transistor T7, and the eighth switching transistor T8 are all off, as shown in Figure 5. Because the first latch signal Sc is low, the tenth switching transistor T10 is on, and the fifth node N5 writes the potential of the positive power supply signal ELVDD. The second enable signal En_b remains low, and the sixth node N maintains the potential of the fourth initialization signal Vint4. Because the first scan signal Sn is low, the sixth node N6 writes the potential of the data signal Data due to the on state of the first switching transistor T1. Since the first latch signal Sc is at a low potential, the third switching transistor T3, the tenth switching transistor T10, and the eleventh switching transistor T11 are turned on. Furthermore, because the second driving transistor T2 and the third switching transistor T3 are simultaneously turned on, forming a diode connection, the second node N2 will set the target potential (ELVDD+Vth_) to... T2 Write to the third node N3.
[0070] The second node N2 writes ELVDD+Vth_ to the third node N3. T2 During the voltage conversion process, the third switching transistor T3 turns on, shorting the drain (third node N3) and gate of the second driving transistor T2 to form a diode. At this time, the source (first node N1) of the second driving transistor T2 is at voltage ELVDD, and the gate (second node N2) of the second driving transistor T2 will start charging and boosting from the voltage of the first initialization signal Vint1 at the previous moment until the target voltage ELVDD+Vth is reached. T2 Up to this point, the second driving transistor T2 is turned off. This charging process is an exponential function type, initially fast and then slowing down. As it gets closer to the target ELVDD+Vth_ T2 The lower the voltage and charging current, the longer the required time (approximately 1.5–2.0 µs), which differs from the time required to write the data signal Data to the sixth node N6 (approximately tens to hundreds of ns), meaning there is at least a tenfold difference between the two. In the pixel driving circuit of this invention, a second storage capacitor C2 and a tenth switching transistor T10 are added, and the first scan signal Sn and the first latch signal Sc are two independent control signals, making the potential of the data signal Data written to the sixth node N6 different from the potential of the second node N2 written to the third node N3 (ELVDD+Vth_). T2They are independent of each other and no longer affect or restrain each other. Even if the first switch transistor T1 is turned off after the first scan signal Sn is written for a very short time, the first latch signal Sc can remain at the on potential until the second node N2 reaches ELVDD+Vth_ T2 The voltage compensation is sufficient, meaning that at the pixel compensation time, the charging of the second node N2 and the sixth node are independent.
[0071] In stage D, both the first latch signal Sc and the first scan signal Sn are on, and the first enable signal En_a, the second enable signal En_b, the second latch signal Sc-1, and the second scan signal Sn+1 are all off (high level). At this time, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, the seventh switching transistor T7, the eighth switching transistor T8, and the ninth switching transistor T9 are all off, as shown in Figure 6. Because the first scan signal Sn is at a low level, the first switching transistor T1 is turned on, and the sixth node N6 writes the potential of the data signal Data. The tenth switching transistor T10 is turned on due to the low-level first latch signal Sc, and the fifth node N5 maintains the potential of the positive power supply signal ELVDD. At the same time, the low-level first latch signal Sc causes the second driving transistor T2 and the third switching transistor T3 to continue forming a diode connection, and the second node N2 sets the target potential (ELVDD+Vth_). T2 Write to the third node N3; write the second node N2 to ELVDD+Vth_ T2 The timing is controlled by the first latch signal Sc and can be flexibly adjusted to be greater than or equal to the time of one line. It is unaffected by refresh rate and high resolution. Unlike existing technologies where the first scan signal Sn can only compensate for the time of one line, this solves the problem of the existing technology's threshold voltage Vth of the driving transistor under high refresh rate and high resolution. T2 This addresses the issue of inadequate compensation due to insufficient charging time.
[0072] In phase E, both the second enable signal En_b and the second scan signal Sn+1 are on, while the first enable signal En_a, the second latch signal Sc-1, the first latch signal Sc, and the first scan signal Sn are all off (high potential). At this time, the first switching transistor T1, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, the tenth switching transistor T10, and the eleventh switching transistor T11 are all off, as shown in Figure 7. Since the second enable signal En_b is low, the ninth switching transistor T9 is on, and the sixth node N6 changes from the potential of the data signal data to the potential of the fourth initialization signal Vint4. At this time, the first storage capacitor C1 and the second storage capacitor C2 can be considered as a single capacitor Cst, as shown in Figure 7. The voltage of the second node N2 is transformed into the positive power supply signal ELVDD+Vth_ due to the coupling effect of the storage capacitor. T2 +Vint4–Data. Because the second scan signal Sn+1 is at a low potential, the seventh switching transistor T7 is turned on, and the fourth node N4 writes the reset voltage of the second initialization signal Vint2 to reset the capacitance of the light-emitting diode itself, so as to reduce the dark state brightness and increase the brightness uniformity. Also because the second scan signal Sn+1 is at a low potential, the eighth switching transistor T8 is turned on, and the first node N1 writes the reset voltage of the third initialization signal Vint3. The purpose is to provide the bias voltage (on bias) of the second driving transistor T2 and solve the hysteresis problem caused by the driving transistor after a long period of bias operation.
[0073] In phase A, both the first enable signal En_a and the second enable signal En_b are on-potentials, and the second latch signal Sc-1, the first latch signal Sc, the first scan signal Sn, and the second scan signal Sn+1 are all off-potentials (high potentials). At this time, the first switching transistor T1, the third switching transistor T3, the sixth switching transistor T6, the seventh switching transistor T7, the eighth switching transistor T8, the tenth switching transistor T10, and the eleventh switching transistor T11 are all off, as shown in Figure 8. The first enable signal En_a is at a low potential, and the potential of the positive power supply signal ELVDD is written to the first node N1. When the maximum gate-source voltage Vgs of the second driving transistor T2... T2 Less than its threshold voltage Vth_ T2 When the second driving transistor T2 turns on, and simultaneously, because the fourth switching transistor T4 and the fifth switching transistor T5 are also turned on, current flows from the positive power supply signal ELVDD to the negative power supply signal ELVSS and the LED emits light. The LED's emitting current I... OLED Satisfy the following formula:
[0074] Where μ is the mobility of the second driving transistor T2, Cox is the dielectric constant of the insulating layer of the second driving transistor T2, W is the width of the second driving transistor, and L is the length of the driving transistor.
[0075] Figure 10 is a driving timing diagram of a pixel driving circuit in one frame according to an embodiment of the present invention. It shows the actual driving timing of a frame of the display panel when the pixel driving circuit of the present invention is used in an OLED display panel. The blue area is the timing of Figure 3 described above. In order to increase the uniformity of the low-brightness display of the display panel, the fourth switching transistor T4 and the fifth switching transistor T5 of the light-emitting control unit need to be turned off multiple times in the timing of the red area from then to the end of the frame. That is, the first enable signal En_a needs to include N pulses (N≥2) to be at the off potential multiple times. If the control electrode of the ninth switching transistor T9 in the prior art is connected to the first enable signal En_a, when the OLED display needs to increase the uniformity of the low-brightness display, the first enable signal En_a needs multiple high-level pulses within one frame to turn off the fourth switching transistor T4 and the fifth switching transistor T5. In this case, the ninth switching transistor T9 will inevitably be switched on and off multiple times, resulting in a large change in the potential of the second node N2 within one frame. Correspondingly, this causes uneven display brightness of the display panel. Figure 11 is a simulated voltage diagram of the second node N2 in the pixel driving circuit of the prior art. The horizontal axis is time (μs) and the vertical axis is voltage (V). The waveform of the first enable signal En_a within one frame (taking 500μs as an example) includes multiple high-level pulses. At this time, the voltage of the second node N2 drops from 4.862V to 4.698V, that is, the voltage of the second node N2 drops by 3.4%.
[0076] In this invention, the other signals in the red region, including the second latch signal Sc-1, the first latch signal Sc, the first scan signal Sn, the second scan signal Sn+1, and the second enable signal En_b, can maintain the potential at the end of the blue region until the start of the next frame, thereby reducing the change in the potential of the second node N2 within a frame. More specifically, the ninth switching transistor T9 of the pixel driving circuit in this invention is controlled by the second enable signal En_b. When the OLED display needs multiple high-level pulses within one frame to turn off the fourth switching transistor T4 and the fifth switching transistor T5 in order to increase the uniformity of the low-brightness display, the switching of the ninth switching transistor T9 is not affected. The change in the potential of the second node N2 within one frame due to the influence of the first enable signal En_a is small, and the display panel displays uniform brightness. Figure 12 is a simulated voltage diagram of the second node N2 of the pixel driving circuit according to an embodiment of this invention. The horizontal axis is time (μs) and the vertical axis is voltage (V). The waveform of the first enable signal En_a within one frame (taking 500μs as an example) includes multiple high-level pulses. The waveform of the second enable signal En_b can be independent of the waveform of the first enable signal En_a. At this time, the voltage of the second node N2 drops from 4.862V to 4.859V, that is, the voltage of the second node N2 drops by 0.06%. The above drop is considered to have no effect.
[0077] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A pixel driving circuit, characterized in that, include: The driving sub-circuit is configured to transmit the voltage of the first node N1 and its own threshold voltage to the third node N3 in response to the second node N2; The light-emitting control unit is configured to control the coupling between the positive power supply signal ELVDD and the first node N1 and the coupling between the third node N3 and the fourth node N4 under the control of the first enable signal En_a. The fourth node N4 is used to couple the anode of a light-emitting diode. The data writing unit is configured to transmit the data signal Data to the sixth node N6 in response to the first scan signal Sn; The first storage capacitor C1 and the second storage capacitor C2 are coupled through the fifth node N5. The first storage capacitor C1 is coupled to the fifth node N5 and the second node N2, and the second storage capacitor C2 is coupled to the sixth node N6 and the fifth node N5. The initialization unit is configured to transmit a third initialization signal Vint3 to a first node N1 in response to a second scan signal Sn+1, transmit a first initialization signal Vint1 to a second node N2 in response to a second latch signal Sc-1, transmit a second initialization signal Vint2 to a fourth node N4 in response to a second scan signal Sn+1, transmit a power supply positive signal ELVDD to a fifth node N5 in response to a first latch signal Sc, and transmit a fourth initialization signal Vint4 to a sixth node N6 in response to a second enable signal En_b. The first compensation unit is configured to write the power supply positive signal ELVDD and the threshold voltage of the driving transistor into the second node N2 in response to the first latch signal Sc.
2. The pixel driving circuit according to claim 1, characterized in that, The light-emitting control unit includes a fourth switching transistor T4 and a fifth switching transistor T5; The fourth switching transistor T4 is coupled to the positive power supply signal ELVDD, the first enable signal En_a and the first node N1. Under the control of the first enable signal En_a, the fourth switching transistor T4 controls the coupling between the positive power supply signal ELVDD and the first node N1. The fifth switching transistor T5 is coupled to the third node N3, the first enable signal En_a and the fourth node N4. The fifth switching transistor T5 is configured to control the coupling between the third node N3 and the fourth node N4 under the control of the first enable signal En_a.
3. The pixel driving circuit according to claim 1, characterized in that, The initialization unit includes a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, a ninth switching transistor T9, and a tenth switching transistor T10. The sixth switching transistor T6 is coupled to the second latch signal Sc-1, the second node N2 and the first initialization signal Vint1; The seventh switching transistor T7 is coupled to the second scan signal Sn+1, the fourth node N4 and the second initialization signal Vint2; The eighth switching transistor T8 is coupled to the second scan signal Sn+1, the first node N1 and the third initialization signal Vint3; The ninth switching transistor T9 is coupled to the second enable signal En_b, the sixth node N6 and the fourth initialization signal Vint4; The tenth switching transistor T10 is coupled to the first latch signal Sc, the fifth node N5, and the positive power supply signal ELVDD.
4. The pixel driving circuit according to claim 3, characterized in that, The data writing unit includes a first switching transistor T1, which is a single-gate transistor or a multi-gate transistor.
5. The pixel driving circuit according to claim 4, characterized in that, The first switching transistor T1 and the ninth switching transistor T9 are transistors of different channel types; The second enable signal En_b is connected to the first scan signal Sn.
6. The pixel driving circuit according to claim 5, characterized in that, The sixth switching transistor T6, the ninth switching transistor T9, and / or the tenth switching transistor T10 are dual-gate transistors, and a storage capacitor is provided between the control terminal and the intermediate terminal of the dual-gate transistor.
7. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit further includes a second supplementary unit configured to write the positive power supply signal ELVDD to the first node N1 in response to the first latch signal Sc.
8. The pixel driving circuit according to claim 4, characterized in that, The first switching transistor T1 is a dual-gate transistor, and a storage capacitor is provided between the control terminal and the intermediate terminal of the first switching transistor T1.
9. The pixel driving circuit according to claim 1, characterized in that, The first compensation unit includes a third switching transistor T3, which is a single-gate transistor or a multi-gate transistor.
10. A driving method, characterized in that, The pixel driving circuit according to any one of claims 1 to 9 comprises: In phase B, the first latch signal Sc and the second latch signal Sc-1 include at least one on potential, and the first latch signal Sc is at a different potential than the second latch signal Sc-1. The first enable signal En_a, the first scan signal Sn and the second scan signal Sn+1 are all off potentials, and the second enable signal En_b is an on point. In stage C, the first latch signal Sc and the second enable signal En_b are both on potentials, and the first enable signal En_a, the second latch signal Sc-1, the first scan signal Sn and the second scan signal Sn+1 are all off potentials. In stage D, the first latch signal Sc and the first scan signal Sn are both on potentials, and the first enable signal En_a, the second enable signal En_b, the second latch signal Sc-1 and the second scan signal Sn+1 are all off potentials. In stage E, both the second enable signal En_b and the second scan signal Sn+1 are on, and the first enable signal En_a, the second latch signal Sc-1, the first latch signal Sc, and the first scan signal Sn are all off; and In phase A, the first enable signal En_a and the second enable signal En_b are both on-potentials, and the second latch signal Sc-1, the first latch signal Sc, the first scan signal Sn and the second scan signal Sn+1 are all off-potentials.