Server startup operation method

Abstract

The present application relates to the technical field of servers, and provides a server startup operation method. The method comprises: a power module sends a power-on signal to a first processor, a baseboard management controller, and a second processor; then the first processor performs an initialization operation on the first processor on the basis of the power-on signal; the baseboard management controller performs a startup operation on the baseboard management controller in parallel on the basis of the power-on signal; the second processor generates an indication signal in parallel on the basis of the power-on signal, and controls the indication signal to be sent to the first processor at a first preset moment; and finally, the first processor controls, on the basis of the indication signal, a server to start an operating system. By using the technical solution, the purposes of shortening the overall startup duration of the server and improving startup efficiency of the server can be achieved.

Description

Server startup procedure

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510378486.0, filed on March 28, 2025, entitled “Server Startup Operation Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of server technology, and in particular to a server startup operation method. Background Technology

[0004] Currently, servers are used in various fields, but the various management firmware within servers are interdependent. Specifically, during server startup, the processor's power-on sequence cannot be executed until the server motherboard's internal circuit board management controller is activated. This execution method results in a long server startup time, which in turn causes related services associated with the server to be unable to start in a timely manner. Summary of the Invention

[0005] This application provides a server startup method that eliminates the need for a fixed startup execution order during server startup, thereby shortening the overall server startup time and improving server startup efficiency.

[0006] This application provides a server startup method, wherein the server includes a power module, a first processor, a baseboard management controller, and a second processor, and the method includes:

[0007] The power-on signal is sent to the first processor, the baseboard management controller, and the second processor via the power module; wherein, the power-on signal is used to indicate that the server's power module is powered on;

[0008] The first processor is initialized according to the power-on signal;

[0009] The baseboard management controller performs a startup operation in parallel based on the power-on signal;

[0010] The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the configuration of the second processor is complete; the first preset time is determined by the time when the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0011] The first processor controls the server to start the operating system according to the instruction signals.

[0012] This application also provides a server startup operation device, which includes a power module, a first processor, a baseboard management controller, and a second processor. The device includes:

[0013] The power module is used to send a power-on signal to the first processor, the baseboard management controller, and the second processor; wherein, the power-on signal is used to indicate that the server's power module is powered on;

[0014] The first processor is used to initialize the first processor according to the power-on signal;

[0015] The baseboard management controller is used to perform a startup operation on the baseboard management controller in parallel according to the power-on signal;

[0016] The second processor is used to generate an indication signal in parallel based on the power-on signal, and control the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the second processor has completed configuration; the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0017] The first processor is used to control the server to start the operating system according to the indication signal.

[0018] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described server startup operation methods.

[0019] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described server startup operation methods.

[0020] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described server startup operation methods.

[0021] This application sends a power-on signal to a first processor, a substrate management controller, and a second processor via a power module. The first processor then initializes itself based on the power-on signal, while the substrate management controller simultaneously performs a startup operation based on the same signal. Simultaneously, the second processor generates an indication signal based on the power-on signal and sends it to the first processor at a predetermined time. Because the first processor, substrate management controller, and second processor process the power-on signal simultaneously, there is no strong correlation. Finally, the first processor controls the server to start the operating system based on the indication signal, thereby shortening the overall server startup time and improving server startup efficiency. Attached Figure Description

[0022] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a schematic diagram of a circuit structure for performing a server startup operation according to some embodiments of this application;

[0024] Figure 2 is a flowchart illustrating a server startup method provided in some embodiments of this application;

[0025] Figure 3 is a flowchart illustrating a server startup method provided in some embodiments of this application;

[0026] Figure 4 is a signaling interaction diagram of a server startup operation provided in some embodiments of this application;

[0027] Figure 5 is a flowchart illustrating a server startup method provided in some embodiments of this application;

[0028] Figure 6 is a signaling interaction diagram of a server startup operation provided in some embodiments of this application;

[0029] Figure 7 is a schematic diagram of the structure of a server startup operation device provided in some embodiments of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] In related technologies, after a server power failure and restart, the complex programmable logic devices (CPLs) can only be powered on after the baseboard management controller is activated. This results in excessively long server boot times, failing to meet the needs of real-world scenarios. Especially in data centers deploying tens of thousands of servers, maintenance personnel cannot wait for the baseboard management controller to initialize sequentially before powering on the servers. Furthermore, in actual operation, the CPLs activate immediately upon receiving the indication signal, causing server crashes during startup. Therefore, this application addresses these issues by providing a server startup method.

[0034] The specific hardware architecture upon which a server startup operation depends is described herein. Specifically, see Figure 1, which illustrates a circuit structure for performing a server startup operation.

[0035] Some embodiments of this application provide a server startup method. The method is described in detail below with reference to the execution flow of such a method. Specifically, please refer to Figure 2, which shows a flowchart of a server startup method. The server includes a power module, a first processor, a baseboard management controller, and a second processor. The method includes:

[0036] S201, The power-on signal is sent to the first processor, the baseboard management controller and the second processor through the power module; wherein, the power-on signal is used to indicate that the power module of the server is powered on.

[0037] Some embodiments of this application are applied to scenarios where a server experiences a sudden power outage and subsequent power restoration. Specifically, before sending a power-on signal to the first processor, the baseboard management controller, and the second processor via the power module, the method further includes:

[0038] The power module experienced an abnormal power outage and was subsequently powered back on.

[0039] In some embodiments, an abnormal power outage of the server's power module causes the server to malfunction, and then power is restored to the server to restore its operation.

[0040] In some embodiments, the power module is electrically connected to the first processor; the power module is electrically connected to the baseboard management controller; the power module is electrically connected to the second processor; and the first processor is electrically connected to the second processor.

[0041] In some embodiments, after an abnormal power failure of the power module, the method further includes:

[0042] If the power module is detected to be powered on, a power-on signal is generated through the power module.

[0043] In some embodiments, a power-on signal is generated by the power module after the power module is powered on again.

[0044] In some embodiments of this application, the power-on signal can be the HPM_STBY_EN signal. The power module simultaneously sends the power-on signal to the first processor, the baseboard management controller, and the second processor. In some embodiments of this application, the first processor can be a Complex Programmable Logic Device (CPLD). The CPLD consists of a programmable interconnect matrix unit surrounding a central programmable logic macrocell. It achieves flexible configuration of logical functions through programmable logic units and interconnect resources. The baseboard management controller (BMC) is integrated into servers, network devices, and other computer systems to monitor the hardware status of devices, perform remote management operations, and provide monitoring and control functions.

[0045] In some embodiments, the second processor (Central Processing Unit, or CPU) can be the core component of the system, responsible for executing program instructions, processing data, and controlling the operation of the entire system.

[0046] In related technologies, the power-on sequence of the CPLD controlling server startup can only be executed after the BMC management firmware of the server motherboard is activated. This results in a longer server restart time. However, in some embodiments of this application, by simultaneously sending power-on signals to the CPLD, BMC, and CPU, the CPLD, BMC, and CPU can work simultaneously, thereby resolving the timing issue between the CPLD and BMC.

[0047] S202. The first processor performs an initialization operation based on the power-on signal.

[0048] In some embodiments, the first processor performs an initialization operation on the first processor according to the power-on signal, including:

[0049] The firmware in the first processor is initialized based on the power-on signal.

[0050] In some embodiments, after receiving a power-on signal, the first processor initializes the firmware in the first processor.

[0051] S203. The baseboard management controller performs a startup operation in parallel according to the power-on signal.

[0052] In some embodiments, the baseboard management controller starts up in parallel after receiving a power-on signal. In some embodiments of this application, the startup operation of the baseboard management controller after receiving a power-on signal and the initialization operation of the first processor after receiving a power-on signal are performed simultaneously.

[0053] S204. The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the second processor has completed configuration; the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation.

[0054] In some embodiments, the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation, including:

[0055] The first preset time is the time when the first processor receives the power-on signal plus the time it takes for the first processor to complete the initialization operation.

[0056] In some embodiments, after receiving the power-on signal, the second processor generates an indication signal in parallel. This indication signal is used to indicate that the second processor configuration is complete. Specifically, the indication signal may be an FPGA_Ready signal. In some embodiments of this application, the time when the second processor sends the indication signal is the same as the time when the first processor receives the indication signal. In some embodiments of this application, for ease of description, let T0 be the time when the first processor receives the power-on signal, F0 be the duration of the first processor completing the initialization operation, and T1 be the first preset time, then T1 = T0 + F0. Generally, F0 is 6 seconds.

[0057] S205. The first processor controls the server to start the operating system according to the instruction signal.

[0058] In some embodiments, after receiving an indication signal, the first processor controls the server to start the operating system.

[0059] This application provides a server startup method. A power-on signal is sent from a power module to a first processor, a baseboard management controller, and a second processor. The first processor then initializes itself based on the power-on signal, while the baseboard management controller simultaneously performs a startup operation based on the same power-on signal. Simultaneously, the second processor generates an indication signal based on the power-on signal and sends this indication signal to the first processor at a first preset time. Since the first processor, baseboard management controller, and second processor process the power-on signal simultaneously, there is no strong correlation. Finally, the first processor controls the server to start the operating system based on the indication signal, thereby shortening the overall server startup time and improving startup efficiency.

[0060] Figure 3 shows a flowchart of a server startup method. The server includes a power module, a first processor, a baseboard management controller, and a second processor. Some embodiments of this application are based on the above embodiments, and some embodiments of this application can be combined with various schemes in one or more of the above embodiments. Specifically, please refer to the following steps:

[0061] S301, The power-on signal is sent to the first processor, the baseboard management controller and the second processor through the power module; wherein, the power-on signal is used to indicate that the power module of the server is powered on.

[0062] In some embodiments, the number of servers is multiple.

[0063] In some embodiments of this application, it can be used in a system consisting of multiple servers. That is, this embodiment can be used in scenarios where multiple servers have experienced a power outage and then been powered on again.

[0064] In some embodiments, the method further includes:

[0065] The power-on signal is monitored in real time by the first processor.

[0066] In some embodiments, the first processor continuously monitors the power-on signal in real time after the server is powered on, and then performs subsequent operations based on the power-on signal.

[0067] S302, The first processor performs an initialization operation based on the power-on signal.

[0068] In some embodiments, the firmware in the first processor is initialized by the first processor according to the power-on signal, including:

[0069] The first processor initializes the memory based on the power-on signal and reads the feature control bits;

[0070] The configuration mode is determined by the first processor based on the feature control bits;

[0071] The initialization operation of the first processor is completed when the first processor loads the bit stream according to the configuration mode and detects that the preset signal bit is the preset signal.

[0072] In some embodiments, the first processor automatically performs a reset operation after power-on, resetting its internal memory, registers, and logic units to their initial states to prepare for subsequent initialization. Then, the firmware program is downloaded to the first processor via a configuration interface. This step typically requires a dedicated programmer or configuration circuitry on a development board. During configuration, the first processor configures its internal logic according to the downloaded firmware program, including setting the functions of I / O (Input / Output) pins, clock frequencies, etc. After configuration, the first processor executes the initialization program in the firmware. The main tasks of the initialization program include: configuring the communication interface with external devices (such as sensors, memory, etc.) to ensure correct data transmission; setting the configuration mode: setting the configuration mode of the first processor according to specific application requirements, such as configuring timer, counter, and other modules; and loading default parameters: loading some default operating parameters into the corresponding registers to provide a foundation for subsequent normal operation. During initialization, the first processor may execute some self-test programs to check whether the hardware is working properly and whether the firmware is loaded correctly. If a problem is found, an error handling mechanism may be triggered, such as reconfiguration or sending an error signal.

[0073] S303, The baseboard management controller performs a startup operation in parallel according to the power-on signal.

[0074] In some embodiments, this step is executed in parallel with step S302, and there is no specific order between them. That is, a power-on signal is sent to the first processor and the substrate management controller respectively, and then the first processor executes the corresponding action, and the substrate management controller also executes the corresponding action.

[0075] In some embodiments, the baseboard management controller is activated in parallel according to a power-on signal, including:

[0076] The baseboard management controller initializes the built-in hardware devices in parallel based on the power-on signal;

[0077] The baseboard management controller initializes the external hardware devices based on the power-on signal to complete the startup operation of the baseboard management controller.

[0078] In some embodiments, the baseboard management controller performs the boot operation as the u-boot (Universal Boot loader) stage of the BMC firmware. Specifically, during the u-boot stage of the BMC firmware boot, the first step is hardware initialization, including configuring critical hardware such as the CPU and memory controller to ensure the system has a basic operating environment. For example, setting the CPU operating frequency and memory access parameters prepares for subsequent system boot. Next, the operating system kernel and root file system are loaded. After hardware initialization, the u-boot stage loads the operating system kernel and the initial root file system into memory. Then, network-related parameters need to be set. This includes configuring the network interface and setting the IP (Internet Protocol) address so that the BMC can communicate with external devices. In some applications with high security requirements, the BMC firmware also performs trust measurements during the u-boot stage. This includes integrity checks on critical components such as the file system, bootloader, and kernel. After confirming the trustworthiness of these components, the baseboard management controller performs the boot operation.

[0079] S304. The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the second processor has completed configuration; the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation.

[0080] In some embodiments, this step can refer to the content of step S204, and will not be repeated here.

[0081] S305. The first processor sends a power-on signal to the second processor at a second preset time after receiving the indication signal, and the second processor controls the server to start the operating system; wherein, the second preset time is determined by the time when the first processor receives the indication signal and the duration of the board management controller completing the startup operation.

[0082] In some embodiments, the second preset time is determined by the time the first processor receives the indication signal and the duration for which the substrate management controller completes the startup operation, including:

[0083] The second preset time is the time when the first processor receives the indication signal plus the time value of the duration for the baseboard management controller to complete the startup operation.

[0084] In some embodiments, the time at which the first processor receives the indication signal can be a first preset time, i.e., T1. Let the second preset time be T2, and the duration for the board management controller to complete the startup operation be F1, then T2 = T1 + F1. Typically, F1 is 10 seconds.

[0085] In some embodiments, the time taken for the baseboard management controller to complete the startup operation is determined based on the historical usage records of the current server.

[0086] Specifically, it can be determined by the average duration of startup operations completed by the baseboard management controller in historical usage records, or by prediction using a preset model; no specific limitation is made here.

[0087] The advantage of this setting is that the duration can be determined in real time according to different usage scenarios, or it can be determined according to the current server model, which is highly flexible. It will not be impossible to implement this embodiment when changing scenarios because the user sets a fixed value.

[0088] It is worth noting that if a delay function is set in the first processor, but the delay time is not the second preset time, that is, the delay is not set at this time, then even if the delay is set, the decoupling function between the first processor and the baseboard management controller cannot be achieved. This is because the signal timing of the first processor has clear timing requirements for the signal timing.

[0089] In some embodiments, the power-on signal can be the RUN_POWER_EN signal. The first processor sends the RUN_POWER_EN signal to the second processor after a delay of F1 following the receipt of the indication signal, and the second processor controls the server to start the operating system. This is configured so that after the server is powered off and then powered on again, there is no need to wait for the BMC to activate; the CPLD directly executes the power-on sequence to ensure the server's decoupling function. However, in practice, the BMC may fail to display the previously stored information during startup, leading to a crash in the basic input / output system under these conditions. Therefore, it is necessary to ensure the BMC completes the startup operation for a sufficient duration. Thus, the CPLD is set to send the RUN_POWER_EN signal to the second processor after a delay of F1 following the receipt of the indication signal to ensure the BMC completes the startup operation for the required duration.

[0090] In some embodiments, controlling the server to boot the operating system via a second processor includes:

[0091] The second processor controls the startup of the basic input / output system to complete the server's operating system startup; the server includes the basic input / output system.

[0092] In some embodiments, the second processor controls the server to boot the operating system. Specifically, it may control the Basic Input Output System (BIOS) to boot, since the BMC has already performed the boot operation in parallel according to the power-on signal. Therefore, currently, only controlling the BIOS to boot is needed to complete the server boot process. For a clearer illustration, please refer to Figure 4, which shows a signaling interaction diagram of a server boot operation. The specific steps are as follows:

[0093] S401, Send a power-on signal to the first processor.

[0094] In some embodiments, this step is performed by the power module.

[0095] S402, Perform initialization operation.

[0096] In some embodiments, this step is performed by a first processor after step S401.

[0097] S403, Send a power-on signal to the board management controller.

[0098] In some embodiments, this step is performed by the power module and is performed simultaneously with step S401.

[0099] S404, Perform the startup operation.

[0100] In some embodiments, this step is performed by the substrate management controller, and is performed in parallel with step S402 and after step S403.

[0101] S405, sends a power-on signal to the second processor.

[0102] In some embodiments, this step is performed by the power module and is performed simultaneously with step S401.

[0103] S406. Generate an indication signal and control the indication signal to be sent to the first processor at a first preset time.

[0104] In some embodiments, this step is performed by a second processor after step S405.

[0105] S407. After receiving the indication signal, a power-on signal is sent to the second processor at the second preset time.

[0106] In some embodiments, this step is performed by a first processor after step S406.

[0107] S408, control the server to start the operating system.

[0108] In some embodiments, this step is performed by a second processor after step S407.

[0109] This application provides a server startup method. The method involves sending a power-on signal from a power module to a first processor, a baseboard management controller (BMC), and a second processor. The power-on signal indicates that the server's power module is powered on. The first processor initializes itself based on the power-on signal. The BMC performs a startup operation in parallel based on the power-on signal. The second processor generates an indication signal in parallel based on the power-on signal and sends this signal to the first processor at a first preset time. Finally, the first processor sends a power-on signal to the second processor at a second preset time after receiving the indication signal, and the second processor controls the server to start the operating system. This technical solution uses a CPLD to monitor the power-on timing signals in real time and sets a minimum time interval. This decoupling of the BMC and CPLD during server power-on is achieved, thereby shortening the server startup time.

[0110] Figure 5 shows a flowchart of a server startup method. The server includes a power module, a first processor, a baseboard management controller, and a second processor. Some embodiments of this application are based on the above embodiments, and some embodiments of this application can be combined with various schemes in one or more of the above embodiments. Specifically, please refer to the following steps:

[0111] S501, The power-on signal is sent to the first processor, the baseboard management controller and the second processor through the power module; wherein, the power-on signal is used to indicate that the power module of the server is powered on.

[0112] In some embodiments, this step can refer to the content of step S301, and will not be repeated here.

[0113] S502, The first processor performs an initialization operation based on the power-on signal.

[0114] In some embodiments, this step can refer to the content of step S302, and will not be repeated here.

[0115] S503, The baseboard management controller performs a startup operation in parallel according to the power-on signal.

[0116] In some embodiments, this step can refer to the content of step S303, and will not be repeated here.

[0117] S504. The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the second processor has completed configuration; the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation.

[0118] In some embodiments, this step can refer to the content of step S304, and will not be repeated here.

[0119] S505: After receiving the instruction signal through the first processor, it sends a power-on signal to the second processor and controls the server to start the operating system through the second processor.

[0120] In some embodiments, the time at which the first processor receives the indication signal can be a first preset time, i.e., T1. In some embodiments of this application, the first processor sends a RUN_POWER_EN signal to the second processor at time T3, and controls the server to start the operating system through the second processor. In some embodiments of this application, T3 is a time slightly later than T1.

[0121] In some embodiments, controlling the server to boot the operating system via a second processor includes:

[0122] The second processor controls the startup of the basic input / output system and controls the basic input / output system to perform initialization operations at a third preset time to complete the server's operating system startup; wherein, the third preset time is determined by the time when the second processor receives the power-on signal and the duration of the board management controller's startup operation; wherein, the server includes the basic input / output system.

[0123] In some embodiments, the third preset time is determined by the time the second processor receives the power-on signal and the duration of the startup operation completed by the baseboard management controller, including:

[0124] The third preset time is the time when the second processor receives the power-on signal plus the time taken for the baseboard management controller to complete the startup operation.

[0125] In some embodiments, the moment when the second processor receives the power-on signal is recorded as the moment when the first processor sends the power-on signal, i.e., T3. In some embodiments of this application, the moment when the second processor controls the basic input / output system to start is also T3, that is, the second processor controls the basic input / output system to start immediately upon receiving the power-on signal. The duration for the board management controller to complete the startup operation is F1, and the third preset time is recorded as T4, then T4 = T3 + F1. It is worth noting that if a delay function is set in the basic input / output system, but not at the third preset time, that is, if the delay is not set at this time point, the decoupling function between the first processor and the board management controller cannot be achieved even if a delay is set.

[0126] The reason for this configuration is that the BMC restarts immediately upon power-on after a power outage. However, the BMC's boot function is not yet complete at this time, causing the BIOS to return an error state when initializing PCI (Peripheral Component Interconnect) devices. This leads to the server BIOS boot program crashing, directly causing the server to crash. In some embodiments of this application, setting a delay for F1 ensures that the baseboard management controller completes the boot operation. Therefore, by delaying F1 before the initialization operation during the BIOS boot process, the crash problem can be resolved. For a clearer illustration, please refer to Figure 6, which shows a signaling interaction diagram of a server boot operation. The specific steps are as follows:

[0127] S601, send a power-on signal to the first processor.

[0128] In some embodiments, this step is performed by the power module.

[0129] S602, Perform initialization operation.

[0130] In some embodiments, this step is performed by a first processor after step S601.

[0131] S603, send a power-on signal to the board management controller.

[0132] In some embodiments, this step is performed by the power module and is performed simultaneously with step S601.

[0133] S604, Perform the startup operation.

[0134] In some embodiments, this step is performed by the substrate management controller, and is performed after step S603 and in parallel with step S602.

[0135] S605 sends a power-on signal to the second processor.

[0136] In some embodiments, this step is performed by the power module and is performed simultaneously with step S601.

[0137] S606. Generate an indication signal and control the indication signal to be sent to the first processor at a first preset time.

[0138] In some embodiments, this step is performed by a second processor after step S605.

[0139] S607, after receiving the instruction signal, sends a power-on signal to the second processor.

[0140] In some embodiments, this step is performed by a first processor after step S606.

[0141] S608, controls the start of the basic input / output system.

[0142] In some embodiments, this step is performed by a second processor after step S607.

[0143] S609. Initialization is performed at the third preset time to complete the server's operating system startup.

[0144] In some embodiments, this step is performed by the basic input / output system after step S608.

[0145] In some embodiments, controlling the basic input / output system to perform an initialization operation at a third preset time includes:

[0146] The basic input / output system is controlled to scan the bus, bridge, and devices step by step at a third preset time.

[0147] Read information from the configuration space and allocate resources to the device.

[0148] This application provides a server startup method. The method involves sending a power-on signal from the power module to a first processor, a baseboard management controller (BMC), and a second processor. The power-on signal indicates that the server's power module is powered on. The first processor initializes itself based on the power-on signal. The BMC performs a startup operation in parallel based on the power-on signal. The second processor generates an indication signal in parallel based on the power-on signal and sends it to the first processor at a first preset time. Finally, upon receiving the indication signal, the first processor sends a power-on signal to the second processor, which then controls the server to start the operating system. This technical solution immediately boots the BIOS after the CPLD is powered off and then powered on again, with a delay before the BIOS's PCI enumeration. This ensures that the BMC can complete its basic functions during the U-boot phase, solving the problem of excessive waiting time after a server power outage.

[0149] Figure 7 is a schematic diagram of a server startup operation device provided in some embodiments of this application. This server startup operation device can be understood as the aforementioned electronic device or a portion of its functional modules. As shown in Figure 7, the server startup operation device 70 includes a power module 701, a first processor 702, a baseboard management controller 703, and a second processor 704. The device 70 includes:

[0150] The power module 701 is used to send a power-on signal to the first processor, the baseboard management controller, and the second processor; wherein, the power-on signal is used to indicate that the power module of the server is powered on;

[0151] The first processor 702 is used to initialize the first processor according to the power-on signal;

[0152] The substrate management controller 703 is used to perform a startup operation on the substrate management controller in parallel according to the power-on signal;

[0153] The second processor 704 is used to generate an indication signal in parallel according to the power-on signal, and control the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the second processor has completed configuration; the first preset time is determined by the time when the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0154] The first processor 702 is used to control the server to start the operating system according to the indication signal.

[0155] In some embodiments, the first processor 702 is specifically used for:

[0156] After receiving the indication signal, a power-on signal is sent to the second processor at a second preset time, and the operating system is started by controlling the server through the second processor; wherein, the second preset time is determined by the time when the first processor receives the indication signal and the duration of the board management controller to complete the startup operation.

[0157] In some embodiments, the second preset time is determined by the time the first processor receives the indication signal and the duration for which the substrate management controller completes the startup operation, including:

[0158] The second preset time is the time when the first processor receives the indication signal plus the time value of the duration for the baseboard management controller to complete the startup operation.

[0159] In some embodiments, the first processor 702 is specifically used for:

[0160] The second processor controls the startup of the basic input / output system to complete the server's operating system startup; the server includes the basic input / output system.

[0161] In some embodiments, the first processor 702 is specifically used for:

[0162] After receiving the instruction signal, the first processor sends a power-on signal to the second processor, and the second processor controls the server to start the operating system.

[0163] In some embodiments, the first processor 702 is specifically used for:

[0164] The second processor controls the startup of the basic input / output system and controls the basic input / output system to perform initialization operations at a third preset time to complete the server's operating system startup; wherein, the third preset time is determined by the time when the second processor receives the power-on signal and the duration of the board management controller's startup operation; wherein, the server includes the basic input / output system.

[0165] In some embodiments, the third preset time is determined by the time the second processor receives the power-on signal and the duration of the startup operation completed by the baseboard management controller, including:

[0166] The third preset time is the time when the second processor receives the power-on signal plus the time taken for the baseboard management controller to complete the startup operation.

[0167] In some embodiments, the first processor 702 is specifically used for:

[0168] The basic input / output system is controlled to scan the bus, bridge, and devices step by step at a third preset time.

[0169] Read information from the configuration space and allocate resources to the device.

[0170] In some embodiments, the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation, including:

[0171] The first preset time is the time when the first processor receives the power-on signal plus the time it takes for the first processor to complete the initialization operation.

[0172] In some embodiments, before the power-on signal is sent to the first processor, the substrate management controller, and the second processor via the power module, the device 70 further includes:

[0173] The power module 701 is used to restore power in case of an abnormal power outage.

[0174] In some embodiments, after an abnormal power failure of the power module, the device 70 further includes:

[0175] The power module 701 is used to generate a power-on signal when the power module is detected to be powered on.

[0176] In some embodiments, the device 70 further includes:

[0177] The first processor 702 is used to monitor the power-on signal in real time.

[0178] In some embodiments, the first processor 702 is specifically configured to perform firmware initialization operations in the first processor according to a power-on signal.

[0179] In some embodiments, the first processor 702 is specifically configured to: initialize the memory according to the power-on signal and read the feature control bits;

[0180] The configuration mode is determined based on the characteristic control bits;

[0181] If the bit stream is loaded according to the configuration mode and the preset signal bit is detected as a preset signal, the initialization operation of the first processor is completed.

[0182] In some embodiments, the baseboard management controller 703 is used to initialize the built-in hardware devices in parallel according to the power-on signal;

[0183] The external hardware devices are initialized based on the power-on signal to complete the startup operation of the baseboard management controller.

[0184] In some embodiments, the power module 701 is electrically connected to the first processor 702; the power module 701 is electrically connected to the baseboard management controller 703; the power module 701 is electrically connected to the second processor 704; and the first processor 702 is electrically connected to the second processor 704.

[0185] In some embodiments, the number of servers is multiple.

[0186] For a description of the features in the embodiment corresponding to the server startup operation device, please refer to the relevant description in the embodiment corresponding to the server startup operation method, which will not be repeated here.

[0187] Some embodiments of this application also provide an electronic device, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the server startup operation method embodiments described above. The specific steps are as follows:

[0188] The power-on signal is sent to the first processor, the baseboard management controller, and the second processor via the power module; wherein, the power-on signal is used to indicate that the server's power module is powered on;

[0189] The first processor is initialized according to the power-on signal;

[0190] The baseboard management controller performs a startup operation in parallel based on the power-on signal;

[0191] The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the configuration of the second processor is complete; the first preset time is determined by the time when the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0192] The first processor controls the server to start the operating system according to the instruction signals.

[0193] Some embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described server startup operation method embodiments when it runs, the specific steps of which are as follows:

[0194] The power-on signal is sent to the first processor, the baseboard management controller, and the second processor via the power module; wherein, the power-on signal is used to indicate that the server's power module is powered on;

[0195] The first processor is initialized according to the power-on signal;

[0196] The baseboard management controller performs a startup operation in parallel based on the power-on signal;

[0197] The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the configuration of the second processor is complete; the first preset time is determined by the time when the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0198] The first processor controls the server to start the operating system according to the instruction signals.

[0199] In some embodiments, the aforementioned non-volatile computer-readable storage media may include, but are not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0200] Some embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described server startup method embodiments. The specific steps are as follows:

[0201] The power-on signal is sent to the first processor, the baseboard management controller, and the second processor via the power module; wherein, the power-on signal is used to indicate that the server's power module is powered on;

[0202] The first processor is initialized according to the power-on signal;

[0203] The baseboard management controller performs a startup operation in parallel based on the power-on signal;

[0204] The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the configuration of the second processor is complete; the first preset time is determined by the time when the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0205] The first processor controls the server to start the operating system according to the instruction signals.

[0206] Some embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps in any of the above-described server startup operation method embodiments. The specific steps are as follows:

[0207] The power-on signal is sent to the first processor, the baseboard management controller, and the second processor via the power module; wherein, the power-on signal is used to indicate that the server's power module is powered on;

[0208] The first processor is initialized according to the power-on signal;

[0209] The baseboard management controller performs a startup operation in parallel based on the power-on signal;

[0210] The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is used to indicate that the configuration of the second processor is complete; the first preset time is determined by the time when the first processor receives the power-on signal and the duration of the first processor completing the initialization operation;

[0211] The first processor controls the server to start the operating system according to the instruction signals.

[0212] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0213] The above provides a detailed description of a server startup method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server startup method, characterized in that, The server includes a power module, a first processor, a baseboard management controller, and a second processor. The method includes: The power module sends a power-on signal to the first processor, the baseboard management controller, and the second processor; wherein the power-on signal is configured to indicate that the power module of the server is powered on. The first processor performs an initialization operation based on the power-on signal; The baseboard management controller performs a startup operation in parallel according to the power-on signal; The second processor generates an indication signal in parallel based on the power-on signal and controls the indication signal to be sent to the first processor at a first preset time; wherein, the indication signal is configured to indicate that the second processor has completed configuration; the first preset time is determined by the time the first processor receives the power-on signal and the duration of the first processor completing the initialization operation; The first processor controls the server to start the operating system according to the instruction signal.

2. The server startup method according to claim 1, characterized in that, The step of controlling the server to start the operating system via the first processor according to the indication signal includes: The first processor sends a power-on signal to the second processor at a second preset time after receiving the indication signal, and the second processor controls the server to start the operating system; wherein, the second preset time is determined by the time when the first processor receives the indication signal and the duration of the startup operation completed by the baseboard management controller.

3. The server startup method according to claim 2, characterized in that, The second preset time is determined by the time when the first processor receives the indication signal and the duration for which the baseboard management controller completes the startup operation, including: The second preset time is the time when the first processor receives the indication signal plus the time when the baseboard management controller completes the startup operation.

4. The server startup method according to claim 2, characterized in that, The step of controlling the server to start the operating system via the second processor includes: The second processor controls the startup of the basic input / output system to complete the startup of the operating system on the server; wherein the server includes the basic input / output system.

5. The server startup method according to claim 1, characterized in that, The step of controlling the server to start the operating system via the first processor according to the indication signal includes: After receiving the indication signal, the first processor sends a power-on signal to the second processor, and the second processor controls the server to start the operating system.

6. The server startup method according to claim 5, characterized in that, The step of controlling the server to start the operating system via the second processor includes: The second processor controls the basic input / output system to start and controls the basic input / output system to perform an initialization operation at a third preset time to complete the server's operating system startup; wherein, the third preset time is determined by the time when the second processor receives the power-on signal and the duration of the startup operation completed by the baseboard management controller; wherein, the server includes the basic input / output system.

7. The server startup method according to claim 6, characterized in that, The third preset time is determined by the time when the second processor receives the power-on signal and the duration of the startup operation completed by the baseboard management controller, including: The third preset time is the time when the second processor receives the power-on signal plus the time taken for the baseboard management controller to complete the startup operation.

8. The server startup method according to claim 6, characterized in that, The control of the basic input / output system to perform initialization operations at a third preset time includes: The basic input / output system is controlled to scan the bus, bridge, and devices step by step at a third preset time. Read the information in the configuration space and allocate resources to the device.

9. The server startup method according to claim 1, characterized in that, The first preset time is determined by the moment when the first processor receives the power-on signal and the duration of the initialization operation completed by the first processor, including: The first preset time is the time when the first processor receives the power-on signal plus the time it takes for the first processor to complete the initialization operation.

10. The server startup method according to claim 1, characterized in that, Before sending the power-on signal to the first processor, the substrate management controller, and the second processor via the power module, the method further includes: The power module experienced an abnormal power outage and was subsequently powered back on.

11. The server startup method according to claim 10, characterized in that, After the power module experiences an abnormal power outage, the method further includes: If the power module is detected to be powered on, a power-on signal is generated through the power module.

12. The server startup method according to claim 11, characterized in that, The method further includes: The power-on signal is monitored in real time by the first processor.

13. The server startup method according to claim 1, characterized in that, The initialization operation performed by the first processor according to the power-on signal includes: The first processor initializes the firmware in the first processor according to the power-on signal.

14. The server startup method according to claim 13, characterized in that, The initialization operation of the firmware in the first processor by the first processor according to the power-on signal includes: The first processor initializes the memory according to the power-on signal and reads the feature control bits; The configuration mode is determined by the first processor based on the feature control bits; The initialization operation of the first processor is completed when the first processor loads the bit stream according to the configuration mode and detects that the preset signal bit is the preset signal.

15. The server startup method according to claim 1, characterized in that, The step of performing a startup operation on the baseboard management controller in parallel according to the power-on signal includes: The baseboard management controller initializes the built-in hardware devices in parallel according to the power-on signal; The baseboard management controller initializes the external hardware devices according to the power-on signal, thereby completing the startup operation of the baseboard management controller.

16. The server startup method according to claim 1, characterized in that, The power module is electrically connected to the first processor; the power module is electrically connected to the baseboard management controller; the power module is electrically connected to the second processor; and the first processor is electrically connected to the second processor.

17. The server startup method according to any one of claims 1-16, characterized in that, The number of servers is multiple.

18. An electronic device, characterized in that, include: Memory, configured to store computer programs; The processor is configured to implement the steps of the server startup operation method as described in any one of claims 1 to 17 when executing the computer program.

19. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the server startup operation method as described in any one of claims 1 to 17.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the server startup operation method as described in any one of claims 1 to 17.

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