Direct-current converter and control method therefor

Abstract

A direct-current converter and a control method therefor. The direct-current converter comprises a multilevel conversion circuit, a resonant circuit, a transformer circuit, a rectifier circuit, and a filter capacitor. The multilevel conversion circuit is composed of n same sub-modules and one bridge arm inductor connected in series. The resonant circuit is connected in parallel to two ends of the bridge arm inductor. One pole of a primary side of the transformer circuit is connected to a connection point between the sub-modules and the bridge arm inductor by means of a series branch of the resonant circuit, and the other pole of the primary side of the transformer circuit is configured to be connected to a negative terminal of a first direct-current source. The rectifier circuit is arranged on a secondary side of the transformer circuit.

Description

DC-DC converters and their control methods

[0001] This disclosure claims priority to Chinese Patent Application No. 202510368707.6, filed on March 25, 2025, entitled "DC Converter and Control Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a DC converter and its control method. Background Technology

[0003] DC-DC converters are used to convert DC power to voltage. Multilevel resonant converters consist of a resonant circuit and a level-shifting circuit. The bridge arm of the level-shifting circuit has a DC bias voltage, which needs to be isolated using capacitors in the resonant circuit. When the input voltage of the DC-DC converter is high, the aforementioned DC bias voltage is also high, requiring the selection of capacitors with high rated voltage to successfully isolate the DC bias voltage. This leads to difficulties in capacitor selection and higher costs. Summary of the Invention

[0004] The following is an overview of the detailed description of this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a DC-DC converter, comprising: a multilevel conversion circuit, a resonant circuit, a transformer circuit, a rectifier circuit, and a filter capacitor; the multilevel conversion circuit consists of n identical sub-modules connected in series with a bridge arm inductor; each sub-module includes a sub-module energy storage capacitor, an upper switching transistor, and a lower switching transistor; the multilevel conversion circuit is configured to connect one end of the sub-module to the positive port of a first DC source, and to connect one end of the bridge arm inductor to the negative port of the first DC source; the resonant circuit is connected in parallel across the bridge arm inductor; one pole of the primary side of the transformer circuit is connected to the connection point between the sub-module and the bridge arm inductor via a series branch of the resonant circuit, and the other pole of the primary side of the transformer circuit is configured to connect to the negative port of the first DC source; the secondary side of the transformer circuit is connected to the rectifier circuit; the DC port of the rectifier circuit is connected in parallel with the filter capacitor.

[0006] In some embodiments, the n identical sub-modules in the multilevel conversion circuit described above are configured to perform voltage division processing on the input DC power; the power devices in the sub-modules are configured to convert power and realize positive and negative changes in the output power.

[0007] In some embodiments, the above submodule is a half-bridge submodule or a full-bridge submodule.

[0008] In some embodiments, the half-bridge submodule includes a submodule energy storage capacitor, an upper switch S1, and a lower switch S2; the source of the upper switch S1 and the drain of the lower switch S2 are connected; the negative terminal of the submodule energy storage capacitor is connected to the source of the lower switch S2; the positive terminal of the submodule energy storage capacitor is connected to the drain of the upper switch S1; the upper switch S1 and the lower switch S2 are connected in series and then in parallel with the submodule energy storage capacitor.

[0009] Each half-bridge submodule is connected in series through a first port and a second port. n identical half-bridge submodules are connected in series and then connected to the bridge arm inductor to form a multi-level conversion circuit. The first port is located between the source of the upper switch S1 and the drain of the lower switch S2, and the second port is located between the negative terminal of the energy storage capacitor of the submodule and the source of the lower switch S2; or, the first port is located between the positive terminal of the energy storage capacitor of the submodule and the drain of the upper switch S1, and the second port is located between the source of the upper switch S1 and the drain of the lower switch S2.

[0010] In some embodiments, the full-bridge submodule includes a submodule energy storage capacitor, a first bridge arm upper switch S3, a first bridge arm lower switch S4, a second bridge arm upper switch S5, and a second bridge arm lower switch S6; the branch formed by the series connection of the first bridge arm upper switch S3 and the first bridge arm lower switch S4, and the branch formed by the series connection of the second bridge arm upper switch S5 and the second bridge arm lower switch S6 are all connected in parallel with the submodule energy storage capacitor;

[0011] Each full-bridge submodule is connected in series through a first port and a second port. n identical full-bridge submodules are connected in series and then connected to the bridge arm inductor to form a multi-level conversion circuit. The first port is located between the upper switch S3 and the lower switch S4 of the first bridge arm, and the second port is located between the upper switch S5 and the lower switch S6 of the second bridge arm.

[0012] In some embodiments, the type of the resonant circuit described above is any one of LLC resonant circuit, CLLC resonant circuit, L resonant circuit, and LC resonant circuit.

[0013] In some embodiments, the transformer circuit includes m sub-transformer circuits; wherein, the primary windings of the m sub-transformer circuits are connected in series to form a primary winding, which constitutes the primary side of the transformer circuit; the secondary windings of the m sub-transformer circuits constitute the secondary side of the transformer circuit; each secondary winding is connected to an AC port of a rectifier circuit; and the DC ports of the m rectifier circuits are connected in parallel; or, the single windings of the primary side of the m sub-transformer circuits are connected in series to form the primary side of the transformer circuit; the secondary windings of the m sub-transformer circuits constitute the secondary side of the transformer circuit; each secondary winding is connected to an AC port of a rectifier circuit; and the DC ports of the m rectifier circuits are connected in parallel.

[0014] In some embodiments, the rectifier circuit described above is a full-bridge rectifier circuit; each secondary winding of the transformer circuit corresponds one-to-one with the AC port of the full-bridge rectifier circuit.

[0015] In some embodiments, the switching transistors of the sub-modules and the rectifier circuits described above are fully controllable power semiconductor devices.

[0016] Secondly, this disclosure provides a control method for a DC-DC converter, used to control the aforementioned DC-DC converter. The method includes: detecting the power transmission direction of the DC-DC converter; comparing the current value collected from the DC output side with a preset command value and then performing closed-loop control of a PI regulator to obtain the phase shift angle of the DC output side, so as to control the power magnitude and transmission direction; and performing voltage balance control on the energy storage capacitor of each sub-module in the multi-level conversion circuit based on a capacitor voltage balance algorithm, generating a quasi-two-level drive signal to control the multi-level conversion circuit, and generating a drive signal to control the rectifier circuit, so as to stabilize the output voltage of the DC-DC converter.

[0017] In some embodiments, the step of performing voltage balance control on the energy storage capacitor of each sub-module in the multi-level conversion circuit based on the capacitor voltage balance algorithm includes: detecting the current capacitor voltage of the energy storage capacitor of each sub-module, and detecting the voltage difference between the current capacitor voltage and the historical capacitor voltage at a specified time; sorting multiple sub-modules in descending order of voltage difference to obtain a first order; sorting multiple sub-modules in ascending order of current capacitor voltage to obtain a second order; and for each sub-module in the first order, inputting the drive signal of the sub-module at the first order position to the sub-module at the same order position in the second order.

[0018] In some embodiments, the step of generating a quasi-two-level drive signal to control a multilevel conversion circuit includes: inputting a first drive signal to the multilevel conversion circuit in a DC-DC converter to control the lower switch of a sub-module in the multilevel conversion circuit to be turned on and the upper switch to be turned off; inputting a second drive signal to the multilevel conversion circuit in a DC-DC converter to control the upper switch of a sub-module in the multilevel conversion circuit to be turned on and the lower switch to be turned off; wherein the duty cycle of the second drive signal is 0.5, and the second drive signal and the first drive signal are complementary; adjusting the signal phase of the drive signal input to each sub-module to obtain a quasi-two-level drive signal, so that the signal phases corresponding to at least some sub-modules have a specified phase difference; wherein the drive signal of the sub-module includes at least one of the first drive signal and the second drive signal.

[0019] In some embodiments, the step of comparing the current value collected from the DC output side with a preset command value and then performing closed-loop control by a PI regulator includes: when the difference between the collected current value and the preset command current value is greater than a specified threshold, the resonant circuit generates current waveforms with different components through closed-loop control by the PI regulator, thereby outputting voltages with different gains.

[0020] In some embodiments, the resonant circuit described above transforms the voltage across the bridge arm inductor to make the current waveform sinusoidal, thereby reducing the current stress on the switching transistor; and realizes the phase difference between the voltage waveform and the current waveform, thereby achieving soft switching.

[0021] In some embodiments, when the multilevel converter circuit is detected to be receiving first DC power and the power transmission direction is from the multilevel converter circuit to the rectifier circuit, the following steps are performed: First current on the DC output side is acquired; based on the first current and a preset first command current, a first phase shift angle of the rectifier circuit's drive signal is determined; and a drive signal for the rectifier circuit is generated based on the first phase shift angle. When the rectifier circuit is detected to be receiving second DC power and the power transmission direction is from the rectifier circuit to the multilevel converter circuit, a second current on the DC output side is acquired; based on the second current and a preset second command current, a second phase shift angle of the quasi-two-level drive signal for the multilevel converter circuit is determined; and a quasi-two-level drive signal for the multilevel converter circuit is generated based on the second phase shift angle.

[0022] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings.

[0023] Brief description of the attached figures

[0024] To more clearly illustrate the technical solutions of the specific embodiments of this disclosure, the drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 is a schematic diagram of the topology of a DC-DC converter provided in the related art;

[0026] Figure 2 is a schematic diagram of another DC-DC converter topology provided in the related technology;

[0027] Figure 3 is a schematic diagram of a DC-DC converter provided in an embodiment of this disclosure;

[0028] Figure 4 is a topology diagram of a submodule provided in an embodiment of this disclosure;

[0029] Figure 5 is a topological schematic diagram of a resonant circuit provided in an embodiment of this disclosure;

[0030] Figure 6 is a topology diagram of a combination of transformer circuit and rectifier circuit provided in an embodiment of this disclosure;

[0031] Figure 7 is a schematic diagram of the topology of a DC-DC converter provided in an embodiment of this disclosure;

[0032] Figure 8 is a waveform diagram of a simulation verification result provided in an embodiment of this disclosure;

[0033] Figure 9 is a flowchart of a control method for a DC-DC converter provided in an embodiment of this disclosure;

[0034] Figure 10 is a waveform diagram of a quasi-two-level modulation provided in an embodiment of this disclosure;

[0035] Figure 11 is a schematic diagram of the control logic of a DC-DC converter provided in an embodiment of this disclosure. Embodiments of the present invention

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] DC-DC converters are used to convert DC power to voltage. Multilevel resonant converters consist of a resonant circuit and a level conversion circuit. Currently, modular multilevel converters (MMCs) can be applied to DC-DC converters.

[0038] In one implementation, as shown in the example in Figure 1, a medium-voltage DC-DC converter is achieved by combining a half-bridge resonant circuit and a modular multilevel converter circuit. However, it has medium and high voltage bus capacitors, and the balance of capacitor voltage needs to be considered. In addition, in order to prevent the bus capacitors and the capacitors of the sub-modules in the MMC from being connected in parallel, inductors Lu and Lp need to be added to the bridge arm. This will affect the inductance parameters in the resonant circuit. Therefore, the design of the bridge arm inductors Lu and Lp needs to consider not only DC ripple but also the resonant circuit.

[0039] In summary, this approach introduces a large number of capacitors and inductors, making the design relatively complex.

[0040] In another implementation, as shown in the example in Figure 2, the problem of bridge arm inductance is eliminated by placing the inductor at the input. However, the bridge arm in this method has a DC bias voltage, which needs to be isolated by using capacitors in the resonant circuit.

[0041] When the input voltage of the DC-DC converter is high, the aforementioned DC bias voltage is also high. In order to successfully isolate the DC bias voltage, it is necessary to select capacitors with higher rated voltages. This makes the selection of capacitors difficult and increases costs.

[0042] Based on this, the DC converter and its control method provided in this disclosure can be applied to DC converters to realize DC power conversion.

[0043] To facilitate understanding of this embodiment, a DC-DC converter disclosed in this embodiment will be described in detail first. As shown in Figure 3, the DC-DC converter includes: a multi-level conversion circuit 31, a resonant circuit 32, a transformer circuit 33, a rectifier circuit 34, and a filter capacitor.

[0044] The multilevel converter circuit 31 consists of n identical sub-modules connected in series with a bridge arm inductor, where n can be an integer greater than or equal to 1. Each sub-module includes a sub-module energy storage capacitor, an upper switching transistor, and a lower switching transistor. The multilevel converter circuit 31 is configured to connect one end of the sub-module to the positive port of the first DC source and one end of the bridge arm inductor to the negative port of the first DC source. A resonant circuit 32 is connected in parallel across the bridge arm inductor.

[0045] In the multi-level converter circuit 31, the first DC power input from the first DC source is divided by n identical sub-modules, as shown by SM1 to SMn in Figure 3. These sub-modules can be either a half-bridge or a full-bridge structure. The number of sub-modules can be set according to the input DC voltage level; the higher the input DC voltage level, the more sub-modules are needed; conversely, the lower the input DC voltage level, the fewer sub-modules are needed.

[0046] The aforementioned n identical sub-modules are connected in series and then connected in series with a bridge arm inductor. The resonant circuit 32 is connected in parallel across the bridge arm inductor. In some embodiments, a first DC power is input from a first DC source. After the first DC power passes through the n identical sub-modules, the voltage across the bridge arm inductor is input to the resonant circuit 32. That is, the voltage across the bridge arm inductor is equal to the input voltage of the resonant circuit 32. Since there is no DC bias voltage across the bridge arm inductor, the input voltage of the resonant circuit 32 has no DC bias voltage, which can isolate the DC bias voltage.

[0047] The resonant circuit 32 can be of various types, such as any one of LLC, CLLC, L, or LC resonant circuits. By making the current waveform sinusoidal, the resonant circuit 32 reduces the current stress on the switching transistor and creates a phase difference between the voltage and current, thereby achieving soft switching and reducing device losses. As an impedance network, the resonant circuit 32 can generate current waveforms with different components for voltages at different switching frequencies, thus outputting voltages with different gains.

[0048] One pole of the primary side of transformer circuit 33 is connected to the connection point of the submodule and the bridge arm inductor via a series branch of resonant circuit 32. The other pole of the primary side of transformer circuit 33 is configured to be connected to the negative port of the first DC source. A rectifier circuit 34 is provided on the secondary side of transformer circuit 33, and the DC port of rectifier circuit 34 is connected in parallel with the filter capacitor.

[0049] Specifically, transformer circuit 33 typically includes multiple sub-transformer circuits, the number of which can be related to the number of rectifier circuits 34. The primary winding of transformer circuit 33 employs a multi-winding, single-winding series connection, or a hybrid configuration of multiple windings and single windings in series. The secondary winding of transformer circuit 33 uses a configuration where each secondary winding is connected in parallel with the AC port of one rectifier circuit 34 to meet the requirements of low voltage and high current. The rectifier circuit 34 adopts a full-bridge structure, and the components in the full-bridge structure can be fully controlled to meet the requirements of bidirectional power transmission. A filter capacitor is connected in parallel across the DC port of rectifier circuit 34.

[0050] The aforementioned DC-DC converter includes a multilevel conversion circuit, a resonant circuit, a transformer circuit, a rectifier circuit, and a filter capacitor. The multilevel conversion circuit consists of n identical sub-modules connected in series with a bridge arm inductor. Each sub-module includes a sub-module energy storage capacitor, an upper switching transistor, and a lower switching transistor. One end of the multilevel conversion circuit with the sub-modules in series is configured to connect to the positive port of the first DC source, and one end of the multilevel conversion circuit with the bridge arm inductor is configured to connect to the negative port of the first DC source. The resonant circuit is connected in parallel across the bridge arm inductor. One terminal of the primary side of the transformer circuit is connected to the junction of the sub-modules and the bridge arm inductor via a series branch of the resonant circuit, and the other terminal of the primary side of the transformer circuit is configured to connect to the negative port of the first DC source. A rectifier circuit is provided on the secondary side of the transformer circuit. The DC port of the rectifier circuit is connected in parallel with the filter capacitor. In this method, the voltage is divided by connecting the same sub-modules in series. Multiple identical sub-modules are connected in series with a bridge arm inductor. The voltage across the bridge arm inductor is equal to the input voltage of the resonant circuit. This method can support diverse requirements for capacitor selection, reduce component selection costs, and isolate DC bias voltage.

[0051] In this embodiment, based on the four parts of the multi-level conversion circuit 31—sub-module, resonant circuit 32, transformer circuit 33, and rectifier circuit 34—and the connection relationship between each part, one or more parts can be transformed into different types of topologies to form DC-DC converters with different topologies.

[0052] In one implementation, the n identical sub-modules in the multilevel conversion circuit 31 are configured to perform voltage division processing on the input DC power; the power devices in the sub-modules are configured to convert power and realize positive and negative changes in the output power.

[0053] Specifically, the aforementioned submodules are either half-bridge or full-bridge submodules. The nth submodule includes a first port, a second port, a submodule energy storage capacitor, and two power devices: an upper switching transistor and a lower switching transistor. These power devices can be either insulated bipolar transistors (IBTS) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The number of submodules, submodule energy storage capacitors, half-bridge submodules, and full-bridge submodules is n, where n ≥ 2.

[0054] In one implementation, the aforementioned half-bridge submodule includes a submodule energy storage capacitor, an upper switch S1, and a lower switch S2. The source of the upper switch S1 and the drain of the lower switch S2 are connected; the negative terminal of the submodule energy storage capacitor is connected to the source of the lower switch S2; the positive terminal of the submodule energy storage capacitor is connected to the drain of the upper switch S1; the upper switch S1 and the lower switch S2 are connected in series and then in parallel with the submodule energy storage capacitor.

[0055] In one implementation, the half-bridge submodule adopts the topology shown in Figure 4(a), with a first port between the source of the upper switch S1 and the drain of the lower switch S2, and a second port between the negative terminal of the submodule energy storage capacitor and the source of the lower switch S2; or, the half-bridge submodule adopts the topology shown in Figure 4(b), with a first port between the positive terminal of the submodule energy storage capacitor and the drain of the upper switch S1, and a second port between the source of the upper switch S1 and the drain of the lower switch S2.

[0056] Each half-bridge submodule is connected in series through the first port and the second port. After n identical half-bridge submodules are connected in series, they are connected to the bridge arm inductor to form a multi-level conversion circuit 31.

[0057] In actual implementation, among the n identical half-bridge submodules connected in series, the first port of the first half-bridge submodule is connected to the positive port of the first DC source; the second port of the (k-1)th half-bridge submodule is connected to the first port of the kth half-bridge submodule, where 2≤k≤n; the second port of the nth half-bridge submodule is connected to the bridge arm inductor. With the upper switch S1 on and the lower switch S2 off, or with the upper switch S1 off and the lower switch S2 on, the voltage levels across the bridge arm inductor differ for the two topologies shown in Figure 4(a) and (b).

[0058] In one implementation, as shown in the topology of Figure 4(c), the aforementioned full-bridge submodule includes a submodule energy storage capacitor, a first-arm upper switch S3, a first-arm lower switch S4, a second-arm upper switch S5, and a second-arm lower switch S6. The branch formed by the series connection of the first-arm upper switch S3 and the first-arm lower switch S4, and the branch formed by the series connection of the second-arm upper switch S5 and the second-arm lower switch S6, are both connected in parallel with the submodule energy storage capacitor. A first port is provided between the first-arm upper switch S3 and the first-arm lower switch S4, and a second port is provided between the second-arm upper switch S5 and the second-arm lower switch S6. Each full-bridge submodule is connected in series through the first port and the second port. n identical full-bridge submodules connected in series are then connected to the arm inductors to form a multi-level conversion circuit 31.

[0059] In actual implementation, among the n identical full-bridge submodules connected in series, the first port of the first full-bridge submodule is connected to the positive port of the first DC source; the second port of the (k-1)th full-bridge submodule is connected to the first port of the kth full-bridge submodule, where 2≤k≤n; the second port of the nth full-bridge submodule is connected to the bridge arm inductor.

[0060] The resonant circuit 32 described above can be any one of LLC resonant circuit, CLLC resonant circuit, L resonant circuit and LC resonant circuit.

[0061] In one implementation, the resonant circuit 32 is located on the primary side of the transformer circuit 33. It can be an LLC resonant circuit as shown in Figure 5(a), where the first resonant capacitor Cr and the first leakage inductance Lr form a first series branch and are connected in series with the primary side of the transformer circuit 33, and the first magnetizing inductance Lm is connected in parallel with the primary side of the transformer circuit 33; or, the resonant circuit 32 can be an L resonant circuit as shown in Figure 5(b), where the first leakage inductance Lr is connected in series with the primary side of the transformer circuit 33; or, the resonant circuit 32 can be an LC resonant circuit as shown in Figure 5(c), where the first resonant capacitor Cr and the first leakage inductance Lr form a first series branch and are connected in series with the primary side of the transformer circuit 33.

[0062] In another implementation, the resonant circuit 32 is set on the primary side and the secondary side of the transformer circuit 33, and adopts the CLLC resonant circuit shown in Figure 5(d). The first resonant capacitor Cr and the first leakage inductance Lr form a first series branch and are connected in series with the primary side of the transformer circuit 33, and the second resonant capacitor Cr2 and the second leakage inductance Lr2 form a second series branch and are connected in series with the secondary side of the transformer circuit 33.

[0063] The aforementioned transformer circuit 33 includes m sub-transformer circuits. The primary windings of the m sub-transformer circuits are connected in series to form a single primary winding, which constitutes the primary side of transformer circuit 33. The secondary windings of the m sub-transformer circuits constitute the secondary side of transformer circuit 33. Each secondary winding is connected to an AC port of a rectifier circuit, and the DC ports of the m rectifier circuits are connected in parallel. As shown in Figure 6(a), the primary windings of the sub-transformer circuits are connected in series to form multiple windings, serving as the primary side of transformer circuit 33. The m secondary windings are connected in parallel after passing through rectifier circuits, serving as the secondary side of transformer circuit 33.

[0064] Alternatively, the single windings of the primary side of each of the m sub-transformer circuits are connected in series to form the primary side of transformer circuit 33, and the secondary windings of the m sub-transformer circuits form the secondary side of transformer circuit 33. Each secondary winding is connected to the AC port of a rectifier circuit, and the DC ports of the m rectifier circuits are connected in parallel. As shown in Figure 6(b), the single windings of the primary side of the sub-transformer circuits are connected in series to form the primary side of transformer circuit 33, and the m secondary windings are connected in parallel after passing through the rectifier circuit to form the secondary side of transformer circuit 33.

[0065] The aforementioned rectifier circuit 34 is a full-bridge rectifier circuit. Specifically, each secondary winding of the transformer circuit 33 corresponds one-to-one with the AC port of the full-bridge rectifier circuit.

[0066] As shown in Figure 6(a), the full-bridge rectifier circuit includes four switching transistors: Q1, Q2, Q3, and Q4. Each secondary winding of the transformer circuit 33 corresponds one-to-one with the AC port of the full-bridge rectifier circuit. One pole of each secondary winding is connected to the midpoint of the bridge arm formed by the first switching transistor Q1 and the second switching transistor Q2, and the other pole of each secondary winding is connected to the midpoint of the bridge arm formed by the third switching transistor Q3 and the fourth switching transistor Q4. One pole of the DC port of the full-bridge rectifier circuit is connected to the positive port of the second DC source, and the other pole of the DC port of the full-bridge rectifier circuit is connected to the negative port of the second DC source.

[0067] The switching transistors of the above sub-modules and the switching transistors of the rectifier circuit 34 are all fully controllable power semiconductor devices.

[0068] Fully controllable devices, also known as self-turn-off devices, can be controlled to turn on or off via a drive signal, such as gate turn-off thyristors, power field-effect transistors, and insulated-gate bipolar transistors. The switching transistors in the submodule and rectifier circuit 34 use fully controllable power semiconductor devices, which can be controlled to turn on or off via a drive signal, and are not easily damaged when using high voltage and high current.

[0069] In practical applications, this embodiment can achieve voltage conversion, specifically voltage conversion between medium-high voltage and low voltage, or voltage conversion between low voltages; no limitation is made here. In a specific embodiment, the first DC source is a medium-high voltage DC bus, and the second DC source is a low voltage DC bus, as shown in Figure 7, which illustrates a topology diagram of a DC-DC converter. Figure 7 will be described in detail below:

[0070] In the DC-DC converter shown in Figure 7, the multilevel converter circuit consists of n identical half-bridge sub-modules (SM1 to SMn) connected in series, followed by a bridge arm inductor Lf. Each half-bridge sub-module includes a sub-module energy storage capacitor Cn, an upper switch S1, and a lower switch S2. The resonant circuit is an LLC resonant circuit, the turns ratio of the primary and secondary sides of the transformer circuit is N:1, the rectifier circuit is a full-bridge rectifier circuit, and the filter capacitor Co is connected in parallel across the DC port of the rectifier circuit.

[0071] In Figure 7, assuming the first DC power and drive signal are input from the medium-voltage DC bus, in the first state, the lower switch S2 of the half-bridge submodule is turned on, and the upper switch S1 is turned off. At this time, according to the KVL equation, that is, Kirchhoff's voltage theorem, we can obtain:

[0072] Vin=VLf;

[0073] Where VLf represents the voltage across the bridge arm inductor, and Vin represents the voltage value of the first DC power. The above formula indicates that the voltage across the bridge arm inductor in the DC-DC converter is the same as the voltage value of the first DC power.

[0074] In the second state, the upper switch S1 of the half-bridge submodule is turned on, and the lower switch S2 is turned off. This state is equivalent to the energy storage capacitors of each submodule in the multi-level converter circuit being connected in series with the bridge arm inductor Lf. Assuming the voltages of the energy storage capacitors of each submodule are equal, we can obtain:

[0075] Vin = nVc + VLf;

[0076] Where n represents the number of energy storage capacitors in the submodule, Vc represents the voltage of one energy storage capacitor in the submodule, Vin represents the voltage value of the first DC power, and VLf represents the voltage across the bridge arm inductor.

[0077] Assuming the duty cycle of the drive signal controlling the conduction of switch S2 is D, then the duty cycle of the drive signal controlling the conduction of switch S1 is 1-D, obtained from the volt-second balance:

[0078] ;

[0079] Solving for nVc, we get nVc = Vin / (1-D). With a duty cycle of D of 0.5, the sum of the voltages of the energy storage capacitors in each sub-module of the multilevel converter circuit is twice the voltage value of the first DC energy. Therefore, in the first two states, the bridge arm inductor generates high and low potential voltages of the first DC energy, respectively, which are the input voltages of the resonant circuit.

[0080] Simulation verification of the DC-DC converter shown in Figure 7 yields the main waveforms shown in Figure 8. In Figure 8, (a) shows the current waveform when the current flows through the sub-module string without being shunt. Figure 8 (b) shows the voltage waveform across the bridge arm inductor Lf. Since there is no DC bias voltage across the bridge arm inductor, the input voltage of the resonant circuit has no DC bias voltage. Figure 8 (c) shows the current waveform when the current flows through the bridge arm inductor Lf. Figure 8 (d) shows the current waveform when the current flows through the first leakage inductance Lr in the resonant circuit.

[0081] Furthermore, this embodiment is also applicable to reverse operation, where the main waveforms are the same, meaning that the DC-DC converter has bidirectional operation capability.

[0082] This disclosure also provides a control method for a DC-DC converter, as shown in FIG9. The method can be executed by the control component of the DC-DC converter, and includes the following steps:

[0083] Step S901: Detect the power transmission direction of the DC converter, compare the current value collected from the DC output side with the preset command value, and then obtain the phase shift angle of the DC output side through closed-loop control of the PI (Proportional-Integral) regulator to control the power magnitude and transmission direction.

[0084] Specifically, the system acquires power from either the first or second DC source. After acquiring the DC power input from either source, it detects the power transmission direction of the DC-DC converter. For example, the power transmission direction can be from the multi-level converter circuit to the rectifier circuit, or vice versa. Then, the current value acquired from the DC output side is compared with a preset command value. Through closed-loop control of the PI regulator, the drive signal on the DC input side is kept constant, causing a phase shift in the drive signal on the DC output side relative to the drive signal on the DC input side. Furthermore, if the acquired current value is lower than the preset command value, the gain of the resonant circuit is increased; if the acquired current value exceeds the preset command value, the gain of the resonant circuit is decreased, ensuring that the acquired current value reaches the preset command value, thereby controlling the power magnitude and transmission direction.

[0085] Step S902: Based on the capacitor voltage balancing algorithm, voltage balancing control is performed on the energy storage capacitor of each sub-module in the multi-level conversion circuit to generate a quasi-two-level drive signal to control the multi-level conversion circuit and a drive signal to control the rectifier circuit, so as to stabilize the output voltage of the DC converter.

[0086] First, based on the magnitude of the DC power input to the DC converter, the number of drive signals input to the DC converter is set, and a duty cycle is introduced to achieve soft switching. By detecting the current capacitor voltage of the energy storage capacitor in each submodule and calculating the voltage difference between the current capacitor voltage and the historical capacitor voltage over a preset time interval, the current capacitor voltage and voltage difference are sorted according to preset rules. Drive signals are then redistributed to each submodule, thereby achieving voltage balancing of the energy storage capacitors in the submodules. For two adjacent submodules, quasi-two-level modulation can be used to control the conduction delay time between the switching transistors of the k-th submodule and the (k-1)-th submodule, where 2≤k≤n, generating a quasi-two-level drive signal in the form of a stepped square wave, thus reducing the difficulty of insulation design in the transformer circuit. After obtaining the phase shift angle through the closed-loop control of the PI regulator, a drive signal to control the rectifier circuit is generated by lagging the phase shift angle of the quasi-two-level drive signal in phase, so that the power transmission direction is from the multi-level converter circuit to the rectifier circuit. Alternatively, a drive signal to control the rectifier circuit is generated by leading the phase shift angle of the quasi-two-level drive signal in phase, so that the power transmission direction is from the rectifier circuit to the multi-level converter circuit.

[0087] The aforementioned control method for the DC-DC converter detects the power transmission direction of the DC-DC converter. After comparing the current value collected from the DC output side with a preset command value, it undergoes closed-loop control via a PI regulator to obtain the phase shift angle of the DC output side, thereby controlling the power magnitude and transmission direction. Based on a capacitor voltage balancing algorithm, voltage balancing control is performed on the energy storage capacitors of each sub-module in the multi-level converter circuit. This generates quasi-two-level drive signals to control the multi-level converter circuit and drive signals to control the rectifier circuit, thus stabilizing the DC-DC converter's output voltage. In this method, closed-loop control is performed after collecting the current from the DC output side, while voltage balancing control is applied to the energy storage capacitors of each sub-module, achieving bidirectional power transmission and obtaining a stable output voltage.

[0088] In one implementation, the current capacitor voltage of the energy storage capacitor of each submodule is detected, as well as the voltage difference between the current capacitor voltage and the historical capacitor voltage at a specified time; multiple submodules are sorted in descending order of voltage difference to obtain a first order; multiple submodules are sorted in ascending order of current capacitor voltage to obtain a second order; for each submodule in the first order, the drive signal of the submodule at the first order position is input to the submodule at the same order position in the second order.

[0089] Specifically, the current capacitor voltage of the energy storage capacitor in each submodule is detected, and the voltage difference between the current capacitor voltage and the historical capacitor voltage at a specified time is calculated. This specified time is typically a historical time with a preset time interval from the current time. Then, multiple submodules are sorted in descending order of voltage difference to obtain a first order; simultaneously, multiple submodules are sorted in ascending order of current capacitor voltage to obtain a second order. Based on the first and second orders, the drive signal of the submodule at the first position in the first order is input to the corresponding first position in the second order, and so on, the drive signal of each submodule at each position in the first order is input to the submodule at the same position in the second order.

[0090] In one implementation, a first drive signal is input to the multilevel conversion circuit in the DC-DC converter to control the lower switch of a submodule in the multilevel conversion circuit to turn on and the upper switch to turn off; a second drive signal is input to the multilevel conversion circuit in the DC-DC converter to control the upper switch of a submodule in the multilevel conversion circuit to turn on and the lower switch to turn off; wherein the duty cycle of the second drive signal is 0.5, and the second drive signal and the first drive signal are complementary; the signal phase of the drive signal input to each submodule is adjusted to obtain a quasi-two-level drive signal, so that the signal phases corresponding to at least some submodules have a specified phase difference; wherein the drive signal of the submodule includes at least one of the first drive signal and the second drive signal.

[0091] Taking the DC-DC converter shown in Figure 3 as an example, a first drive signal is input from the first DC source to the multilevel conversion circuit in the DC-DC converter, controlling the lower switch S2 of the half-bridge submodule to turn on and the upper switch S1 to turn off. This first drive signal can continuously cycle in multiple switching cycles to form a working cycle, and the duty cycle of the first drive signal in each switching cycle is 0.5. A second drive signal is input from the first DC source to the multilevel conversion circuit in the DC-DC converter, controlling the lower switch S2 of the half-bridge submodule to turn on and the upper switch S1 to turn off. This second drive signal is complementary to the first drive signal, and both the second drive signal and the first drive signal can be PWM signals with a duty cycle of 0.5.

[0092] After achieving voltage balance of the energy storage capacitors in the submodules, the signal phase of the drive signal input to each submodule is adjusted to obtain a quasi-two-level drive signal. The drive signal of this submodule can be either the first drive signal or the second drive signal, or either the first drive signal or the second drive signal. In practical applications, quasi-two-level modulation is used to control the conduction delay time between the switching transistors of the k-th submodule and the (k-1)-th submodule, where 2≤k≤n, so that a quasi-two-level drive signal in the form of a stepped square wave is generated. As shown in Figure 10, g1, g2, g3, and g4 are PWM signals with a duty cycle of 0.5 for one switching cycle, and Dt is the specified phase difference.

[0093] In one implementation, when the difference between the acquired current value and the preset command current value is greater than a specified threshold, the resonant circuit generates current waveforms with different components through closed-loop control of the PI regulator, thereby outputting voltages with different gains.

[0094] Specifically, after acquiring the current value of the DC output current, it is compared with the preset command current value. Through the closed-loop control of the PI regulator, the phase shift angle can be obtained. If the difference between the acquired current value and the preset command current value is greater than a specified threshold, the gain of the resonant circuit is reduced, the current waveform generated by the resonant circuit is changed, and the operating frequency of the DC converter is increased through closed-loop control.

[0095] Furthermore, the resonant circuit transforms the voltage across the bridge arm inductor, causing the current waveform to exhibit a sinusoidal transformation to reduce the current stress on the switching transistor; it also achieves a phase difference between the voltage waveform and the current waveform, thereby realizing soft switching.

[0096] In actual implementation, after the voltage across the inductor of the bridge arm is input to the resonant circuit, the capacitor in the resonant circuit can buffer the electric field energy, causing the voltage waveform to lag behind the current waveform; the inductor in the resonant circuit can buffer the electromagnetic energy, causing the current waveform to lag behind the voltage waveform, thus making the current waveform sinusoidal, reducing the current stress on the switching transistor. At the same time, it can realize the phase difference between the voltage waveform and the current waveform, thereby achieving soft switching.

[0097] In one implementation, when the first DC power is detected to be input to the multilevel converter circuit and the power transmission direction is from the multilevel converter circuit to the rectifier circuit, the first current on the DC output side is acquired; based on the first current and the preset first command current, the first phase shift angle of the drive signal of the rectifier circuit is determined; and the drive signal of the rectifier circuit is generated based on the first phase shift angle.

[0098] The first command current is typically the current value that the first current needs to be converted to.

[0099] In the example shown in Figure 3, if the first DC power is input from the first DC source, then when the first DC power is detected to be input from the multilevel converter circuit and the power transmission direction is from the multilevel converter circuit to the rectifier circuit, the first current output from the second DC source is collected; then the first current is compared with the preset first command current, and the first phase shift angle of the rectifier circuit drive signal is obtained through closed-loop control. The rectifier circuit drive signal is generated according to the first phase shift angle. For example, the quasi-two-level drive signal of the multilevel converter circuit is kept fixed, and the rectifier circuit drive signal with the first phase shift angle is generated that lags behind the multilevel converter circuit quasi-two-level drive signal.

[0100] The driving signal of the rectifier circuit generates a first phase shift angle relative to the quasi-two-level driving signal of the multi-level converter circuit.

[0101] When the second DC power is detected to be input into the rectifier circuit and the power transmission direction is from the rectifier circuit to the multilevel converter circuit, the second current on the DC output side is collected; based on the second current and the preset second command current, the second phase shift angle of the quasi-two-level drive signal of the multilevel converter circuit is determined; and the quasi-two-level drive signal of the multilevel converter circuit is generated based on the second phase shift angle.

[0102] The second command current is typically the current value that the second current needs to be converted to.

[0103] In the example shown in Figure 3, if a second DC power is input from a second DC source, then when the second DC power is detected to be input into the rectifier circuit and the power transmission direction is from the rectifier circuit to the multilevel converter circuit, the second current output from the first DC source is collected; then the second current is compared with a preset second command current, and the second phase shift angle of the quasi-two-level drive signal is obtained through closed-loop control. The quasi-two-level drive signal of the multilevel converter circuit is generated based on the second phase shift angle. For example, the drive signal of the rectifier circuit is kept constant, and the quasi-two-level drive signal of the multilevel converter circuit, which lags behind the drive signal of the rectifier circuit, is generated as the second phase shift angle.

[0104] In one specific embodiment, as shown in Figure 11, a control logic diagram of a DC-DC converter is illustrated, which will be described in detail below.

[0105] Step S110: Determine whether power is transmitted from the first DC source side to the second DC source side. If power is transmitted from the first DC source side to the second DC source side, proceed to step S111; otherwise, proceed to step S113.

[0106] Step S111: Collect the first current output from the second DC source.

[0107] Step S112, closed-loop control. Specifically, the first current and the preset first command current are compared, and then the first phase shift angle is obtained through closed-loop control. Then proceed to the next step S116.

[0108] Step S113: Determine whether power is transmitted from the second DC source side to the first DC source side. If power is transmitted from the second DC source side to the first DC source side, proceed to step S114; otherwise, end the process.

[0109] Step S114: Collect the second current output from the first DC source.

[0110] Step S115, closed-loop control. Specifically, the second current and the preset second command current are compared, and then the second phase shift angle is obtained through closed-loop control. Then proceed to the next step S116.

[0111] Step S116: Capacitor voltage equalization. Specifically, a capacitor voltage balancing algorithm is used to control the voltage balance of the energy storage capacitors in each sub-module of the multi-level conversion circuit.

[0112] Step S117, Quasi-two-level modulation. Specifically, the signal phase of the drive signal input to each sub-module in the multi-level conversion circuit is adjusted to obtain a quasi-two-level drive signal.

[0113] Step S118: Redistribute the drive signals. Specifically, adjust the signal phase of the drive signals input to each submodule to obtain quasi-two-level drive signals; then, according to the power transmission direction, control the drive signal of the rectifier circuit to generate a first phase shift angle relative to the quasi-two-level drive signal of the multilevel converter circuit, or control the quasi-two-level drive signal of the multilevel converter circuit to generate a second phase shift angle relative to the drive signal of the rectifier circuit; finally, redistribute the drive signals for the multilevel converter circuit and the rectifier circuit.

[0114] The topology of this embodiment, combined with quasi-two-level modulation and capacitor balancing algorithm, can reduce the insulation requirements of the transformer and balance the voltage of the energy storage capacitor of the submodule by exchanging the drive signals of the submodule corresponding to the energy storage capacitor of the submodule.

[0115] This embodiment can achieve a resonant circuit without DC bias voltage, reduce the selection requirements of capacitors in the resonant circuit, and provide more possibilities for capacitor selection when using medium and high voltage input.

[0116] The computer program product provided in this disclosure includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods in the preceding method embodiments. For specific implementation, please refer to the control method embodiments of a DC-DC converter, which will not be repeated here.

[0117] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0118] Furthermore, in the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0119] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0120] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0121] Finally, it should be noted that the above embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

A DC-DC converter includes a multilevel conversion circuit, a resonant circuit, a transformer circuit, a rectifier circuit, and a filter capacitor; The multilevel conversion circuit consists of n identical sub-modules connected in series with a bridge arm inductor; each sub-module includes a sub-module energy storage capacitor, an upper switching transistor, and a lower switching transistor; the multilevel conversion circuit is configured to connect one end of the sub-module to the positive port of a first DC source, and to connect one end of the bridge arm inductor to the negative port of the first DC source; the resonant circuit is connected in parallel across the two ends of the bridge arm inductor; One pole of the primary side of the transformer circuit is connected to the connection point of the submodule and the bridge arm inductor through a series branch of the resonant circuit; the other pole of the primary side of the transformer circuit is configured to be connected to the negative port of the first DC source; the secondary side of the transformer circuit is connected to the rectifier circuit; the DC port of the rectifier circuit is connected in parallel with the filter capacitor. The DC converter of claim 1, wherein In the multi-level conversion circuit, n identical sub-modules are configured to perform voltage division processing on the DC power input from the first DC source; the power devices in the sub-modules are configured to convert power and realize positive and negative changes in the output power. The DC converter of claim 1, wherein The submodule is either a half-bridge submodule or a full-bridge submodule. The DC converter according to claim 3, wherein The half-bridge submodule includes a submodule energy storage capacitor, an upper switch S1, and a lower switch S2; the source of the upper switch S1 and the drain of the lower switch S2 are connected; the negative terminal of the submodule energy storage capacitor is connected to the source of the lower switch S2; the positive terminal of the submodule energy storage capacitor is connected to the drain of the upper switch S1; the upper switch S1 and the lower switch S2 are connected in series and then in parallel with the submodule energy storage capacitor. Each half-bridge submodule is connected in series through a first port and a second port. After n identical half-bridge submodules are connected in series, they are connected to the bridge arm inductor to form the multi-level conversion circuit. The first port is located between the source of the upper switch S1 and the drain of the lower switch S2, and the second port is located between the negative terminal of the energy storage capacitor of the submodule and the source of the lower switch S2. Alternatively, the first port is located between the positive terminal of the energy storage capacitor of the submodule and the drain of the upper switch S1, and the second port is located between the source of the upper switch S1 and the drain of the lower switch S2. The DC converter according to claim 3, wherein The full-bridge submodule includes the submodule energy storage capacitor, a first bridge arm upper switch S3, a first bridge arm lower switch S4, a second bridge arm upper switch S5, and a second bridge arm lower switch S6; the branch formed by the series connection of the first bridge arm upper switch S3 and the first bridge arm lower switch S4, and the branch formed by the series connection of the second bridge arm upper switch S5 and the second bridge arm lower switch S6 are all connected in parallel with the submodule energy storage capacitor. Each of the full-bridge submodules is connected in series through a first port and a second port. After n identical full-bridge submodules are connected in series, they are connected to the bridge arm inductor to form the multi-level conversion circuit. The first port is located between the upper switch S3 and the lower switch S4 of the first bridge arm, and the second port is located between the upper switch S5 and the lower switch S6 of the second bridge arm. The DC converter of claim 1, wherein The type of resonant circuit is any one of LLC resonant circuit, CLLC resonant circuit, L resonant circuit and LC resonant circuit. The DC converter of claim 1, wherein The transformer circuit includes m sub-transformer circuits; The primary windings of m sub-transformer circuits are connected in series to form a primary winding, which forms the primary side of the transformer circuit. The secondary windings of m sub-transformer circuits form the secondary side of the transformer circuit. Each secondary winding is connected to an AC port of a rectifier circuit. The DC ports of m rectifier circuits are connected in parallel. Alternatively, the primary windings of the m sub-transformer circuits are connected in series to form the primary side of the transformer circuit, the secondary windings of the m sub-transformer circuits form the secondary side of the transformer circuit, each secondary winding is connected to an AC port of a rectifier circuit, and the DC ports of the m rectifier circuits are connected in parallel. The DC converter of claim 1, wherein The rectifier circuit is a full-bridge rectifier circuit; each secondary winding of the transformer circuit corresponds one-to-one with the AC port of the full-bridge rectifier circuit. The DC converter of claim 1, wherein The switching transistors of the submodule and the rectifier circuit are both fully controllable power semiconductor devices. A control method for a DC-DC converter, used to control the DC-DC converter as described in any one of claims 1-9; the method includes: The power transmission direction of the DC converter is detected. The current value collected on the DC output side is compared with the preset command value and then controlled by the closed loop of the PI regulator to obtain the phase shift angle of the DC output side, so as to control the power magnitude and transmission direction. Based on the capacitor voltage balancing algorithm, voltage balancing control is performed on the energy storage capacitor of each sub-module in the multi-level converter circuit to generate a quasi-two-level drive signal to control the multi-level converter circuit and a drive signal to control the rectifier circuit, so as to stabilize the output voltage of the DC converter. The control method of the DC converter according to claim 10, wherein The steps for voltage balance control of the energy storage capacitor in each sub-module of the multi-level converter circuit based on the capacitor voltage balance algorithm include: The current capacitor voltage of the energy storage capacitor of each submodule is detected, and the voltage difference between the current capacitor voltage and the historical capacitor voltage at a specified time is detected. The sub-modules are sorted in descending order of voltage difference to obtain a first order; The sub-modules are sorted in ascending order of their current capacitor voltages to obtain a second order; For each submodule at a sequential position in the first sequence, the drive signal of the submodule at that sequential position is input to the submodule at the same sequential position in the second sequence. The control method of the DC converter according to claim 10, wherein The step of generating a quasi-two-level drive signal to control the multilevel conversion circuit includes: A first drive signal is input to the multilevel conversion circuit in the DC-DC converter to control the lower switch of the submodule in the multilevel conversion circuit to be turned on and the upper switch to be turned off. A second drive signal is input to the multilevel conversion circuit in the DC-DC converter to control the upper switch of the submodule in the multilevel conversion circuit to be turned on and the lower switch to be turned off; wherein, the duty cycle of the second drive signal is 0.5, and the second drive signal and the first drive signal are complementary; The signal phase of the drive signal input to each of the sub-modules is adjusted to obtain the quasi-two-level drive signal, so that the signal phase corresponding to at least a portion of the sub-modules has a specified phase difference; wherein, the drive signal of the sub-module includes at least one of the first drive signal and the second drive signal. The control method of the DC converter according to claim 10, wherein The process of comparing the current value acquired from the DC output side with the preset command value and then implementing closed-loop control via a PI regulator includes: If the difference between the acquired current value and the preset command current value is greater than a specified threshold, the resonant circuit generates current waveforms with different components through closed-loop control of the PI regulator, thereby outputting voltages with different gains. The control method for a DC-DC converter according to claim 13, wherein, The resonant circuit transforms the voltage across the bridge arm inductor, making the current waveform sinusoidal to reduce the current stress on the switching transistor. Achieving a phase difference between voltage and current waveforms enables soft switching. The control method for a DC-DC converter according to claim 10, wherein, When the first DC power is detected to be input to the multilevel converter circuit and the power transmission direction is from the multilevel converter circuit to the rectifier circuit, the first current on the DC output side is collected; based on the first current and the preset first command current, the first phase shift angle of the drive signal of the rectifier circuit is determined. The drive signal for the rectifier circuit is generated based on the first phase shift angle; When a second DC power is detected input to the rectifier circuit and the power transmission direction is from the rectifier circuit to the multilevel converter circuit, the second current on the DC output side is collected. Based on the second current and the preset second command current, the second phase shift angle of the quasi-two-level drive signal of the multi-level conversion circuit is determined; The quasi-two-level drive signal of the multi-level conversion circuit is generated based on the second phase shift angle.

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