Stack-up structure for printed circuit board, and printed circuit board

Abstract

Provided in the embodiments of the present disclosure are a stack-up structure for a printed circuit board, and a printed circuit board. The stack-up structure comprises: a signal plane portion, which comprises a signal isolation ground layer and a signal layer, wherein the signal layer and the signal isolation ground layer are stacked one above the other; a power plane portion, which is stacked below the signal plane portion by means of a connection layer, and comprises a pair of power return ground layers and a plurality of power layers arranged between the pair of power return ground layers; a signal via and a signal isolation ground via, which extend from the surface of the signal plane portion away from the power plane portion into the signal plane portion, without extending into the power plane portion; and a plurality of power vias and a plurality of power return ground vias, wherein at least one power via and at least one power return ground via extend from the surface of the signal plane portion away from the power plane portion, pass through the signal plane portion, the connection layer and the power plane portion, and reach the surface of the power plane portion away from the signal plane portion.

Description

Laminate structure for printed circuit boards and printed circuit boards

[0001] This application claims priority to Chinese Patent Application No. 202510376642.X, filed on March 27, 2025, entitled "Layer Structure for Printed Circuit Board and Printed Circuit Board", the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure generally relate to the field of electronic device technology, and more specifically, to a stack-up structure for a printed circuit board and a printed circuit board. Background Technology

[0003] As chip power consumption continues to increase, the maximum continuous current required by the chip also increases, leading to a corresponding increase in transmission loss between the voltage regulator and the chip. Optimizing transmission loss becomes a key area for improving product competitiveness and cost reduction.

[0004] To reduce transmission loss, a common approach is to optimize trace routing and increase the copper thickness of the power layer. However, limited by the size of the voltage regulator and the fan-out requirements of high-speed traces, this approach offers minimal benefits in terms of transmission loss optimization. Another approach is to add copper strips on the back of the printed circuit board using surface mount technology to reduce transmission loss. However, soldering these copper strips carries the risk of misalignment, and the chip backplane needs to be custom-designed by cutting out or increasing its height to accommodate the copper strips, increasing manufacturing complexity. Furthermore, vertical power supply is also an effective way to address transmission loss by mounting the power module on the back of the chip, which shortens the conduction distance. However, this approach lacks maturity, and heat dissipation and power dynamic performance issues can become bottlenecks. Summary of the Invention

[0005] In a first aspect of this disclosure, a stack-up structure for a printed circuit board is provided. The stack-up structure includes: a signal plane portion including a signal isolation ground layer and a signal layer for transmitting signals, the signal layer being stacked with the signal isolation ground layer; a power plane portion stacked with the signal plane portion via a connection layer, and including a pair of power return ground layers and a plurality of power layers disposed between the pair of power return ground layers; signal vias and signal isolation ground vias extending from a surface of the signal plane portion remote from the power plane portion into the signal plane portion, but not extending into the power plane portion; and a plurality of power vias and a plurality of power return ground vias, at least one of the power vias and at least one of the power return ground vias extending from a surface of the signal plane portion remote from the power plane portion, through the signal plane portion, the connection layer, and the power plane portion, into a surface of the power plane portion remote from the signal plane portion.

[0006] In a second aspect of this disclosure, a printed circuit board is provided, including a stacked structure according to a first aspect of this disclosure.

[0007] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0008] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0009] Figure 1 shows a schematic cross-sectional view of a stacked structure for a printed circuit board according to an embodiment of the present disclosure;

[0010] Figure 2A shows a top view of the stacked structure from one side of the signal plane portion;

[0011] Figure 2B shows a top view of the stacked structure from one side of the power plane portion;

[0012] Figures 3A and 3B illustrate exemplary arrangements of the signal plane portion of the stacked structure; and

[0013] Figure 4 shows a schematic cross-sectional view of a laminated structure employing embedded cavity treatment according to an embodiment of the present disclosure;

[0014] Explanation of reference numerals in the attached figures: 100 Stack-up structure; 110 Signal plane portion; 111 Signal isolation ground layer; 112 Signal layer; 120 Power plane portion; 121 Power return ground layer; 122 Power layer; 130 Connector layer; 140 Dielectric layer; 150 Power return ground via; 151 Signal isolation ground via; 160 Power via; 161 Signal via; 170 Capacitor. Detailed Implementation

[0015] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0016] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0017] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0018] As mentioned earlier, with the continuous increase in chip power consumption, the maximum continuous current required by the chip also increases, leading to a corresponding increase in transmission loss between the regulator and the chip. Optimizing transmission loss has become a key area for improving product competitiveness and cost reduction. A common approach to reduce transmission loss is to optimize trace routing and increase the copper thickness of the power layer. However, limited by the size of the regulator and the fan-out requirements of high-speed traces, this approach offers minimal benefits in terms of transmission loss optimization. Another approach is to add copper strips to the back of the printed circuit board using surface mount technology to reduce transmission loss. However, soldering the copper strips carries the risk of soldering misalignment, and the chip backplane needs to be custom-designed by cutting out or increasing its height to accommodate the copper strips, increasing the manufacturing complexity. Furthermore, vertical power supply is also an effective means of addressing transmission loss by mounting the power module on the back of the chip, which can shorten the conduction distance. However, this approach lacks maturity, and heat dissipation and power dynamic performance issues can become bottlenecks.

[0019] To address, or at least partially address, the aforementioned problems or other potential issues of conventional printed circuit board (PCB) solutions, embodiments of this disclosure provide a stack-up scheme for PCBs. In this scheme, by stacking signal plane portions and power plane portions, with at least one power via and at least one power return via penetrating the entire stack-up structure in both the signal plane and power plane portions, while the signal vias and signal isolation vias in the signal plane portion do not extend into the power plane portion, a portion of the copper foil in the power plane is intact, enhancing current conduction capability. Furthermore, since the bottom layer of the signal plane portion is connected to the interconnect layer, the bottom layer becomes an inner layer instead of an outer layer, allowing the bottom layer to be configured as a high-speed signal layer. This further reduces the number of high-speed signal layers within the signal plane portion, achieving a reduced-layer design and significantly reducing product layout complexity. Furthermore, by embedding capacitors in the power plane layer, the need for soldering the bottom layer of the PCB is reduced, while simultaneously improving signal integrity and reliability. Embodiments of this disclosure will now be described with reference to Figures 1 to 4.

[0020] Figure 1 shows a schematic cross-sectional view of a printed circuit board stack-up structure 100 according to some embodiments of the present disclosure. As shown in Figure 1, the stack-up structure 100 described herein generally includes a signal plane portion 110, a power plane portion 120, an interconnect layer 130, signal vias 161, signal isolation ground vias 151, a plurality of power vias 160, and a plurality of power return ground vias 150.

[0021] In some embodiments, as shown in FIG1, the signal plane portion 110 includes a plurality of signal isolation ground layers 111 and a plurality of signal layers 112 for transmitting signals. The plurality of signal layers 112 are stacked with the plurality of signal isolation ground layers 111. In some embodiments, the plurality of signal layers 112 and the plurality of signal isolation ground layers 111 are alternately arranged, with each signal layer 112 spaced apart from adjacent signal isolation ground layers 111 by a dielectric layer 140. In other embodiments, two or more signal isolation ground layers 111 may be provided between adjacent signal layers 112 to ensure signal isolation performance.

[0022] Alternatively, in some embodiments, the signal plane portion 110 may include a single signal isolation ground layer 111 or a single signal layer 112, and the scope of this disclosure is not limited in this respect.

[0023] As shown in Figure 1, the power plane portion 120 includes paired power return ground layers 121 and multiple power layers 122 disposed between the paired power return ground layers 121. The multiple power layers 122 are spaced apart from the paired power return ground layers 121 by dielectric layers 140. Adjacent power layers 122 are also spaced apart from each other by dielectric layers 140.

[0024] As shown in Figure 1, a connecting layer 130 is disposed between the power plane portion 120 and the signal plane portion 110 to join them together, such that the power plane portion 120 and the signal plane portion 110 are stacked on top of each other. The stacked structure 100 is an asymmetrical stacked structure. When the stacked structure 100 is placed in the orientation shown in Figure 1, the signal plane portion 110 is located above the power plane portion 120. It should be understood that when the stacked structure 100 is placed in other orientations, the power plane portion 120 and the signal plane portion 110 may have other relative positional relationships.

[0025] In some embodiments, as shown in FIG1, a single power via 160 and a single power return via 150 extend from the surface of the signal plane portion 110 away from the power plane portion 120, through the signal plane portion 110, the interconnect layer 130, and the power plane portion 120, to the surface of the power plane portion 120 away from the signal plane portion 110. FIG1 only shows a single power via 160 and a single power return via 150 as an example to illustrate the principles of this disclosure. It should be understood that other power vias 160 and power return vias 150 may also have a similar arrangement, i.e., extending from the surface of the signal plane portion 110 away from the power plane portion 120 to the surface of the power plane portion 120 away from the signal plane portion 110. As shown in FIGS. 2A and 2B, in the signal plane portion 110 and the power plane portion 120, a plurality of power vias 160 and a plurality of power return vias 150 are arranged in an array.

[0026] Alternatively or alternatively, in some embodiments, one or more of the plurality of power vias 160 and the plurality of power return vias 150 may extend from the surface of the signal plane portion 110 away from the power plane portion 120 into the power plane portion 120, but not to the surface of the power plane portion 120 away from the signal plane portion 110.

[0027] As shown in Figures 1 to 2B, signal vias 161 and signal isolation vias 151 extend from the surface of the signal plane portion 110 away from the power plane portion 120 into the signal plane portion 110, but do not extend into the power plane portion 120. Figure 1 shows only a single signal via 161 and a single signal isolation via 151 as an example to illustrate the principles of this disclosure. It should be understood that other signal vias 161 and signal isolation vias 151 may also have a similar arrangement, i.e., extending from the surface of the signal plane portion 110 away from the power plane portion 120 into the signal plane portion 110, but not extending into the power plane portion 120. As shown in Figure 2B, only a plurality of power vias 160 and a plurality of power return vias 150 are arranged in an array on the surface of the power plane portion 120 away from the signal plane portion 110, while the signal vias 161 and signal isolation vias 151 do not extend into the surface of the power plane portion 120 away from the signal plane portion 110. This arrangement allows a portion of the copper foil in the power plane section 120 to remain intact, thereby enhancing current conduction capability.

[0028] In some embodiments, as shown in Figures 2A and 2B, there are multiple signal vias 161 and signal isolation ground vias 151. Each power via 160 is disposed adjacent to at least one power return ground via 150, and each signal via 161 is disposed adjacent to at least one signal isolation ground via 151. In this manner, electromagnetic interference can be reduced, and signal integrity and electromagnetic compatibility can be improved.

[0029] In some embodiments, the signal plane portion 110 is formed during a first lamination process, the power plane portion 120 is formed during a second lamination process, and the signal plane portion 110 and the power plane portion 120 are stacked together by a connecting layer 130 during a third lamination process. Signal vias 161 and signal isolation vias 151 are formed in the signal plane portion 110 after the first lamination process and before the third lamination process, and a plurality of power vias 160 and a plurality of power return vias 150 are formed in the signal plane portion 110 and the power plane portion 120 after the third lamination process. By laminating the signal plane portion 110 and the power plane portion 120 separately and then laminating them together a second time, the manufacturing accuracy and reliability of the multilayer stacked structure can be effectively improved, and the processing difficulty can be reduced.

[0030] In some embodiments, as shown in FIG1, there are multiple signal layers 112, and one of the multiple signal layers 112 of the signal plane portion 110 is in contact with the connection layer 130. Alternatively, in other embodiments, one of the multiple signal isolation ground layers 111 of the signal plane portion 110 may be in contact with the connection layer 130.

[0031] In some embodiments, as shown in FIG1, there are multiple signal vias 161 and multiple signal isolation ground vias 151. At least one of the multiple signal vias 161 and at least one of the multiple signal isolation ground vias 151 extend from the surface of the signal plane portion 110 away from the power plane portion 120 to the signal layer 112 of the multiple signal layers 112 that contacts the connection layer 130.

[0032] In some embodiments, the signal layer 112 adjacent to the connection layer 110 among the plurality of signal layers 112 is a high-speed signal layer. High-speed signal lines typically need to be located in the inner layer of the signal plane portion 110, and the number of its layers determines the number of layers in the multilayer stacked structure. By connecting the bottom layer of the signal plane portion 110 to the connection layer 130, the bottom layer is changed from the outer layer to the inner layer, so the bottom layer can be set as a high-speed signal layer. As a result, the number of high-speed signal layers in the signal plane portion 110 can be further reduced, thereby achieving a layer reduction design and significantly reducing the difficulty of product design layout.

[0033] The layer reduction design of the signal plane portion 110 will be further described below with reference to Figures 3A and 3B. Figure 3A shows an example structure of the signal plane portion 110. As shown in Figure 3A, the signal plane portion 110 includes an L1 signal layer, an L2 isolation ground layer, an L3 signal layer, an L4 isolation ground layer, an L5 signal layer, an L6 isolation ground layer, and an L7 signal layer. Since high-speed signal lines usually need to be arranged in the inner layers, the L3 and L5 signal layers can be arranged as high-speed signal layers, with two high-speed signal layers, making the entire signal plane portion 110 a 7-layer structure. Figure 3B shows another example structure of the signal plane portion 110. As shown in Figures 1 and 3B, after the signal plane portion 110 and the power plane portion 120 are pressed together, the L7 signal layer at the bottom of the signal plane portion 110 contacts the connection layer 130, and the L7 signal layer at the bottom changes from the outer layer to the inner layer. Therefore, the L7 signal layer can be arranged as a high-speed signal layer. When two high-speed signal layers are required, the L3 signal layer and the L7 signal layer can be arranged as high-speed signal layers. This can eliminate the need for the L5 signal layer and the L6 isolation ground layer of the signal plane portion 110, thereby achieving a layer reduction design that reduces the number of layers by two.

[0034] In some embodiments, as shown in FIG4, the power plane portion 120 further includes at least one capacitor 170, which is coupled between at least one power return ground layer 121 and an adjacent power layer 122 in a pair of power return ground layers 121. For example, the capacitor 170 is coupled between the power return ground layer 121 at the bottom of the power plane portion 120 and an adjacent power layer 122. One electrode of the capacitor 170 is connected to the power return ground layer 121, and the other electrode is connected to the power layer 122 adjacent to the power return ground layer 121. By embedding capacitors in the power plane layer, the need for soldering on the bottom layer of the printed circuit board is reduced, while signal integrity and reliability are improved.

[0035] In some embodiments, as shown in FIG1, the power plane portion 120 can be a four-layer structure, including two power layers 122 and two power return ground layers 121. As shown in FIG1, one power return ground layer 121 is adjacent to the connection layer 130, and the other power return ground layer 121 is arranged on the side of the power plane portion 120 away from the connection layer 130. With this arrangement, the power return ground layer 121 located at the bottom of the power plane portion 120 can isolate the power layer 122 from electromagnetic interference to the outside world, and the power return ground layer 121 located at the top of the power plane portion 120 can isolate the power layer 122 from interlayer crosstalk to the signal plane portion 110. In other embodiments, more power layers 122 can be provided between the two power return ground layers 121.

[0036] In some embodiments, taking into account power loss, manufacturing cycle and cost, the two power layers 122 in the power plane portion 120 may be designed with thick copper, for example, including 5 oz (ounce) copper foil.

[0037] The stack-up structure for printed circuit boards provided in this disclosure significantly optimizes transmission loss compared to conventional stack-up structures, for example, reducing it by 30%. For instance, for a core voltage of 1V, the transmission loss of the stack-up structure in this disclosure can be optimized by 30-40W.

[0038] Embodiments of this disclosure are also embodied in the following examples.

[0039] Example 1. A stacked structure for a printed circuit board, comprising:

[0040] The signal plane portion includes a signal isolation ground layer and a signal layer for transmitting signals, wherein the signal layer and the signal isolation ground layer are stacked together.

[0041] The power plane portion is superimposed on the signal plane portion via a connection layer, and includes a pair of power return ground layers and a plurality of power layers disposed between the pair of power return ground layers;

[0042] Signal vias and signal isolation vias, the signal vias and the signal isolation vias extending from a surface of the signal plane portion away from the power plane portion into the signal plane portion, but not extending into the power plane portion; and

[0043] Multiple power vias and multiple power return vias, at least one of the power vias and at least one of the power return vias extending from a surface of the signal plane portion away from the power plane portion, through the signal plane portion, the interconnect layer and the power plane portion, to a surface of the power plane portion away from the signal plane portion.

[0044] Example 2. According to the stacked structure described in Example 1, wherein there are multiple signal vias and multiple signal isolation ground vias, each power via is disposed adjacent to at least one power return ground via, and each signal via is disposed adjacent to at least one signal isolation ground via.

[0045] Example 3. According to the stacked structure described in Example 1, wherein the signal plane portion is formed in a first lamination process, the power plane portion is formed in a second lamination process, and the signal plane portion and the power plane portion are stacked together by the connecting layer in a third lamination process, and

[0046] The signal vias and signal isolation vias are formed in the signal plane portion after the first pressing process and before the third pressing process, and the plurality of power vias and plurality of power return vias are formed in the signal plane portion and the power plane portion after the third pressing process.

[0047] Example 4. The stacked structure according to Example 1, wherein there are multiple signal layers, and one of the multiple signal layers is in contact with the connection layer.

[0048] Example 5. According to the stacked structure of Example 4, wherein there are multiple signal vias and multiple signal isolation ground vias, and at least one of the multiple signal vias and at least one of the multiple signal isolation ground vias extends from the surface of the signal plane portion away from the power plane portion to the signal layer of the multiple signal layers that contacts the connection layer.

[0049] Example 6. According to the stacked structure described in Example 5, the signal layer adjacent to the connection layer among the plurality of signal layers is a high-speed signal layer.

[0050] Example 7. According to the stacked structure of Example 1, wherein the power plane portion further includes at least one capacitor coupled between at least one power return ground in the pair of power return grounds and an adjacent power ground.

[0051] Example 8. The stacked structure according to Example 1, wherein the power layer comprises 5 oz of copper foil.

[0052] Example 9. The stacked structure according to Example 1, wherein the power plane portion comprises two power layers.

[0053] Example 10. A printed circuit board comprising a stacked structure according to any one of Examples 1-9.

[0054] Various implementations of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A multilayer structure (100) for a printed circuit board, comprising: The signal plane portion (110) includes a signal isolation ground layer (111) and a signal layer (112) for transmitting signals, wherein the signal layer (112) and the signal isolation ground layer (111) are stacked together; The power plane portion (120) is superimposed on the signal plane portion (110) via a connection layer (130) and includes a pair of power return ground layers (121) and a plurality of power layers (122) disposed between the pair of power return ground layers (121). Signal via (161) and signal isolation via (151) extend from the surface of the signal plane portion (110) away from the power plane portion (120) into the signal plane portion (110) and do not extend into the power plane portion (120); as well as Multiple power vias (160) and multiple power return vias (150), at least one of the power vias (160) and at least one of the power return vias (150) extend from the surface of the signal plane portion (110) away from the power plane portion (120), through the signal plane portion (110), the connection layer (130) and the power plane portion (120), to the surface of the power plane portion (120) away from the signal plane portion (110).

2. The stacked structure (100) according to claim 1, wherein there are multiple signal vias (161) and signal isolation ground vias (151), each power via (160) is disposed adjacent to at least one power return ground via (150), and each signal via (161) is disposed adjacent to at least one signal isolation ground via (151).

3. The stacked structure (100) according to claim 1, wherein the signal plane portion (110) is formed in a first pressing process, the power plane portion (120) is formed in a second pressing process, and the signal plane portion (110) and the power plane portion (120) are stacked together through the connecting layer (130) in a third pressing process, and The signal via (161) and the signal isolation via (151) are formed in the signal plane portion (110) after the first pressing process and before the third pressing process, and the plurality of power vias (160) and the plurality of power return vias (150) are formed in the signal plane portion (110) and the power plane portion (120) after the third pressing process.

4. The stacked structure (100) according to claim 1, wherein there are multiple signal layers (112), and one of the multiple signal layers (112) is in contact with the connection layer (130).

5. The stacked structure (100) according to claim 4, wherein there are multiple signal vias (161) and multiple signal isolation ground vias (151), and at least one of the multiple signal vias (161) and at least one of the multiple signal isolation ground vias (151) extends from the surface of the signal plane portion (110) away from the power plane portion (120) to the signal layer (112) of the multiple signal layers (112) that contacts the connection layer (130).

6. The stacked structure (100) according to claim 5, wherein the signal layer (112) adjacent to the connection layer (110) among the plurality of signal layers (112) is a high-speed signal layer.

7. The stacked structure (100) according to claim 1, wherein the power plane portion (120) further includes at least one capacitor (170), the at least one capacitor (170) being coupled between at least one power return ground layer (121) in the paired power return ground layers (121) and an adjacent power layer (122).

8. The stacked structure (100) according to claim 1, wherein the power layer (122) comprises 5 oz copper foil.

9. The stacked structure (100) according to claim 1, wherein the power plane portion (120) comprises two power layers (122).

10. A printed circuit board comprising a stacked structure (100) according to any one of claims 1-9.

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