Semiconductor device and manufacturing method therefor

Abstract

Provided in the embodiments of the present disclosure are a semiconductor device and a manufacturing method therefor, which at least facilitate an improvement in the reliability of semiconductor devices. The semiconductor device comprises: active portions, a word line structure, an electrically conductive shielding portion, a bit line structure and a capacitor structure, wherein the plurality of active portions are sequentially arranged at intervals in a first direction, and a first spacing area or a second spacing area is provided between every two adjacent active portions in the first direction; each active portion comprises a first doped area, a channel area and a second doped area, which are distributed in sequence in a second direction; the word line structure extends in a third direction and is located on the side of the channel areas facing the first spacing areas; the electrically conductive shielding portion extends in the third direction and is located in the second spacing areas and spaced apart from the active portions; the bit line structure extends in the first direction and is in electrical contact with the first doped areas of the plurality of active portions; and the capacitor structure extends in the second direction and is in electrical contact with the second doped areas of the active portions.

Description

Semiconductor devices and their manufacturing methods

[0001] This application claims priority to Chinese Patent Application No. 202510363124.4, filed on March 24, 2025, entitled "Semiconductor Device and Method of Manufacturing Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random-Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0004] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The word line of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor for storage through the bit line.

[0005] Currently, the reliability of semiconductor structures needs to be improved. Summary of the Invention

[0006] This disclosure provides a semiconductor device and a method for manufacturing the same, which at least helps to improve the reliability of the semiconductor device.

[0007] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor device, including: a plurality of active portions arranged sequentially at intervals along a first direction, with a first interval region or a second interval region between adjacent active portions along the first direction, the first interval region and the second interval region being located on opposite sides of the same active portion along the first direction, the active portion including a first doped region, a channel region and a second doped region sequentially distributed along a second direction; a word line structure located on the side of the channel region facing the first interval region and extending along a third direction; a conductive shielding portion located in the second interval region and spaced from the active portions, the conductive shielding portion extending along a third direction, and at least partially facing the word line structure in the first direction; a bit line structure extending along the first direction and electrically contacting the first doped regions of the plurality of active portions; and a capacitor structure extending along the second direction and electrically contacting the second doped regions of the active portions.

[0008] In some embodiments, the width of the second interval region is smaller than the width of the first interval region along the first direction.

[0009] In some embodiments, the word line structure includes: a word line conductive portion located on one side of the channel region toward the first spacing region, and the word line conductive portion extending along a second direction; a gate dielectric layer located at least between the channel region and the word line conductive portion; wherein, along the first direction, the thickness of the word line conductive portion is greater than or equal to the thickness of the conductive shielding portion.

[0010] In some embodiments, the orthographic projection of the word line structure onto the reference plane lies within the orthographic projection of the conductive shield onto the reference plane, wherein the reference plane is a plane perpendicular to the first direction.

[0011] The dimension of the conductive shielding portion in the second direction is larger than the dimension of the word line conductive portion in the second direction.

[0012] In some embodiments, the material of the conductive shield is the same as the material of the word line conductive portion.

[0013] In some embodiments, the material of the conductive shielding portion includes TiN, TaN, Cu, Al, or W.

[0014] In some embodiments, the resistivity of the material of the conductive shield is greater than or equal to the resistivity of the material of the word line conductive portion.

[0015] In some embodiments, the thickness of the conductive shielding portion is 5nm to 15nm.

[0016] In some embodiments, the spacing between the conductive shield and the adjacent active portion is the same along the first direction.

[0017] In some embodiments, the conductive shield is grounded.

[0018] In some embodiments, the conductive shield is connected to a voltage.

[0019] In some embodiments, the lower electrode layer of the capacitor structure is cylindrical or columnar.

[0020] In some embodiments, the lower electrode layer of the capacitor structure includes a first horizontal U-shaped portion and a second horizontal U-shaped portion with opposite opening orientations, wherein the first horizontal U-shaped portion covers the end of the second doped region, the U-shaped bottom wall of the second horizontal U-shaped portion is shared with the U-shaped bottom wall of the first horizontal U-shaped portion, and the second horizontal U-shaped portion extends in the opposite direction to the first horizontal U-shaped portion.

[0021] In some embodiments, the semiconductor device further includes: a substrate, a plurality of active portions located on the substrate, and a bottom active portion spaced apart from the substrate, wherein the bottom active portion is the active portion closest to the substrate along a first direction, and the bit line structure and the capacitor structure further extend into the substrate; and a conductive shielding portion is located between the bottom active portion and the substrate.

[0022] In some embodiments, the semiconductor device includes active portions arranged at intervals along a second direction, and in the second direction, second doped regions of adjacent active portions face each other, and the capacitor structures corresponding to the facing second doped regions share an upper electrode layer.

[0023] In some embodiments, the semiconductor device further includes: an isolation layer filling a first spacer region and a second spacer region, wherein a second doped region is recessed relative to the isolation layer located on opposite sides of the second doped region, and the isolation layer exposes the end of the second doped region; the capacitor structure includes: a lower electrode layer covering the surface of the end of the second doped region exposed by the isolation layer, and also covering the surface of the isolation layer facing the active portion, wherein the lower electrode layers corresponding to adjacent second doped regions along a first direction are disconnected from each other; a capacitor dielectric layer located on the surface of the lower electrode layer and also located on the side of the isolation layer, the capacitor dielectric layer forming a hollow annulus extending along the first direction to form a groove; an upper electrode layer located on the surface of the capacitor dielectric layer; and a conductive filling layer located on the surface of the upper electrode layer and filling the groove.

[0024] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate, on which a plurality of semiconductor layers are formed at intervals along a first direction, adjacent semiconductor layers having a first spacer region or a second spacer region, the first spacer region and the second spacer region being located on opposite sides of the same semiconductor layer along the first direction, and the semiconductor layers having capacitor holes and bit line holes arranged at intervals along a second direction and extending in the first direction, the semiconductor layer between the capacitor holes and the bit line holes including a first doped region, a channel region and a second doped region arranged at intervals along the second direction; forming a conductive screen. The conductive shielding portion is located in the second spacer region, and the conductive shielding portion is at least partially opposite and spaced from the channel region; the semiconductor layer is etched to form mutually separated active portions, the active portions including a first doped region, a channel region and a second doped region sequentially distributed along a second direction; a word line structure is formed, the word line structure is located on the surface of the channel region facing the first spacer region and extends along a third direction; a bit line structure is formed in a bit line hole, the bit line structure extends along a first direction and is electrically contacted with the first doped region of the plurality of active portions; a capacitor structure is formed in a capacitor hole, the capacitor structure extends along a second direction and is electrically contacted with the second doped region of the active portion.

[0025] In some embodiments, the width of the second spacing region is smaller than the width of the first spacing region along the first direction; the process steps for forming the conductive shielding portion include: forming a first isolation layer, the first isolation layer being located on the surface of the semiconductor layer facing the first spacing region and the surface facing the second spacing region, and after forming the first isolation layer, a first gap is formed between the first isolation layers facing each other in the first spacing region, and a second gap is formed between the first isolation layers facing each other in the second spacing region, and the width of the first gap is greater than the width of the second gap along the first direction; forming an initial conductive layer that fills the first gap and the second gap; using a wet process to etch away the initial conductive layer located in the first gap; performing lateral etching on the initial conductive layer located in the second gap to etch away a portion of the initial conductive layer adjacent to the capacitor hole and bit line hole, and the remaining initial conductive layer being used to form the conductive shielding portion.

[0026] In some embodiments, forming an initial conductive layer that fills the first gap and the second gap includes: forming a conductive metal layer that fills the first gap, the second gap, the bit line via, and the capacitor via; removing the conductive metal layer located in the bit line via and the capacitor via, and removing the conductive metal layer located on the sidewall of the first isolation layer facing the bit line via and the sidewall facing the capacitor via, with the remaining conductive metal layer serving as the initial conductive layer; and performing lateral etching on the initial conductive layer located in the second gap, including: performing a first lateral etching on the sidewall of the initial conductive layer facing the bit line via and the sidewall facing the capacitor via; and after performing the first lateral etching, performing a second lateral etching on the sidewall of the initial conductive layer facing the capacitor via, with the remaining initial conductive layer serving as a conductive shield.

[0027] Another aspect of this disclosure provides an electronic device, including: a processor; and

[0028] A memory, wherein the memory is coupled to the processor, and at least one of the memory and the processor includes a semiconductor memory according to any embodiment of the present disclosure.

[0029] The technical solutions provided in this disclosure have at least the following advantages:

[0030] In the semiconductor device provided in this embodiment, a first spacing region or a second spacing region is provided between adjacent active portions along a first direction. The word line structure is located on the surface of the channel region facing the first spacing region. Conductive shielding portions are spaced apart on the side of the channel region of the active portion facing the second spacing region. Thus, in the first spacing region between adjacent active portions, the word line structures corresponding to different active portions can mutually shield each other to avoid a gate effect between the word line structures of one active portion and another active portion. In the second spacing region between adjacent active portions, the conductive shielding portions can shield to avoid a gate effect between the word line structures of one active portion and another active portion, thereby improving the reliability of the semiconductor device. Multiple active transistors are arranged at intervals along a first direction and a third direction. A capacitor structure is electrically contacted with the second doped region of the active transistors to form a memory cell. The spatial array arrangement of multiple memory cells improves space utilization. A word line structure extends along a third direction, and multiple transistor structures arranged along this direction share the same word line structure, thereby improving the control capability of the word line structure. A bit line structure extends along the first direction, and multiple transistors arranged along this direction share the same bit line structure, thereby improving the efficiency of the bit line structure. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0033] Figure 2 is a schematic diagram of the cross-sectional structure along the AA1 direction in Figure 1;

[0034] Figures 3 to 9 are schematic diagrams of the various steps of a semiconductor device manufacturing method provided in the embodiments of this disclosure.

[0035] Figure 10 is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure.

[0036] Explanation of reference numerals in the attached figures:

[0037] X, First direction; Y, Second direction; Z, Third direction; I, First doped region; II, Second doped region; III, Channel region; 100, Substrate; 101, Active part; 102, Word line structure; 1021, Gate dielectric layer; 1022, Word line conductive part; 103, Conductive shielding part; 104, Bit line structure; 105, Capacitor structure; 115, Lower electrode layer; 125, Capacitor dielectric layer; 135, Upper electrode layer; 145, Conductive filling layer; 111, First spacer region; 113, First isolation layer; 112, Second spacer region; 123, Second isolation layer; 200, Isolation layer; 201, Semiconductor layer; 202, First part; 203, Second part; 204, Bit line via; 205, Capacitor via. Embodiments of the present invention

[0038] As can be seen from the background technology, the reliability of semiconductor devices needs to be improved.

[0039] With the increasing demand for high performance and low cost in semiconductor devices, higher requirements are being placed on the integration density of semiconductor devices. 3D Dynamic Random Access Memory (3D DRAM) architecture stacks memory cells to achieve higher throughput per unit wafer area. Compared to ordinary planar DRAM architecture, 3D DRAM architecture can effectively reduce the unit cost of DRAM.

[0040] In current 3D DRAM architectures, word lines typically surround the channel region of the active area to form a gate-ring structure, which improves the control capability of the word lines. However, gate-ring structures are more difficult to manufacture, and because the stacked active areas are close together, the word lines corresponding to different active areas are even closer together, leading to greater coupling effects between adjacent word lines. Reducing the thickness of the word lines in the gate-ring structure can easily result in higher resistance, leading to significant delays in the semiconductor device and affecting read / write performance. Setting the word lines to only one side of the active area to form a single-gate structure can improve the size of the word lines while reducing manufacturing complexity, but the problem of a passing gate effect between the active area and the word lines of adjacent active areas still exists, resulting in lower reliability of the semiconductor device.

[0041] This disclosure provides a semiconductor device and its manufacturing method. In the semiconductor device, multiple active portions are stacked along a first direction. Adjacent active portions are separated by a first or second spacer. Word line structures are located on the surface of the channel region of the active portions near the first spacer. A conductive shield is provided in the second spacer region between adjacent active portions to isolate the active portions from the corresponding word line structures of another adjacent active portion, thus preventing a gate effect between the active portions and adjacent word line structures. Having the word line structure located on one side of the active portions along the first direction can help increase the size of the word line structure, reduce its resistance, thereby reducing the delay of the semiconductor device and improving read / write speeds. Furthermore, a one-sided word line structure helps reduce manufacturing complexity.

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0043] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 2 is a schematic cross-sectional view of Figure 1 along the AA1 direction.

[0044] Referring to Figures 1 and 2, the semiconductor device includes: an active part 101, a word line structure 102, a conductive shielding part 103, a bit line structure 104, and a capacitor structure 105.

[0045] Multiple active portions 101 are arranged sequentially at intervals along a first direction X. Adjacent active portions 101 along the first direction X have a first interval region 111 or a second interval region 112. The first interval region 111 and the second interval region 112 are respectively located on opposite sides of the same active portion 101 along the first direction X. The active portion 101 includes a first doped region I, a channel region III and a second doped region II distributed sequentially along the second direction Y.

[0046] The word line structure 102 is located on the side of the channel region III facing the first interval region 111, and the word line structure 102 extends along the third direction Z.

[0047] The conductive shielding portion 103 is located in the second interval region 121 and is spaced apart from the active portion 101. The conductive shielding portion 103 extends along the third direction Z, and in the first direction X, the conductive shielding portion 103 is at least partially opposite to the word line structure 102.

[0048] Bit line structure 104 extends along the first direction X and is in electrical contact with the first doped region I of the plurality of active parts 101.

[0049] The capacitor structure 105 extends along the second direction Y and is in electrical contact with the second doped region II of the active part 101.

[0050] In the semiconductor device provided in this embodiment, a first spacing region 111 or a second spacing region 112 is provided between adjacent active portions 101 along the first direction X. The word line structure 102 is located on the side surface of the channel region III facing the first spacing region 111. The conductive shielding portion 103 is spaced apart on the side of the channel region III of the active portion 101 facing the second spacing region 121. Thus, in the first spacing region 111 between adjacent active portions 101, the word line structures 102 corresponding to different active portions 101 can play a mutual shielding role to avoid the generation of a threshold effect between the active portion 101 and the word line structure 102 of another active portion 101. In the second spacing region 121 between adjacent active portions 101, the conductive shielding portion 103 can play a shielding role to avoid the generation of a threshold effect between the active portion 101 and the word line structure 102 of another active portion 101, thereby improving the reliability of the semiconductor device. Multiple active units 101 are arranged at intervals along the first direction X and the third direction Z. The capacitor structure 105 is electrically contacted with the second doped region II of the active units 101 to form a memory cell. The multiple memory cells arranged in a spatial array are beneficial to improving space utilization. The word line structure 102 extends along the third direction Z, and the multiple transistor structures arranged along the third direction Z share the same word line structure 102 to improve the control capability of the word line structure 102. The bit line structure 104 extends along the first direction X, and the multiple transistors arranged along the first direction X share the same bit line structure 104 to improve the efficiency of the bit line structure 104.

[0051] In some embodiments, the conductive shield 103 can be short-circuited, i.e., grounded, to serve as a shield; in other embodiments, the conductive shield 103 can also be subjected to a voltage to serve as a back gate, thereby adjusting the threshold voltage of the transistor structure.

[0052] The active part 101 may be made of semiconductor materials such as silicon, gallium arsenide, silicon carbide, or gallium nitride. The active part 101 may also be made of at least one of IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide), or ITO (indium tin oxide).

[0053] Referring to FIG1, in some embodiments, the width of the second spacing region 121 along the first direction X is smaller than the width of the first spacing region 111. This allows the conductive shielding portion 103 to effectively suppress the gate effect between the active portion 101 and the word line structure 102 corresponding to another adjacent active portion 101, while providing more space for the word line structure 102, thereby reducing the resistance of the word line structure 102 and improving the transmission efficiency of the semiconductor device.

[0054] In some embodiments, the word line structure includes: a word line conductive portion 1022, located on the side of the channel region III facing the first spacing region 110, and extending along the second direction Y; a gate dielectric layer 1021, located at least between the channel region III and the word line conductive portion 1022; wherein the thickness of the word line conductive portion 1022 is greater than or equal to the thickness of the conductive shielding portion 103. Thus, the conductive shielding portion 103 occupies a smaller size along the first direction X. While satisfying the requirement to suppress the gate effect, the size of the word line conductive portion 1022 is maximized to reduce the resistance of the word line structure 102, thereby improving the reliability of the transistor structure while reducing the size of the semiconductor device.

[0055] In some embodiments, the gate dielectric layer 1021 is also located on the surface of the first doped region I facing the first spacer region 110. During the formation of the gate dielectric layer 1021, the gate dielectric layer 1021 covers the surface of the first doped region I and the channel region III of the active portion 101. After the word line conductive portion 1022 is formed, only the word line conductive portion 1022 of the first doped region I can be removed, while the gate dielectric layer 1021 of the first doped region I is retained, thus eliminating a process step and improving the manufacturing efficiency of the semiconductor device.

[0056] The material of the word line conductive part 1022 includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0057] The material of the gate dielectric layer 1021 includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof. For example, the gate dielectric layer 1021 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON, etc.

[0058] The material of the conductive shielding part 103 includes at least one of TiN, TaN, Cu, Al or W.

[0059] The material of the conductive shield 103 can be the same as the material of the word line conductive portion. This allows the conductive shield 103 to be formed using the same process as the word line conductive portion, thereby improving the manufacturing efficiency of the semiconductor device. In other embodiments, the material of the conductive shield 103 can be different from the material of the word line conductive portion.

[0060] In some embodiments, the resistivity of the material of the conductive shield 103 is greater than or equal to the resistivity of the material of the word line conductive portion. This allows the conductive shield 103 to provide sufficient shielding while reducing the material cost of the conductive shield 103.

[0061] In some embodiments, the orthographic projection of the word line structure 102 onto the reference plane may lie within the orthographic projection of the conductive shielding portion 103 onto the reference plane, wherein the reference plane is a plane perpendicular to the first direction X. This helps ensure that the conductive shielding portion 103 provides sufficient shielding for the word line structure 102.

[0062] As shown in FIG1, in some embodiments, the dimension of the conductive shielding portion 103 in the second direction Y is larger than the dimension of the word line conductive portion 1022 in the second direction Y.

[0063] Along the first direction X, the thickness of the conductive shielding portion 103 can be 5nm to 15nm, specifically 5nm, 8nm, 10nm, 11nm, 13nm, 14nm, or 15nm. The size of the conductive shielding portion 103 is within this range, which allows it to occupy as little space as possible while still providing sufficient shielding effectiveness, thereby improving the integration density of the semiconductor device.

[0064] In some embodiments, the spacing between the conductive shielding portion 103 and the adjacent active portion 101 is the same along the first direction X, which facilitates the control of process parameters. In the actual manufacturing process of semiconductor devices, process errors may exist, so the spacing between the conductive shielding portion 103 and the adjacent active portion 101 may be different.

[0065] The semiconductor device may further include: a substrate 100, a plurality of active portions 101 located on the substrate 100, and the active portions 101 of the bottom layer spaced apart from the substrate 100, wherein the active portions 101 of the bottom layer are the active portions 101 closest to the substrate 100 along the first direction X, and the bit line structure 104 and the capacitor structure 105 extend into the substrate 100; a conductive shielding portion 103 is also located between the active portions 101 of the bottom layer and the substrate 100. The fact that the bit line structure 104 and the capacitor structure 105 extend into the substrate 100 can help reduce the precision of the process dimensions and facilitate the improvement of the process dimension tolerance; the conductive shielding portion 103 is also located between the active portions 101 of the bottom layer and the substrate 100, so that the conductive shielding portion 103 can shield the active portions 101 from the substrate 100, or when a voltage is applied to the conductive shielding portion 103, it can act as a back gate for the active portions 101 of the bottom layer, thereby adjusting the threshold voltage of the transistor structure of the bottom layer.

[0066] The substrate 100 can be a semiconductor substrate, including silicon substrates, silicon germanium substrates, gallium arsenide substrates, silicon carbide substrates, or gallium nitride substrates, etc.

[0067] The material of the bit line structure 104 can be a single metal, a metal compound, or an alloy. Among them, the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound can be tungsten nitride, tantalum nitride, or titanium nitride; and the alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0068] It should be noted that other structures in the semiconductor device are hidden in Figures 1 and 2 for clarity. In some embodiments, the semiconductor device may further include: an isolation layer 200, which fills the first spacer region 111 and the second spacer region 121; a second doped region II is recessed relative to the isolation layer 200 located on opposite sides of the second doped region II along the first direction X, and the isolation layer 200 exposes the end of the second doped region II. The recess of the second doped region II relative to the isolation layer 200 located on opposite sides of the second doped region II along the first direction X allows the lower electrode layer to have a larger area, which is beneficial to increasing the charge storage capacity of the capacitor structure 105.

[0069] The material of the isolation layer 200 includes silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0070] The capacitor structure may include: a lower electrode layer, which covers the surface of the exposed end of the second doped region of the isolation layer and also covers the surface of the isolation layer facing the active portion, wherein the lower electrode layers corresponding to adjacent second doped regions along a first direction are disconnected from each other; a capacitor dielectric layer, which is located on the surface of the lower electrode layer and also on the side of the isolation layer, and the capacitor dielectric layer forms a hollow annulus extending along the first direction to form a groove; an upper electrode layer, which is located on the surface of the capacitor dielectric layer; and a conductive filling layer, which is located on the surface of the upper electrode layer and fills the groove. The lower electrode layers in the capacitor structures corresponding to different active portions are disconnected from each other, and the upper electrode layers are shared, thus improving the space utilization and charge storage capacity of the capacitor structure.

[0071] In some embodiments, the lower electrode layer may be disposed around the end of the second doped region, thereby increasing the contact area between the lower electrode layer and the second doped region and improving the transport efficiency between the lower electrode layer and the second doped region.

[0072] The material of the lower electrode layer includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0073] The materials for the capacitor dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0074] The material of the upper electrode layer includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0075] The materials for the conductive filler layer include copper, silver, gold, tungsten, tin, or lead.

[0076] In some embodiments, the lower electrode layer may be a U-shaped structure, and the upper electrode layer is located inside the U-shaped structure of the lower electrode layer; in other embodiments, the upper electrode layer may be a U-shaped structure, and the lower electrode layer is located inside the U-shaped structure of the upper electrode layer.

[0077] In some embodiments, the semiconductor device includes active portions 101 spaced apart along the second direction Y, and second doped regions II of adjacent active portions 101 are directly opposite each other along the second direction Y. The capacitor structures 105 corresponding to the directly opposite second doped regions II share the same upper electrode layer, which can further improve the space utilization of the semiconductor device along the second direction Y and the charge storage capability of the capacitor structure 105.

[0078] In Figure 1, two sets of active portions 101 are arranged along the second direction Y as an example; in other embodiments, multiple sets of active portions may be arranged along the second direction, and adjacent sets of active portions may share the upper electrode layer of the capacitor structure or share the bit line.

[0079] In the semiconductor device provided in this embodiment, a first spacing region 111 or a second spacing region 112 is provided between adjacent active portions 101 along the first direction X. The word line structure 102 is located on the side surface of the channel region III facing the first spacing region 111. The conductive shielding portion 103 is spaced apart on the side of the channel region III of the active portion 101 facing the second spacing region 121. Thus, in the first spacing region 111 between adjacent active portions 101, the word line structures 102 corresponding to different active portions 101 can play a mutual shielding role to avoid the generation of a threshold effect between the active portion 101 and the word line structure 102 of another active portion 101. In the second spacing region 121 between adjacent active portions 101, the conductive shielding portion 103 can play a shielding role to avoid the generation of a threshold effect between the active portion 101 and the word line structure 102 of another active portion 101, thereby improving the reliability of the semiconductor device. Multiple active units 101 are arranged at intervals along the first direction X and the third direction Z. The capacitor structure 105 is electrically contacted with the second doped region II of the active units 101 to form a memory cell. The multiple memory cells arranged in a spatial array are beneficial to improving space utilization. The word line structure 102 extends along the third direction Z, and the multiple transistor structures arranged along the third direction Z share the same word line structure 102 to improve the control capability of the word line structure 102. The bit line structure 104 extends along the first direction X, and the multiple transistors arranged along the first direction X share the same bit line structure 104 to improve the efficiency of the bit line structure 104.

[0080] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, which can be used to form the aforementioned semiconductor device to improve its performance. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0081] Figures 3 to 9 are schematic diagrams of the various steps of a semiconductor device manufacturing method provided in this embodiment. The semiconductor structure manufacturing method provided in this embodiment will be described in detail below with reference to the accompanying drawings. Among them, Figures 4 to 8 are schematic diagrams along the BB1 ​​and CC1 directions of Figure 3; Figure 9 is a partially enlarged schematic diagram of the structure corresponding to the dashed box S in Figure 8.

[0082] Referring to Figures 3 to 9, a method for manufacturing a semiconductor device includes:

[0083] Referring to Figures 3 and 4, a substrate 100 is provided, on which a plurality of semiconductor layers 201 are formed at intervals along a first direction X. A first spacer region 111 or a second spacer region 121 is provided between adjacent semiconductor layers 201. The first spacer region 111 and the second spacer region 121 are located on opposite sides of the same semiconductor layer 201 along the first direction X. The semiconductor layer 201 has capacitor holes 205 and bit line holes 204 arranged at intervals along a second direction Y and extending in the first direction X. The semiconductor layer 201 between the capacitor holes 205 and the bit line holes 204 includes a first doped region I, a channel region III and a second doped region III arranged at intervals along the second direction Y.

[0084] Specifically, the steps of providing a substrate 100 and forming semiconductor layers 201 include: forming alternating layers of initial sacrificial layers and initial semiconductor layers on the substrate 100, wherein the thicknesses of the initial sacrificial layers on opposite sides of the same initial semiconductor layer are different; and patterning the initial sacrificial layers and initial semiconductor layers in the thickness direction of the substrate 100 to form a plurality of semiconductor layers 201 including a first portion 202 extending along a second direction Y and a second portion 203 extending along a third direction Z, wherein the width of the first portion 202 in the third direction Z is greater than that of the second portion 203. 03. Fill the patterned area with insulating material along the width of the second direction Y; pattern the semiconductor layer 201 and the initial sacrificial layer along the thickness direction of the substrate 100 to form a capacitor hole 205 and a bit line hole 204. The capacitor hole 205 is located in the first portion 202 of the semiconductor layer 201 and between the two second portions 203. The bit line hole 204 is located in the first portion 202 of the semiconductor layer 201 and on the side of the second portion 203 away from the capacitor hole 205; remove the initial sacrificial layer based on the capacitor hole 205 and the bit line hole 204.

[0085] The initial sacrificial layer material includes one of silicon, germanium, silicon germanide, silicon carbide, and gallium arsenide. The insulating material includes silicon oxide, silicon nitride, or silicon oxynitride.

[0086] Referring to Figures 5A to 5F, a conductive shielding portion 103 is formed, which is located in the second interval region 121. The conductive shielding portion 103 is at least partially opposite to and spaced apart from the channel region III.

[0087] Based on the different initial sacrificial layer thicknesses of the semiconductor layer 201 on both sides along the first direction X in the aforementioned process steps, the width of the second spacing region 121 is smaller than the width of the first spacing region 111 along the first direction X; the process steps for forming the conductive shielding portion 103 include: forming a first isolation layer 113, the first isolation layer 113 being located on the surface of the semiconductor layer 201 facing the first spacing region 111 and the surface facing the second spacing region 121, and after forming the first isolation layer 113, a first gap 1111 is formed between the first isolation layers 113 facing each other in the first spacing region 111, and a first gap 1111 is formed between the first isolation layers 113 facing each other in the second spacing region 121. A second gap 1211 is formed between the first isolation layers 113, and the width W1 of the first gap is greater than the width W2 of the second gap along the first direction X; initial conductive layers 103b and 103c are formed to fill the first gap 1111 and the second gap 1211; the initial conductive layer 103b located in the first gap 1111 is removed by etching using a wet process; the initial conductive layer 103c located in the second gap 1211 is laterally etched to remove part of the initial conductive layer adjacent to the capacitor hole 205 and the bit line hole 204, and the remaining initial conductive layer is used to form the conductive shielding part 103.

[0088] Since the width W1 of the first slit is greater than the width W2 of the second slit, the first slit 1111 is more conducive to the entry of the etching solution. During the wet etching process to remove the initial conductive layer 103c located in the first slit 1111, the etching rate of the initial conductive layer 103b in the first slit 1111 is faster than the etching rate of the initial conductive layer 103c in the second slit 1211. By controlling the wet etching time, the initial conductive layer 103b in the first slit 1111 can be removed more quickly, while the initial conductive layer 103c in the second slit 1211 is retained. Furthermore, during the lateral etching of the initial conductive layer 103c located in the second slit 1211, the time of the etching solution in the capacitor hole 205 or the bit line hole 204 can be controlled respectively, so that the remaining initial conductive layer 103c in the second slit 1211 serves as a conductive shield, and the position of the conductive shield 103 is directly opposite the position of the channel region III.

[0089] Please refer to Figures 5B to 5D. The specific steps for forming the initial conductive layers 103b and 103c that fill the first gap 1111 and the second gap 1211 include: forming a conductive metal layer 103a, which fills the first gap 1111, the second gap 1211, the bit line hole 204, and the capacitor hole 205; removing the conductive metal layer 103a located in the bit line hole 204 and the capacitor hole 205, and removing the conductive metal layer 103a located on the sidewall of the first isolation layer 113 facing the bit line hole 205 and the sidewall facing the capacitor hole 204, with the remaining conductive metal layer serving as the initial conductive layers 103b and 103c. Since the widths of the first gap 1111 and the second gap 1211 are different, in order to fill the second gap 1211 with the initial conductive layer 103c, the first gap 1111, the second gap 1211, the bit line hole 204 and the capacitor hole 2005 can be filled first, and then the conductive metal layer 103a in the capacitor hole 205, the bit line hole 204 and the first gap 1111 can be gradually removed, so that the initial conductive layer 103c in the second gap 1211 is retained.

[0090] Referring to Figures 5E to 5F, the specific steps for lateral etching of the initial conductive layer 103c located within the second slot 1211 include: performing a first lateral etching on the sidewalls of the initial conductive layer 103c facing the bit line hole 204 and the capacitor hole 205; after performing the first lateral etching, performing a second lateral etching on the sidewalls of the initial conductive layer 103c facing the capacitor hole, with the remaining initial conductive layer serving as a conductive shielding portion. In other words, the initial conductive layer in the second slot is first etched to the same length using the first lateral etching, and then a portion of the initial conductive layer near the capacitor hole is etched using the second lateral etching, thereby aligning the remaining initial conductive layer with the channel region of the active portion.

[0091] Referring again to FIG. 5F, after forming the conductive shielding portion 103, the process includes: forming a second isolation layer 123, which is located on the surface of the semiconductor layer 201 facing the first spacer region 111. The specific steps are as follows: filling the capacitor hole 205, bit line hole 204, the first gap (excluding the conductive shielding portion 103), and the second gap with insulating material; removing the insulating material from the capacitor hole 205 and bit line hole 204, then removing the insulating material from the first gap, and finally removing the first isolation layer on the surface of the semiconductor layer 201 facing the first spacer region 111; forming the second isolation layer 123, which covers the surface of the semiconductor layer 201 facing the first spacer region 111. Because the width of the first gap is greater than the width of the second gap, the etching solution in the second gap is difficult to enter during the removal of the insulating material in the first gap. By controlling the etching time, the insulating material in the first spacer region and the first isolation layer can be removed, while a large amount of the insulating material in the second isolation region and the first isolation layer are retained.

[0092] In other embodiments, the sacrificial layer materials on the two sides of the semiconductor layer along the first direction can be different to facilitate the selective etching of the first spacer region and the second spacer region in stages, and the second isolation layer and the first isolation layer and the conductive shielding portion can be formed in the second spacer region respectively.

[0093] Referring to FIG6, the semiconductor layer 201 is etched to form mutually discrete active regions 101. The active regions 101 include a first doped region I, a channel region III, and a second doped region II distributed sequentially along the second direction Y.

[0094] Specifically, the etching process for the semiconductor layer 201 includes: removing insulating material along the thickness direction of the substrate 100 to expose the sidewalls of the semiconductor layer 201; performing lateral etching on the sidewalls of the semiconductor layer 201, with the remaining semiconductor layer 201 serving as the active portion 101; and then refilling with insulating material. Referring to Figures 3 and 6, since the width of the first portion 202 of the semiconductor layer 201 along the third direction Z is greater than the width of the second portion 203 along the second direction Y, during the lateral etching of the sidewalls of the semiconductor layer 201, the second portion 203 between the first portions 202 is etched more quickly, and the first portion 202 becomes narrower after etching, with the remaining first portion 202 serving as the active portion 101.

[0095] In other embodiments, the width of the first portion of the semiconductor layer in the third direction may be less than or equal to the width of the second portion in the second direction. During the patterning process of the insulating material in the thickness direction of the substrate, only the two sidewalls of the second portion between the first portions in the second direction may be exposed. After etching the second portion between the first portions, the semiconductor layer is spaced apart in the third direction, thereby making the remaining first portion an active portion.

[0096] Referring to FIG7, a word line structure 102 is formed, which is located on the surface of the channel region III facing the first spacer region 111 and extends along the third direction Z; a bit line structure 104 is formed in the bit line hole 204, which extends along the first direction X and is in electrical contact with the first doped region I of the plurality of active parts 101.

[0097] Specifically, the steps of forming the word line structure 102 and the bit line structure 104 include: removing the insulating material in the bit line hole 204; removing the second isolation layer 123 based on the bit line hole 204 to expose the surfaces of the first doped region I and the channel region III facing the first spacer region 111; forming an initial word line structure that covers the surfaces of the first doped region I and the channel region III facing the first spacer region 111; performing back etching on the initial word line structure to remove the initial word line structure on the surface of the first doped region I facing the first spacer region 111, with the initial word line structure on the surface of the channel region III facing the first spacer region 111 serving as the word line structure 102; filling the surface of the first doped region I facing the first spacer region 111 with insulating material; etching the insulating material on the sidewall of the bit line hole 204 to expose the surface of the active portion 101 facing the bit line hole 204; and forming the bit line structure 104 within the bit line hole 204.

[0098] In the steps of forming word line structure 102 and bit line structure 104, capacitor hole 205 is filled with insulating material to occupy the position of the capacitor structure to be formed subsequently.

[0099] In some embodiments, after removing the second isolation layer 123 based on the bit line hole 204 to expose the surfaces of the first doped region I and the channel region III facing the first spacer region 111, the method further includes: removing a portion of the thickness of insulating material in the first spacer region 111, which allows the subsequently formed word line structure 102 to be larger in size, which is beneficial to reducing the resistance of the word line structure 102 and improving the transmission efficiency of the semiconductor device.

[0100] Referring to Figure 8, a capacitor structure 105 is formed in the capacitor hole 205. The capacitor structure 105 extends along the second direction Y and is in electrical contact with the second doped region II of the active part 101.

[0101] Specifically, referring to Figures 8 and 9, the specific steps for forming the capacitor structure 105 include: removing the insulating material from the capacitor hole 205 to expose the surface of the second doped region II of the active portion 101 facing the capacitor hole 205; performing lateral etching on the second doped region II to make the insulating material, the first isolation layer 113, and the second isolation layer 123 in the first spacer region 111 and the second spacer region 121 on opposite sides of the second doped region II along the first direction X recessed inward; forming an initial lower electrode layer, the initial lower electrode layer covering the capacitor... The inner wall of the capacitor hole 205 and the surface of the second doped region II of the active part 101 are formed; a portion of the initial lower electrode layer of the inner wall of the capacitor hole 205 is removed along the first direction X, and the remaining initial lower electrode layer is used as the lower electrode layer 115; a capacitor dielectric layer 125 is formed, which covers the inner wall of the capacitor hole 205 and the surface of the lower electrode layer 115; an upper electrode layer 135 is formed, which covers the surface of the capacitor dielectric layer 125; a conductive filling layer 145 is formed, which covers the surface of the upper electrode layer 135 and fills the capacitor hole 205.

[0102] Referring to Figures 8 and 9, during the lateral etching of the second doped region II, the surface of the second doped region II facing the capacitor hole 205 protrudes in the direction of the capacitor hole 205, thereby increasing the contact area between the subsequently formed lower electrode layer 115 and the second doped region II, which is beneficial to improving the transmission efficiency between the active part 101 and the capacitor structure 105.

[0103] Referring back to FIG1 and continuing to FIG9, in some embodiments, the lower electrode layer 115 of the capacitor structure 105 includes a first horizontal U-shaped portion and a second horizontal U-shaped portion with opposite opening orientations. The first horizontal U-shaped portion covers the end of the second doped region II, and the U-shaped bottom wall of the second horizontal U-shaped portion is shared with the U-shaped bottom wall of the first horizontal U-shaped portion. The second horizontal U-shaped portion extends in opposite directions to the first horizontal U-shaped portion. Both the first and second U-shaped portions extend in the second direction Y. The opening of the first horizontal U-shaped portion faces the bit line hole 104, and the opening of the second U-shaped portion faces the capacitor hole 105. The extension dimension of the first horizontal U-shaped portion in the second direction Y is smaller than that of the second horizontal U-shaped portion in the second direction Y. In the first direction X, the dimensions of the first horizontal U-shaped portion and the second U-shaped portion are the same.

[0104] Referring again to Figures 1 and 9, in the first direction X, the top surface of the first U-shaped portion does not exceed the top surface of the channel region III in the active portion 101. In this embodiment, by recessing the size of the second doped region II in the first direction X, the size is narrowed, allowing the first horizontal U-shaped portion to cover the end of the second doped region II without exceeding the overall height of the active portion 101, thus avoiding adverse effects.

[0105] In other embodiments, the step of forming the capacitor structure includes: removing a first isolation layer and a second isolation layer on both sides of the semiconductor layer in a first direction to expose a second doped region of the semiconductor layer; forming a lower electrode layer that covers the surface of the second doped region and the inner wall of the capacitor hole, and removing the lower electrode on the inner wall of the capacitor hole to disconnect the lower electrode layers on the second doped regions of different semiconductor layers from each other; forming a capacitor dielectric layer that covers the surface of the lower electrode layer and the inner wall of the capacitor hole; forming an upper electrode layer that covers the surface of the capacitor dielectric layer; and forming a conductive filling layer that covers the surface of the upper electrode layer and fills the capacitor hole.

[0106] The first isolation layer 113, the second isolation layer 123, and the insulating material filled between the active part 101, the word line structure 102, the bit line structure 104, the capacitor structure 105, and the conductive shielding part 103 serve as the isolation layers in the above embodiments.

[0107] The semiconductor structure manufacturing method provided in this disclosure includes forming a plurality of active portions 101 spaced apart along a first direction X and a third direction Z. A capacitor structure 105 is electrically contacted with the second doped region II of the active portions 101 to form a memory cell. The spatial array arrangement of the plurality of memory cells is beneficial to improving space utilization. The formed word line structure 102 extends along the third direction Z, and the plurality of transistor structures arranged along the third direction Z share the same word line structure 102 to improve the control capability of the word line structure 102. The formed bit line structure 104 extends along the first direction X, and the plurality of transistors arranged along the first direction X share the same bit line structure 104 to improve the efficiency of the bit line structure 104. A first spacing region 111 or a second spacing region 112 is provided between adjacent active portions 101 along the first direction X. The word line structure 102 is located on the surface of the channel region III facing the first spacing region 111. The conductive shielding portion 103 is spaced apart on the side of the channel region III of the active portion 101 facing the second spacing region 121. In this way, within the first spacing region 111 between adjacent active portions 101, the word line structures 102 corresponding to different active portions 101 can play a mutual shielding role to avoid the generation of a threshold effect between the active portion 101 and the word line structure 102 of another active portion 101. Within the second spacing region 121 between adjacent active portions 101, the conductive shielding portion 103 can play a shielding role to avoid the generation of a threshold effect between the active portion 101 and the word line structure 102 of another active portion 101, thereby improving the reliability of the semiconductor device.

[0108] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A plurality of active portions (101) are arranged at intervals along a first direction (X). Adjacent active portions (101) along the first direction (X) have a first interval region (111) or a second interval region (121). The first interval region (111) and the second interval region (121) are respectively located on opposite sides of the same active portion (101) along the first direction (X). The active portion (101) includes a first doped region (I), a channel region (III), and a second doped region (II) arranged sequentially along a second direction (Y). A character line structure (102) is located on the side of the channel region (III) facing the first interval region (111), and the character line structure (102) extends in the third direction (Z); A conductive shielding portion (103) is located in the second interval region (121) and spaced apart from the active portion (101). The conductive shielding portion (103) extends along the third direction (Z) and is at least partially opposite to the word line structure (102) in the first direction (X). Bit line structure (104) extends along the first direction (X) and is in electrical contact with the first doped region (I) of the plurality of active portions (101); A capacitor structure (105) extends along the second direction (Y) and is in electrical contact with the second doped region (II) of the active portion (101).

2. The semiconductor device according to claim 1, characterized in that, Along the first direction (X), the width of the second interval (121) is smaller than the width of the first interval (111).

3. The semiconductor device according to claim 1, characterized in that, The word line structure includes: A word line conductive portion (1022) is located on the side of the channel region (III) facing the first interval region (111), and the word line conductive portion (1022) extends along the second direction (Y); A gate dielectric layer (1021) is located at least between the channel region (III) and the word line conductive portion (1022); Wherein, along the first direction (X), the thickness of the word line conductive portion (1022) is greater than or equal to the thickness of the conductive shield portion (103).

4. The semiconductor device according to claim 3, characterized in that, The orthographic projection of the word line structure (102) on the reference plane is located within the orthographic projection of the conductive shielding part (103) on the reference plane, wherein the reference plane is a plane perpendicular to the first direction (X).

5. The semiconductor device according to claim 3, characterized in that, The size of the conductive shielding part (103) in the second direction (Y) is larger than the size of the word line conductive part (1022) in the second direction (Y).

6. The semiconductor device according to any one of claims 3 to 5, characterized in that, The material of the conductive shielding part (103) is the same as the material of the word line conductive part (1022).

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The material of the conductive shielding part (103) includes TiN, TaN, Cu, Al or W.

8. The semiconductor device according to any one of claims 3 to 7, characterized in that, The resistivity of the material of the conductive shield (103) is greater than or equal to the resistivity of the material of the word line conductive part (1022).

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The thickness of the conductive shielding part (103) is 5nm~15nm.

10. The semiconductor device according to claim 1, characterized in that, Along the first direction (X), the distance between the conductive shield (103) and the adjacent active part (101) is the same.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A substrate (100) is provided, and a plurality of said active portions (101) are located on the substrate (100), and the bottom active portions (101) are spaced apart from the substrate (100), wherein the bottom active portion (100) is the active portion (101) closest to the substrate (100) along the first direction (X), and the bit line structure (104) and the capacitor structure (105) also extend into the substrate; The conductive shielding part (103) is also located between the bottom active part (101) and the substrate (100).

12. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes active portions (101) spaced apart along the second direction (Y), and the second doped regions (II) of adjacent active portions (101) face each other along the second direction (Y), and the capacitor structures (105) corresponding to the facing second doped regions (II) share an upper electrode layer (135, 145).

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: An isolation layer is filled in the first spacer region (111) and the second spacer region (121), the second doped region (II) is recessed relative to the isolation layer located on opposite sides of the second doped region (II), and the isolation layer exposes the end of the second doped region (II); The capacitor structure (105) includes: The lower electrode layer (115) covers the surface of the end of the second doped region (II) exposed by the isolation layer, and also covers the surface of the isolation layer facing the active part (101), wherein the lower electrode layers (115) corresponding to adjacent second doped regions (II) along the first direction (X) are disconnected from each other. A capacitor dielectric layer (125) is located on the surface of the lower electrode layer (115) and also on the side of the isolation layer. The capacitor dielectric layer (125) forms a hollow annulus extending along the first direction to form a groove. An upper electrode layer (135) is located on the surface of the capacitor dielectric layer (125); A conductive filler layer (145) is located on the surface of the upper electrode layer (135) and fills the groove.

14. The semiconductor device according to claim 1, characterized in that, The conductive shielding part is grounded.

15. The semiconductor device according to claim 1, characterized in that, The conductive shielding part is connected to a voltage.

16. The semiconductor device according to claim 1, characterized in that, The lower electrode layer of the capacitor structure includes a first horizontal U-shaped portion and a second horizontal U-shaped portion with opposite opening orientations. The first horizontal U-shaped portion covers the end of the second doped region. The U-shaped bottom wall of the second horizontal U-shaped portion is shared with the U-shaped bottom wall of the first horizontal U-shaped portion. The second horizontal U-shaped portion extends in the opposite direction to the first horizontal U-shaped portion.

17. A method for manufacturing a semiconductor device, characterized in that, include: A substrate (100) is provided on which a plurality of semiconductor layers (201) are formed at intervals along a first direction (X). A first spacer region (111) or a second spacer region (121) is provided between adjacent semiconductor layers (201). The first spacer region (111) and the second spacer region (121) are located on opposite sides of the same semiconductor layer (201) along the first direction (X). The semiconductor layer (201) has capacitor holes (205) and bit line holes (204) arranged at intervals along a second direction (Y) and extending in the first direction (X). The semiconductor layer (201) located between the capacitor holes (205) and the bit line holes (204) includes a first doped region (I), a channel region (III) and a second doped region (II) arranged at intervals along the second direction (Y). A conductive shielding portion (103) is formed, the conductive shielding portion (103) is located in the second interval region (101), and the conductive shielding portion (103) is at least partially opposite and spaced apart from the channel region (III); The semiconductor layer (201) is etched to form mutually separated active regions (101), the active regions (101) including a first doped region (I), a channel region (III) and a second doped region (II) sequentially distributed along the second direction (Y). A character line structure (102) is formed, the character line structure (102) is located on the surface of the channel region (III) facing the first interval region (111), and the character line structure (102) extends in the third direction (Z); A bit line structure (105) is formed within the bit line hole (205), the bit line structure (105) extends along a first direction (X) and is in electrical contact with the first doped region (I) of the plurality of active portions (101); A capacitor structure (104) is formed within the capacitor hole (204), the capacitor structure (104) extends along the second direction (Y) and is in electrical contact with the second doped region (II) of the active part (101).

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, Along the first direction (X), the width of the second interval (121) is smaller than the width of the first interval (111); The process steps for forming the conductive shielding portion (103) include: A first isolation layer (113) is formed, the first isolation layer (113) being located on the surface of the semiconductor layer (201) facing the first spacer region (111) and the surface facing the second spacer region (121), and after the formation of the first isolation layer (113), a first gap (1111) is formed between the first isolation layers (111) facing each other in the first spacer region (111), and a second gap (1211) is formed between the first isolation layers (113) facing each other in the second spacer region (111), and the width of the first gap (1111) is greater than the width of the second gap (1211) along the first direction (X); An initial conductive layer (103b, 103c) is formed to fill the first gap (1111) and the second gap (11211). The initial conductive layer (103b) located in the first gap (1111) is removed by etching using a wet process. Laterally etch the initial conductive layer (103c) located in the second gap (1211) to etch away a portion of the initial conductive layer (103c) adjacent to the capacitor hole (205) and the bit line hole (204), and the remaining initial conductive layer is used to form the conductive shield (103).

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The formation of the initial conductive layer filling the first gap (1111) and the second gap (1211) includes: A conductive metal layer (103a) is formed, which fills the first gap (1111), the second gap (1211), the bit line hole (205), and the capacitor hole (204). Remove the conductive metal layer (103a) located in the bit line hole (205) and the capacitor hole (204), and remove the conductive metal layer (103a) located on the sidewall of the first isolation layer (113) facing the bit line hole (205) and the sidewall facing the capacitor hole (204). The remaining conductive metal layer (103a) serves as the initial conductive layer (103b, 103c). The lateral etching of the initial conductive layer (103c) located within the second gap (1211) includes: The initial conductive layer (103c) is subjected to a first lateral etching on the sidewalls facing the bit line hole (205) and the capacitor hole (204); After the first lateral etching is performed, the sidewall of the initial conductive layer (103c) facing the capacitor hole (204) is etched a second lateral etching, and the remaining initial conductive layer serves as the conductive shield (103).

20. An electronic device (1), characterized in that, include: Processor (10); as well as A memory (20), wherein the memory (20) is coupled to the processor (10), and at least one of the memory (20) and the processor (10) comprises a semiconductor memory according to any one of claims 1-16.

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