Multi-chip packaging structure, circuit board assembly, and optical communication device

Abstract

Embodiments of the present application provide a multi-chip packaging structure, a circuit board assembly, and an optical communication device, which are used for improving the layout of optoelectronic devices in multi-chip packaging structures and optimizing the heat dissipation performance of the multi-chip packaging structures. The multi-chip packaging structure comprises a first chip, a second chip, a processing chip, and a first substrate. One of the first chip and the second chip is an optical chip, and the other is an electrical chip. The first chip is electrically connected to the second chip, and the processing chip is electrically connected to the electrical chip. The first chip and the second chip are stacked, thereby improving the layout of optoelectronic devices in the multi-chip packaging structure, and reducing the area occupied by the multi-chip packaging structure. A heat dissipation structure is provided in the first substrate, the processing chip is provided on the first substrate, the first chip is provided on the first substrate and located on the heat dissipation structure, and the second chip is located on the side of the first chip facing away from the heat dissipation structure. In this way, the heat dissipation problem of the first chip due to the stacked arrangement can be alleviated, thereby optimizing the heat dissipation performance of the multi-chip packaging structure.

Description

A multi-chip package structure, circuit board assembly and optical communication device

[0001] This application claims priority to Chinese Patent Application No. 202510373064.4, filed on March 25, 2025, entitled "A Multi-Chip Packaging Structure, Circuit Board Assembly and Optical Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of optical communication, and more particularly to a multi-chip package structure, circuit board assembly, and optical communication device. Background Technology

[0003] Current typical optoelectronic devices often employ pluggable optical modules, which integrate optical chips, electrical chips, and optoelectronic interfaces into a single structural unit, transmitting data with the processing chip via pluggable connectors. However, pluggable optical modules have several design limitations. For example, in scenarios where port speeds are constantly increasing, raising the transmission rate leads to a decrease in signal integrity and an increase in link loss in pluggable optical modules. Furthermore, in the context of miniaturization in optoelectronic devices, reducing the size of pluggable optical modules results in increasingly cramped internal space, not only increasing the difficulty of optoelectronic device layout design but also causing serious heat dissipation problems. Summary of the Invention

[0004] This application provides a multi-chip package structure, a circuit board assembly, and an optical communication device, which improves the layout of optoelectronic devices in the multi-chip package structure and optimizes the heat dissipation problem of the multi-chip package structure.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] A first aspect of this application provides a multi-chip package structure, comprising: a first chip, a second chip, a processing chip, and a first substrate. One of the first chip and the second chip is an optical chip, and the other is an electrical chip. The first chip and the second chip are stacked and electrically connected, and the processing chip and the electrical chip are electrically connected. The first substrate has a heat dissipation structure, the processing chip is disposed on the first substrate, the first chip is disposed on the first substrate and located on the heat dissipation structure, and the second chip is located on the side of the first chip opposite to the heat dissipation structure.

[0007] The multi-chip package structure provided in this application includes a first chip, a second chip, and a processing chip. One of the first chip and the second chip is an optical chip, and the other is an electrical chip. The processing chip is disposed on a first substrate, and the processing chip and the electrical chip are electrically connected. The optical chip and the electrical chip are also electrically connected. The optical chip, the electrical chip, and the processing chip are integrated into a single package structure, which reduces the distance between the optical chip / electrical chip and the processing chip, thereby supporting higher speeds and lower power consumption. The stacked arrangement of the first chip and the second chip improves the layout of optoelectronic devices in the multi-chip package structure, resulting in a smaller footprint. The first substrate has a heat dissipation structure. The first chip is disposed on the first substrate and located on the heat dissipation structure, while the second chip is located on the side of the first chip facing away from the heat dissipation structure. The heat dissipation structure improves the heat dissipation problem of the first chip caused by the stacked arrangement, thereby optimizing the heat dissipation of the multi-chip package structure.

[0008] In some embodiments, the multi-chip package structure further includes a second substrate, which is located on and electrically connected to the first substrate, and the processing chip is disposed on the side of the second substrate opposite to the first substrate. This facilitates the connection between the first and second substrates and provides better heat dissipation than disposing the chip on the side of the second substrate closer to the first substrate.

[0009] In some embodiments, the multi-chip package structure further includes a first adapter board. A first chip and a second chip are disposed on opposite sides of the first adapter board, and the first chip and the second chip are electrically connected through the first adapter board. That is, the first chip, the first adapter board, and the second chip are stacked, which can reduce the space between the optical chip and the electrical chip, increasing the packaging density of the multi-chip package structure, and also shorten the connection distance between the optical chip and the electrical chip, improving the performance of photoelectric transmission and electro-optical transmission.

[0010] In some embodiments, a portion of the second chip is disposed on the first adapter board, and another portion of the second chip is disposed on the second substrate. The processing chip and the second chip are electrically connected through the second substrate. The second chip can be electrically connected to the first chip through the first adapter board, and the second chip can also be connected to the processing chip through the first substrate.

[0011] In some embodiments, the multi-chip package structure further includes a second adapter board; a portion of the second chip is disposed on the first adapter board, another portion of the second chip is disposed on the second adapter board, the second chip and the processing chip are disposed on opposite sides of the second adapter board, and the processing chip and the second chip are electrically connected through the second adapter board. The second chip can be electrically connected to the first chip through the first adapter board, and the second chip can also be connected to the processing chip through the second adapter board.

[0012] In some embodiments, a second chip is disposed on a first adapter board, and the second chip and a processing chip are disposed on opposite sides of the first adapter board. The processing chip and the second chip are electrically connected through the first adapter board. The second chip can be connected to the first chip and the processing chip through the first adapter board.

[0013] In some embodiments, the heat dissipation structure includes a groove formed within a first substrate, and a heat dissipation material is disposed within the groove. The heat dissipation material can be used to dissipate heat from the first chip. In some examples, the heat dissipation material is a metal. In some examples, the height of the heat dissipation material can be higher than other areas of the first substrate, thereby placing the first chip at a suitable height.

[0014] In some embodiments, the heat dissipation structure includes a plurality of holes formed in a first substrate, the hole walls having a metal layer. The holes on the first substrate can increase the surface area of ​​the first substrate, and the metal layer on the hole walls can improve the heat dissipation effect of the heat dissipation structure.

[0015] In some embodiments, the hole penetrates the first substrate along the thickness direction. Holes penetrating the first substrate along the thickness direction are less expensive.

[0016] In some embodiments, the first chip is an optical chip, and the second chip is an electrical chip. The optical chip is disposed on a first substrate and located on a heat dissipation structure, and the electrical chip is electrically connected to the processing chip through a first adapter plate, a second adapter plate, or a second substrate. Compared to connecting the electrical chip to the processing chip through the optical chip, directly connecting the electrical chip to the processing chip results in lower signal delay and loss, and faster data transmission speed.

[0017] In some embodiments, the multi-chip package structure further includes an optical interface, which is connected to the optical chip, and a heat dissipation structure is disposed on the side of the first substrate near the optical interface. Since the optical chip is disposed on the first substrate and located on the heat dissipation structure, and the heat dissipation structure is disposed on the side of the first substrate near the optical interface, the optical chip is disposed on the side of the first substrate near the optical interface, thereby facilitating the connection between the optical chip and the optical interface.

[0018] A second aspect of this application provides a circuit board assembly, which includes a circuit board and any of the multi-chip package structures provided in the first aspect of this application, wherein the multi-chip package structure is disposed on the circuit board. This circuit board assembly has the same beneficial effects as the aforementioned multi-chip package structure, and will not be repeated here.

[0019] A third aspect of this application provides an optical communication device, which includes a housing and any of the circuit board assemblies provided in the second aspect of this application, the circuit board assembly being disposed within the housing. This optical communication device has the same beneficial effects as the circuit board assembly described above, and will not be repeated here. Attached Figure Description

[0020] Figure 1 is a schematic diagram of the structure of an optical communication device provided by related technologies;

[0021] Figure 2 is a schematic diagram of the structure of an optical communication device provided in an embodiment of this application;

[0022] Figure 3 is a schematic diagram of a multi-chip packaging structure provided by related technologies;

[0023] Figure 4 is a schematic diagram of another multi-chip packaging structure provided by related technologies;

[0024] Figure 5 is a schematic diagram of another multi-chip packaging structure provided by related technologies;

[0025] Figure 6 is a schematic diagram of a multi-chip packaging structure provided in an embodiment of this application;

[0026] Figure 7 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0027] Figure 8 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0028] Figure 9 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0029] Figure 10 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0030] Figure 11 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0031] Figure 12 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0032] Figure 13 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0033] Figure 14 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0034] Figure 15 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application;

[0035] Figure 16 is a schematic diagram of another multi-chip packaging structure provided in an embodiment of this application.

[0036] Reference numerals: 100-Communication equipment; 10-Housing; 11-Control module; 12-Optical module interface; 111-Retiming chip; 112-DSP chip; 20-Circuit board assembly; 21-Circuit board; 30-Optical module; 31-Optical interface; 40-Multi-chip package structure; 41-Processing chip; 42-Electrical chip; 43-Optical chip; 44-First substrate; 45-Second substrate; 51-First chip; 52-Second chip; 61-First adapter board; 62-Second adapter board; 63-Through hole structure; 70-Heat dissipation structure; 71-First heat dissipation component; 72-Second heat dissipation component. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0038] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0039] Furthermore, in the embodiments of this application, directional terms such as "upper" and "lower" are defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation in which the components are placed in the accompanying drawings.

[0040] With the development of optical communication technology, optical communication systems are being used more and more widely. An optical communication system includes multiple communication devices for transmitting optical signals, and the requirements for the optical signal transmission effect of these devices are becoming increasingly stringent.

[0041] Figure 1 shows a schematic diagram of the structure of an optical communication device 100 provided by related technology. The communication device 100 may include a housing 10, an optical module 30, a control module 11, and an optical module interface 12. The optical module interface 12 is disposed on the housing 10. The optical module 30 is detachably connected to the control module 11 through the optical module interface 12 on the housing 10. The optical module 30 may include an optical chip and an electrical chip. The optical chip may be a photonic integrated circuit (PIC) chip, and the electrical chip may be an electronic integrated circuit (EIC) chip. The control module 11 may include at least one of a processing chip 41, a retimer chip 111, or a digital signal processing (DSP) chip 112. For example, the processing chip 41 may be an application-specific integrated circuit (ASIC) chip. When the optical module 30 is connected to the control module 11 through the optical module interface 12, the DSP chip 112 and the retimer chip 111 are electrically connected, enabling signal transmission between the optical module 30 and the processing chip 41.

[0042] As port speeds continue to increase, single-channel electrical paths have evolved from 56G to 112G, 224G, and the future 448G. For example, increasing the signal rate from 56GB / s to 112GB / s doubles the insertion loss for a given length of low-loss trace. In other words, increasing port speeds leads to increased insertion loss in signal transmission between the optical module 30 and the processing chip 41, as shown in Figure 1, resulting in increased system power consumption and manufacturing costs.

[0043] Therefore, this application provides an optical communication device 100, as shown in FIG2. The optical communication device 100 may include a housing 10 and a circuit board assembly 20, with the circuit board assembly 20 disposed within the housing 10. The optical communication device 100 provided in this application embodiment may include an x ​​processing unit (xPU), such as a central processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), deep learning processing unit (DPU), neural network processing unit (NPU), or brain processing unit (BPU), etc. The optical communication device 100 provided in this application embodiment may also be an optoelectronic server or a data center switch. The circuit board assembly 20 may include an optical board, and the circuit board 21 may be, for example, a printed circuit board (PCB). The circuit board assembly 20 may be disposed inside the optical communication device 100.

[0044] Continuing with Figure 2, the circuit board assembly 20 includes a circuit board 21 and a multi-chip package structure 40, which is disposed on the circuit board 21. The multi-chip package structure 40 may include a processing chip 41, an electrical chip 42, and an optical chip 43. The processing chip 41 and the electrical chip 42 are electrically connected, and the electrical chip 42 and the optical chip 43 are electrically connected. In some examples, the multi-chip package structure 40 may also be referred to as an optical module. The processing chip 41, the electrical chip 42, and the optical chip 43 are packaged inside the housing 10, reducing the distance between the processing chip 41 and the electrical chip 42 and optical chip 43, thus supporting higher speeds. Furthermore, eliminating the DSP chip and retimer chip results in lower power consumption. In some embodiments, continuing with Figure 2, the multi-chip package structure 40 includes an optical interface 31, which is electrically connected to the optical chip 43. The optical interface 31 can be used to connect a pigtail 22.

[0045] For ease of explanation, an xyz coordinate system is established in Figure 2. The direction from circuit board 21 to multi-chip package structure 40 is the z-direction, the extension direction of pigtail 22 is the x-direction, and the y-direction is perpendicular to the xz plane. The x-direction is called the first direction x, the y-direction is called the second direction y, and the z-direction is called the third direction z. The coordinate systems in subsequent figures are similar and will not be repeated below.

[0046] To achieve a smaller and more efficient multi-chip package structure 40, there are various deployment methods for the processing chip 41, the electrical chip 42, and the optical chip 43.

[0047] Figure 3 shows a multi-chip package structure 40 provided by related technologies. The multi-chip package structure 40 may further include a first substrate 44, on which the processing chip 41, the electrical chip 42, and the optical chip 43 are all disposed. The bottom of the first substrate 44 includes electrical connection points, through which the first substrate 44 can be connected to a circuit board. For example, the electrical connection points may be in the form of ball grid array (BGA) electrical connection points.

[0048] However, in the multi-chip packaging structure 40 provided by the related technology, the processing chip 41, the electrical chip 42 and the optical chip 43 are laid flat on the first substrate 44, and the overall packaging area of ​​the multi-chip packaging structure 40 is relatively large.

[0049] To reduce the footprint of the multi-chip package structure 40, as shown in Figure 4, another multi-chip package structure 40 provided by related technologies can be constructed by stacking the electrical chip 42 and the optical chip 43. For example, the multi-chip package structure 40 may include a first chip 51 and a second chip 52, where one of the first chip 51 and the second chip 52 is an optical chip and the other is an electrical chip.

[0050] However, in the multi-chip package structure 40 shown in Figure 4, since the first chip 51 and the second chip 52 are stacked, the heat generated by the second chip 52 located above will be transferred to the first chip 51 located below. Since both the electrical chip and the optical chip are thermally sensitive elements, this heat will seriously affect the working performance of the chip.

[0051] To improve the heat dissipation of the multi-chip package structure 40, as shown in Figure 5, another multi-chip package structure 40 provided by related technologies is presented. The multi-chip package structure may further include a first heat dissipation component 71 and a second heat dissipation component 72. The first heat dissipation component 71 is disposed above the processing chip 41, and the second heat dissipation component 72 is disposed above the second chip 52. For example, the first heat dissipation component 71 and the second heat dissipation component 72 can be a heat spreader or a heat sink.

[0052] However, the heat dissipation problem of the first chip 51 in the multi-chip package structure 40 shown in Figure 5 still cannot be improved. To further improve the optoelectronic device layout in the multi-chip package structure 40 and optimize its heat dissipation, this application provides a multi-chip package structure 40, as shown in Figure 6. This multi-chip package structure 40 includes: a first chip 51, a second chip 52, a processing chip 41, and a first substrate 44. One of the first chip 51 and the second chip 52 is an optical chip, and the other is an electrical chip. The first chip 51 and the second chip 52 are stacked and electrically connected, and the processing chip 41 is electrically connected to the electrical chip. The first substrate 44 has a heat dissipation structure 70. The processing chip 41 is disposed on the first substrate 44, and the first chip 51 is disposed on the first substrate 44 and located on the heat dissipation structure 70. The second chip 52 is located on the side of the first chip 51 facing away from the heat dissipation structure 70.

[0053] In the multi-chip package structure 40 provided in this application embodiment, the optical chip, electrical chip, and processing chip 41 are integrated into one package structure, which can reduce the distance between the optical chip and electrical chip and the processing chip 41, thereby supporting higher speed and lower power consumption. The first chip 51 and the second chip 52 are stacked, which can improve the layout of optoelectronic devices in the multi-chip package structure 40, making the multi-chip package structure 40 occupy a smaller area. The first substrate 44 has a heat dissipation structure 70. The first chip 51 is disposed on the first substrate 44 and located on the heat dissipation structure 70. The second chip 52 is located on the side of the first chip 51 away from the heat dissipation structure 70. The heat dissipation structure 70 can improve the heat dissipation problem of the first chip 51 caused by the stacking arrangement, thereby optimizing the heat dissipation problem of the multi-chip package structure 40.

[0054] As shown in FIG6, the multi-chip package structure 40 provided in this application embodiment may further include a first heat dissipation component 71 and a second heat dissipation component 72. The first heat dissipation component 71 is disposed above the processing chip 41, and the second heat dissipation component 72 is disposed above the second chip 52. Based on this, the first heat dissipation component 71 can be used to dissipate heat from the processing chip 41, and the second heat dissipation component 72 can be used to dissipate heat from the second chip 52, resulting in better heat dissipation performance of the multi-chip package structure 40.

[0055] To reduce the contact thermal resistance between the first heat dissipation component 71 and the processing chip 41, and the contact thermal resistance between the second heat dissipation component 72 and the second chip 52, and the contact thermal resistance between the heat dissipation structure 70 and the first chip 51, in some embodiments, the multi-chip package structure 40 may further include a thermal interface material (TIM). The TIM may be disposed between the first heat dissipation component 71 and the processing chip 41, and / or, the TIM may be disposed between the second heat dissipation component 72 and the second chip 52, and / or, the TIM may be disposed between the heat dissipation structure 70 and the first chip 51.

[0056] There are various ways to implement the heat dissipation structure 70. In one possible implementation, as shown in FIG7, the heat dissipation structure 70 may include a groove formed in the first substrate 44, and a heat dissipation material is disposed in the groove. This application embodiment does not limit the form of the heat dissipation material. In some examples, the heat dissipation material is a metal, which has good thermal conductivity and can help dissipate heat from the first chip.

[0057] In another possible implementation, as shown in FIG8, the heat dissipation structure 70 may include a plurality of holes 73 formed in the first substrate 44, and the inner wall surface of the holes 73 may have a metal layer. The holes 73 can increase the surface area of ​​the first substrate 44, and the metal layer on the inner wall surface of the holes 73 can improve the thermal conductivity of the heat dissipation structure 70. In some examples, continuing as shown in FIG8, the holes 73 penetrate the first substrate 44 along the thickness direction (i.e., the third direction z) of the first substrate.

[0058] In some examples, referring to Figures 2 and 7, the heat dissipation structure 70 is located at one end of the first substrate near the optical interface 31, which facilitates the connection between the optical chip 43 and the optical interface 31.

[0059] Since metal traces cannot be installed inside the heat dissipation structure 70, in some embodiments, as shown in FIG9, the first chip 51 includes an active surface 511 and a passive surface 512 disposed opposite to each other, with electrical connection points provided on the active surface 511. The passive surface 512 faces the heat dissipation structure 70. For example, the first chip 51 is an optical chip. The transmitting end of the optical chip may include a modulator, such as a Mach-Zehnder modulator (MZM), a micro ring modulator (MRM), an electro absorption modulator (EAM), etc., and the active surface 511 includes electrical connection points corresponding to the transmitting end. The receiving end of the optical chip may include a wavelength division multiplexing (WDM) and a photodiode, and the active surface 511 includes electrical connection points corresponding to the receiving end.

[0060] Based on this, in order to achieve the connection between the first chip and the second chip, in some embodiments, as shown in FIG6, the second chip 52 passes through the first chip 51 and the first substrate 44 and is connected to the processing chip 41 through the first substrate 44.

[0061] In other embodiments, as shown in FIG10, the multi-chip package structure 40 may further include a first adapter board 61. The first chip 51 and the second chip 52 are disposed on opposite sides of the first adapter board 61, and the first chip 51 and the second chip 52 are electrically connected through the first adapter board.

[0062] The first adapter board 61 is used to bring the electrical connection points on the first chip 51 from its lower surface to its upper surface. The electrical connection points may include grounding and high-speed signals such as TX+, TX-, and GND for the transmitting end. They may also include high-speed current signals such as RX and GND for the receiving end. In some examples, the electrical connection points may also include the power supply electrodes for the chip's heater.

[0063] To facilitate the connection between the second chip 52 and the first adapter board 61, as shown in Figure 10, the second chip 52 may include an active surface and a passive surface, with the active surface of the second chip 52 facing the first adapter board 61.

[0064] In order to achieve the connection between the electrical chip and the processing chip, in some embodiments, as shown in FIG11, the height of the heat dissipation structure 70 can be lower than other areas of the first substrate 44, so that the first chip 51 and the second chip 52 are at a suitable height, and the second chip 52 can be electrically connected to the processing chip 41.

[0065] In some embodiments, as shown in FIG12, the multi-chip package structure 40 may further include a second substrate 45. The second substrate 45 is located on and electrically connected to the first substrate 44, and the processing chip 41 is disposed on the side of the second substrate 45 opposite to the first substrate 44. In some examples, continuing as shown in FIG12, the height of the heat dissipation structure 70 may be higher than other areas of the first substrate 44, thereby placing the first chip 51 and the second chip 52 at a suitable height, and the second chip 52 may be electrically connected to the processing chip 41.

[0066] There are various ways to connect the electrical chip and the processing chip. In some embodiments, as shown in FIG12, a portion of the second chip 52 is disposed on the first adapter plate 61, and another portion of the second chip 52 is disposed on the second substrate 45. The processing chip 41 and the second chip 52 are electrically connected through the second substrate 45. In this case, the second chip 52 can be electrically connected to the first chip 51 through the first adapter plate 61, and the second chip 52 can also be connected to the processing chip 41 through the second substrate 45. For example, the portion of the second chip 52 disposed on the first adapter plate 61 can be connected to the first chip 51 by electrode bonding.

[0067] In some other embodiments, as shown in FIG13, the second chip 52 is disposed on the first adapter board 61, and the second chip 52 and the processing chip 41 are disposed on opposite sides of the first adapter board 61. The processing chip 41 and the second chip 52 are electrically connected through the first adapter board 61.

[0068] In other embodiments, as shown in FIG14, the multi-chip package structure 40 further includes a second adapter board 62. A portion of the second chip 52 is disposed on the first adapter board 61, and another portion of the second chip 52 is disposed on the second adapter board 62. The second chip 52 and the processing chip 41 are disposed on opposite sides of the second adapter board 62, and the processing chip 41 and the second chip 52 are electrically connected through the second adapter board 62.

[0069] In the above embodiments, one of the first chip 51 and the second chip 52 is an optical chip, and the other is an electrical chip. In some examples, continuing as shown in FIG12, the first chip 51 is an optical chip, and the second chip 52 is an electrical chip. The electrical chip can be connected to the processing chip 41 through the second substrate 45. Taking the input signal as an example, the optical signal is input from the optical interface to the optical chip, the optical chip converts the optical signal into a current signal and sends it to the electrical chip, the electrical chip converts the current signal into a voltage signal and sends it to the processing chip 41, and the processing chip 41 processes the voltage signal.

[0070] In other examples, the first chip 51 is an electrical chip, and the second chip 52 is an optical chip. The optical chip can be connected to the processing chip 41 via the second substrate 45. The electrical chip is connected to the processing chip 41 via a bridge of the optical chip. Taking the input signal as an example again, the optical signal is input from the optical interface to the optical chip, the optical chip converts the optical signal into a current signal and sends it to the electrical chip, the electrical chip converts the current signal into a voltage signal and sends it back to the optical chip, the optical chip sends the voltage signal to the processing chip 41, and the processing chip 41 processes the voltage signal.

[0071] Therefore, compared to the connection between the electrical chip and the processing chip 41 via the optical chip, the optical chip is disposed on the first substrate 44 and located on the heat dissipation structure 70, and the electrical chip is electrically connected to the processing chip 41 via the first adapter plate 61, the second adapter plate 62 or the second substrate 45, resulting in lower signal delay and loss and faster data transmission speed.

[0072] In some embodiments, as shown in FIG12, the second chip 52 is an electrical chip. The electrical connection point between the electrical chip and the processing chip 41 may include a high-speed signal from the transmitting end, a high-speed signal from the receiving end, and a ground signal, and may also include a control channel signal. The processing chip 41 can adjust the electrical chip through the control channel signal, and the adjustment method of the processing chip 41 is simpler.

[0073] There are multiple ways to connect the processing chip 41 and the second chip 52 through a first intermediate layer or a second intermediate layer.

[0074] In some embodiments, the processing chip 41 includes an active surface and a passive surface. As shown in FIG13, the passive surface of the processing chip 41 faces the first adapter plate 61. As shown in FIG14, the passive surface of the processing chip 41 faces the second adapter plate 62. For example, the processing chip 41 also includes a via structure 63, which penetrates the processing chip 41 along the thickness direction (z-direction). The via structure 63 is used to lead the electrical connection point on the lower surface of the first adapter plate 61 or the second adapter plate 62 to the active surface of the processing chip 41, thereby realizing the electrical connection between the processing chip 41 and the second chip 52.

[0075] In other embodiments, as shown in FIG15 or FIG16, the processing chip 41 includes two active surfaces disposed opposite each other. For example, as shown in FIG15, the processing chip 41 is connected to an electrical connection point on the lower surface of the first adapter plate 61 via an active surface adjacent to the first adapter plate 61. For example, as shown in FIG16, the processing chip 41 is connected to an electrical connection point on the lower surface of the second adapter plate 62 via an active surface adjacent to the second adapter plate 62.

[0076] It should be noted that, as shown in Figure 12, the processing chip 41 and the second chip 52, as shown in Figures 13, 14, 15 or 16, can also be equipped with a heat sink or heat fin for top heat dissipation, thereby achieving better heat dissipation effect.

[0077] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multi-chip packaging structure, characterized in that, include: The chip consists of a first chip, a second chip, and a processing chip, wherein one of the first chip and the second chip is an optical chip and the other is an electrical chip. The first chip and the second chip are stacked and electrically connected; the processing chip and the electrical chip are electrically connected. A first substrate has a heat dissipation structure therein, and a processing chip is disposed on the first substrate. The first chip is disposed on the first substrate and located on the heat dissipation structure, and a second chip is located on the side of the first chip away from the heat dissipation structure.

2. The multi-chip packaging structure according to claim 1, characterized in that, The multi-chip packaging structure also includes: The second substrate is located on the first substrate and is electrically connected to the first substrate, and the processing chip is disposed on the side of the second substrate opposite to the first substrate.

3. The multi-chip packaging structure according to claim 1 or 2, characterized in that, The multi-chip packaging structure also includes: A first adapter board; the first chip and the second chip are disposed on opposite sides of the first adapter board, and the first chip and the second chip are electrically connected through the first adapter board.

4. The multi-chip packaging structure according to claim 3, characterized in that, A portion of the second chip is disposed on the first adapter board, and another portion of the second chip is disposed on the second substrate. The processing chip and the second chip are electrically connected through the second substrate.

5. The multi-chip packaging structure according to claim 3, characterized in that, The multi-chip packaging structure also includes a second adapter board; A portion of the second chip is disposed on the first adapter board, and another portion of the second chip is disposed on the second adapter board. The second chip and the processing chip are disposed on opposite sides of the second adapter board, and the processing chip and the second chip are electrically connected through the second adapter board.

6. The multi-chip packaging structure according to claim 3, characterized in that, The second chip is disposed on the first adapter board, and the second chip and the processing chip are disposed on opposite sides of the first adapter board. The processing chip and the second chip are electrically connected through the first adapter board.

7. The multi-chip packaging structure according to any one of claims 1-6, characterized in that, The heat dissipation structure includes a groove formed in the first substrate, and a heat dissipation material is disposed in the groove.

8. The multi-chip packaging structure according to any one of claims 1-6, characterized in that, The heat dissipation structure includes a plurality of holes formed in a first substrate, the holes penetrating the first substrate along the thickness direction of the first substrate, and the hole walls having a metal layer.

9. The multi-chip packaging structure according to any one of claims 1-8, characterized in that, The first chip is an electrical chip, and the second chip is an optical chip.

10. The multi-chip packaging structure according to any one of claims 1-9, characterized in that, The first chip includes an active surface and a passive surface disposed opposite to each other, with the passive surface facing the heat dissipation structure.

11. A circuit board assembly, characterized in that, The invention includes a circuit board and a multi-chip package structure as described in any one of claims 1-10, wherein the multi-chip package structure is disposed on the circuit board.

12. An optical communication device, characterized in that, It includes a housing and a circuit board assembly as described in claim 11, the circuit board assembly being disposed within the housing.

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