Storage module and electronic device

Abstract

A storage module and an electronic device. The storage module comprises a plurality of storage chips and a plurality of groups of signal ports; each storage chip implements input and output of signals by means of a corresponding group of signal ports, the memory chip being electrically connected to each signal port by means of independent signal lines; and a target resistor is connected in series in some or all of the signal lines. The difference between a resistance value of the target resistor at a first temperature and a resistance value of the target resistor at a second temperature is less than or equal to a first preset value, the first temperature being room temperature, and the second temperature being a maximum value of an operating temperature specified for the storage module, such that a change in the resistance values of the target resistor at room temperature and a high temperature is small, thus improving the integrity of signal transmission at high temperatures.

Description

Storage modules and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510377030.2, filed on March 26, 2025, entitled “A Storage Module and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of integrated circuits, and more particularly to a memory module and an electronic device. Background Technology

[0003] Registered Dual In-Line Memory Modules (RDIMMs) are primarily used in high-performance computing environments such as servers and workstations, supporting higher memory capacities. RDIMMs often encounter heavy loads, and series resistors are used on the signal lines to absorb reflected signals and improve signal integrity. However, this also leads to heat generation, further affecting impedance mismatch and reducing signal transmission performance. Summary of the Invention

[0004] This disclosure provides a storage module and an electronic device that can improve the integrity of signal transmission at high temperatures.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a storage module, the storage module including multiple storage chips and multiple sets of signal ports, each storage chip realizing signal input and output through a corresponding set of signal ports; the storage chips and each signal port are electrically connected through independent signal lines, and a target resistor is connected in series in some or all of the signal lines; wherein, the difference between the resistance value of the target resistor at a first temperature and the resistance value of the target resistor at a second temperature is less than or equal to a first preset value; the first temperature is room temperature, and the second temperature is the maximum value of the operating temperature specified by the storage module.

[0007] In some embodiments, the target resistor includes a first resistor and a second resistor connected in parallel; the resistance of the first resistor has a positive coefficient of variation with temperature; and the resistance of the second resistor has a negative coefficient of variation with temperature.

[0008] In some embodiments, the memory module includes a reference ground layer and a signal trace layer, the reference ground layer and the signal trace layer are arranged along a third direction, the third direction being perpendicular to the substrate plane of the memory chip; the signal line is located in the signal trace layer, a cutout region exists in the reference ground layer, and the projection of the target resistor along the third direction falls in the cutout region.

[0009] In some embodiments, the second resistor comprises only one negative temperature coefficient resistor.

[0010] In some embodiments, the second resistor includes a plurality of negative temperature coefficient resistors, the different resistors being connected in series and / or in parallel.

[0011] In some embodiments, the second resistor includes a negative temperature coefficient resistor, and / or a positive temperature coefficient resistor, and / or a fixed resistance resistor, with different resistors connected in series and / or in parallel.

[0012] In some embodiments, the first resistor is a surface mount resistor; the negative temperature coefficient resistor is an NTC thermistor; and the difference between the resistance value of the target resistor and the resistance value of the first resistor at a first temperature is less than or equal to a second preset value.

[0013] In some embodiments, the signal port includes a data port; the target resistor is connected in series on the signal line between the memory chip and each of the data ports.

[0014] In some embodiments, the signal line is divided into a first main line, a second branch line, a third branch line, a fourth branch line, a fifth branch line, and a sixth main line; a first end of the first main line is connected to the memory chip; a second end of the first main line is connected to the first end of the second branch line and the first end of the third branch line; a second end of the second branch line is connected to the first end of the first resistor; a second end of the third branch line is connected to the first end of the second resistor; a first end of the fourth branch line is connected to the second end of the first resistor; a second end of the fifth branch line is connected to the second end of the second resistor; the second ends of the fourth branch line and the second ends of the fifth branch line are connected to the first end of the sixth main line; and a second end of the sixth main line is connected to the data port.

[0015] The width of the first main line is the same as the width of the sixth main line; the widths of the second branch line, the third branch line, the fourth branch line, and the fifth branch line are the same; the width of the first main line is greater than the width of the second branch line.

[0016] In some embodiments, the storage module is a dual in-line memory module including registers; the storage chip is a dynamic random access memory chip; the first preset value is: the resistance of the target resistor at a first temperature × A; the value of A ranges from 2% to 10%.

[0017] Secondly, embodiments of this disclosure provide an electronic device, the electronic device including the storage module as described in the first aspect.

[0018] This disclosure provides a storage module and an electronic device. Since the resistance of the target resistor connected in series with the signal line changes very little at both room temperature and high temperature, it can mitigate the effects of high temperature and maintain high transmission performance and signal integrity at both room temperature and high temperature. Attached Figure Description

[0019] Figures 1 and 2 are schematic diagrams of the structure of the storage module in the related technology;

[0020] Figure 3 is a schematic diagram of the structure of a storage module provided in an embodiment of this disclosure;

[0021] Figures 4 to 6 are schematic diagrams of the structure of a target resistor provided in an embodiment of this disclosure;

[0022] Figure 7 is a schematic diagram of the structure of a storage module provided in an embodiment of this disclosure;

[0023] Figure 8 is a schematic diagram of the connection of a target resistor provided in an embodiment of this disclosure;

[0024] Figure 9 is a schematic diagram of the structure of a storage module in related technologies;

[0025] Figure 10 is a schematic diagram of the structure of a storage module provided in an embodiment of this disclosure;

[0026] Figure 11 shows a schematic diagram of the back of a circuit board of a storage module provided in an embodiment of the present disclosure;

[0027] Figures 12 to 15 are schematic diagrams of signal transmission simulation results of the storage module provided in the embodiments of this disclosure;

[0028] Figure 16 is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0029] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0031] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0032] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0034] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0035] Dual In-Line Memory Module (DIMM);

[0036] Unbuffered DIMM (UDIMM);

[0037] Registered DIMM (RDIMM);

[0038] Low-load LRDIMM (Load-Reduced DIMM);

[0039] Non-volatile DIMM (NVDIMM)

[0040] Data Center Persistent Memory Module (DCPMM)

[0041] Dynamic Random Access Memory (DRAM);

[0042] Synchronous Dynamic Random Access Memory (SDRAM);

[0043] Double Data Rate SDRAM (DDR);

[0044] Fifth generation DDR (DDR5);

[0045] Low-power DDR (LPDDR);

[0046] Static Random Access Memory (SRAM)

[0047] NAND flash memory;

[0048] Metal-Oxide-Semiconductor (MOS);

[0049] Bits per second (Mbps);

[0050] Ohm.

[0051] Please refer to Figure 1, which shows a schematic diagram of a memory module. As shown in Figure 1, this memory module is an RDIMM, which includes registers and multiple chips (i.e., memory chips, such as DRAM, DDR, LPDDR). A single DIMM may contain up to 40 chips. The data signals from the chips are transmitted to the signal ports of the memory module via signal lines. These signal lines have series resistors to achieve impedance matching. When the memory module is running at full speed, the heat generated by the series resistors on the signal lines can be significant, especially for higher DDR5 speeds, such as 5600Mbps, 6400Mbps, and future even higher DDR formats, where higher power consumption leads to an increase in the overall temperature of the DIMM.

[0052] Please refer to Figure 2, which shows the series resistor on the DQ signal line in the DIMM. This series resistor is 15 ohms. When the temperature varies from 25°C to 100°C, the dielectric constant and physical properties of the substrate, the DC impedance of the copper wire, and the resistance value of the series resistor all change with temperature. This causes the impedance matching that was present at room temperature (25°C) to be compromised at high temperatures. Experiments have shown that the resistance of the series resistor is 15 ohms at room temperature (25°C), but 17.5 ohms at 100°C. This impedance mismatch at different temperatures alters the signal line's transmission performance, and the accuracy of signal transmission cannot be guaranteed at extreme temperatures.

[0053] Overall, due to the large number of memory chips integrated on the RDIMM, the series resistors on the data signal lines generate significant heat at high speeds, causing the overall temperature of the RDIMM to rise. This temperature increase leads to an increase in the resistance of the series resistors, which in turn compromises signal integrity at high temperatures.

[0054] Based on this, the present disclosure provides a storage module that reduces the adverse effects of temperature rise by connecting a series resistor and a thermistor in parallel on the data signal line, thereby ensuring the effectiveness of signal transmission.

[0055] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0056] In one embodiment of this disclosure, referring to FIG3, a schematic diagram of the structure of a storage module 10 provided in this embodiment is shown. As shown in FIG3, the storage module 10 includes a plurality of storage chips 11.

[0057] It should be noted that the memory chip 11 in this embodiment is a memory with storage function. Its basic structure includes a memory array, an address decoder, a control circuit, and an input / output interface. The input / output interface is used to transmit at least command address signals and data signals. The address decoder is used to decode the address signals. The control circuit is used to read data signals from the memory array according to the command signals and the decoded address signals, or to store data signals into the memory array. The memory array has multiple memory cell units, and the specific structures of these memory cell units are varied, enabling the formation of different types of memory chips 11. The memory chip 11 includes, but is not limited to, SRAM, DRAM, SDRAM, DDR, LPDDR, and NAND.

[0058] Storage module 10 is a module that integrates multiple storage chips 11, which may include, but are not limited to, DIMM, UDIMM, RDIMM, LRDIMM, NVDIMM, DCPMM, Single In-Line Memory Module (SIMM), and in-memory computing module.

[0059] As shown in Figure 3, the storage module 10 includes multiple sets of signal ports 12, and each storage chip 11 realizes signal input and output through a corresponding set of signal ports 12.

[0060] The memory chip 11 is electrically connected to each signal port 12 through an independent signal line. That is, the input and output ports of the memory chip 11 are connected to the corresponding signal ports 12 through signal lines, and a target resistor is connected in series in some or all of the signal lines. The difference between the resistance value of the target resistor at the first temperature and the resistance value of the target resistor at the second temperature is less than or equal to a first preset value. The first temperature is room temperature, and the second temperature is the maximum value of the operating temperature specified by the memory module 10.

[0061] It should be noted that the first preset value is a relatively small value, so the resistance of the target resistor changes very little at room temperature and high temperature, which improves the effect of high temperature. The resistance of the target resistor is close at both room temperature and high temperature, thus achieving impedance matching and maintaining high transmission performance and signal integrity.

[0062] Depending on the type of storage module 10, the value of the second temperature may vary, for example, 85℃, 100℃, 125℃, etc.

[0063] In some implementations, at other temperatures between the first and second temperatures, the resistance value of the target resistor is also less than or equal to the first preset value, just as it is at the first temperature.

[0064] In some embodiments, the first preset value is: the resistance of the target resistor at the first temperature × A; the value of A ranges from 2% to 10%.

[0065] In one example, the first preset value is equal to 10% of the resistance of the target resistor at the first temperature, meaning that the resistance of the target resistor will not fluctuate by more than 10% as the temperature changes.

[0066] In another example, the first preset value is equal to 5% of the resistance of the target resistor at the first temperature, meaning that the resistance of the target resistor will not fluctuate by more than 5% as the temperature changes.

[0067] In another example, the first preset value is equal to 2% of the target resistor's resistance at the first temperature. That is, the resistance of the target resistor will not fluctuate by more than 2% as the temperature changes.

[0068] It should be noted that signal port 12 is at least allowed to be a data port, used to transmit data signals DQ. Here, each memory chip 11 has multiple data ports, depending on its bit width. A 4-bit memory chip 11 has 4 DQ ports; an 8-bit memory chip 11 has 8 DQ ports; a 16-bit memory chip 11 has 16 DQ ports; a 32-bit memory chip 11 has 32 DQ ports, and so on. Furthermore, a memory module 10 has a large number of memory chips 11, and the amount of data signal transmitted is relatively large. Therefore, under full-speed operation, the heat generated by the series resistors on the signal lines of the data ports becomes a significant problem.

[0069] Therefore, in some embodiments, the aforementioned target resistor is connected in series on the signal line between the memory chip 11 and each data port. Thus, the resistance value of the target resistor remains close at different temperatures, ensuring it always operates at relatively ideal parameters and guaranteeing the integrity of the data signal DQ transmission.

[0070] Additionally, signal port 12 may include one or more of the following: a clock port, a command address port, and a data strobe port. Here, the clock port is used to transmit the clock signal CK, the command address port is used to transmit the command address signal CA, and the data strobe port is used to transmit the data strobe signal DQS.

[0071] In some embodiments, a target resistor is also connected in series on the signal line between the memory chip 11 and the clock port (and / or command address port, and / or data strobe port).

[0072] It should be noted that the number of clock ports, command address ports, and data strobe ports is limited, and the number of signals transmitted through these ports is also less than the number of signals transmitted through the data ports. Therefore, the heat generation problem is not serious. Thus, in some embodiments, the aforementioned target resistor does not need to be connected in series on the signal lines between the memory chip 11 and the clock port (and / or command address port, and / or data strobe port). Ordinary surface-mount resistors can be connected in series, or no resistors can be connected in series at all, reducing the circuit area.

[0073] In some embodiments, please refer to FIG4, the target resistor 13 includes a first resistor 131 and a second resistor 132 connected in parallel; the resistance value of the first resistor 131 has a positive coefficient of change with temperature; the resistance value of the second resistor 132 has a negative coefficient of change with temperature.

[0074] In this way, since the resistance of the first resistor 131 increases with the temperature and the resistance of the second resistor decreases with the temperature, the resistance of the first resistor 131 and the second resistor connected in parallel fluctuates within a very small range. As a result, the overall resistance remains unchanged within the allowable error range, which offsets the effect of temperature rise and improves the integrity of data signal transmission and impedance matching.

[0075] In some embodiments, the first resistor 131 can be an existing series resistor, meaning that the resistance value of the first resistor 131 can provide good impedance matching at room temperature. Meanwhile, the parameters of the second resistor 132 are selected based on the parameters of the first resistor 131.

[0076] At this point, the conditions for selecting the second resistor 132 are as follows:

[0077] (1) The difference between the resistance value of the target resistor 13 at the first temperature and the resistance value of the target resistor 13 at the second temperature is less than or equal to the first preset value, that is, the equivalent resistance value of the target resistor 13 remains unchanged within the allowable error range over a wide temperature range.

[0078] (2) The difference between the resistance value of the target resistor 13 and the resistance value of the first resistor 131 is less than or equal to the second preset value. That is, within a wide temperature range, the equivalent resistance value of the target resistor 13 and the resistance value of the first resistor 131 are approximately the same within the allowable error range.

[0079] In this way, the resistance value of the target resistor 13 is close to that of the original series resistor, ensuring impedance matching; at the same time, the parameters of the second resistor 132 are used to compensate for temperature changes, so that the resistance value of the target resistor 13 fluctuates less over a wide temperature range, maintaining signal integrity.

[0080] In one example, the second preset value = the resistance of the first resistor 131 at the first temperature × B, where the value of B ranges from 1% to 5%.

[0081] In a specific example, see Figure 5, the second resistor unit 132 includes only one negative temperature coefficient resistor.

[0082] For example, the first resistor 131 can be one or more of the following resistors: surface mount resistor, thin film resistor, thick film resistor, metal film resistor, metal oxide film resistor, carbon film resistor, wire wound resistor, zero-ohm resistor, or adjustable resistor. Surface mount resistors are surface-mount devices widely used in electronic equipment, characterized by their small size, high precision, and low temperature coefficient.

[0083] For example, a negative temperature coefficient resistor can be an NTC thermistor, which is typically made of metal oxides such as manganese, nickel, and cobalt.

[0084] For example, the absolute value of the temperature coefficient of the first resistor 131 is less than the absolute value of the temperature coefficient of the second resistor 132.

[0085] Thus, the first resistor 131 has a relatively small temperature coefficient, resulting in a smaller resistance value as temperature changes, while the second resistor 132 has a much larger resistance value than the first resistor 131. This allows the first resistor 131 to provide the primary resistance value for the target resistor. The second resistor 132 has a relatively large temperature coefficient, resulting in a much larger resistance value as temperature changes, and is mainly used to compensate for the temperature variations introduced by the first resistor 121.

[0086] At this point, taking the second resistor 132 as a single NTC thermistor as an example, the NTC thermistor needs to be selected based on the first resistor 131. A specific operating temperature value (such as the aforementioned room temperature and maximum temperature) is selected for calculation to ensure the matching of the operating extreme points of the NTC thermistor and the first resistor 131. For example, using formula (3), based on the resistance value R0 of the first resistor 131 at room temperature and the second preset value R0(1±B), the acceptable range of the resistance value Rn0 of the NTC thermistor at room temperature is calculated; using formula (4), based on the resistance value R0 of the first resistor 131 at room temperature, the first preset value R0(1±A), the second preset value R0(1±B), and the resistance value R1 of the first resistor 131 at a second temperature (e.g., 100℃), the acceptable range of the resistance value Rn1 of the NTC thermistor at a second temperature is calculated. Furthermore, the parameters Rn0 and Rn1 of the NTC thermistor also need to conform to formula (5) to select the required NTC thermistor.

[0087] In one specific embodiment, at 25°C, the resistance of the first resistor 131 is 15 ohms; the resistance of the second resistor 132 is 1000 ohms; at 100°C, the resistance of the first resistor 131 is 17.5 ohms; and the resistance of the second resistor 132 is 85 ohms.

[0088] At this point, at 25°C, the resistance of the target resistor 13 is 14.78 ohms, a change of 1.46% compared to the resistance of the first resistor 131 at 25°C (15 ohms). At 100°C, the resistance of the target resistor 13 is 14.51 ohms, a change of 3.25% compared to the resistance of the first resistor 131 at 25°C (15 ohms), and a change of 1.82% compared to the resistance of the target resistor 13 at 25°C (14.78 ohms). Therefore, the resistance of the target resistor 13 does not change significantly at different temperatures and is close to the resistance of the original series resistor, maintaining good impedance matching and improving the integrity of signal transmission.

[0089] In other embodiments, the first resistor 131 can be a negative temperature coefficient resistor, the second resistor 132 can be a positive temperature coefficient resistor, and the absolute value of the temperature coefficient of the first resistor 131 is less than the absolute value of the temperature coefficient of the second resistor. In this case, the second resistor 132 can be a PTC thermistor, such as barium titanate material.

[0090] In another specific example, the second resistor 132 includes multiple negative temperature coefficient resistors, which are connected in series and / or in parallel.

[0091] In yet another specific example, the second resistor 132 includes a negative temperature coefficient resistor, and / or a positive temperature coefficient resistor, and / or a fixed resistance resistor, the different resistors being connected in series and / or in parallel.

[0092] In this way, since the resistance coefficient with temperature may not be ideal, a second resistor 132 is formed by connecting a resistor with a positive temperature coefficient, multiple NTC thermistors with different temperature coefficients, and a resistor with a fixed resistance value in series and / or in parallel. Matching and fitting can be performed at multiple temperatures, so that the resistance value of the target resistor 13 can remain basically unchanged at multiple temperatures, better offsetting the effects of temperature changes and improving the integrity of signal transmission.

[0093] For example, as shown in Figure 6(a), the second resistor 132 includes a plurality of resistors connected in parallel.

[0094] Example (1), the second resistor 132 includes multiple resistors with negative temperature coefficients connected in parallel;

[0095] Example (2), the second resistor 132 includes a resistor with a negative temperature coefficient and a resistor with a positive temperature coefficient connected in parallel, and the final temperature coefficient of the second resistor 132 is negative.

[0096] Example (3), the second resistor 132 includes a resistor with a negative temperature coefficient and a resistor with a fixed resistance value connected in parallel.

[0097] Example (4), the second resistor 132 includes a resistor with a negative temperature coefficient, a resistor with a fixed resistance value and a resistor with a positive temperature coefficient connected in parallel.

[0098] As shown in Figure 6(b), the second resistor 132 includes multiple resistors connected in series.

[0099] Example (1), the second resistor 132 includes a plurality of resistors with negative temperature coefficients connected in series;

[0100] Example (2), the second resistor 132 includes a resistor with a negative temperature coefficient and a resistor with a positive temperature coefficient connected in series, and the final temperature coefficient of the second resistor 132 is negative;

[0101] Example (3), the second resistor 132 includes a resistor with a negative temperature coefficient and a resistor with a fixed resistance connected in series.

[0102] Example (4), the second resistor 132 includes at least one resistor with a negative temperature coefficient, a fixed resistance resistor and a resistor with a positive temperature coefficient connected in series.

[0103] As shown in Figure 6(c), the second resistor 132 includes multiple resistor branches connected in parallel; each resistor branch includes several resistors connected in series, as shown in the following example.

[0104] Example (1): The resistors in the right-hand resistor branch (first branch) are resistors with a negative temperature coefficient, and the resistors in the left-hand resistor branch (second branch) are all resistors with a negative temperature coefficient.

[0105] Example (2): The resistors in the right resistor branch are resistors with a negative temperature coefficient, while the resistors in the left resistor branch are all resistors with a positive temperature coefficient.

[0106] Example (3): The resistors in the right resistor branch are resistors with a negative temperature coefficient, while the resistors in the left resistor branch are all resistors with a fixed resistance value.

[0107] Example (4): The resistor in the right resistor branch is a resistor with a negative temperature coefficient, and the resistors in the left resistor branch are a resistor with a negative temperature coefficient and a resistor with a fixed resistance value, respectively.

[0108] Example (5): The resistor in the right resistor branch is a resistor with a negative temperature coefficient, and the resistors in the left resistor branch are resistors with a negative temperature coefficient and resistors with a positive temperature coefficient, respectively.

[0109] Example (6): The resistor in the right resistor branch is a resistor with a negative temperature coefficient, and the resistors in the left resistor branch are a resistor with a fixed resistance value and a resistor with a positive temperature coefficient, respectively.

[0110] Example (7): The resistor in the right resistor branch is a resistor with a positive temperature coefficient, and the resistors in the left resistor branch are a resistor with a negative temperature coefficient and a resistor with a fixed resistance value, respectively.

[0111] Example (8): The resistor in the right resistor branch is a resistor with a positive temperature coefficient, and the resistors in the left resistor branch are resistors with a negative temperature coefficient and resistors with a positive temperature coefficient, respectively.

[0112] Example (9): The resistor in the right resistor branch is a resistor with a fixed resistance value, and the resistors in the left resistor branch are a resistor with a negative temperature coefficient and a resistor with a fixed resistance value, respectively.

[0113] Example (10): The resistor in the right resistor branch is a resistor with a fixed resistance value, and the resistors in the left resistor branch are resistors with negative temperature coefficient and resistors with positive temperature coefficient, respectively.

[0114] As shown in Figure 6(d), the second resistor 132 includes resistor branches connected in series; each resistor branch includes several resistors connected in parallel, as shown in the following example.

[0115] Example (1): The resistors in the lower resistor branch (first branch) are resistors with a negative temperature coefficient, and the resistors in the upper resistor branch (second branch) are all resistors with a negative temperature coefficient.

[0116] Example (2): The resistors in the lower resistor branch are resistors with a negative temperature coefficient, while the resistors in the upper resistor branch are all resistors with a positive temperature coefficient.

[0117] Example (3): The resistors in the lower resistor branch are resistors with a negative temperature coefficient, while the resistors in the upper resistor branch are all resistors with a fixed resistance value.

[0118] Example (4): The resistors in the lower resistor branch are all resistors with negative temperature coefficients, and the resistors in the upper resistor branch are resistors with negative temperature coefficients and resistors with fixed resistance values, respectively.

[0119] Example (5): The resistors in the lower resistor branch are all resistors with negative temperature coefficients, and the resistors in the upper resistor branch are resistors with negative temperature coefficients and resistors with positive temperature coefficients, respectively.

[0120] Example (6): The resistors in the lower resistor branch are all resistors with negative temperature coefficients, while the resistors in the upper resistor branch are resistors with fixed resistance and resistors with positive temperature coefficients, respectively.

[0121] Example (7): The resistor in the lower resistor branch is a resistor with a positive temperature coefficient, and the resistors in the upper resistor branch are a resistor with a negative temperature coefficient and a resistor with a fixed resistance value, respectively.

[0122] Example (8): The resistor in the lower resistor branch is a resistor with a positive temperature coefficient, and the resistors in the upper resistor branch are resistors with a negative temperature coefficient and resistors with a positive temperature coefficient, respectively.

[0123] Example (9): The resistors in the lower resistor branch are resistors with fixed resistance values, and the resistors in the upper resistor branch are resistors with negative temperature coefficients and resistors with fixed resistance values, respectively.

[0124] Example (10): The resistors in the lower resistor branch are resistors with fixed resistance values, and the resistors in the upper resistor branch are resistors with negative temperature coefficients and resistors with positive temperature coefficients, respectively.

[0125] In the above description, a fixed resistance value refers to a resistor whose resistance value changes little with temperature, such as a surface mount resistor.

[0126] In this way, by combining resistors of different types and parameters, the performance curve of the second resistor 132 can be controlled more precisely, so that the resistance value of the target resistor 13 can remain basically unchanged at multiple temperatures.

[0127] It should be noted that in this embodiment, the target resistor 13 is counteracted by introducing a second resistor 132 to offset the effect of temperature rise on the first resistor 131. However, the introduction of the second resistor 132 may lead to an increase in capacitance to ground. Therefore, in some embodiments, please refer to FIG7, the memory module 10 includes a reference ground layer 21 and a signal trace layer 22, which are arranged along a third direction, perpendicular to the substrate plane of the memory chip 11; the aforementioned signal lines are located in the signal trace layer 22, a cutout area exists in the reference ground layer 21, and the projection of the target resistor 13 along the third direction falls on the cutout area.

[0128] Thus, please refer to Figure 8, which shows a top view of the storage module 10. In the reference stratum, by hollowing out the portion opposite to the target resistor 13, additional ground capacitance is avoided, and no negative impact is generated on the storage module 10.

[0129] In some embodiments, as shown in FIG8, each signal line is divided into a first main line 141, a second branch line 142, a third branch line 143, a fourth branch line 144, a fifth branch line 145, and a sixth main line 146. The first end of the first main line 141 is connected to the memory chip 11, and the second end of the first main line 141 is connected to the first end of the second branch line 142 and the first end of the third branch line 143. The second end of the second branch line 142 is connected to the first end of the first resistor 131 (corresponding solder block), and the second end of the third branch line 143 is connected to the first end of the second resistor 132 (corresponding solder block). The first end of the fourth branch line 144 is connected to the second end of the first resistor 131 (corresponding solder block), and the second end of the fifth branch line 145 is connected to the second end of the second resistor 132 (corresponding solder block). The second ends of the fourth branch line 144 and the fifth branch line 145 are connected to the first end of the sixth main line 146, and the second end of the sixth main line 146 is connected to the data port.

[0130] It should be understood that the second resistor 132 is located next to the first resistor 131, as shown in Figure 8. The second resistor 132 is located to the right of the first resistor 131. However, the second resistor 132 can also be located to the left of the first resistor 131. Within the limits of the process, the closer the two are, the better, so as to reduce the circuit area and the trace length.

[0131] Additionally, in the accompanying drawings, the first resistor 131 and the NTC thermistor are of the same size; this is merely illustrative and does not constitute a specific limitation.

[0132] The first resistor 131 and the second resistor 132 are both soldered onto the circuit board. Figure 8 also shows the solder block.

[0133] In some embodiments, as shown in FIG8, the width of the first main line 141 is the same as the width of the sixth main line 146; the widths of the second branch line 142, the third branch line 143, the fourth branch line 144, and the fifth branch line 145 are the same; and the width of the first main line 141 is greater than the width of the second branch line 142.

[0134] In this way, the branch lines are relatively thin and have higher impedance. As a result, the impedance of the branch lines after parallel connection is approximately the same as the impedance of the original signal lines, thus maintaining smooth signal transmission.

[0135] In addition, the connection method of the branch lines shown in Figure 8 is only an illustration and does not constitute any limitation. The angle between the branch lines has no special meaning. If branch lines are needed, L-shaped ones can also be used.

[0136] Referring to Figure 9(a), a front view of a storage module 30 in a related embodiment is shown. Referring to Figure 9(b), a rear view of a storage module 30 in a related embodiment is shown.

[0137] Referring to Figure 10(a), it shows a front structural schematic diagram of a storage module 10 provided in an embodiment of the present disclosure. Referring to Figure 10(b), it shows a rear structural schematic diagram of a storage module 10 provided in an embodiment of the present disclosure.

[0138] Storage modules 10 and 30 have similar basic structures. Storage module 10 includes a first region, RCD chips, and a second region arranged sequentially along a first direction. The first region has 10 storage chips 11, and the second region has 9 storage chips 11. The two opposite edges of storage module 30 along the second direction are referred to as the first edge and the third edge, and the two opposite edges of storage module 30 along the first direction are referred to as the second edge and the fourth edge. The length of storage module 30 along the first edge is greater than the length of storage module 10 along the second edge. All data ports are arranged parallel to each other along the first direction, and all data ports are located close to the first edge.

[0139] Here, the RCD chip can be called a Register Clock Driver. Its main functions include signal buffering, clock signal distribution, signal enhancement, and load reduction, making it an important module in an RDIMM. Meanwhile, for DIMMs that do not contain registers, there is no need to configure an RCD chip.

[0140] Please refer to Figure 9. There is a series resistor 31 on the signal line between the memory chip 11 and the data port. Multiple series resistors 31 are arranged in parallel along the first direction and are close to the first edge of the memory module 30.

[0141] Referring to Figure 10, a target resistor 13 is provided on the signal line between the memory chip and the data port. The target resistor 13 includes a first resistor 131 and an NTC thermistor (equivalent to a second resistor 132) connected in parallel. Multiple target resistors 13 are arranged parallel to each other along a first direction and are close to the first edge of the memory module 30. The first resistor 131 and the second resistor 132 are also arranged parallel to each other along the first direction. Referring to Figure 11, which shows a schematic diagram of the back of a circuit board for the memory module 10, as shown in Figure 11, the second resistor 132 is positioned close to the first resistor 131; within permissible limits, the closer the two are, the better.

[0142] Meanwhile, for Figure 10, the target resistor 13, which is formed by the first resistor 131 and the NTC thermistor in parallel, is connected in series only for the signal lines of the data port. This design is not performed for other ports such as the clock port and the command address port.

[0143] The following are the test data for the two circuit structures mentioned above.

[0144] For the storage module 30 shown in Figure 9, that is, when only a series resistor (15Ω at room temperature and 17.5 ohms at 100℃) is set on the data signal line without a negative temperature coefficient resistor:

[0145] Please refer to Figure 12, which shows the signal transmission eye diagram of the storage module 30 during read and write operations at 25°C. The height of the read window is 249.9916 and the width is 130.4926. (b) shows the signal transmission eye diagram of the RDIMM module during write operations at 100°C. The height of the write window is 318.49 and the width is 131.4356.

[0146] Please refer to Figure 13, which shows the signal transmission eye diagram of the read and write operations of the storage module 30 at 100°C. The height of the read window is 240.1031 and the width is 130.3741; the height of the write window is 300.6178 and the width is 131.6875.

[0147] Comparing Figures 12 and 13, it can be seen that at 100℃, the height of both the read window and the write window is significantly reduced compared to 25℃, which may affect signal integrity and cause data reception / transmission errors.

[0148] Regarding the storage module 10 shown in Figure 10, with the target resistor (first resistor + NTC thermistor) set on the signal line, the resistance of the first resistor is 15Ω and the resistance of the NTC thermistor is 1000Ω at 25℃; at 100℃, the resistance of the first resistor is 17.5Ω and the resistance of the NTC thermistor is 85Ω:

[0149] Please refer to Figure 14, which shows the signal transmission eye diagram of the read and write operations of the storage module 10 at 25°C. The height of the read window is 251.2149 and the width is 130.5339; the height of the write window is 318.5836 and the width is 131.6836.

[0150] Please refer to Figure 15, which shows the signal transmission eye diagram of the storage module 30 at 100°C for read and write operations. The height of the read window is 252.2896 and the width is 130.4031; the height of the write window is 320.8556 and the width is 131.7787.

[0151] Comparing Figures 14 and 15, it can be seen that at 100℃, the heights of the read window and the write window remain basically unchanged compared to 25℃, indicating good signal integrity and ensuring the correctness of data reception / transmission.

[0152] Furthermore, comparing Figures 12 and 14, it can be seen that the signal transmission performance of the two circuits is similar at room temperature; comparing Figures 13 and 15, it can be seen that at higher temperatures, the heights of the read window and write window of the storage module 10 provided in this embodiment of the present disclosure are significantly increased, thereby increasing the integrity of signal transmission.

[0153] In summary, this disclosure mainly relates to the series resistance of signal lines on RDIMM, and particularly to the integrity of data signal transmission, the thermal effects of the board material and metal circuits. It addresses the impact of temperature rise on the original series resistance by adding a parallel thermistor, and is applicable to signal routing design on RDIMM or other similar DDR traces.

[0154] Specifically, for RDIMMs, when there are a large number of memory chips 10 and the operating speed is relatively high, the signal lines used for data signal transmission will generate significant heat, causing the overall temperature of the RDIMM to rise. This temperature rise mainly leads to two consequences: first, the characteristic impedance of the signal traces decreases, and second, the original series resistance and the DC resistance of the traces increase. This results in the signal integrity at room temperature being compromised at high temperatures.

[0155] To address the above issues, this embodiment improves the situation by connecting an NTC thermistor (equivalent to the second resistor 32) in parallel with the original series resistor (equivalent to the first resistor 131). Furthermore, for the entire DIMM, this processing is mainly applied to the DQ single-ended signal line because the DQ single-ended line has a higher speed and is more affected by impedance changes. This is not necessary for the CA signal line, CK signal line, and DQS signal line.

[0156] Simultaneously, after connecting the NTC thermistor in parallel, due to the potential increase in capacitance to ground caused by the thermistor, vias need to be drilled at the bottom of both resistors to reference ground, and the traces connected to the two pads need to be thinned to increase the line impedance. Also, the NTC thermistor should be placed next to the original series resistor; the main principle is that they should be as close as possible within the limits of the process, as shown in Figure 8. The left and right positions of the NTC thermistor and the original series resistor are not limited, depending on space constraints. This treatment is applied to each DQ single-ended signal line on the RDIMM. The choice of thermistor can be changed according to the application scenario. Under normal temperature variations, with the DIMM temperature peak below 100℃, a 1000-ohm NTC thermistor is a good choice. In more extreme environments, the NTC thermistor value can be increased or decreased as needed.

[0157] In another embodiment of this disclosure, referring to FIG16, a schematic diagram of the composition structure of an electronic device 50 provided in an embodiment of this disclosure is shown. As shown in FIG16, the electronic device 50 includes at least the aforementioned storage module 10.

[0158] The storage module 10 includes multiple storage chips 11 and multiple sets of signal ports 12. Each storage chip 11 implements signal input and output through a corresponding set of signal ports 12. The storage chip 11 and each signal port 12 are electrically connected through independent signal lines. That is, the input and output ports of the storage chip 11 are connected to the corresponding signal ports 12 through signal lines. A target resistor is connected in series in some or all of the signal lines. The difference between the resistance value of the target resistor at a first temperature and the resistance value of the target resistor at a second temperature is less than or equal to a first preset value. The first temperature is room temperature, and the second temperature is the maximum value of the operating temperature specified by the storage module 10.

[0159] In this way, the resistance of the target resistor changes very little at both room temperature and high temperature, mitigating the effects of high temperature. Regardless of whether it is at room temperature or high temperature, the resistance of the target resistor remains close, thus achieving impedance matching and maintaining high transmission performance and signal integrity.

[0160] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A storage module (10), wherein, The storage module includes multiple storage chips (11) and multiple sets of signal ports (12). Each storage chip realizes signal input and output through a corresponding set of signal ports. The memory chip is electrically connected to each of the signal ports through independent signal lines, and a target resistor (13) is connected in series in some or all of the signal lines. Wherein, the difference between the resistance value of the target resistor at the first temperature and the resistance value of the target resistor at the second temperature is less than or equal to a first preset value; the first temperature is room temperature, and the second temperature is the maximum value of the operating temperature specified by the storage module.

2. The storage module according to claim 1, wherein, The target resistor includes a first resistor and a second resistor connected in parallel; The resistance of the first resistor changes with temperature by a positive coefficient. The resistance of the second resistor changes with temperature by a negative coefficient.

3. The storage module according to claim 2, wherein, The storage module includes a reference ground layer and a signal trace layer, which are arranged along a third direction, and the third direction is perpendicular to the substrate plane of the storage chip. The signal line is located in the signal trace layer, there is a hollow area in the reference ground layer, and the projection of the target resistor along a third direction falls in the hollow area.

4. The storage module according to claim 2 or 3, wherein, The second resistor consists of only one resistor with a negative temperature coefficient.

5. The storage module according to claim 2 or 3, wherein, The second resistor includes multiple negative temperature coefficient resistors, which are connected in series and / or in parallel.

6. The storage module according to claim 2 or 3, wherein, The second resistor includes a negative temperature coefficient resistor, and / or a positive temperature coefficient resistor, and / or a fixed resistance resistor, with different resistors connected in series and / or in parallel.

7. The storage module according to claim 4, wherein, The first resistor is a surface-mount resistor; the negative temperature coefficient resistor is an NTC thermistor. The difference between the resistance value of the target resistor and the resistance value of the first resistor at the first temperature is less than or equal to a second preset value.

8. The storage module according to claim 2, wherein, The signal port includes a data port; the target resistor is connected in series on the signal line between the memory chip and each of the data ports.

9. The storage module according to claim 8, wherein, The signal lines are divided into a first main line, a second branch line, a third branch line, a fourth branch line, a fifth branch line, and a sixth main line; The first end of the first main line is connected to the memory chip; the second end of the first main line is connected to the first end of the second branch line and the first end of the third branch line; the second end of the second branch line is connected to the first end of the first resistor; the second end of the third branch line is connected to the first end of the second resistor; the first end of the fourth branch line is connected to the second end of the first resistor; the second end of the fifth branch line is connected to the second end of the second resistor; the second ends of the fourth branch line and the second ends of the fifth branch line are connected to the first end of the sixth main line; and the second end of the sixth main line is connected to the data port. The width of the first main line is the same as the width of the sixth main line; the widths of the second branch line, the third branch line, the fourth branch line, and the fifth branch line are the same; the width of the first main line is greater than the width of the second branch line.

10. The storage module according to claim 1, wherein, The storage module is a dual in-line memory module that includes registers; The memory chip is a dynamic random access memory chip; The first preset value is: the resistance of the target resistor at the first temperature × A; the value of A ranges from 2% to 10%.

11. An electronic device comprising a storage module as described in any one of claims 1-10.

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