Image sensor and forming method therefor

Abstract

Disclosed in the present invention is a method for forming an image sensor. At least a portion of a gate electrode of a vertical transfer transistor of an image sensor is "U"-shaped, wherein a side surface away from a floating diffusion region and a bottom surface of an adjacent shallow trench are wrapped and controlled by the gate electrode, so as to improve the charge conduction capability of the vertical transfer transistor; in addition, the bottom surface of the shallow trench outside the gate electrode is pinned, so as to reduce a dark current.

Description

An image sensor and its formation method This application claims priority to Chinese Patent Application No. 202510382007.2, filed on March 27, 2025, entitled "An Image Sensor and a Method for Forming the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an image sensor and a method for forming the same. Background Technology

[0002] With the rapid development of image sensors and their increasingly widespread applications, the demands on image sensor performance are constantly rising. Pixel unit sizes are shrinking, and full-well capacitance density is rapidly increasing, placing immense pressure on charge readout. In the pixel unit structure, the design of the transfer transistor is particularly crucial for pixel readout. For pixels fabricated at advanced nodes, the transfer transistor has undergone a series of optimized designs, especially the vertical transfer transistor (VLT), which not only effectively improves readout capability but also reduces the isolation burden on the photodiode. This brings significant convenience to pixel unit design.

[0003] Vertical transfer transistors (VTIPs) protrude their bottom surface onto the photodiode, thus increasing the gate oxide area and enhancing the VTIP's control over the transmission channel. Simultaneously, the deeper VTIP bottom surface allows for a deeper photodiode, significantly reducing the risk of punch-through between the photodiode and surrounding areas, thereby further improving the photodiode's design depletion voltage. However, in existing VTIP designs, the VTIP can only partially control the transmission channel from the VTIP to the floating diffusion region. The gate control range is limited, and the further the semiconductor substrate is from the channel surface, the weaker the gate's control becomes, leading to low electron readout efficiency and poor turn-off. Therefore, current VTIP designs have limited control over the transmission channel, which is detrimental to electron transport. Summary of the Invention

[0004] The present invention aims to provide a method for forming an image sensor, comprising: at least a portion of the gate of the vertical transfer transistor of the image sensor having a "U" shape; wherein the side away from the floating diffusion region and the bottom surface of the adjacent shallow trench are wrapped and controlled by the gate to improve the charge conduction capability of the vertical transfer transistor, and simultaneously pin the bottom surface of the shallow trench outside the gate to reduce dark current.

[0005] In some embodiments, the method further includes: etching a portion of the gate near the floating diffusion region, causing the gate surface near the floating diffusion region to sink below the upper surface of the floating diffusion region, thereby reducing the electric field strength of the floating diffusion region.

[0006] In some embodiments, the method further includes: etching all gates near the floating diffusion region so that their surfaces are all submerged below the upper surface of the floating diffusion region.

[0007] In some embodiments, the floating diffusion region has an elongated structure extending to the photodiode, and the vertical transfer transistor wraps around the end of the elongated structure to form a U-shaped gate structure, thereby increasing the capacitance of the vertical transfer transistor to the floating diffusion region and improving its conduction capability.

[0008] In some embodiments, the width of the head at the end of the elongated structure is greater than the width of the strip portion connected to the end of the elongated structure.

[0009] In some embodiments, the connection between the head of the end of the elongated structure and the strip portion of the elongated structure is located inside the gate region of the vertical transfer transistor.

[0010] In some embodiments, the head width of the elongated structure of the floating diffusion region is more than 20 nanometers wider than the width of the elongated portion of the structure.

[0011] In some embodiments, the length / width of the elongated structure of the floating diffusion region is greater than 1.2.

[0012] In some embodiments, the top width of the elongated structure of the floating diffusion region is less than 200 nanometers.

[0013] In some embodiments, the method further includes: etching a semiconductor substrate to form a shallow trench and the floating diffusion region, filling the shallow trench with a dielectric material to form a shallow trench isolation structure; etching the dielectric material in the shallow trench isolation structure to the bottom of the shallow trench, filling it with a gate material, and forming the gate of the vertical transfer transistor and the gates of other pixel transistors by etching the gate material.

[0014] In some embodiments, the method further includes: etching a semiconductor substrate to form a shallow trench, filling the shallow trench with a dielectric material to form a shallow trench isolation structure; etching an active region adjacent to the floating diffusion region and the shallow trench to form a first trench with an etching depth similar to the depth of the shallow trench, and forming an elongated structure of the floating diffusion region; filling the first trench with a gate material, and etching the gate material to form the gate of the vertical transfer transistor and the gates of other pixel transistors.

[0015] In some embodiments, the method further includes: simultaneously forming the gate of the vertical transfer transistor and the gates of other pixel transistors by etching the gate material once.

[0016] In some embodiments, the method further includes: forming the gates of the vertical transfer transistors and other pixel transistors with different gate surface depressions by repeatedly etching the gate material.

[0017] In some embodiments, the gate of the vertical transfer transistor corresponds one-to-one with the end of the floating diffusion region it encloses.

[0018] In some embodiments, the gate material comprises one or more combinations of polysilicon, doped semiconductor material, and metallic material.

[0019] The present invention also provides an image sensor comprising: at least a portion of the gate of a vertical transfer transistor having a "U" shape; wherein the side away from the floating diffusion region and the bottom surface of the adjacent shallow trench are wrapped and controlled by the gate to improve the charge conduction capability of the vertical transfer transistor and simultaneously pin the bottom surface of the shallow trench outside the gate to reduce dark current.

[0020] This invention proposes a novel image sensor formation method based on the above-described scheme, which improves the control capability of the vertical transfer transistor (VLT). In this scheme, the gate of the VLT is designed in a U-shape, increasing the control area of ​​the readout channel from the photodiode to the floating diffusion region, thereby enhancing the control capability of the VLT and ultimately improving its readout efficiency. Attached Figure Description

[0021] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0022] Figure 1 is a functional block diagram of an image sensor according to an exemplary embodiment of the present invention.

[0023] Figure 2 is a schematic diagram of the structure of an image sensor according to an embodiment of the present invention.

[0024] Figure 3 is a schematic diagram of the cross section along A1-A2 in Figure 2.

[0025] Figure 4 is a schematic diagram of the cross section along B1-B2 in Figure 2.

[0026] Figures 5 to 12 are cross-sectional schematic diagrams of the formation process of an image sensor according to an embodiment of the present invention.

[0027] Figures 13 to 20 are cross-sectional schematic diagrams of the formation process of another image sensor according to an embodiment of the present invention.

[0028] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0030] Figure 1 is a functional block diagram of an image sensor 100 according to an exemplary embodiment of the present invention.

[0031] The image sensor 100 includes a pixel array 105, a readout circuit 110, a functional logic 115, and a control circuit 120.

[0032] The pixel array 105 includes a two-dimensional (“2D”) array of multiple image sensor pixels 125 (e.g., pixels P1, P2…Pn). As shown, each pixel is arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

[0033] After each pixel has acquired its image data or image charge, the image data is read out by readout circuit 110 and transmitted to functional logic 115. Readout circuit 110 may include amplifier circuitry, analog-to-digital converter (“ADC”), etc. Functional logic 115 may simply store or process the image data. In one embodiment, readout circuit 110 may read out one row of image data at a time along readout column line 102, or may utilize other techniques (not shown) to read out the image data, such as column / row readout, serial readout, or simultaneous parallel readout of all pixels.

[0034] Control circuitry 120 is connected to pixel array 105 to control pixel array 105. For example, control circuitry 120 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal may be a global shutter signal, enabling all pixels within pixel array 105 to simultaneously capture their respective image data during a single acquisition window. In other embodiments, the shutter signal may be a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

[0035] This invention provides a method for forming an image sensor, comprising: at least a portion of the gate of the vertical transfer transistor of the image sensor is U-shaped; wherein the side away from the floating diffusion region and the bottom surface of the adjacent shallow trench are wrapped and controlled by the gate to improve the charge conduction capability of the vertical transfer transistor, and simultaneously pin the bottom surface of the shallow trench outside the gate to reduce dark current.

[0036] The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0037] Figures 2(a) and 2(b) are schematic diagrams of the structure of the image sensor according to an embodiment of the present invention.

[0038] Figure 3 is a schematic diagram of the cross section along A1-A2 in Figure 2.

[0039] Figure 4 is a schematic diagram of the cross section along B1-B2 in Figure 2.

[0040] Referring to Figures 2, 3, and 4, a shallow trench isolation structure 21 is formed in the semiconductor substrate 20. The floating diffusion (FD) region of the image sensor can be shared by four photodiodes (PDs) (including PD1, PD2, PD3, and PD4).

[0041] The floating diffusion zone FD includes the floating diffusion zone FD1 located in the central region and the floating diffusion zone FD2 located away from the central region.

[0042] As shown in Figures 2(a) and 2(b), at least a portion of the gate 22 of the vertical transfer transistor of the image sensor is U-shaped; wherein the side away from the floating diffusion region FD (i.e. the side surface of the floating diffusion region FD2) and the adjacent shallow trench bottom surface 201 are wrapped and controlled by the gate 22 to improve the charge conduction capability of the vertical transfer transistor and simultaneously pin the shallow trench bottom surface 201 outside the gate to reduce dark current.

[0043] Specifically, as shown in Figure 2(a), the floating diffusion region FD has an elongated strip structure extending to the photodiode PD (i.e., the floating diffusion region FD2). The gate 22 of the vertical transfer transistor wraps around the end of the elongated strip structure to form a U-shaped gate 22, thereby increasing the capacitance of the vertical transfer transistor to the floating diffusion region FD and improving its conduction capability. The gate 22 of the vertical transfer transistor corresponds one-to-one with the end of the floating diffusion region FD it wraps.

[0044] As shown in Figure 2(b), in another embodiment, the width of the end FD2a of the elongated structure enclosing the gate 22 of the vertical transfer transistor can be greater than the width of the strip portion FD2b connected to the end. The connection point between the head of the end FD2a of the elongated structure and the strip portion FD2b of the elongated structure is located inside the gate region of the vertical transfer transistor.

[0045] In some embodiments, the width of the head FD2a of the elongated structure in the floating diffusion region is more than 20 nanometers larger than the width of the strip portion FD2b of the elongated structure.

[0046] In one embodiment, the gate 22 of the vertical transfer transistor may include a first gate portion 221 and a second gate portion 222. Specifically, the side surface of the floating diffusion region FD2 may be wrapped by the second gate portion 222, and the upper surface of the second portion 222 is lower than the upper surface of the floating diffusion region FD. Specifically, the gate surface near the floating diffusion region FD (i.e., the floating diffusion region FD2) is sunk below the upper surface of the floating diffusion region FD to reduce the electric field strength of the floating diffusion region FD. Alternatively, the entire gate near the floating diffusion region FD (i.e., the floating diffusion region FD2) has its entire surface sunk below the upper surface of the floating diffusion region FD.

[0047] In one embodiment, the length / width of the elongated structure of the floating diffusion region FD (i.e., the floating diffusion region FD2) is greater than 1.2.

[0048] In one embodiment, the top width (D1 in Figure 3) of the elongated structure of the floating diffusion region FD (i.e., the floating diffusion region FD2) is less than 200 nanometers.

[0049] The following describes the formation process of an image sensor according to an embodiment of the present invention with reference to Figures 5 to 12. The cross-sectional process can be compared with the cross-section A1-A2 in Figure 2.

[0050] Referring to Figure 5, a semiconductor substrate 30 is provided. A patterned mask layer 301 is formed on the semiconductor substrate 30. The mask layer 301 can be made of materials such as silicon oxide or silicon nitride.

[0051] Referring to Figure 6, the semiconductor substrate 30 is etched to form a shallow trench 300 and a floating diffusion region FD.

[0052] Referring to Figure 7, a shallow trench isolation structure 32 is formed by filling the shallow trench 300 with a dielectric material. The dielectric material can be silicon oxide.

[0053] Referring to Figure 8, a patterned mask layer 302 is formed on the semiconductor substrate 30.

[0054] Referring to Figure 9, the dielectric material in the shallow trench isolation structure 32 is etched down to the bottom of the shallow trench 300 to form a trench 303. The shape of the trench 303 can be "U".

[0055] Referring to Figure 10, a gate material 33 is filled, and a patterned mask layer 304 is formed on the gate material 33. The gate material 33 comprises one or more combinations of polysilicon, doped semiconductor material, and metal material.

[0056] Referring to Figure 11, the gate 32 of the vertical transfer transistor and the gates of other pixel transistors are formed by etching the gate material 33. The gate 32 of the vertical transfer transistor includes a first portion 321 and a second portion 322. The upper surface of the second portion 322 of the gate 32 is lower than the surface of the semiconductor substrate 30 or the upper surface of the floating diffusion region FD. Specifically, the gate of the vertical transfer transistor and the gate 32 of other pixel transistors can be formed simultaneously by etching the gate material 33 once. Alternatively, the gate 32 of the vertical transfer transistor and the gates of other pixel transistors with different gate surface depressions can be formed by etching the gate material 33 multiple times.

[0057] Referring to Figure 12, the mask layer 301 above the floating diffusion region FD is removed, and ion doping of the floating diffusion region FD is formed by ion implantation.

[0058] The following describes another image sensor formation process according to an embodiment of the present invention with reference to Figures 13 to 20. The cross-sectional process can be compared with the cross-section A1-A2 in Figure 2.

[0059] Referring to Figure 13, a semiconductor substrate 40 is provided. A patterned mask layer 401 is formed on the semiconductor substrate 40. The mask layer 401 can be made of materials such as silicon oxide or silicon nitride.

[0060] Referring to Figure 14, the semiconductor substrate 40 is etched to form a shallow trench 400.

[0061] Referring to Figure 15, a shallow trench isolation structure 42 is formed by filling the shallow trench 400 with a dielectric material. The dielectric material can be silicon oxide.

[0062] Referring to Figure 16, a patterned mask layer 402 is formed on the semiconductor substrate 40.

[0063] Referring to Figure 17, the active region (part of the semiconductor substrate 40) adjacent to the floating diffusion region FD and the shallow trench 400 is etched to form a trench 403 with an etching depth similar to that of the shallow trench 400, and to form an elongated structure of the floating diffusion region FD. The shape of the trench 403 can be "U".

[0064] Referring to Figure 18, a gate material 43 is filled, and a patterned mask layer 404 is formed on the gate material 43. The gate material 43 comprises one or more combinations of polysilicon, doped semiconductor material, and metal material.

[0065] Referring to Figure 19, the gate 42 of the vertical transfer transistor and the gates of other pixel transistors are formed by etching the gate material 43. The gate 42 of the vertical transfer transistor includes a first portion 421 and a second portion 422. The upper surface of the second portion 422 of the gate 42 is lower than the surface of the semiconductor substrate 40 or the upper surface of the floating diffusion region FD. Specifically, the gate of the vertical transfer transistor and the gate 42 of other pixel transistors can be formed simultaneously by etching the gate material 43 once. Alternatively, the gates 42 of the vertical transfer transistor and the gates of other pixel transistors with different gate surface depressions can be formed by etching the gate material 43 multiple times.

[0066] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming an image sensor, characterized in that, include: At least a portion of the gate of the vertical transfer transistor of the image sensor is U-shaped; wherein the side away from the floating diffusion region and the bottom surface of the adjacent shallow trench are wrapped and controlled by the gate to improve the charge conduction capability of the vertical transfer transistor and simultaneously pin the bottom surface of the shallow trench outside the gate to reduce dark current.

2. The method as described in claim 1, characterized in that, Also includes: The gate portion near the floating diffusion region is etched, causing the gate surface near the floating diffusion region to sink below the upper surface of the floating diffusion region, thereby reducing the electric field strength of the floating diffusion region.

3. The method as described in claim 1, characterized in that, Also includes: Etch all gates near the floating diffusion region so that their surfaces are completely submerged below the upper surface of the floating diffusion region.

4. The method as described in claim 1, characterized in that, The floating diffusion region has an elongated strip structure extending to the photodiode. The vertical transfer transistor wraps around the end of the elongated strip structure to form a U-shaped gate structure, thereby increasing the capacitance of the vertical transfer transistor to the floating diffusion region and improving its conduction capability.

5. The method as described in claim 4, characterized in that, The width of the head at the end of the elongated structure is greater than the width of the strip portion connected to the end of the elongated structure.

6. The method as described in claim 5, characterized in that, The connection point between the head of the elongated structure and the strip portion of the elongated structure is located inside the gate region of the vertical transfer transistor.

7. The method as described in claim 4, characterized in that, The length / width of the elongated structure in the floating diffusion zone is greater than 1.

2.

8. The method as described in claim 4, characterized in that, The top width of the elongated structure of the floating diffusion region is less than 200 nanometers.

9. The method as described in claim 5, characterized in that, The head width of the elongated structure in the floating diffusion region is more than 20 nanometers wider than the width of the elongated section of the structure.

10. The method as described in claim 1, characterized in that, include: Etching a semiconductor substrate to form shallow trenches and the floating diffusion region, and filling the shallow trenches with dielectric material to form a shallow trench isolation structure; The dielectric material in the shallow trench isolation structure is etched down to the bottom of the shallow trench, and the gate material is filled in. By etching the gate material, the gate of the vertical transfer transistor and the gates of other pixel transistors are formed.

11. The method as described in claim 1, characterized in that, include: A semiconductor substrate is etched to form shallow trenches, and a dielectric material is filled into the shallow trenches to form a shallow trench isolation structure. The active region adjacent to the floating diffusion region and the shallow trench is etched to form the first trench with an etching depth similar to that of the shallow trench, and to form the elongated structure of the floating diffusion region. The first trench is filled with gate material, and the gate of the vertical transfer transistor and the gates of other pixel transistors are formed by etching the gate material.

12. The gate material etching method as described in claim 10 or 11, characterized in that, include: The gate of the vertical transfer transistor and the gates of other pixel transistors are formed simultaneously by etching the gate material once.

13. The gate material etching method as described in claim 10 or 11, characterized in that, include: By repeatedly etching the gate material, gates of the vertical transfer transistors and other pixel transistors with different gate surface depressions are formed respectively.

14. The method as described in claim 1, characterized in that, The gate of the vertical transfer transistor corresponds one-to-one with the end of the floating diffusion region it encloses.

15. The method for forming a vertical transfer transistor as claimed in claim 1, characterized in that, The gate material comprises one or more combinations of polycrystalline silicon, doped semiconductor materials, and metallic materials.

16. An image sensor, characterized in that, include: At least a portion of the gate of the vertical transfer transistor is U-shaped; wherein the side away from the floating diffusion region and the bottom surface of the adjacent shallow trench are wrapped and controlled by the gate to improve the charge conduction capability of the vertical transfer transistor and simultaneously pin the bottom surface of the shallow trench outside the gate to reduce dark current.

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