Transistor structure, memory and memory preparation method

Abstract

A transistor structure, a memory and a memory preparation method. The transistor structure comprises: an active body, which comprises a source region, a drain region and a channel region located between the source region and the drain region; a first oxide layer, which is located on a surface of the source region and / or the drain region, wherein the thickness of the first oxide layer is less than or equal to 2 nm; a first isolation layer, which is located on the face of the first oxide layer that is away from the source region and / or the drain region; a gate oxide layer, which is located on a surface of the channel region; and a gate conductive layer, which is located on the face of the gate oxide layer that is away from the channel region. The transistor structure solves the problems of an existing transistor structure having increased contact resistance and being prone to leaking electricity.

Description

Transistor structure, memory and memory fabrication method

[0001] This application claims priority to Chinese Patent Application No. 202510369657.3, filed on March 25, 2025, entitled "Transistor Structure, Memory and Method for Memory Fabrication", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a body tube structure, a memory, and a method for fabricating the memory. Background Technology

[0003] As memory integration density continues to increase, higher demands are being placed on the arrangement and size of transistors in memory array structures. Researchers have developed other transistor structures, such as embedded transistor structures, vertical transistor structures, and three-dimensional stacked transistor structures, to meet the demand for high integration and high density of transistors.

[0004] As the size of transistor structures decreases, the contact resistance between transistors and bit lines and storage contacts increases. At the same time, leakage problems at the source and drain of transistors become more and more serious, affecting transistor performance. Summary of the Invention

[0005] This application addresses the shortcomings of existing methods by proposing a transistor structure, a memory, and a method for fabricating the memory, in order to solve the problems of increased contact resistance and easy leakage in existing transistor structures.

[0006] According to a first aspect of the present disclosure, a transistor structure is provided, comprising: an active body including a source region, a drain region, and a channel region located between the source region and the drain region; a first oxide layer located on the surface of the source region and / or the drain region, the thickness of the first oxide layer being less than or equal to 2 nanometers; a first isolation layer located on the side of the first oxide layer away from the source region and / or the drain region; a gate oxide layer located on the surface of the channel region; and a gate conductive layer located on the side of the gate oxide layer away from the channel region.

[0007] In some embodiments, the active body can be arranged parallel to the substrate, perpendicular to the substrate, or stacked parallel to the substrate; the material of the active body is silicon.

[0008] In some embodiments, the gate conductive layer may be located on one side, two sides, three sides of the channel region or surround the channel region.

[0009] In some embodiments, the surface of the first isolation layer away from the active body is flush with the surface of the gate conductive layer away from the active body.

[0010] In some embodiments, the doping types of the source and drain regions are different from those of the channel region.

[0011] In some embodiments, the gate conductive layer further extends onto the surface of a portion of the source and drain regions, with an extension length of 5 nanometers to 15 nanometers.

[0012] In some embodiments, the doping types of the source and drain regions are the same as those of the channel region.

[0013] In some embodiments, the gate conductive layer further extends onto the surface of a portion of the source and drain regions, with an extension length of 15 nanometers to 20 nanometers.

[0014] According to a second aspect of the present disclosure, a memory is provided, including the transistor structure described above, and further comprising: a bit line structure electrically connected to one end of a source region or a drain region; a memory structure connected to the other end of a source region or a drain region; a second isolation layer located between adjacent bit line structures; and a third isolation layer located between adjacent gate conductive layers.

[0015] According to a second aspect of the present disclosure, a method for fabricating a memory is provided, comprising forming an active body on a substrate, the active body including a source region, a drain region, and a channel region located between the source region and the drain region; forming a first oxide layer on the surface of the source region and / or the drain region, the thickness of the first oxide layer being less than or equal to 2 nanometers; forming a first isolation layer on the side of the first oxide layer away from the source region and / or the drain region; forming a gate oxide layer on the surface of the channel region; and forming a gate conductive layer on the side of the gate oxide layer away from the channel region.

[0016] In some embodiments, the active body is an active pillar perpendicular to the substrate, and the method for preparing the active pillar includes: etching a first groove on the substrate extending along a plurality of first directions and arranged along a second direction, and filling the first groove with a second isolation layer; forming a second groove on the substrate extending along a plurality of second directions and arranged along the second direction, and filling the second groove with a third isolation layer; the depth of the first groove is greater than the depth of the second groove; the first direction is perpendicular to the second direction.

[0017] In some embodiments, forming a first oxide layer on the surface of the source region and / or drain region, the thickness of the first oxide layer being less than or equal to 2 nanometers, includes: filling a third isolation layer in a second groove, the third isolation layer including a first isolation sublayer and a second isolation sublayer, the first isolation sublayer being located on the sidewall of the second groove and the second isolation sublayer being located within the first isolation sublayer; etching away a portion of the second isolation layer and a portion of the first isolation sublayer to expose the source region or drain region;

[0018] An in-situ water vapor generation process is used to form a first oxide layer on the surface of the source or drain region, and the thickness of the first oxide layer is less than or equal to 2 nanometers.

[0019] In some embodiments, forming a gate conductive layer on the side of the gate oxide layer away from the channel region includes: forming a first isolation layer on the side of the first oxide layer away from the source region and / or drain region; etching away a portion of the first isolation sublayer and a portion of the second isolation layer to expose the channel region; forming a gate oxide layer on the surface of the channel region; and forming a gate conductive layer on the side of the gate oxide layer away from the channel region.

[0020] In some embodiments, the method further includes: forming a bit line structure at the bottom of the second groove, the bit line structure being electrically connected to one end of the source region or the drain region; and forming a storage structure at the other end of the source region or the drain region, the storage structure being electrically connected to the other end of the source region or the drain region.

[0021] In this embodiment, a first oxide layer and a first isolation layer are formed in the source region and / or drain region of the active device, and the thickness of the first oxide layer is less than or equal to 2 nanometers. This can prevent the first isolation layer from directly contacting the source region and / or drain region to form a very high interface state density, which would lead to an increase in turn-off voltage and leakage current. At the same time, the thickness of the first oxide layer is less than or equal to 2 nanometers, which can reduce the loss of the active device and reduce the contact resistance between the active device and the bit line and / or memory structure. Attached Figure Description

[0022] Figure 1 is a three-dimensional schematic diagram of a transistor structure according to an exemplary embodiment;

[0023] Figure 2 is a cross-sectional view along the position line direction of the three-dimensional schematic diagram shown in Figure 1;

[0024] Figure 3 is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0025] Figure 4 is a top view schematic diagram of a memory according to an exemplary embodiment;

[0026] Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are schematic cross-sectional views of the memory along the aa' direction during the fabrication process.

[0027] Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are schematic cross-sectional views of the memory along the bb' direction during the fabrication process.

[0028] Figures 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, and 13C are schematic cross-sectional views of the memory along the cc' direction during the fabrication process.

[0029] Figures 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, and 13D are schematic cross-sectional views of the memory along the dd' direction during the fabrication process.

[0030] Figure 14 is a partially enlarged schematic diagram of the cross-section shown in Figure 13A.

[0031] Explanation of reference numerals in the attached figures: 10: Substrate; 11: Active material; 111: Drain region; 112: Channel region; 113: Source region; 12: First oxide layer; 13: First isolation layer; 14: Gate oxide layer; 15: Gate conductive layer; 16: Bit line structure; 17: Storage structure; 18: Second isolation layer; 19: Third isolation layer; 191: First isolation sublayer; 192: Second isolation sublayer; T1: First trench; T2: Second trench; T3: Third trench; T4: Fourth trench; T5: Fifth trench. Detailed Implementation

[0032] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0033] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0034] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0035] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0036] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0037] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0038] Figure 1 is a perspective view of a transistor structure according to an exemplary embodiment; Figure 2 is a cross-sectional view along the bit line direction of the perspective view shown in Figure 1. Referring to Figures 1 and 2, the transistor structure includes an active body 11, which includes a source region 113, a drain region 111, and a channel region 112 located between the source region 113 and the drain region 111; a first oxide layer 12, located on the surface of the source region 113 and / or the drain region 111, with a thickness of less than or equal to 2 nanometers; a first isolation layer 13, located on the side of the first oxide layer 12 away from the source region 113 and / or the drain region 111; a gate oxide layer 14, located on the surface of the channel region 112; and a gate conductor. The gate conductive layer 15 is located on the side of the gate oxide layer 14 away from the channel region 112. The first oxide layer 12 is located between the first isolation layer 13 and the source region 113 and / or the drain region 111. This can prevent the first isolation layer from directly contacting the source region 113 and / or the drain region 111. A very high interface state density is formed in the contact area between the first isolation layer and the source region 113 and / or the drain region 111, which makes the source region 113 and / or the drain region 111 prone to leakage. At the same time, the thickness of the first oxide layer 12 is less than or equal to 2 nanometers, which will not significantly reduce the diameter of the source region 113 and / or the drain region 111. This will increase the contact resistance between the source region 113 and / or the drain region 111 and the bit line and the diameter of the memory structure, affecting the performance of the transistor structure.

[0039] Referring again to Figures 1 and 2, in some embodiments, the active body 11 can be arranged parallel to the substrate, perpendicular to the substrate, stacked parallel to the substrate, or stacked perpendicular to the substrate, etc. The shape of the active body 11 can be one or more shapes such as strip, strip, cylinder, conical column, fork, or U-shape. The material of the active body 11 is silicon, which can be single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, germanium silicon, silicon-on-insulator, or germanium-on-insulator, or combinations thereof. The active body 11 includes a source region 113, a drain region 111, and a channel region 112 located between the source region 113 and the drain region 111. The direction of the channel region 112 is consistent with the extension direction of the active body.

[0040] Referring again to Figures 1 and 2, in some embodiments, the first oxide layer 12 is located on the surface of the source region 113 and / or the drain region 111. That is, it can be located only on the surface of the source region 113, or only on the surface of the drain region 111, or simultaneously on the surfaces of both the source region 113 and the drain region 111. It can be located on one side, both sides, three sides, or surrounding the source region 113 and / or the drain region 111. The first oxide layer 12 can be formed using an in-situ steam generation (ISSG) process, where hydrogen and oxygen are introduced into the surface of the source region 113 and / or the drain region 111 to generate water vapor at high temperature, thereby oxidizing the silicon material on the surface of the source region 113 and / or the drain region 111 to generate a silicon dioxide layer. The silicon dioxide layer prepared using the in-situ steam generation (ISSG) process has a more compact atomic arrangement at the interface, closer to a single-crystal structure, due to the direct bonding between silicon and oxygen on the surface of the source region 113 and / or drain region 111. This results in low defect density, low stress, and an interface state density that can be lower than 1*10^6. 10 cm -2The following measures can prevent problems such as threshold voltage drift, increased leakage current, and decreased reliability in transistor structures caused by high interface state density. Furthermore, the silicon dioxide layer prepared using In-Situ Steam Generation (ISSG) offers strong process controllability. The thickness of the silicon dioxide layer can be effectively controlled according to process requirements, reducing silicon consumption on the surface of source region 113 and / or drain region 111, increasing the area of ​​source region 113 and / or drain region 111, and reducing contact resistance with bit lines and memory structures. Finally, the silicon dioxide layer prepared using In-Situ Steam Generation (ISSG) has a relatively high density, making it less susceptible to etching. This allows for etching selectivity compared to silicon dioxide layers formed using Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other methods. When etching silicon dioxide layers formed by other methods, the silicon dioxide layer prepared using In-Situ Steam Generation (ISSG) may not be etched.

[0041] Referring again to Figures 1 and 2, in some embodiments, the first isolation layer 13 is located on the side of the first oxide layer 12 away from the source region 113 and / or the drain region 111. The area of ​​the first isolation layer 13 is greater than or equal to the area of ​​the first oxide layer 12, conformally covering the first oxide layer 12, which can protect the first oxide layer 12 from damage during subsequent processes. The material of the first isolation layer 13 can be silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof.

[0042] Referring again to Figures 1 and 2, in some embodiments, the gate oxide layer 14 is located on the surface of the channel region 112. The gate oxide layer 14 may be located on one side, two sides, three sides, or surround the channel region 112. The gate oxide layer 14 may be prepared by in-situ steam generation (ISSG), rapid thermal oxidation (RTO), atomic layer deposition (ALD), chemical vapor deposition (CVD), and the material of the gate oxide layer 14 is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof. The gate conductive layer 15 is located on the side of the gate oxide layer 14 away from the channel region 112. It can conformally cover the surface of the gate oxide layer 14, for example, located on one, two, three sides of the channel region 112 or surrounding the channel region 112. It can also partially overlap with the gate oxide layer 14, independently located on one, two, three sides of the channel region 112 or surrounding the channel region 112. The area of ​​the gate conductive layer 15 is less than or equal to the area of ​​the gate oxide layer 14. The gate conductive layer 15 can be produced using one or more methods such as chemical vapor deposition (CVD), physical vapor deposition (CVD), sputtering, and electroplating. The material of the gate conductive layer 15 can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), and nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, and Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon and conductive doped silicon germanium).

[0043] Referring again to Figures 1 and 2, in some embodiments, the surface of the first isolation layer 13 away from the active body 10 is flush with the surface of the gate conductive layer 15 away from the active body 10. The first isolation layer 13 is located on the side of the first oxide layer 12 away from the source region 113 and / or the drain region 111, and the gate conductive layer 15 is located on the side of the gate oxide layer 14 away from the channel region 112. The thickness of the first oxide layer is less than or equal to 2 nanometers. The thickness of the gate oxide layer 14 is adjusted according to the device performance requirements, so the side of the gate oxide layer 14 away from the channel region 112 is not necessarily flush with the side of the first oxide layer 12 away from the source region 113 and / or the drain region 111. The first oxide layer 12 and the first isolation layer... 13. The thicknesses of the gate oxide layer 14 and the gate conductive layer 15 are different, but they restrict each other. In addition, the diameter of the channel region 112 can also be different from the diameter of the source region 113 and / or the drain region 111. The diameter of the channel region 112 is smaller than the diameter of the source region 113 and / or the drain region 111, forming a dumbbell-shaped active body 10. This can provide process space for the gate oxide layer 14 and the gate conductive layer 15, reducing the difficulty of the fabrication process. The surface of the first isolation layer 13 away from the active body 10 is flush with the surface of the gate conductive layer 15 away from the active body 10, which can make the outer surface of the transistor flush, which is beneficial to simplify the fabrication process and can effectively control the distance between adjacent transistor structures.

[0044] Referring again to Figures 1 and 2, in some embodiments, the doping type of the source region 113 and the drain region 111 is different from that of the channel region 112. For example, the doped ions in the formed source region 113 and drain region 111 are P-type ions, which may include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions. The doped ions in the channel region are N-type ions, which may include, but are not limited to, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, forming a PN junction. In a P-type transistor structure, the source region 113 and drain region 111 can be doped with N-type ions, which can include, but are not limited to, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. The channel region is doped with P-type ions, which can include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions, forming an NPN transistor structure. Taking the channel region 112 as an example, the P-type ion doping concentration of the channel region 112 can be 10. 17 -10 18 atoms / cm 3The gate conductive layer 15 extends on the surface of part of the source region 113 and the drain region 111, with an extension length of 5 nanometers to 15 nanometers. It can more effectively adjust the conductivity of the channel through the electric field, improve the gate's control accuracy of carrier distribution, thereby optimizing the switching characteristics of the device, alleviating the drain-induced barrier reduction (DIBL) problem, and improving the device's stability and anti-interference ability.

[0045] Referring again to Figures 1 and 2, in some embodiments, the doping type of the source region 113 and drain region 111 is the same as that of the channel region 112. The source region 113 and drain region 111 are co-doped with P-type ions, which can include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions, forming a P-type junctionless transistor structure. The source region 113 and drain region 111 are co-doped with N-type ions, which can include, but are not limited to, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, forming an N-type junctionless transistor structure. Taking the N-type junctionless transistor structure as an example, the N-type ion concentration in the channel region 112 can be 10-1. 16 -3*10 16 atoms / cm 3 The gate conductive layer 15 extends on the surface of part of the source region 113 and the drain region 111, with an extension length of 15 nanometers to 20 nanometers. It can more effectively adjust the conductivity of the channel through the electric field, improve the gate's control accuracy of carrier distribution, thereby optimizing the switching characteristics of the device, alleviating the drain-induced barrier reduction (DIBL) problem, and improving the device's stability and anti-interference ability.

[0046] Referring again to Figures 1 and 2, this embodiment of the present disclosure also provides a memory, which includes the transistor structure described above, and further includes a bit line structure 16, which is electrically connected to one end of the source region 113 or the drain region 111; and a storage structure 17, which is electrically connected to the other end of the source region 113 or the drain region 111. The switching on and off of the transistor is controlled by a voltage signal on the gate conductive layer 15, thereby reading data information stored in the storage structure 17 through the bit line structure 16, or writing data information into the storage structure 17 for storage through the bit line structure 16. In some embodiments, the bit line structure 16 is made of a conductive material, which may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). In some embodiments, a transition contact layer (not shown) is further provided between the bit line structure 16 and the source region 113 or the drain region 111. The transition contact layer is made of a conductive material, which may be a metal silicide material, to reduce the contact resistance between the bit line structure 16 and the source region 113 or the drain region 111.

[0047] Referring again to Figures 1 and 2, in some embodiments, the storage structure 17 is electrically connected to the other end of the source region 113 or the drain region 111. The storage structure 17 may include one or more of a capacitor, a ferroelectric storage structure, a phase change storage structure, a resistive switching storage structure, and a magnetic switching storage structure, for storing information transmitted from the bit line structure 16.

[0048] In some embodiments, the memory is an array structure composed of multiple transistors. Multiple gate conductive layers 15 extend along a second direction to form word line structures. Each word line structure is connected to an active body structure arranged along the second direction. Multiple bit line structures 16 extend along a first direction. Each bit line structure 16 is connected to an active body structure arranged along the first direction. A second isolation layer 18 is provided between adjacent bit line structures 16, and a third isolation layer 19 is provided between adjacent word line structures. The second isolation layer 18 and the third isolation layer 19 are made of low dielectric constant materials, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. The materials of the second isolation layer 18 and the third isolation layer 19 can be the same or different, thereby reducing the coupling between adjacent word line structures and between adjacent bit line structures 17. The second isolation layer 18 and the third isolation layer 19 can be processed by deposition processes, which may include, but are not limited to, at least one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0049] Figure 3 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 4 is a top view of a memory according to an exemplary embodiment; Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are cross-sectional views of the memory along the aa' direction during fabrication; Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are cross-sectional views of the memory during fabrication. Figure 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, and 13C are cross-sectional schematic diagrams of the memory along the cc' direction during the fabrication process; Figure 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, and 13D are cross-sectional schematic diagrams of the memory along the dd' direction during the fabrication process; Figure 14 is a partially enlarged schematic diagram of the cross-sectional schematic diagram shown in Figure 5A.

[0050] The method for fabricating a memory according to an embodiment of this disclosure will now be described in detail with reference to the accompanying drawings. Referring to FIG3, the fabrication method includes at least the following steps:

[0051] S310: An active body is formed on the substrate, the active body including a source region, a drain region and a channel region located between the source region and the drain region;

[0052] S320: A first oxide layer is formed on the surface of the source region and / or drain region, and the thickness of the first oxide layer is less than or equal to 2 nanometers;

[0053] S330: A first isolation layer is formed on the side of the first oxide layer away from the source region and / or drain region;

[0054] S340: A gate oxide layer is formed on the surface of the channel region; a gate conductive layer is formed on the side of the gate oxide layer away from the channel region.

[0055] It should be understood that the steps shown in Figure 3 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 3 can be adjusted according to actual needs.

[0056] In the semiconductor structure manufacturing method disclosed herein, firstly, forming a vertical transistor structure on a substrate can reduce the area occupied by the transistor structure and increase the storage density. Secondly, forming a first oxide layer on the surface of the source or drain region of the transistor structure can reduce the interface state density on the surface of the source or drain region of the transistor structure, and can prevent problems such as threshold voltage drift, increased leakage current, and decreased reliability caused by high interface state density. Thirdly, the thickness of the formed first oxide layer is less than or equal to 2 nanometers, which reduces silicon consumption on the surface of the source or drain region, increases the area of ​​the source or drain region, and reduces the contact resistance of the storage structure.

[0057] Figure 4 is a top view schematic diagram of a memory according to an exemplary embodiment. In some embodiments, multiple active body structures 11 are arranged in an array, multiple gate conductive layers 15 extend along a second direction and are arranged along a first direction to form a gate conductive layer structure 15 forming a word line structure. Each word line structure connects to the active body structures 11 arranged along the second direction. Multiple bit line structures 16 extend along the first direction and are arranged along the second direction. Each bit line structure 16 connects to the active body structures 11 arranged along the first direction, wherein the first direction and the second direction are perpendicular. aa' is a cross-sectional schematic diagram along the bit line structure 16, bb' is a cross-sectional schematic diagram along the bit line structure, cc' is a cross-sectional schematic diagram along the gate conductive layer 15, and dd' is a cross-sectional schematic diagram along the gate conductive layer 15.

[0058] Referring to Figures 3, 4, 5A, 5B, 5C, and 5D, in some embodiments, a substrate 10 is provided. The material of the substrate 10 includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. In this application, a single-crystal silicon substrate is used as an example for illustration.

[0059] Referring to Figures 3, 6A, 6B, 6C, and 6D, in some embodiments, S310: an active body is formed on the substrate as an active pillar 11, wherein the method for forming the active pillar 11 includes patterning and etching a plurality of first grooves T1 extending along a first direction and arranged along a second direction on the substrate 10. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, photoresist can be deposited on the surface of the mask layer, an etching pattern can be formed on the photoresist after exposure, and the mask layer and the substrate 10 can be etched along the etching pattern to form the first grooves T1. The method for depositing the mask layer can include, but is not limited to, at least one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The etching method can be dry etching, wet etching, or a combination thereof.

[0060] Referring to Figures 7A, 7B, 7C, and 7D, in some embodiments, a second isolation material is deposited in the first groove T1, and then ground flat to form a second isolation layer 18. The material of the second isolation layer 18 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, thereby reducing the coupling between adjacent bit line structures 17. The second isolation layer 18 can be deposited using a deposition process, which may include, but is not limited to, at least one of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PED), and Spin-on Dielectric (SOD). Embodiments in this application are illustrated using silicon oxide as an example.

[0061] Referring to Figures 8A, 8B, 8C, and 8D, in some embodiments, a plurality of second grooves T2 extending along a second direction and arranged along a first direction are patterned and etched on the substrate 10. The first groove T1 and the second groove T2 are perpendicular to each other, and the depth of the first groove T1 is greater than the depth of the second groove T2, forming an active pillar 11 perpendicular to the substrate 10. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, photoresist can be deposited on the surface of the mask layer, and after exposure, an etching pattern is formed on the photoresist. The mask layer, part of the second isolation layer 18, and the substrate 10 are etched along the etching pattern to form the second grooves T2. The method of depositing the mask layer can include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric layer deposition. At least one of the following processes: Dielectric (SOD) and others. The etching method can be dry etching, wet etching, or a combination thereof.

[0062] Referring to Figures 9A, 9B, 9C, and 9D, in some embodiments, a third isolation material is deposited in the second groove T2, and then ground flat to form a third isolation layer 19. The third isolation layer 19 includes a first isolation sublayer 191 and a second isolation sublayer 192. The first isolation sublayer 191 is deposited on the sidewall of the second groove T2, and the second isolation sublayer 192 is deposited within the first isolation sublayer 191. The first and second isolation sublayers 191 and 192 completely fill the second groove T2. The materials of the first and second isolation sublayers 191 and 192 can be low-dielectric-constant materials, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, thereby reducing coupling between adjacent active pillar structures 11. The materials of the first and second isolation sublayers 191 and 192 can be the same or different. The first and second isolation sublayers 191 and 192 can be deposited using processes including, but not limited to, chemical vapor deposition (CVD). At least one of the following processes is used: physical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The first isolation sublayer 191 and the second isolation sublayer 192 can be fabricated using the same or different processes. In this embodiment, the first isolation sublayer 191 is made of silicon oxide, and the second isolation sublayer 192 is made of silicon nitride.

[0063] Referring to Figures 10A, 10B, 10C, and 10D, in some embodiments, a portion of the second isolation layer 18 and a portion of the first isolation sublayer 191 are selectively etched away to expose the source region 113 or the drain region 111, or a portion of the source region 113 or the drain region 111, forming a third groove T3. The third groove T3 surrounds the source region 113 or the drain region 111 and extends in the second direction. As can be seen from the above, the materials of the second isolation layer 18 and the first isolation sublayer 191 are both... The material of the active pillar 11 is single-crystal silicon, and the material of the second isolation sublayer 192 is silicon nitride. A method with etching selectivity can be selected, such as dry etching or wet etching, to etch away part of the second isolation layer 18 and part of the first isolation sublayer 191, while retaining the active pillar 11 and the second isolation sublayer 192, forming a third groove T3 that exposes the source region 113 or the drain region 111. Through selective etching, the number of photomasks can be reduced, the process time can be reduced, and the generation efficiency can be improved.

[0064] Referring to Figures 3, 11A, 11B, 11C, and 11D, in some embodiments, S320: A first oxide layer 12 is formed on the surface of the source region 113 or the drain region 111 using an in-situ steam generation (ISSG) process. The process time is controlled so that the thickness of the first oxide layer is less than or equal to 2 nanometers. Specifically, hydrogen and oxygen are introduced into the surface of the source region 113 or the drain region 111 to generate water vapor at high temperature, thereby oxidizing the silicon material on the surface of the source region 113 and / or the drain region 111 to generate a silicon dioxide layer. The silicon dioxide layer prepared using the in-situ steam generation (ISSG) process is advantageous because the silicon and oxygen on the surface of the source region 113 or the drain region 111 are directly bonded, resulting in a denser interfacial atomic arrangement, closer to a single-crystal structure, lower defect density, lower stress, and an interfacial state density that can be lower than 1*102. 10 cm -2 The following measures can prevent problems such as threshold voltage drift, increased leakage current, and decreased reliability in transistor structures caused by high interface state density. Furthermore, the silicon dioxide layer prepared using in-situ steam generation (ISSG) offers strong process controllability. The thickness of the generated silicon dioxide layer can be effectively controlled according to process requirements, reducing silicon consumption on the surface of source region 113 and / or drain region 111, increasing the area of ​​source region 113 and / or drain region 111, and reducing contact resistance with bit lines and memory structures. Finally, the silicon dioxide layer prepared using in-situ steam generation (ISSG) has a relatively high density and is not easily etched. This allows for a higher etching selectivity compared to silicon dioxide layers formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other methods. When etching silicon dioxide layers formed by other methods (e.g., the second isolation layer 18 and the first isolation sub-layer 191), the silicon dioxide layer prepared using in-situ steam generation (ISSG) may not be etched. Since in-situ steam generation (ISSG) can only oxidize the silicon material in the source region 113 and / or the drain region 111, the first oxide layer 12 is not formed on the surface of the first isolation sub-layer 192.

[0065] Referring again to Figures 3, 11A, 11B, 11C, and 11D, in some embodiments, S330: A first isolation layer 13 is deposited on the surface of the first oxide layer 12. The first isolation layer 13 fills the gap between the first oxide layer 12 and the second isolation sublayer 192 along the first direction, forming a third groove T4 spaced apart in the second direction. After the first isolation layer 13 is formed, the surface of the area of ​​the source region 113 and / or the drain region 111 is sequentially deposited with the first oxide layer 12 and the first isolation layer 13, while the second isolation layer 18 is exposed and the fourth groove T4 spaced apart in the second direction is arranged. The first isolation layer 13 is a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride, thereby reducing the coupling between adjacent active pillars 11. The first isolation layer 13 can be produced by a deposition process, which may include, but is not limited to, at least one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0066] Referring to Figures 12A, 12B, 12C, and 12D, in some embodiments, a portion of the second isolation layer 18 and a portion of the first isolation sublayer 191 are etched along the fourth groove T4 to expose the channel region 112, forming a fifth groove T5. Since the density of the first oxide layer 12 formed using the in-situ steam generation (ISSG) process is relatively high, and the surface of the first oxide layer 12 is protected by the first isolation layer 13, the first oxide layer 12 will not be damaged even when the second isolation layer 18 and the first isolation sublayer 191 are etched. The fifth groove T5 extends along the second direction, exposing the periphery of the channel region 112, leaving sufficient process space for the subsequent fabrication of the gate conductive layer 15.

[0067] Referring to Figures 3, 13A, 13B, 13C, and 13D, in some embodiments, S340: a gate oxide layer 14 is formed on the surface of the channel region 112, and a gate conductive layer 15 is formed on the surface of the gate oxide layer. The gate oxide layer can be formed using one or more processes such as in-situ steam generation (ISSG), chemical vapor deposition (CVD), atomic layer deposition (ALD), and high-density plasma deposition (HDP). The material of the gate oxide layer 14 is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof. In some embodiments, the channel region 112 can be trimmed by etching away some silicon atoms on the surface of the channel region to form a dumbbell-shaped active pillar 11. This provides sufficient process space for the formation of the gate oxide layer 14 and the gate conductive layer 15, improving gate control capability and transistor performance. The gate conductive layer 15 is made of a conductive material, which may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The gate conductive layer 15 can be formed by one or more of the following methods: chemical vapor deposition (CVD), physical vapor deposition (CVD), sputtering, electroplating, etc.

[0068] Figure 14 is a partially enlarged cross-sectional view of the cross-section shown in Figure 13A. In some embodiments, due to the presence of the second isolation sublayer 192, in the first direction, the surface of the first isolation layer 13 away from the active body is flush with the surface of the gate conductive layer 15 away from the active body.

[0069] Referring again to Figures 14, 9A, 9B, 9C, and 9D, in some embodiments, before forming the first isolation sublayer 191 and the second isolation sublayer 192 within the second groove T2, a bit line structure 16 is also formed at the bottom of the second groove T2. The bit line structure 16 extends along a first direction and connects the drain region 111 or the source region 113 arranged along the first direction. The bit line structure 16 is made of a conductive material, and the material of the bit line structure 16 may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo)). The materials used include: niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), and nickel (Ni); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, and Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon and conductive doped silicon-germanium). In some embodiments, a transition contact layer (not shown) is further provided between the bit line structure 16 and the source region 113 or the drain region 111. The transition contact layer is made of a conductive material, which may be a metal silicide material, to reduce the contact resistance between the bit line structure 16 and the source region 113 or the drain region 111.

[0070] Referring again to Figures 14, 8A, 8B, 8C, and 8D, in some embodiments, after forming the second groove T2 and exposing the active pillar 11, ion implantation can be performed on the active pillar to form a drain region 111, a channel region 112, and a source region 113. The drain region 111, channel region 112, and source region 113 are arranged in a direction perpendicular to the substrate. In some embodiments, the doping type of the source region 113 and drain region 111 is different from the doping type of the channel region 112. For example, the doped ions in the formed source region 113 and drain region 111 are P-type ions. P-type ions can include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions. The doped ions in the channel region are... The ion type is N-type ion, which can include, but is not limited to, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, forming a PNP transistor structure. Alternatively, the source region 113 and drain region 111 can be doped with N-type ions, which can include, but are not limited to, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. The channel region is doped with P-type ions, which can include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions, forming an NPN transistor structure. Taking the channel region 112 as an example, the P-type ion doping concentration of the channel region 112 can be 10. 17 -1018 atoms / cm 3 The gate conductive layer 15 extends on the surface of part of the source region 113 and the drain region 111, with an extension length of 5 nanometers to 15 nanometers. It can more effectively adjust the conductivity of the channel through the electric field, improve the gate's control accuracy of carrier distribution, thereby optimizing the switching characteristics of the device, alleviating the drain-induced barrier reduction (DIBL) problem, and improving the device's stability and anti-interference ability.

[0071] In other embodiments, the doping type of the source region 113 and drain region 111 is the same as that of the channel region 112. The source region 113 and drain region 111 are co-doped with P-type ions, which can include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions, forming a P-type junctionless transistor structure. The source region 113 and drain region 111 are co-doped with N-type ions, which can include, but are not limited to, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, forming an N-type junctionless transistor structure. Taking the N-type junctionless transistor structure as an example, the N-type ion concentration in the channel region 112 can be 10-1. 16 -3*10 16 atoms / cm 3 The gate conductive layer 15 extends on the surface of part of the source region 113 and the drain region 111, with an extension length of 15 nanometers to 20 nanometers. It can more effectively adjust the conductivity of the channel through the electric field, improve the gate's control accuracy of carrier distribution, thereby optimizing the switching characteristics of the device, alleviating the drain-induced barrier reduction (DIBL) problem, and improving the device's stability and anti-interference ability.

[0072] Referring again to FIG14, in some embodiments, after forming the gate conductive layer 15, a storage structure 17 is further formed on the upper part of the source region 113 or the drain region 112. The storage structure 17 is electrically connected to one end of the source region 113 or the drain region 111. The storage structure 17 may include one or more of a capacitor, a ferroelectric storage structure, a phase change storage structure, a resistive switching storage structure, and a magnetic switching storage structure, for storing information transmitted from the bit line structure 16.

[0073] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A transistor structure, characterized in that, include: An active body (11) includes a source region (113), a drain region (111), and a channel region (112) located between the source region (113) and the drain region (111); A first oxide layer (12) is located on the surface of the source region (113) and / or the drain region (111), and the thickness of the first oxide layer (12) is less than or equal to 2 nanometers. A first isolation layer (13) is located on the side of the first oxide layer (12) away from the source region (113) and / or the drain region (111); A gate oxide layer (14) is located on the surface of the channel region (112); A gate conductive layer (15) is located on the side of the gate oxide layer (14) away from the channel region (112).

2. The transistor structure according to claim 1, characterized in that, The active body (11) can be arranged parallel to the substrate, perpendicular to the substrate, or stacked parallel to the substrate in any one of the following ways: The active body (11) is made of silicon.

3. The transistor structure according to claim 1 or 2, characterized in that, The gate conductive layer (15) may be located on one side, two sides, three sides of the channel region (112) or surround the channel region (112).

4. The transistor structure according to any one of claims 1-3, characterized in that, The surface of the first isolation layer (13) away from the active body (11) is flush with the surface of the gate conductive layer (15) away from the active body (11).

5. The transistor structure according to any one of claims 1-4, characterized in that, The doping type of the source region (113) and the drain region (111) is different from that of the channel region (112).

6. The transistor structure according to claim 5, characterized in that, The gate conductive layer (15) also extends on the surface of a portion of the source region (113) and the drain region (111), with an extension length of 5 nanometers to 15 nanometers.

7. The transistor structure according to any one of claims 1-6, characterized in that, The doping type of the source region (113) and the drain region (111) is the same as that of the channel region (112).

8. The transistor structure according to claim 7, characterized in that, The gate conductive layer (15) also extends on the surface of a portion of the source region (113) and the drain region (111), with an extension length of 15 nanometers to 20 nanometers.

9. A memory, characterized in that, include: The transistor structure as described in any one of claims 1 to 8; Bit line structure (16), wherein the bit line structure (16) is electrically connected to one end of the source region (113) or the drain region (111); Storage structure (17), wherein the storage structure (17) is electrically connected to the other end of the source region (113) or the drain region (111); A second isolation layer (18) is located between adjacent bit line structures (16); A third isolation layer (19) is located between adjacent gate conductive layers (15).

10. A method for fabricating a memory, characterized in that, An active body (11) is formed on a substrate, the active body (11) including a source region (113), a drain region (111), and a channel region (112) located between the source region (113) and the drain region (111); A first oxide layer (12) is formed on the surface of the source region (113) and / or the drain region (111), wherein the thickness of the first oxide layer (12) is less than or equal to 2 nanometers; A first isolation layer (13) is formed on the side of the first oxide layer (12) away from the source region (113) and / or the drain region (111); A gate oxide layer (14) is formed on the surface of the channel region (112); A gate conductive layer (15) is formed on the side of the gate oxide layer (14) away from the channel region (112).

11. The preparation method according to claim 10, characterized in that, The active body (11) is an active pillar perpendicular to the substrate, and the method for preparing the active pillar includes: A first groove (T1) extending along a plurality of first directions and arranged along a second direction is etched on the substrate, and a second isolation layer (18) is filled in the first groove (T1); A second groove (T2) extending along a plurality of second directions and arranged along the second directions is formed on the substrate, and a third isolation layer (19) is filled in the second groove (T2); The depth of the first groove (T1) is greater than the depth of the second groove (T2); The first direction is perpendicular to the second direction.

12. The preparation method according to claim 11, characterized in that, A first oxide layer (12) is formed on the surface of the source region (113) and / or the drain region (111), the first oxide layer (12) having a thickness of less than or equal to 2 nanometers, comprising: A third isolation layer (19) is filled in the second groove (T2). The third isolation layer (19) includes a first isolation sub-layer and a second isolation sub-layer. The first isolation sub-layer is located on the side wall of the second groove (T2), and the second isolation sub-layer is located inside the first isolation sub-layer. Etching removes part of the second isolation layer (18) and part of the first isolation sublayer, exposing the source region (113) or drain region (111); A first oxide layer (12) is formed on the surface of the source region (113) or the drain region (111) using an in-situ water vapor generation process, wherein the thickness of the first oxide layer (12) is less than or equal to 2 nanometers.

13. The preparation method according to claim 12, characterized in that, A gate conductive layer (15) is formed on the side of the gate oxide layer (14) away from the channel region (112), comprising: A first isolation layer (13) is formed on the side of the first oxide layer (12) away from the source region (113) and / or the drain region (111); Etching removes part of the first isolation sublayer and part of the second isolation layer (18) to expose the trench region (112); A gate oxide layer (14) is formed on the surface of the channel region (112); A gate conductive layer (15) is formed on the side of the gate oxide layer (14) away from the channel region (112).

14. The preparation method according to claim 11, characterized in that, Also includes: A bit line structure (16) is formed at the bottom of the second groove (T2), and the bit line structure (16) is electrically connected to one end of the source region (113) or the drain region (111); A storage structure (17) is formed at the other end of the source region (113) or the drain region (111), and the storage structure (17) is electrically connected to the other end of the source region (113) or the drain region (111).

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