Semiconductor device and manufacturing method therefor, and electronic device
Patent Information
- Application Number
- PCT/CN2025/140835
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-28
- Filing Date
- 2025-12-08
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025140835_01102026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their fabrication methods, electronic devices
[0001] This application claims priority to Chinese patent application No. 202510387621.8, filed on March 28, 2025, entitled "Semiconductor Device and Preparation Method Thereof, Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field
[0002] This article relates to, but is not limited to, the field of semiconductor device technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology
[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This application provides a method for fabricating a semiconductor device, including:
[0006] A semiconductor substrate with a preset thickness is provided, the preset thickness being set as the dimension of the semiconductor substrate in a first direction, the first direction being perpendicular to the semiconductor substrate;
[0007] The semiconductor substrate is etched to form a plurality of semiconductor strips, all of which extend along a second direction. The plurality of semiconductor strips are arranged in an array in the first direction and the third direction. The second direction and the third direction are parallel to the semiconductor substrate, and the second direction intersects the third direction.
[0008] The memory cell is formed based on the semiconductor substrate.
[0009] In some exemplary embodiments, etching the semiconductor substrate to form a plurality of semiconductor strips includes:
[0010] A first dielectric layer is formed on the top surface of the semiconductor substrate. The first dielectric layer has a plurality of first trenches. The first trenches extend along a second direction. The plurality of first trenches are spaced apart in a third direction. The first trenches penetrate the first dielectric layer in the first direction to expose the semiconductor substrate.
[0011] The semiconductor substrate is etched using the first dielectric layer as a mask.
[0012] In some exemplary embodiments, forming a first dielectric layer on the top surface of the semiconductor substrate includes:
[0013] Hard mask material is deposited on the top surface and the outer periphery of the semiconductor substrate, and the hard mask material located on the outer periphery of the semiconductor substrate forms a support structure surrounding the semiconductor substrate;
[0014] The hard mask material located on the top surface of the semiconductor substrate is etched to form a plurality of the first trenches.
[0015] In some exemplary embodiments, the etching of the semiconductor substrate using the first dielectric layer as a mask includes:
[0016] The semiconductor substrate is etched using Bosch etching process until a plurality of second trenches and a plurality of lateral trenches are formed on the semiconductor substrate. The plurality of second trenches are spaced apart in the third direction, and the plurality of lateral trenches are spaced apart in the first direction.
[0017] The Bosch etching process includes a cyclic passivation process and an etching process.
[0018] The second trench is formed by recessing the semiconductor substrate to a predetermined depth in the first direction away from the first dielectric layer, and the second trench is configured to separate adjacent semiconductor strips in the third direction.
[0019] The lateral groove is formed by a recess in the sidewall of the second trench toward the third direction, and the lateral groove is configured to separate adjacent semiconductor strips in the first direction.
[0020] In some exemplary embodiments, the second trench includes a plurality of first grooves stacked in the first direction, wherein the first grooves of any two second trenches are arranged in a one-to-one correspondence in the third direction, and the lateral groove is configured to connect two adjacent first grooves in the third direction;
[0021] The etching process includes introducing an etching gas into the first trench, the etching gas generating plasma and etching the semiconductor substrate to form the first groove and the lateral groove, the lateral groove being located between two adjacent first grooves in the third direction.
[0022] In some exemplary embodiments, the passivation process includes:
[0023] Passivating gas is introduced into the first trench to form a first protective layer covering the trench wall, or to form a second protective layer covering the trench wall of the first groove and the trench wall of the lateral groove.
[0024] Remove the first protective layer covering the bottom wall of the first trench, or remove the second protective layer covering the bottom wall of the first trench.
[0025] In some exemplary embodiments, forming a memory cell based on the semiconductor substrate includes:
[0026] Remove the first protective layer, the second protective layer, and the first dielectric layer to expose the plurality of semiconductor strips;
[0027] A second element, a bit line, a first element, and a word line are sequentially formed on the semiconductor strip.
[0028] In some exemplary embodiments, the semiconductor substrate is made of silicon, germanium, silicon-germanium, or germanium-tin, wherein the silicon comprises single-crystal silicon with a crystal plane index of (111).
[0029] This application provides a semiconductor device including a substrate and a plurality of memory cell columns disposed on the substrate. Each memory cell column includes a plurality of memory cells, which are stacked along a first direction. Each memory cell includes a first element, which includes a semiconductor pillar and a gate electrode. The semiconductor pillar extends along a second direction, which is parallel to the substrate and the first direction is perpendicular to the substrate.
[0030] The substrate and the semiconductor pillar are formed by etching a semiconductor substrate of a preset thickness, the preset thickness being the dimension of the semiconductor substrate in the first direction.
[0031] In some exemplary embodiments, the semiconductor pillar is made of single-crystal silicon with a crystal plane index of (111).
[0032] In some exemplary embodiments, the semiconductor pillar has a rhomboid cross-section perpendicular to the second direction.
[0033] In some exemplary embodiments, the first element includes a gate insulating layer located between a semiconductor pillar and a gate electrode, the gate insulating layer having a rhomboid cross-section perpendicular to the second direction;
[0034] The storage cell further includes a second element disposed on the semiconductor pillar. The second element includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer. The first electrode layer, the capacitor dielectric layer, and the second electrode layer are arranged sequentially in a direction away from the semiconductor pillar. The cross-sections of the first electrode layer, the capacitor dielectric layer, and the second electrode layer perpendicular to the second direction are all set to rhombus shape.
[0035] In some exemplary embodiments, it also includes multiple bit lines and multiple word lines;
[0036] Multiple bit lines extend along the first direction, and multiple semiconductor pillars stacked at the same position along the first direction share the same bit line;
[0037] The extension direction of the word line is perpendicular to the extension direction of the semiconductor pillar. A plurality of memory cells are arranged at intervals along the extension direction of the word line. Each word line is formed by connecting the gate electrodes of the first elements of a plurality of memory cells arranged along the extension direction of the word line.
[0038] This application provides an electronic device, including a semiconductor device obtained according to the above-described semiconductor device fabrication method, or including the above-described semiconductor device.
[0039] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.
[0040] The semiconductor device fabrication method of this application embodiment can realize the processing and forming of multilayer semiconductor strips, and the fabricated semiconductor strips are strain-free, have a smaller dislocation density, are simpler to fabricate, and can effectively reduce the device manufacturing cost.
[0041] Overview of the attached figures
[0042] Figure 1 is a schematic diagram of a method for fabricating a semiconductor device according to an exemplary embodiment of the present invention;
[0043] Figure 2 is a schematic diagram of a semiconductor device according to an exemplary embodiment of this invention;
[0044] Figure 3 is a schematic diagram of section aa in Figure 2;
[0045] Figure 4 is a schematic diagram of the bb section in Figure 2;
[0046] Figure 5 is a schematic diagram of the cc section in Figure 2;
[0047] Figure 6 is a schematic diagram of another method for fabricating a semiconductor device according to this exemplary embodiment;
[0048] Figure 7 is a schematic cross-sectional view of a semiconductor substrate according to an exemplary embodiment of the present invention;
[0049] Figure 8 is a first fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of this invention;
[0050] Figure 9 is a second fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of this invention;
[0051] Figure 10 is a schematic diagram of the dd section in Figure 9;
[0052] Figure 11 is a third fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0053] Figure 12 is a fourth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0054] Figure 13 is a fifth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0055] Figure 14 is a sixth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0056] Figure 15 is a seventh fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0057] Figure 16 is an eighth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0058] Figure 17 is a ninth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0059] Figure 18 is a tenth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;
[0060] Figure 19 is a schematic diagram of the eleventh fabrication step of a semiconductor device according to this exemplary embodiment;
[0061] Figure 20 is a schematic diagram of the twelfth fabrication step of a semiconductor device according to this exemplary embodiment.
[0062] Detailed Explanation
[0063] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.
[0064] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.
[0065] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.
[0066] One technical approach to three-dimensional dynamic random access memory (3D-DRAM) requires the fabrication of dozens to hundreds of horizontally placed single-crystal silicon transistors. Currently, single-crystal silicon can only be grown using epitaxial technology. The fabrication technology for multilayer single-crystal silicon transistors is typically based on alternating epitaxial growth of silicon and germanium-silicon layers, followed by etching to remove the germanium-silicon layers to form multilayer single-crystal silicon. The applicant has found that this method is highly dependent on epitaxial equipment, and the more layers stacked, the greater the strain accumulated in the thin film. When the strain is released, many dislocations are generated, which is detrimental to the subsequent integration of devices.
[0067] Figure 1 is a schematic diagram of a semiconductor device fabrication method according to an exemplary embodiment of the present invention. As shown in Figure 1, the fabrication method may include: Step S1, providing a semiconductor substrate of a preset thickness, the preset thickness being set as the dimension of the semiconductor substrate in a first direction, the first direction being perpendicular to the semiconductor substrate; Step S2, etching the semiconductor substrate to form a plurality of semiconductor strips, the plurality of semiconductor strips extending along a second direction, the plurality of semiconductor strips being arranged in an array in the first direction and a third direction, the second direction and the third direction being parallel to the semiconductor substrate, and the second direction intersecting the third direction; Step S3, forming a memory cell based on the semiconductor substrate. The semiconductor device fabrication method of this embodiment can realize multilayer semiconductor strip processing and forming, and the fabricated semiconductor strips are strain-free, have lower dislocation density, are simpler to fabricate, and can effectively reduce device manufacturing costs.
[0068] Figure 2 is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention. Figure 3 is a schematic cross-sectional view of aa in Figure 2. Figure 4 is a schematic cross-sectional view of bb in Figure 2. Figure 5 is a schematic cross-sectional view of cc in Figure 2. In some exemplary embodiments, as shown in Figures 2 to 5, the semiconductor device may include a substrate 101, a plurality of memory cell columns 200, a plurality of bit lines 300, and a plurality of word lines 400. Each memory cell column 200 may include a plurality of memory cells 201 spaced apart on the substrate 101 along a first direction perpendicular to the substrate 101. Each memory cell 201 may include a first element 202 and a second element 203. Both the first element 202 and the second element 203 are electronic elements. The first element 202 may be a transistor, and the second element 203 may be a transistor or a capacitor. The first element 202 may include a semiconductor pillar 204 and a gate electrode 205. The semiconductor pillar 204 may extend along a second direction, which is parallel to the substrate 101 and intersects a third direction. The third direction is parallel to the substrate 101. In some exemplary embodiments, the third direction is perpendicular to the second direction. Each semiconductor pillar 204 may include a first region 206, a channel region 207, and a second region 208 arranged sequentially in a second direction. A gate electrode 205 may be disposed on the outer periphery of the channel region 207, and a second element 203 is configured to surround the end of the second region 208 away from the channel region 207. In this example, the second element 203 may be a capacitor, but is not limited thereto; for example, the second element 203 may be a transistor complementary to the first element 202. Multiple bit lines 300 extend along a first direction and are spaced apart in a third direction. Multiple memory cells 201 in two adjacent memory cell columns 200 in the second direction share a bit line 300. Multiple word lines 400 extend along a third direction. Multiple memory cell columns 200 are spaced apart in the third direction. Each word line 400 is formed by connecting the gate electrodes 205 of the first element 202 of the multiple memory cells 201 arranged along the third direction. However, it is not limited to this. For example, multiple bit lines 300 extend along a third direction and are spaced apart in the first direction. The bit lines 300 are parallel to the substrate 101. The memory cells 201 arranged along the third direction share a bit line 300. Multiple word lines 400 extend along the first direction and are perpendicular to the substrate 101. Each word line 400 is formed by connecting the gate electrode 205 of the first element 202 of the multiple memory cells 201 arranged along the first direction.
[0069] In some exemplary embodiments, as shown in Figures 2 to 5, the substrate 101 may be made of a semiconductor material. The substrate 101 may be a single-layer structure. For example, the substrate 101 may be a silicon (Si) substrate. The material of the substrate 101 may include single-crystal silicon with a crystal plane index of (111), but is not limited thereto. For example, the material of the substrate 101 may include semiconductor materials such as germanium (Ge), silicon germanium (SiGe), and germanium tin (GeSn).
[0070] In some exemplary embodiments, as shown in Figures 2 to 5, a plurality of memory cells 201 in a memory cell column 200 extend along a second direction, and the plurality of memory cells 201 in a memory cell column 200 are arranged at equal intervals along a first direction. In addition to including a semiconductor pillar 204 and a gate electrode 205, the first element 202 also includes a gate insulating layer 209 located between the semiconductor pillar 204 and the gate electrode 205. The semiconductor pillar 204 may extend along the second direction, and each semiconductor pillar 204 may include a first region 206, a channel region 207, and a second region 208 arranged sequentially. The material of the semiconductor pillar 204 may include semiconductor materials. For example, the semiconductor pillar 204 may be the same material as the substrate 101, i.e., the material of the semiconductor pillar 204 includes silicon, such as single-crystal silicon with a crystal plane index of (111), but is not limited thereto. For example, the materials of the semiconductor pillar 204 and the substrate 101 may both include semiconductor materials such as germanium (Ge), silicon-germanium (SiGe), and germanium-tin (GeSn). The oxide layer quality of single-crystal silicon with a crystal plane index of (111) is generally better than that of single-crystal silicon with a crystal plane index of (100). It also has a lower interface state density, making it suitable for applications requiring high-quality oxide layers in memory devices. The surface atoms of single-crystal silicon with a crystal plane index of (111) are more densely packed, resulting in lower surface energy, making it suitable for manufacturing high-quality thin films or interfaces and contributing to improved quality of interlayer insulating layers. Single-crystal silicon with a crystal plane index of (111) has a slower etching rate and stronger etching anisotropy, making it suitable for manufacturing precise beveled or vertical structures. In 3D memory or MEMS memory devices, single-crystal silicon with a crystal plane index of (111) helps to achieve more complex structures. Single-crystal silicon with a crystal plane index of (111) has better thermal stability, making it suitable for high-temperature processing steps and applicable to a wider range of memory devices.
[0071] In some exemplary embodiments, as shown in Figures 2 to 5, the cross-section of the semiconductor pillar 204 perpendicular to its extension direction can be a rhombus shape, which improves the transistor's electric field optimization, conduction performance, and switching speed. Currently, the electric field concentration problem at the corners of the channel of rectangular transistors is quite prominent, which easily leads to the risk of gate oxide breakdown. The rhombus-shaped semiconductor pillar 204 can optimize the channel shape, disperse the electric field intensity, and significantly reduce the breakdown risk.
[0072] In some exemplary embodiments, as shown in Figures 2 to 5, a gate insulating layer 209 is sandwiched between the channel region 207 and the gate electrode 205. The gate insulating layer 209 can be made of a high-dielectric-constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate insulating layer 209 can be formed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD. The cross-section of the gate insulating layer 209 is influenced by the morphology of the semiconductor pillar 204, and the cross-section of the gate insulating layer 209 is rhomboid. The gate electrode 205 can be disposed on the outer periphery of the channel region 207 of the semiconductor pillar 204. The material of the gate electrode 205 can be a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The material of the gate electrode 205 can also be conductive polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, amorphous silicon, etc. The cross-section of the gate electrode 205 is also affected by the morphology of the semiconductor pillar 204 and the gate insulating layer 209, and the cross-section of the gate electrode 205 is rhomboid.
[0073] In some exemplary embodiments, as shown in Figures 2 to 5, the second element 203 is a capacitor. The second element 203 is configured to surround the end of the second region 208 away from the channel region 207. The second element 203 may include a first electrode layer 210, a capacitor dielectric layer 211, and a second electrode layer 212 sequentially disposed outward from the semiconductor pillar 204. The first electrode layer 210 and the second electrode layer 212 may be made of metal or a conductive metal compound. In this example, the first electrode layer 210 and the second electrode layer 212 may be made of the same material, both of which are titanium nitride (TiN). The capacitor dielectric layer 211 may be made of a high dielectric constant dielectric material. The cross-sections of the first electrode layer 210, the capacitor dielectric layer 211, and the second electrode layer 212 are affected by the morphology of the semiconductor pillar 204, and the cross-sections of the first electrode layer 210, the capacitor dielectric layer 211, and the second electrode layer 212 are rhomboid.
[0074] In some exemplary embodiments, as shown in Figures 2 to 5, multiple bit lines 300 are provided, each bit line 300 extending along a first direction. The material of the bit lines 300 can be metal; in this example, the material of the bit lines 300 can be tungsten. Multiple memory cells 201 in a memory cell column 200 share a single bit line 300. The first element 202 of each memory cell 201 is located on the side of the second element 203 near the bit line 300. The first region 206 of the semiconductor pillar 204 is connected to the bit line 300. Two memory cell columns 200 arranged sequentially in the second direction can share a bit line 300. The first region 206 of the semiconductor pillar 204 of the multiple memory cells 201 of the two memory cell columns 200 are all connected to a bit line 300, but not limited to this. For example, the two memory cell columns 200 arranged sequentially in the second direction can each be connected to a bit line 300, that is, the multiple memory cells 201 of one memory cell column 200 are connected to one bit line 300, and the multiple memory cells 201 of the other memory cell column 200 are connected to another bit line 300.
[0075] In some exemplary embodiments, as shown in Figures 2 to 5, a word line 400 may be formed by connecting the gate electrodes 205 of a plurality of first elements 202. Multiple word lines 400 are provided, all extending along a third direction, and the material of the word line 400 may be metal. A plurality of memory cell columns 200 are arranged at equal intervals along a third direction. A plurality of memory cells 201 corresponding to each other in the third direction may be arranged at intervals along the third direction. The gate electrodes 205 of the plurality of memory cells 201 are connected to form a word line 400. This can also be understood as the gate electrodes 205 of the plurality of memory cells 201 being part of a single word line 400.
[0076] Figure 6 is a schematic diagram of another method for fabricating a semiconductor device according to this exemplary embodiment. As shown in Figure 6, a method for fabricating a semiconductor device can be applied to fabricating semiconductor devices as shown in Figures 2 to 5. The method includes:
[0077] S1: Prepare the semiconductor substrate.
[0078] Figure 7 is a schematic cross-sectional view of a semiconductor substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 7, preparing the semiconductor substrate includes:
[0079] A plate-shaped semiconductor substrate 100 is formed, perpendicular to a first direction. The thickness of the semiconductor substrate 100 can be the dimension of the semiconductor substrate 100 in the first direction. The preset thickness of the semiconductor substrate 100 can be L4, and the value of L4 can be from 500 μm to 1000 μm. In this exemplary embodiment, the value of L4 can be 700 μm. The preset thickness L4 can be determined according to the layer height of the semiconductor device. The semiconductor substrate 100 can be a silicon substrate, that is, the material of the semiconductor substrate 100 can include silicon, and can be single crystal silicon with a crystal plane index of (111), but is not limited thereto. For example, the material of the semiconductor substrate 100 can include semiconductor materials such as germanium (Ge), silicon germanium (SiGe), and germanium tin (GeSn). The semiconductor pillar 204 and the substrate 101 can be formed by etching the semiconductor substrate 100.
[0080] S2: Deposited hard mask material.
[0081] Figure 8 is a first fabrication schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 7 and 8, the deposition of a hard mask material includes:
[0082] A hard mask material 500 is deposited on the outer periphery of the semiconductor substrate 100 and on one side of the semiconductor substrate 100 in the first direction (the top surface of the semiconductor substrate 100). The hard mask material 500 can be made of a material with high temperature resistance, chemical corrosion resistance, and high mechanical strength, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or titanium nitride (TiN). The hard mask material 500 is mainly used to protect and guide the processing of the underlying material.
[0083] The hard mask material 500 covering the top surface of the semiconductor substrate 100 may be a first dielectric layer 501; the hard mask material 500 surrounding the outer periphery of the semiconductor substrate 100 may be a support structure 502.
[0084] S3: Formation of the first trench.
[0085] Figure 9 is a second fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention, and Figure 10 is a cross-sectional schematic diagram of the dd section in Figure 9. In some exemplary embodiments, as shown in Figures 8 to 10, a first trench is formed, including:
[0086] The hard mask material 500 covering the top surface of the semiconductor substrate 100 is etched to form a first dielectric layer 501 having a first trench 503. The first trench 503 extends along a second direction, and a plurality of first trenches 503 are arranged at intervals in a third direction. The first trenches 503 penetrate the first dielectric layer 501 in a first direction to expose the semiconductor substrate 100. The trench walls of the first trench 503 may include trench sidewalls 503-1 at both ends in the third direction and at both ends in the second direction, and trench bottom walls 503-2 of the first trench 503. The exposed semiconductor substrate 100 may constitute the trench bottom walls 503-2 of the first trench 503.
[0087] The minimum distance between adjacent first grooves 503 in the third direction is set to L1, the maximum size of the first groove 503 in the third direction is set to L3, and the ratio of L1 to L3 is set to 0.1 to 2. In this example, the ratio of L1 to L3 can be 1.
[0088] S4: Etch the semiconductor substrate to form semiconductor strips.
[0089] Figures 11 to 17 are schematic diagrams illustrating the fabrication of a semiconductor device according to an exemplary embodiment of the present invention. In some exemplary embodiments, as shown in Figures 10 to 17, etching is performed on the semiconductor substrate to form semiconductor strips, including:
[0090] The etching process employs Bosch etching technology, which involves cyclically performing passivation and etching processes until multiple second trenches spaced apart in a third direction and multiple lateral trenches spaced apart in a first direction are formed on the semiconductor substrate 100. The second trenches are configured to separate adjacent semiconductor strips in the third direction, and the lateral trenches are configured to separate adjacent semiconductor strips in the first direction. However, this is not a limitation; other etching processes can be used to form semiconductor strips.
[0091] In some exemplary embodiments, the structure formed in the previous step is placed in an inductively coupled plasma (ICP) etching machine for a Bosch etching process. The ICP etching machine generates high-density plasma, thereby improving the etching rate and selectivity. The Bosch etching process, also known as the Bosch process, is an advanced technology used in semiconductor manufacturing to etch specific material layers on silicon wafers. The Bosch etching process is particularly suitable for processing feature dimensions at the deep submicron scale. The Bosch process achieves highly anisotropic etching results by alternating etching and passivation steps. During passivation, a passivation gas can be introduced into the equipment, which can form a polymer film on the surface. In this example, the passivation gas can be octafluorocyclobutane (C4F8). During etching, an etching gas can be introduced into the equipment. The etching gas isotropically etches the semiconductor substrate 100. The polymer film formed by the passivation gas protects the structure it covers from etching by the etching gas. In this example, the etching gas can be sulfur hexafluoride (SF6).
[0092] In some exemplary embodiments, after Bosch etching process, semiconductor substrate 100 can be processed into substrate 101 and semiconductor strip 102, semiconductor strip 102 including two semiconductor pillars 204 as described above, that is, semiconductor strip 102 can be divided into two semiconductor pillars 204, both semiconductor pillars 204 extending along the second direction.
[0093] In some exemplary embodiments, the passivation and etching processes are performed cyclically, i.e., the passivation and etching processes are performed alternately. First, the structure formed in the previous step is passivated. As shown in Figures 10 and 11, passivation gas is introduced into the first trench 503 to form a protective layer 600. The protective layer 600 may include a first protective layer 601 covering the trench wall of the first trench 503. Subsequently, as shown in Figure 12, the first protective layer 601 covering the bottom wall 503-2 of the first trench 503 is removed, and a first opening 603 is formed on the first protective layer 601, exposing the semiconductor substrate 100, thus completing the first passivation process. Next, the first etching process is performed. Etching gas is introduced into the first trench 503, and the generated plasma etches the semiconductor substrate 100 in all directions. As shown in Figure 13, the etching direction can be as indicated by the arrows, i.e., etching downwards in a first direction or etching in a third direction. The first etching process forms a first groove 103 and a lateral groove 104 located between two adjacent first grooves 103 in the third direction. The groove wall of the first groove 103 may include the bottom wall 103-1 of the first groove 103 away from the first dielectric layer 501 in the first direction. The minimum distance between adjacent first grooves 503 in the third direction is set as L1, and the dimension of the first groove 103 in the first direction is set as L2. The ratio of L1 to L2 is set to 0.2 to 1. In this example, the ratio of L1 to L2 can be 1. The etching process can determine the flow rate and the time of etching gas introduction according to the required size of the first groove 103. For example, if a larger space of first groove 103 needs to be formed, the flow rate of etching gas and the time of etching gas introduction can be increased, or only the flow rate of etching gas can be increased, or only the time of etching gas introduction can be increased.
[0094] Then, a second passivation process is performed, as shown in Figures 13 and 14. Passivation gas is introduced into the first trench 503 to form a protective layer 600. The protective layer 600 may include a second protective layer 602 covering the first groove 103 and the side groove 104. Subsequently, as shown in Figure 15, the second protective layer 602 covering the bottom wall 103-1 of the first groove 103 is removed, and a second opening 604 is formed on the second protective layer 602, exposing the semiconductor substrate 100, thus completing the second passivation process. Next, a second etching process is performed. Etching gas is introduced into the first trench 503 and plasma is generated. The etching gas performs anisotropic etching on the semiconductor substrate 100, as shown in Figure 16. The etching direction can be as indicated by the arrow, that is, further etching downwards from the first groove 103. The second etching process yields another first groove 103 and a lateral groove 104 located between two adjacent first grooves 103 in the third direction. Two adjacent first grooves 103 in the first direction are stacked, and a rhomboid semiconductor strip 102 is formed between two adjacent lateral grooves 104 in the first direction. After a predetermined number of passivation and etching processes, as shown in FIG17, a plurality of second trenches 105 are formed on the semiconductor substrate 100. The second trenches 105 extend along a second direction, and the plurality of second trenches 105 are spaced apart in the third direction. Each second trench 105 includes a plurality of first grooves 103 stacked in the first direction, such that the second trench 105 can be recessed to a predetermined depth by the top surface of the semiconductor substrate 100, and the orthographic projection of the second trench 105 on the substrate 101 can overlap with the orthographic projection of the first trench 503 on the substrate 101. The second trenches 105 are configured to separate adjacent semiconductor strips 102 in the third direction. As shown in Figure 17, a plurality of lateral trenches 104 are also formed on the semiconductor substrate 100. The lateral trenches 104 are formed by the trench sidewall of the second trench 105 recessed in the third direction. The lateral trenches 104 on one side of any two second trenches 105 are arranged one-to-one in the third direction. The lateral trenches 104 connect two adjacent second trenches 105 in the third direction. The lateral trenches 104 are configured to separate adjacent semiconductor strips 102 in the first direction.
[0095] In some exemplary embodiments, as shown in FIG17, a semiconductor substrate 100 is etched to form a plurality of semiconductor strips 102 and a substrate 101. The plurality of semiconductor strips 102 extend along a second direction and are arranged in an array in a first direction and a third direction. The etched size of the semiconductor substrate 100 is smaller than a predetermined thickness of the semiconductor substrate 100, such that the remaining unetched portion of the semiconductor substrate 100 forms the substrate 101.
[0096] S5: Remove the protective layer.
[0097] Figure 18 is a tenth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 17 and 18, removing the protective layer includes:
[0098] Remove all protective layers 600 formed during the passivation process, such as the first protective layer 601 covering the trench wall of the first trench 503 and the second protective layer 602 covering the trench wall of the lateral trench 104, leaving only the semiconductor substrate 100 and the hard mask material.
[0099] S6: Remove the first dielectric layer and the support structures located at both ends of the third direction.
[0100] In some exemplary embodiments, as shown in Figures 17 and 18, removing the first dielectric layer and the support structures located at the third-direction ends includes:
[0101] Part of the hard mask material is removed, specifically the first dielectric layer 501 and the support structures 502 at both ends of the semiconductor substrate 100 in the third direction. The support structures 502 at both ends of the semiconductor substrate 100 in the second direction are retained, supporting the semiconductor strips 102 at both ends of the second direction. After removing part of the hard mask material, all semiconductor strips 102 are exposed for subsequent fabrication of other structures.
[0102] S7: Forms the second element, bit line, first element, and word line.
[0103] Figure 19 is an eleventh fabrication schematic diagram of a semiconductor device according to this exemplary embodiment, and Figure 20 is a twelfth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 19 and 20, the formation of a second element, a bit line, a first element, and a word line includes:
[0104] First, as shown in Figures 3 and 19, second elements 203 are formed at both ends of the semiconductor strip 102. The semiconductor strip 102 can be divided into two semiconductor pillars 204, and the second elements 203 can be formed at one end of the two semiconductor pillars near the support structure 502. A first electrode layer 210, a capacitor dielectric layer 211, and a second electrode layer 212 are sequentially deposited on the semiconductor strip 102. The first electrode layer 210 and the second electrode layer 212 can be made of metal or a conductive metal compound. In this example, the first electrode layer 210 and the second electrode layer 212 can be made of the same material, both being titanium nitride (TiN). The capacitor dielectric layer 211 can be a high dielectric material. The first electrode layer 210, the capacitor dielectric layer 211, and the second electrode layer 212 all have a rhombic cross-section perpendicular to the second direction. In other exemplary embodiments, the plurality of second electrode layers 212 spaced apart along a third direction and the first direction can be a single integrated structure to increase the capacitance area of the second element 203.
[0105] Subsequently, as shown in Figures 3 and 20, bit lines 300 are formed on semiconductor strips 102, wherein bit lines 300 extend along a first direction and are connected to a plurality of semiconductor strips 102 stacked in the first direction, and bit lines 300 divide the semiconductor strips 102 connected to them into two semiconductor pillars 204.
[0106] Finally, as shown in Figures 3, 4, and 20, a gate insulating layer 209 and a gate electrode 205 are sequentially deposited on the outer periphery of the channel region 207 of the semiconductor pillar 204. The gate electrode 205 can be made of a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The gate electrode 205 can also be made of conductive polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, amorphous silicon, etc. The gate insulating layer 209 can be made of a high-dielectric-constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate insulating layer 209 can be formed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD. The gate electrodes 205 located on the plurality of semiconductor pillars 204 arranged sequentially in a third direction are connected to form word lines 400 extending along a first direction.
[0107] In some exemplary embodiments, an electronic device includes the aforementioned semiconductor device, or includes a semiconductor device obtained by the aforementioned semiconductor device fabrication method. The electronic device can be any electronic product with storage functionality, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.
[0108] In some exemplary embodiments, a method for fabricating a semiconductor device, as shown in FIG1, includes:
[0109] A semiconductor substrate with a preset thickness is provided, the preset thickness being set as the dimension of the semiconductor substrate in a first direction, the first direction being perpendicular to the semiconductor substrate;
[0110] The semiconductor substrate is etched to form a plurality of semiconductor strips, all of which extend along a second direction. The plurality of semiconductor strips are arranged in an array in the first direction and the third direction. The second direction and the third direction are parallel to the semiconductor substrate, and the second direction intersects the third direction.
[0111] The memory cell is formed based on the semiconductor substrate.
[0112] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0113] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.
[0114] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
[0115] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0116] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0117] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0118] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A method for fabricating a semiconductor device, comprising: A semiconductor substrate with a preset thickness is provided, the preset thickness being set as the dimension of the semiconductor substrate in a first direction, the first direction being perpendicular to the semiconductor substrate; The semiconductor substrate is etched to form a plurality of semiconductor strips, all of which extend along a second direction. The plurality of semiconductor strips are arranged in an array in the first direction and the third direction. The second direction and the third direction are parallel to the semiconductor substrate, and the second direction intersects the third direction. The memory cell is formed based on the semiconductor substrate.
2. The method for fabricating a semiconductor device as described in claim 1, wherein, The etching of the semiconductor substrate to form multiple semiconductor strips includes: A first dielectric layer is formed on the top surface of the semiconductor substrate. The first dielectric layer has a plurality of first trenches. The first trenches extend along a second direction. The plurality of first trenches are spaced apart in a third direction. The first trenches penetrate the first dielectric layer in the first direction to expose the semiconductor substrate. The semiconductor substrate is etched using the first dielectric layer as a mask.
3. The method for fabricating a semiconductor device as described in claim 2, wherein, The formation of a first dielectric layer on the top surface of the semiconductor substrate includes: Hard mask material is deposited on the top surface and the outer periphery of the semiconductor substrate, and the hard mask material located on the outer periphery of the semiconductor substrate forms a support structure surrounding the semiconductor substrate; The hard mask material located on the top surface of the semiconductor substrate is etched to form a plurality of the first trenches.
4. The method for fabricating a semiconductor device as described in claim 2, wherein, The etching of the semiconductor substrate using the first dielectric layer as a mask includes: The semiconductor substrate is etched using Bosch etching technology to form a plurality of second trenches and a plurality of lateral trenches on the semiconductor substrate. The plurality of second trenches are spaced apart in the third direction, and the plurality of lateral trenches are spaced apart in the first direction. The Bosch etching process includes a cyclic passivation process and an etching process. The second trench is formed by recessing the semiconductor substrate to a predetermined depth in the first direction away from the first dielectric layer, and the second trench is configured to separate adjacent semiconductor strips in the third direction. The lateral groove is formed by a recess in the sidewall of the second trench toward the third direction, and the lateral groove is configured to separate adjacent semiconductor strips in the first direction.
5. The method for fabricating a semiconductor device as described in claim 4, wherein, The second groove includes a plurality of first grooves stacked in the first direction, wherein the first grooves of any two second grooves are arranged in a one-to-one correspondence in the third direction, and the lateral groove is configured to connect two adjacent first grooves in the third direction; The etching process includes introducing an etching gas into the first trench, the etching gas generating plasma and etching the semiconductor substrate to form the first groove and the lateral groove, the lateral groove being located between two adjacent first grooves in the third direction.
6. The method for fabricating a semiconductor device as described in claim 5, wherein, The passivation process includes: Passivating gas is introduced into the first trench to form a first protective layer covering the trench wall, or to form a second protective layer covering the trench wall of the first groove and the trench wall of the lateral groove. Remove the first protective layer covering the bottom wall of the first trench, or remove the second protective layer covering the bottom wall of the first trench.
7. The method for fabricating a semiconductor device as described in claim 6, wherein, The formation of memory cells based on the semiconductor substrate includes: Remove the first protective layer, the second protective layer, and the first dielectric layer to expose the plurality of semiconductor strips; A second element, a bit line, a first element, and a word line are sequentially formed on the semiconductor strip.
8. The method for fabricating a semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor substrate is made of silicon, germanium, silicon-germanium or germanium-tin, wherein the silicon is monocrystalline silicon with a crystal plane index of (111).
9. A semiconductor device comprising a substrate and a plurality of memory cell columns disposed on the substrate, each memory cell column comprising a plurality of memory cells, the plurality of memory cells being stacked along a first direction, each memory cell comprising a first element, the first element comprising a semiconductor pillar and a gate electrode, the semiconductor pillar extending along a second direction parallel to the substrate, the first direction being perpendicular to the substrate; The substrate and the semiconductor pillar are formed by etching a semiconductor substrate of a preset thickness, the preset thickness being the dimension of the semiconductor substrate in the first direction.
10. The semiconductor device of claim 9, wherein, The semiconductor pillar is made of single-crystal silicon with a crystal plane index of (111).
11. The semiconductor device of claim 9, wherein, The semiconductor pillar has a rhomboid cross-section perpendicular to the second direction.
12. The semiconductor device of claim 11, wherein, The first element includes a gate insulating layer located between a semiconductor pillar and a gate electrode, the gate insulating layer having a rhomboid cross-section perpendicular to the second direction; The storage cell further includes a second element disposed on the semiconductor pillar. The second element includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer. The first electrode layer, the capacitor dielectric layer, and the second electrode layer are arranged sequentially in a direction away from the semiconductor pillar. The cross-sections of the first electrode layer, the capacitor dielectric layer, and the second electrode layer perpendicular to the second direction are all set to rhombus shape.
13. The semiconductor device of claim 9, further comprising a plurality of bit lines and a plurality of word lines; Multiple bit lines extend along the first direction, and multiple semiconductor pillars stacked at the same position along the first direction share the same bit line; The extension direction of the word line is perpendicular to the extension direction of the semiconductor pillar. A plurality of memory cells are arranged at intervals along the extension direction of the word line. Each word line is formed by connecting the gate electrodes of the first elements of a plurality of memory cells arranged along the extension direction of the word line.
14. An electronic device comprising a semiconductor device obtained by the method of fabricating a semiconductor device according to any one of claims 1 to 8, or comprising a semiconductor device according to any one of claims 9 to 13.