Chip structure, memory and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a chip structure, a memory and an electronic device, which are used to shorten power supply lines and free up wire winding resources on the front side of a chip. The chip structure comprises a memory array and peripheral logic devices located at the periphery of the memory array. The chip structure comprises a device layer, a first metal wiring disposed on the device layer, and a back power supply structure configured to supply power to memory cells disposed in the device layer. The back power supply structure comprises a second metal wiring disposed on the side of the device layer away from the first metal wiring, and an electrically conductive structure located in the memory array and extending through the device layer, wherein the electrically conductive structure connects the first metal wiring and the second metal wiring.

Description

Chip structure, memory and electronic devices

[0001] This application claims priority to Chinese patent application filed on March 24, 2025, with application number 202510359638.2 and entitled "Chip Structure, Memory and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a chip structure, memory, and electronic device. Background Technology

[0003] With the development of semiconductor technology, the process nodes of transistors are gradually decreasing, the size of transistors is getting smaller and the density is getting higher and higher, requiring more and more metal wiring to complete the interconnection of power, ground and signal lines.

[0004] However, on the one hand, metal wiring has become a bottleneck limiting further increases in transistor integration density. On the other hand, increasingly fine metal wiring makes the power supply voltage drop (IR Drop) problem more and more significant. Summary of the Invention

[0005] This application provides a chip structure, memory, and electronic device for shortening power supply lines and freeing up winding resources on the front side of the chip.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] A first aspect of this application provides a chip structure including a memory array and peripheral logic devices located around the memory array. The chip structure includes a device layer, a first metal wiring disposed on the device layer, and a back power supply structure for supplying power to memory cells disposed on the device layer. The back power supply structure includes a second metal wiring disposed on the side of the device layer away from the first metal wiring, and a conductive structure located in the memory array and penetrating the device layer. The conductive structure connects the first metal wiring and the second metal wiring.

[0008] The chip structure provided in this application embodiment does not require an additional increase in chip structure area. By setting a conductive structure within the memory array, and connecting the first and second metal wirings, a back-side power supply structure composed of the second metal wiring and the conductive structure completes the back-side power supply network technology for the chip structure. The solution in this application embodiment allows power supply to the memory cells at the device layer to be completed within the memory array, without needing to pass through higher metal layers. This reduces the transmission path of the power supply lines, thereby improving voltage drop, enhancing chip structure performance, and reducing power consumption. Furthermore, since power supply to the memory cells at the device layer does not require passing through higher metal layers, it saves valuable metal line resources. These saved higher metal layers can be used for signal traces, thereby improving the chip structure's transmission rate. Simultaneously, because the solution in this application embodiment improves voltage drop, it eliminates the need for excessive front-side traces in the memory array for power supply, thus reducing the usable area on the front side of the memory array.

[0009] In one possible implementation, the storage array includes storage cell areas and edge areas, with the edge areas located around the storage cell areas. The storage cell areas are used to store information, while the edge areas assist the storage cell areas in reading and writing information; at least a portion of the second metal wiring is located in the edge areas. This reduces the transmission path of the power supply lines.

[0010] In one possible implementation, the conductive structure is located in the edge region. This allows power to be supplied to the memory cells of the device layer using the original structure of the chip.

[0011] In one possible implementation, the chip structure also includes a connection region located between the memory cell region and the edge region; conductive structures are located within the connection region. In this way, power supply to the memory cells of the device layer is completed within the memory array, without needing to pass through higher metal layers, reducing the transmission path of the power supply lines, thereby improving voltage drop and enhancing chip structure performance.

[0012] In one possible implementation, the edge region includes a first edge region and a second edge region; the first edge region extends along a first direction, and the second edge region extends along a second direction; the first and second directions intersect, and both directions are parallel to the plane of the memory array; the conductive structure includes a first conductive structure and a second conductive structure; the first conductive structure is located in the first edge region; the second conductive structure is located in the second edge region; and a second metal wiring provides different power supply potentials to the memory cells of the device layer through the first and second conductive structures, respectively. In this way, different potentials can be provided to the memory cells of the device layer.

[0013] In one possible implementation, the conductive structure includes a first via and a first connection structure; the first via penetrates the device layer; the first connection structure is located on the side of the first via away from the second metal wiring and is electrically connected to the first via. This provides an embodiment of the conductive structure.

[0014] In one possible implementation, the extension direction of the first connection structure is the same as the extension direction of the first via, parallel to the plane of the device layer. This increases the design freedom of the chip structure.

[0015] In one possible implementation, the size of the conductive structure is larger than the size of the device layer along its thickness direction; the conductive structure is also in contact with both the first and second metal wirings. This provides an embodiment of the conductive structure. The formation process of the conductive structure is simple and easy to fabricate.

[0016] In one possible implementation, the conductive structure includes a first connection structure, an interconnect structure, and a second connection structure; the interconnect structure and the second connection structure are connected and penetrate the device layer, and the first connection structure is located on the side of the interconnect structure away from the second metal wiring; the second connection structure is in contact with the second metal wiring; the first connection structure is electrically connected to the second connection structure through the interconnect structure. This provides an embodiment of the conductive structure.

[0017] In one possible implementation, the first metal wiring includes a first metal layer and a second metal layer stacked together; the first metal layer is located on the side of the second metal layer closer to the device layer; the extension direction of the first metal layer intersects the extension direction of the second metal layer.

[0018] In one possible implementation, the second metal wiring powers the memory cells of the device layer through the first metal layer. This provides VDD power to the chip structure.

[0019] In one possible implementation, the second metal layer of the memory cell region is connected to the second metal layer of the edge region, and the second metal wiring supplies power to the memory cells of the device layer through the second metal layer. This provides VSS power to the chip structure.

[0020] In one possible implementation, the first metal wiring further includes a third metal layer and a fourth metal layer; the third metal layer is located on the side of the second metal layer away from the first metal layer; the fourth metal layer is located on the side of the third metal layer away from the second metal layer; the first metal wiring in the memory cell area and the first metal wiring in the edge area are connected through the fourth metal layer, and the second metal wiring supplies power to the memory cells of the device layer through the fourth metal layer. This provides VSS power to the chip structure.

[0021] In one possible implementation, the chip architecture includes static random access memory (SRAM). This allows the SRAM to be powered using a rear-side power supply network.

[0022] A second aspect of the embodiments of this application provides a memory, including: a controller and a chip structure according to any one of the first aspects, wherein the controller is electrically connected to the chip structure.

[0023] The memory provided in the second aspect of the embodiments of this application includes the chip structure of any one of the first aspects, and its beneficial effects are the same as those of the chip structure, which will not be repeated here.

[0024] A third aspect of this application provides an electronic device, including: a printed circuit board and a memory as described in the second aspect, wherein the printed circuit board and the memory are electrically connected.

[0025] The electronic device provided in the third aspect of the embodiments of this application includes the memory of the second aspect, and its beneficial effects are the same as those of the memory, which will not be repeated here. Attached Figure Description

[0026] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0027] Figure 2A is a schematic diagram of a chip structure according to an embodiment of this application;

[0028] Figure 2B is a schematic diagram of another chip structure illustrated in an embodiment of this application;

[0029] Figure 2C is a schematic diagram of another chip structure illustrated in an embodiment of this application;

[0030] Figure 3 is a schematic diagram of another chip structure illustrated in an embodiment of this application;

[0031] Figure 4A is a schematic diagram of a chip structure provided in an embodiment of this application;

[0032] Figure 4B is a schematic diagram of a storage array provided in an embodiment of this application;

[0033] Figure 5 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0034] Figure 6 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0035] Figure 7 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0036] Figure 8 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0037] Figure 9 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0038] Figure 10 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0039] Figure 11 is a schematic diagram of another chip structure provided in an embodiment of this application;

[0040] Figure 12 is a schematic diagram of another chip structure provided in an embodiment of this application.

[0041] Reference numerals in the figures: 1-Electronic device; 2-Display module; 3-Middle frame; 4-Housing; 5-Cover plate; 10-Chip structure; 20-Memory array; 30-Peripheral logic device; 40-Transition region; 41-Connection structure; 21-Memory cell area; 201-Memory cell; 22-Edge area; 23-Connection area; 221-First edge area; 222-Second edge area; 11-Back power supply structure; 110-Substrate; 210-Device layer; 300-First wiring layer; 310-First dielectric layer 320 - First metal wiring; 330 - Second via; 321 - First metal layer; 322 - Second metal layer; 323 - Third metal layer; 324 - Fourth metal layer; 400 - Second wiring layer; 410 - Second dielectric layer; 420 - Second metal wiring; 500 - Conductive structure; 501 - First conductive structure; 502 - Second conductive structure; 510 - First via; 521 - First connection structure; 522 - Second connection structure; 530 - Interconnect structure. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0043] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0044] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0045] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0046] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0047] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include car navigation systems, car DVDs, etc. Financial terminal products include ATMs, self-service terminals, etc. Communication electronics products include servers, storage devices, radar, base stations, and other communication equipment. This application does not impose special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following embodiments all use mobile phones as an example for illustration.

[0048] An example of the structure of an electronic device is shown in Figure 1. The electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0049] The display module 2 has a light-emitting side that allows the display image to be seen and a non-light-emitting side that is opposite to the light-emitting side. The back of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0050] For example, display module 2 may include a display panel (DP).

[0051] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0052] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0053] The aforementioned electronic device 1 may further include a chip structure disposed on a printed circuit board. The printed circuit board is used to carry the chip structure and is electrically connected to the chip structure to enable signal communication.

[0054] In some embodiments, the chip structure can be a semiconductor structure such as a memory device or integrated circuit packaged and applied to electronic devices in the form of a chip. Of course, it can also be applied directly to electronic devices without packaging.

[0055] For example, an integrated circuit may include a circuit module for implementing a single function, or it may include multiple circuit modules for implementing different functions. The circuit module may be a circuit with any function, such as a driver circuit, pixel circuit, amplifier circuit, power management circuit, charging protection circuit, control circuit (e.g., a central processing unit (CPU)), and image sensor circuit.

[0056] For example, storage devices (such as internal memory) can include random access memory (RAM), read-only memory (ROM), etc. Based on their operating principles, RAM can also include ferroelectric random access memory (FeRAM), dynamic random access memory (DRAM), phase-change random access memory (PCRAM), resistive random access memory (ReRAM), or magnetic random access memory (MRAM). Based on whether the stored information persists after the external power supply is removed, memory can be classified as volatile memory (RAM) and non-volatile memory (NVM). Volatile memory, represented by static random accessory memory (SRAM) or dynamic random access memory, requires a continuous external power supply for information storage. When no external power is applied, the stored information is lost. Non-volatile memories are represented by traditional read-only memory (ROM), flash memory, ferroelectric memory, magnetic random access memory, resistive random access memory (RRAM), and phase-change memory. These non-volatile memories all achieve the characteristic of not losing information when power is off through their unique physical principles.

[0057] The fabrication process of the aforementioned chip structure includes front end of line (FEOL) and back end of line (BEOL) processes.

[0058] The process of fabricating active or passive devices (e.g., transistors or resistors) on a substrate is called the front-end process. The process of fabricating metal wiring based on the front-end process is called the back-end process. The front-end process is the process of forming active or passive devices on a substrate, while the back-end process refers to the process of connecting different devices or different layers on the substrate through metal wiring.

[0059] It should be noted here that the chip structure also includes signal interconnects for connecting transistors and metal wiring, and these signal interconnects also include power lines for supplying power to active or passive devices.

[0060] For example, the transistor here could be a field-effect transistor (FET).

[0061] It is clarified here that field-effect transistors can include planar transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs), and can also include three-dimensional transistors such as fin field-effect transistors (FinFETs), gate all-around field-effect transistors (GAAFETs), or forksheet field-effect transistors (forksheet FETs or FSFETs). This application does not limit the specifics; appropriate configuration based on actual conditions is acceptable.

[0062] In some embodiments, the chip structure described above includes a device layer composed of active or passive devices fabricated by front-end processes.

[0063] For example, active devices may include electronic components such as transistors, vacuum tubes, and integrated circuits. Passive devices may include electronic components such as resistors, capacitors, or inductors.

[0064] In some embodiments, the chip structure further includes wiring stacks fabricated by back-end processes.

[0065] With the development of semiconductor technology, the front-end process has become a key factor in determining the power consumption, performance, and power performance area (PPA) of the aforementioned chip structures (such as SRAM, DRAM, or CPU).

[0066] According to Dennard scaling, as transistor size shrinks, transistor power density remains constant; the power of a chip structure is proportional to its area. Therefore, as transistor size continues to shrink, the power-to-average power (PPA) of the chip structure can be continuously optimized.

[0067] However, with the development of semiconductor technology, the process nodes of transistors have gradually decreased, and the size of traditional planar transistors has been miniaturized to physical limits. In order to further improve the integration of chip structures and reduce the process nodes of chip structures, transistors have evolved from planar chip structures to three-dimensional devices such as fin field-effect transistors, gate-around field-effect transistors, or forked strip field-effect transistors, and chip packaging has evolved into advanced packaging technologies.

[0068] When transistors are close together, increasingly smaller power lines are needed to power the transistors, as shown in Figure 2A, which provides a frontside power delivery network (FSPDN) technology.

[0069] For example, the power supply of the chip structure may include a positive power supply voltage (V device, VDD) and a negative power supply voltage (V series, VSS). As shown in Figure 2A, both VDD and VSS are transmitted to the device layer from the front power line of the chip structure to power the transistors in the device layer.

[0070] However, as transistor process nodes shrink, transistor sizes become smaller and densities increase, requiring more and more metal wiring to interconnect power, ground, and signal lines. On the one hand, metal wiring resources may become a bottleneck limiting further increases in transistor integration density; on the other hand, increasingly fine metal wiring makes the power supply voltage drop (IR Drop) problem more and more significant.

[0071] To optimize power supply capabilities and free up front-side wiring resources, as exemplified in Figure 2B, the power lines of the chip structure can be moved to the back side of the chip, i.e., a backside power delivery network (BSPDN). In this case, power to the device layer can be transmitted over a long distance on the back side of the chip, passing through conductive structures to the front side, directly powering the transistors on the device layer. Alternatively, power to the device layer can also be transmitted over a long distance on the back side of the chip, passing through conductive structures to the front side, powering a localized short-distance power supply network on the front side. Or, as exemplified in Figure 2C, power to the device layer can all be transmitted over a long distance on the back side of the chip, passing through conductive structures to the front side, powering a localized short-distance power supply network on the front side.

[0072] In this way, unlike the traditional FSPDN technology, BSPDN technology can design a power supply network on the back of the chip, that is, the power lines are set on the back of the chip, which can improve the power integrity of the chip structure, reduce the power supply voltage drop, and increase the maximum frequency.

[0073] The transistors in the chip structure provided in this application embodiment may include FinFETs or GAAFETs. Among them, the transistors include FinFETs, and the SRAM powered by BSPDN technology is more complex.

[0074] In some embodiments, a chip structure is illustrated, which may be the SRAM described above. As shown in FIG3, the chip structure 10 includes a memory array 20, peripheral logic devices 30, and a transition region 40 located between the memory array 20 and the peripheral logic devices 30.

[0075] In the chip structure 10 shown in Figure 3, a transition region 40 is provided between the memory array 20 and the peripheral logic device 30. A connecting structure 41 is provided in the peripheral logic device 30 to connect the power line provided on the back of the chip structure 10. The connecting structure 41 is connected to the transition region 40. The power line is connected to the power line provided on the front of the chip structure 10 through the transition region 40, so as to realize the power supply to the memory array 20.

[0076] However, since the chip structure 10 is powered by an additional transition region 40 and a connecting structure 41, the area of ​​the transition region 40 and the connecting structure 41 needs to be relatively large in order to reduce resistance, resulting in a large size for the chip structure 10. On the other hand, since the distance between the transition region 40 and the memory array 20 is relatively large, and the lower metal layers surrounding the memory array 20 are largely occupied, it is necessary to wind around to a higher metal layer to power the internal structure of the memory array 20, resulting in an additional voltage drop.

[0077] Therefore, in order to reduce the size of the chip structure, this application embodiment also provides a chip structure that can be applied to the aforementioned SRAM or DRAM. It should be noted that the type of transistors included in the SRAM is not limited in this application embodiment; it can be FinFET SRAM or GAAFET SRAM.

[0078] As shown in Figure 4A, according to the regional division, the chip structure 10 includes a memory array 20 and a peripheral logic device 30. As shown in Figure 4A, the peripheral logic device 30 is located around the memory array 20.

[0079] For example, as shown in FIG4B, the storage array 20 has a bit cell area 21 and an edge area 22, which is located around the bit cell area 21.

[0080] The storage cell area 21 is mainly used for storing information, while the edge area 22 serves as an auxiliary circuit for the storage array 20. Its primary function is to ensure the correctness of read and write operations in the storage cell area 21, assisting in the reading and writing of information. The storage cell area 21 and the edge area 22 work together.

[0081] For example, the storage cell area 21 includes data storage cells, inverters, access transistors, and storage nodes. The edge area 22 includes a pre-charge circuit, an equalization circuit, a column selection circuit, a reference voltage generation circuit, and a noise suppression circuit.

[0082] In other words, the storage cell area 21 is used to store information, while the edge area 22 does not have any functional circuitry for storing information.

[0083] For example, as shown in FIG4B, the storage array 20 may further include multiple storage cells 201. That is, multiple storage cells 201 are located in the storage cell area 21. The multiple storage cells 201 may be arranged in an array. In this embodiment of the application, the number of storage cells 201 is not limited, and can be reasonably set according to the actual situation. In this case, the edge area 22 is located on the periphery of the storage cell area 21 composed of multiple storage cells 201.

[0084] Referring again to FIG4B, the edge region 22 may include a first edge region 221 and a second edge region 222. For example, the first edge region 221 extends along a first direction x, and the second edge region 222 extends along a second direction y.

[0085] It should be noted here that the extension direction of the first edge region 221 can be the extension direction of the bit line. The extension direction of the second edge region 222 can be the extension direction of the word line.

[0086] Peripheral logic devices 30 are disposed around the periphery of the storage array 20 and are used for reading and writing information, and for signal transmission with the storage array 20. The number of peripheral logic devices 30 is not limited in this embodiment; it can be set reasonably according to actual conditions.

[0087] As shown in Figure 5, along the thickness direction, the chip structure 10 mainly includes a device layer 210, a first wiring layer 300, a second wiring layer 400, and a conductive structure 500.

[0088] As shown in Figure 5, the device layer 210 is disposed on the substrate 110, and the first wiring layer 300 is disposed on the side of the device layer 210 away from the substrate 110.

[0089] For example, the substrate 110 includes a first surface 111 and a second surface 112 opposite to each other. The device layer 210 is disposed on the first surface 111 of the substrate 110. The device layer 210 and the first wiring layer 300 are sequentially disposed on the first surface 111 of the substrate 110.

[0090] Regarding the substrate 110, the material of the substrate 110 is not limited in this embodiment. Exemplarily, the material of the substrate 110 can be a semiconductor. For example, it can be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), or silicon germanium-on-insulator (SiGe-on-insulator, SGOI). The substrate 110 can also be doped (e.g., P-type doped, N-type doped) or undoped.

[0091] The semiconductor material of the substrate 110 may include any one or a combination of silicon, germanium, compound semiconductors, and alloy semiconductors. Compound semiconductors may include, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide. Alloy semiconductors may include, for example, silicon-germanium (SiGe), germanium-tin (GeSn), silicon-germanium-tin (SiGeSn), gallium arsenide-phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide-phosphide (GaInAsP).

[0092] SOI includes a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate 110, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates.

[0093] Alternatively, for example, substrate 110 is a wafer, such as a silicon wafer.

[0094] It should be noted that the thickness of the substrate 110 is not limited in the embodiments of this application. Depending on actual needs, the substrate 110 may also be omitted.

[0095] For example, device layer 210 may include active devices or passive devices. Active devices may include electronic components such as transistors, vacuum tubes, and integrated circuits. Passive devices may include electronic components such as resistors, capacitors, or inductors.

[0096] Device layer 210 is used to form the circuit structure of chip structure 10. For example, device layer 210 includes memory cell 201 disposed on device layer 210.

[0097] The first wiring layer 300 connects to the device layer 210, that is, the first wiring layer 300 connects to the active or passive devices included in the device layer 210.

[0098] Referring again to Figure 5, the second wiring layer 400 is disposed on the side of the substrate 110 away from the first wiring layer 300. That is, the second wiring layer 400 is disposed on the side of the substrate 110 away from the device layer 210. Alternatively, the second wiring layer 400 is disposed on the second surface 112 of the substrate 110.

[0099] In other words, the second wiring layer 400 and the first wiring layer 300 are respectively disposed on two opposite surfaces of the substrate 110.

[0100] For ease of understanding, it can be assumed that the device layer 210 and the first wiring layer 300 are disposed on the front side of the substrate 110, and the second wiring layer 400 is disposed on the back side of the substrate 110.

[0101] Regarding the first wiring layer 300, as shown in FIG5, the first wiring layer 300 includes a first dielectric layer 310 and a first metal wiring 320 located within the first dielectric layer 310.

[0102] The first wiring layer 300 is connected to the device layer 210, that is, the first metal wiring 320 is electrically connected to the memory cell 201 of the device layer 210.

[0103] Regarding the second wiring layer 400, as shown in FIG5, the second wiring layer 400 includes a second dielectric layer 410 and a second metal wiring 420 located within the second dielectric layer 410.

[0104] That is, the first metal wiring 310 is disposed on the device layer 210, and the second metal wiring 420 is disposed on the side of the device layer 210 away from the first metal wiring 320.

[0105] For example, a first metal wiring 320 is disposed on the side of device layer 210 away from substrate 110. A second metal wiring 420 is disposed on the side of substrate 110 away from the first metal wiring 320. The first metal wiring 320 and the second metal wiring 420 are respectively disposed on two opposite surfaces of substrate 110.

[0106] As shown in Figure 5, the chip structure 10 also includes a conductive structure 500 that penetrates the device layer 210. It should be noted that when the chip structure 10 also includes a substrate 110, the conductive structure 500 penetrates both the substrate 110 and the device layer 210. The conductive structure 500 is located in the memory array 20.

[0107] For example, the conductive structure 500 may be located in the edge region 22 of the chip structure 10.

[0108] At this point, the memory array 20 of the chip structure 10 may include a device layer 210, a first metal wiring 320 located on the device layer 210, and a back power supply structure 11. The back power supply structure 11 includes a second wiring layer 400 and a conductive structure 500. The back power supply structure 11 is used to supply power to the memory cells 201 of the device layer 210.

[0109] The first metal wiring 320 is electrically connected to the second metal wiring 420 through the conductive structure 500. That is, the conductive structure 500 is electrically connected to the first metal wiring 320 and the second metal wiring 420.

[0110] In this way, the power supply lines for the chip structure 10 can be powered through the conductive structure 500 located in the edge region 22, thereby providing power to the memory cells 201 of the device layer 210.

[0111] For example, at least a portion of the second metal wiring 420 is located in the edge region 22.

[0112] In this way, the power supply lines of the chip structure 10 are transmitted from the second metal wiring 420 to the first metal wiring 320 via the conductive structure 500, which makes the power supply lines of the chip structure 10 smaller.

[0113] In some embodiments, as shown in FIG5, the first wiring layer 300 further includes a first via 330. The first via 330 and the first metal wiring 320 are stacked.

[0114] The first metal wiring 320 is electrically connected to the memory cell 201 of the device layer 210 through the first via 330.

[0115] It is clarified here that the first wiring layer 300 is a multilayer metal disposed on the device layer 210. In this embodiment, the number of metal layers included in the first wiring layer 300 is not limited; it can be reasonably set according to the actual situation.

[0116] For example, as shown in FIG5, the first metal wiring 320 includes a first metal layer 321 and a second metal layer 322. The first metal layer 321 is located on the side of the second metal layer 322 near the device layer 210.

[0117] At this time, the second via 330 is used to connect the first metal layer 321 and the second metal layer 322.

[0118] For example, as shown in Figures 5 and 6, the back power supply structure 11 supplies power to the memory cells 201 of the device layer 210 through the first metal layer 321. For instance, the second metal wiring 420 supplies power to the memory cells 201 of the device layer 210 through the first metal layer 321. That is, the second metal wiring 420 of the second wiring layer 400 is transmitted to the first metal layer 321 of the first wiring layer 300 via the conductive structure 500, and then transmitted from the first metal layer 321 to the memory cells 201 of the device layer 210 to complete the VDD power supply to the memory cell area 21.

[0119] For example, as shown in Figures 5 and 7, the first metal wiring 320 located in the edge region 22 extends through the edge region 22 along the thickness direction of the device layer 210. In this case, the metal layer corresponding to the VSS power supply of the memory cell region 21 includes a first metal layer 321 and a second metal layer 322. As shown in Figure 5, the second metal layer 322 of the memory cell region 21 is connected to the second metal layer 322 of the edge region 22, and the second metal wiring 420 supplies power to the memory cell 201 of the device layer 210 through the second metal layer 322.

[0120] In other words, the power supply line is as follows: the second metal wiring 420 of the second wiring layer 400 is transmitted to the first wiring layer 300 via the conductive structure 500, and then transmitted to the second metal layer 322 via the first metal layer 321 and the second via 330 of the first wiring layer 300, and then transmitted to the memory cell 201 of the device layer 210 via the second metal layer 322 to complete the VSS power supply to the memory cell area 21.

[0121] For example, as shown in FIG8, the first wiring layer 300 includes four metal layers. That is, the first wiring layer 300 also includes a third metal layer 323 and a fourth metal layer 324. The third metal layer 323 is located on the side of the second metal layer 322 away from the first metal layer 321, and the fourth metal layer 324 is located on the side of the third metal layer 323 away from the second metal layer 322.

[0122] That is, the first metal wiring 320 includes a first metal layer 321, a second metal layer 322, a third metal layer 323 and a fourth metal layer 324 stacked in sequence, and the first metal layer 321 is located on the side of the fourth metal layer 324 closer to the device layer 210.

[0123] Correspondingly, the second via 330 is used to connect the first metal layer 321 and the second metal layer 322, the second metal layer 322 and the third metal layer 323, the third metal layer 323 and the fourth metal layer 324.

[0124] For example, as shown in Figures 8 and 9, the first metal wiring 320 located in the edge region 22 does not penetrate the edge region 22 along the thickness direction of the device layer 210, and the second metal layer 322 of the edge region 22 and the second metal layer 322 of the memory cell region 21 are disconnected. At this time, as shown in Figure 8, the first metal wiring 320 of the memory cell region 21 and the first metal wiring 320 of the edge region 22 are connected through the fourth metal layer 324.

[0125] The metal layers corresponding to the VSS power supply of the memory cell region 21 include a first metal layer 321, a second metal layer 322, a third metal layer 323, and a fourth metal layer 324. As shown in Figure 8, the first metal wiring 320 of the memory cell region 21 and the first metal wiring 320 of the edge region 22 are connected through the fourth metal layer 324, and the second metal wiring 420 supplies power to the memory cell 201 of the device layer 210 through the fourth metal layer 324.

[0126] At this time, the power supply line is as follows: the second metal wiring 420 of the second wiring layer 400 is transmitted to the first wiring layer 300 through the conductive structure 500, and then transmitted to the fourth metal layer 324 through the first metal layer 321, the second metal layer 322, the third metal layer 323 and the second via 330 of the first wiring layer 300, and then transmitted to the memory cell area 21 by the fourth metal layer 324 to complete the VSS power supply to the memory cell area 21.

[0127] In this embodiment, the power supply route of VSS is not limited, but is related to the distribution of the first metal wiring 320 in the edge region 22.

[0128] In some embodiments, continuing to refer to FIG8, the conductive structure 500 includes a first via 510 and a first connection structure 521. The first connection structure 521 is located on the side of the first via 510 away from the second metal wiring 420.

[0129] As shown in Figure 8, the first via 510 penetrates the device layer 210, and the first connection structure 521 is located within the first dielectric layer 310 and is electrically connected to the first via 510. It should be noted that, for ease of illustration, the substrate 110 is not shown in Figure 8. When the chip structure 10 also includes the substrate 110, the first via penetrates both the substrate 110 and the device layer 210.

[0130] In other words, the first connection structure 521 and the first through hole 510 constitute the conductive structure 500.

[0131] For example, along a direction parallel to the plane where the device layer 210 is located, the extension direction of the first connection structure 521 is the same as the extension direction of the first via 510.

[0132] In this way, the first connection structure 521 can extend along the plane parallel to the device layer 210, increasing the design freedom of the first connection structure 521 and thus increasing the design area of ​​the first connection structure 521.

[0133] In some embodiments, as shown in FIG10, the chip structure 10 further includes a connection region 23, which is located between the memory cell region 21 and the edge region 22. For example, the connection region 23 is located between the memory cell region 21 and the second edge region 222.

[0134] For example, the conductive structure 500 may be located in the edge region 22. For instance, the conductive structure 500 may be located in the first edge region 221.

[0135] In this way, there are fewer metal traces in the first edge region 221 of the chip structure 10, and the original structure of the chip structure 10 can be used to power the memory cell 201 of the device layer 210, which can reduce the size of the chip structure 10 and reduce the transmission path of the power supply line.

[0136] Alternatively, for example, the conductive structure 500 may be located in the connection region 23. For instance, the conductive structure 500 may also be located between the second edge region 22 and the memory cell region 21.

[0137] In this way, since the path for powering the memory cell region 21 within the second edge region 222 of the chip structure 10 is occupied, by placing the conductive structure 500 within the connection region 23 between the second edge region 222 and the memory cell region 21, the memory cell 201 of the device layer 210 of the memory cell region 21 can be directly powered without bypassing the second edge region 222. This reduces the transmission path of the power supply line, improves voltage drop, and enhances the performance of the chip structure 10.

[0138] The chip structure 10 may also include multiple conductive structures 500. The multiple conductive structures 500 include a first conductive structure 501 and a second conductive structure 502.

[0139] For example, the first conductive structure 501 is located in the first edge region 221, and the second conductive structure 502 is located in the second edge region 222. The second metal wiring 420 provides different power supply potentials to the memory cells 201 of the device layer 210 through the first conductive structure 501 and the second conductive structure 502, respectively.

[0140] In other words, the power supply potential provided by the second metal wiring 420 to the memory cell 201 of the device layer 210 through the first conductive structure 501 is different from the power supply potential provided by the second metal wiring 420 to the memory cell 201 of the device layer 210 through the second conductive structure 502.

[0141] In this way, different power supply lines can be provided for the chip structure 10. The device layer 210 can be divided into multiple circuit modules, and different circuit modules of the device layer 210 can be powered by the second metal wiring 420 through different conductive structures 500.

[0142] For example, the multiple conductive structures 500 included in the chip structure 10 may be the same or different, and this application embodiment does not limit this.

[0143] As shown in Figure 10, part of the first connection structure 521 extends along the first direction x, and part of the first connection structure 521 extends along the second direction y. The first direction x and the second direction y intersect. The first direction x and the second direction y constitute the plane on which the memory array 20 is located. That is, both the first direction y and the second direction z intersect with the thickness direction of the chip structure 10.

[0144] In this way, the conductive structure 500 can extend along the first direction x, and the conductive structure 500 can also extend along the second direction y, which can improve the design freedom of the chip structure 10. This application embodiment does not limit this, and can be reasonably set according to the actual situation.

[0145] For example, the extension direction of the conductive structure 500 is the same as the extension direction of the first metal layer 321 along a direction parallel to the plane where the device layer 210 is located.

[0146] This reduces the size of the connection line between the conductive structure 500 and the first metal wiring 320, which is more conducive to reducing the size of the power supply line of the second metal wiring 420.

[0147] In other embodiments, as shown in FIG11, the size of the conductive structure 500 is larger than the size of the device layer 210 along the thickness direction of the device layer 210. That is, the thickness of the conductive structure 500 is greater than the thickness of the device layer 210.

[0148] To clarify, when the chip structure 10 also includes a substrate 110, the size of the conductive structure 500 is larger than the size of the substrate 110 and the device layer 210 along the thickness direction of the device layer 210. In other words, the thickness of the conductive structure 500 is greater than the thickness of the substrate 110 and the device layer 210.

[0149] As exemplarily shown in FIG11, the conductive structure 500 further extends into the first dielectric layer 310 and the second dielectric layer 410.

[0150] In other words, the conductive structure 500 extends into the first dielectric layer 310 of the first wiring layer 300 and is in contact with the first metal wiring 320 of the first wiring layer 300.

[0151] The conductive structure 500 extends into the second dielectric layer 410 of the second wiring layer 400 and is in contact with the second metal wiring 420 of the second wiring layer 400.

[0152] To clarify, the contact connection between the conductive structure 500 and the first metal wiring 320 can be understood as the conductive structure 500 and the first metal wiring 320 being in direct contact and electrically connected. Similarly, the contact connection between the conductive structure 500 and the second metal wiring 420 can be understood as the conductive structure 500 and the second metal wiring 420 being in direct contact and electrically connected.

[0153] At this point, the first metal wiring 320 and the second metal wiring 420 can be electrically connected through the conductive structure 500.

[0154] This provides an embodiment of the conductive structure 500. The formation process of the conductive structure 500 is simple and easy to fabricate.

[0155] In some other embodiments, as shown in FIG12, the conductive structure 500 includes a first connection structure 521, an interconnection structure 530, and a second connection structure 522.

[0156] As shown in Figure 12, the interconnect structure 530 and the second connection structure 522 are connected and penetrate the device layer 210. The first connection structure 521 is located on the side of the interconnect structure 530 away from the second connection structure 522. It should be noted that when the chip structure 10 also includes a substrate 110, the interconnect structure 530 and the second connection structure 522 are connected and penetrate the substrate 110 and the device layer 210.

[0157] In other words, the first connection structure 521 is located within the first dielectric layer 310.

[0158] The second connection structure 522 extends into the second dielectric layer 420 and is in contact with the second metal wiring 420 of the second wiring layer 400.

[0159] At this time, the first connection structure 521 is electrically connected to the second connection structure 522 through the interconnection structure 530.

[0160] In other words, the first connection structure 521, the interconnection structure 530, and the second connection structure 522 constitute the conductive structure 500.

[0161] This provides an embodiment of the conductive structure 500. The structure of the conductive structure 500 is not limited in this application embodiment; it can be reasonably set according to actual conditions.

[0162] The chip structure 10 provided in this application embodiment can be applied to a memory. For example, the chip structure 10 may include static random access memory (SRAM). Alternatively, for example, the chip structure 10 may also include dynamic random access memory (DRAM). That is, the chip structure 10 can be applied to SRAM or DRAM.

[0163] In some embodiments, the chip structure 10 is applied to SRAM, that is, the SRAM is powered by the back power supply structure 11 of the chip structure 10 (e.g., to power the SRAM memory cell 201). This frees up space for signal interconnects above the device layer 210 in the SRAM, reducing congestion on the front wiring layer, making signal transmission smoother, reducing signal latency, and improving the read / write speed and data transfer efficiency of the SRAM. Powering via the back power supply structure 11 also solves problems such as voltage drop and interference, which is beneficial to improving the performance and integration of the SRAM. At the same time, placing the power lines on the back of the SRAM helps to reduce power consumption and improve energy efficiency.

[0164] In other embodiments, the chip structure 10 is applied to a DRAM, meaning that the DRAM is powered by the back power supply structure 11 of the chip structure 10 (e.g., to power the memory cells 201 of the DRAM). This improves voltage stability and signal integrity, which is beneficial for improving the performance and integration of the DRAM. Simultaneously, placing the power lines on the back of the DRAM optimizes power distribution, thereby reducing voltage fluctuations within the DRAM, improving data transmission reliability and data transmission rate, and helping to reduce power consumption and improve energy efficiency.

[0165] Compared to DRAM, SRAM uses bistable flip-flops to store information, and multiple transistors are used to form memory cells. The information stored in SRAM is not lost when power is not interrupted. This allows the back power supply structure 11 to provide a more stable power supply to the SRAM, reducing voltage fluctuations and signal interference. Furthermore, the refresh circuit does not affect the SRAM, further demonstrating the advantages of the back power supply structure in reducing resistance and interference, thereby improving power supply efficiency and stability, and enhancing SRAM performance. Compared to DRAM, SRAM has a lower integration density, which allows more space for the back power supply structure 11, facilitating better implementation of back power supply technology without significantly impacting the existing SRAM structural layout.

[0166] The chip structure 10 provided in this embodiment does not require an additional increase in its area. By setting a conductive structure 500 within the memory array 20, connecting the first metal wiring 320 and the second metal wiring 420, a back-side power supply structure 11 composed of the second metal wiring 320 and the conductive structure 500 completes the back-side power supply network technology for the chip structure 10. In this embodiment, power supply to the memory cells 201 of the device layer 210 can be completed within the memory array 20, without needing to pass through higher metal layers. This reduces the transmission path of the power supply lines, thereby improving voltage drop, enhancing the performance of the chip structure 10, and reducing power consumption. Furthermore, since power supply to the memory cells 201 of the device layer 210 does not require passing through higher metal layers, it saves metal line resources. These saved higher metal layers can be used for signal traces, thereby improving the transmission rate of the chip structure 10. Simultaneously, since the solution in this embodiment improves voltage drop, it eliminates the need for excessive front-side traces in the memory array 20, thus reducing the usable area on the front side of the memory array 20.

[0167] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip structure, characterized by include: The memory array and peripheral logic devices located around the memory array; The device layer includes a memory unit disposed on the device layer; A first metal wiring is disposed on the device layer; the first metal wiring is electrically connected to the memory cell of the device layer. The back-side power supply structure includes a second metal wiring and a conductive structure; the second metal wiring is disposed on the side of the device layer away from the first metal wiring; The conductive structure is located in the memory array and extends through the device layer; the first metal wiring is electrically connected to the second metal wiring through the conductive structure.

2. The chip structure of claim 1, wherein The storage array has a storage cell area and an edge area, wherein the storage cells are located in the storage cell area and the edge area is located outside the storage cell area; The storage unit is used to store information, and the edge area is used to assist the storage unit in reading and writing the information; at least a portion of the second metal wiring is located in the edge area.

3. The chip structure of claim 2, wherein, The conductive structure is located in the edge region.

4. The chip structure according to claim 2 or 3, characterized in that The chip structure further includes a connection region located between the memory cell region and the edge region; the conductive structure is located in the connection region.

5. The chip structure according to any of claims 2-4, characterized in that, The edge region includes a first edge region and a second edge region; the first edge region extends along a first direction, and the second edge region extends along a second direction; the first direction and the second direction intersect, and both the first direction and the second direction are parallel to the plane where the storage array is located; The conductive structure includes a first conductive structure and a second conductive structure; the first conductive structure is located in the first edge region; the second conductive structure is located in the second edge region; the second metal wiring provides different power supply potentials to the memory cells of the device layer through the first conductive structure and the second conductive structure, respectively.

6. The chip structure according to any one of claims 1 to 5, characterized in that The conductive structure includes a first via and a first connection structure; the first via penetrates the device layer; the first connection structure is located on the side of the first via away from the second metal wiring and is electrically connected to the first via.

7. The chip structure of claim 6, wherein, Along a direction parallel to the plane where the device layer is located, the extension direction of the first connection structure is the same as the extension direction of the first via.

8. The chip structure according to any one of claims 1 to 7, characterized in that Along the thickness direction of the device layer, the size of the conductive structure is larger than the size of the device layer; the conductive structure is also in contact with the first metal wiring and the second metal wiring, respectively.

9. The chip structure according to any of claims 1 to 8, characterized in that The conductive structure includes a first connection structure, an interconnect structure, and a second connection structure; the interconnect structure and the second connection structure are connected and penetrate the device layer, and the first connection structure is located on the side of the interconnect structure away from the second connection structure; the second connection structure is in contact with the second metal wiring; the first connection structure is electrically connected to the second connection structure through the interconnect structure.

10. The chip structure according to any of claims 1 to 9, characterized in that The first metal wiring includes a first metal layer and a second metal layer stacked together; the first metal layer is located on the side of the second metal layer closer to the device layer; the extension direction of the first metal layer intersects the extension direction of the second metal layer.

11. The chip structure of claim 10, wherein, The second metal wiring supplies power to the memory cell of the device layer through the first metal layer.

12. The chip structure according to claim 10 or 11, characterized in that The storage array includes a storage cell area and an edge area, wherein the edge area is located outside the storage cell area; The second metal layer of the memory cell region is connected to the second metal layer of the edge region, and the second metal wiring supplies power to the memory cell of the device layer through the second metal layer; or, The first metal wiring further includes a third metal layer and a fourth metal layer; the third metal layer is located on the side of the second metal layer away from the first metal layer; the fourth metal layer is located on the side of the third metal layer away from the second metal layer; The first metal wiring in the storage cell area and the first metal wiring in the edge area are connected through the fourth metal layer, and the second metal wiring supplies power to the storage cell in the device layer through the fourth metal layer.

13. The chip structure according to any of claims 1 to 12, characterized in that The chip structure includes a static random access memory.

14. A memory, comprising: include: The controller and the chip structure as described in any one of claims 1-13, wherein the controller is electrically connected to the chip structure.

15. An electronic device, comprising: include: The printed circuit board and the memory as claimed in claim 14, wherein the printed circuit board is electrically connected to the memory.

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