Radio frequency receiver and electronic device
Patent Information
- Application Number
- PCT/CN2025/146335
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2025-12-27
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025146335_01102026_PF_FP_ABST
Abstract
Description
A radio frequency receiver and electronic device
[0001] This application claims priority to Chinese Patent Application No. 202510389405.7, filed on March 27, 2025, entitled “A Radio Frequency Receiver and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the fields of wireless communication and wireless positioning technology, and in particular to a radio frequency receiver and electronic device. Background Technology
[0003] Wireless technology is widely used in applications such as communications, target positioning, and radar detection. In wireless applications, electronic devices can transmit radio frequency (RF) signals to a target to complete the transmission of relevant service signals. Simultaneously, electronic devices need to receive RF signals to complete the reception of relevant service signals. To achieve the reception of RF signals, electronic devices typically include a receiver, which enables the reception and processing of target RF signals.
[0004] To improve the anti-interference capability of electronic devices in receiving target radio frequency signals and achieve higher precision in receiving and processing these signals, it is usually necessary to design more complex receiver components or increase the number of receivers to operate at more frequencies. However, these methods significantly increase the complexity of the circuit system, increasing both component area and power consumption. Modern intelligent electronic devices are mostly developing towards low power consumption, high precision, and high integration. Therefore, how to improve the processing accuracy of received radio frequency signals while reducing component area and power consumption remains a major challenge. Summary of the Invention
[0005] This application provides a radio frequency receiver and electronic device that improves the processing accuracy of received radio frequency signals while reducing device area overhead and power consumption.
[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0007] In a first aspect, a radio frequency (RF) receiver is provided, comprising a first receiving channel, a second receiving channel, a phase-locked loop (PLL), and a frequency divider circuit. The first receiving channel includes a first mixer for down-converting a first RF signal based on a first local oscillator (LO) signal. The PLL is coupled to both the first mixer and the frequency divider circuit, and provides the first LO signal to both the first mixer and the frequency divider circuit. The second receiving channel includes a second mixer and a third mixer, with the second mixer coupled to the third mixer. The frequency divider circuit is coupled to both the second mixer and the third mixer. The frequency divider circuit is used to: divide the first LO signal to obtain multiple second LO signals and multiple third LO signals; provide the multiple second LO signals to the second mixer; and provide the multiple third LO signals to the third mixer. The second receiving channel is used to perform a second down-conversion on the second RF signal based on the multiple second LO signals and the multiple third LO signals.
[0008] In receiver applications, when a multi-channel, multi-frequency receiver architecture is required, stronger anti-interference performance is needed. Therefore, the receiver can be configured as a sliding intermediate frequency (SIF) receiver. In a SIF receiver, a two-stage mixing structure can be used for down-conversion mixing to improve processing accuracy and anti-interference performance. Traditional two-stage mixing structures require two phase-locked loops (PLLs) to provide two local oscillator signals with fixed phases and frequencies to the two mixing structures, which then perform mixing based on their respective local oscillator signals. Furthermore, since down-conversion mixing generates image signals that interfere with signal processing, traditional two-stage mixing structures require an image signal filter between the two mixing structures to remove these image signals, ensuring that the final mixed target signal is a sinusoidal signal for subsequent digital processing. In this embodiment, while achieving high anti-interference performance and high processing accuracy based on a two-stage mixing structure, a single PLL provides the first local oscillator signal, and a frequency divider circuit generates the required local oscillator signals for both mixing structures based on this first local oscillator signal. Furthermore, each mixer structure receives multiple local oscillator signals as input, and during down-conversion mixing, each structure synthesizes multiple clock signals based on these input local oscillator signals. Based on the two-stage mixing and multi-clock synthesis, image signals can be suppressed, eliminating the need for image signal filters between the two-stage mixer structures. This allows the output signal to be a sinusoidal signal after the second down-conversion mixing. This implementation reduces the area and power consumption overhead of image signal filters. Moreover, by multiplexing the phase-locked loop and frequency divider circuit, multiple local oscillator signals required by the two-stage mixer structure can be obtained by using only one first local oscillator signal for frequency division, reducing the dependence on multiple phase-locked loop structures.
[0009] In one possible implementation, the second receiving channel includes multiple third mixers; each second mixer is coupled to one of the multiple third mixers; and a frequency divider circuit is coupled to one of the multiple third mixers. Outputting a third local oscillator signal to the third mixer includes outputting multiple corresponding third local oscillator signals to each third mixer, with different frequency values for the corresponding third local oscillator signals between different third mixers. In this embodiment, a single second receiving channel can have multiple receiving channels operating at different frequencies, thereby achieving multi-channel, multi-frequency receiving applications. Multiple receiving channels can reuse the second mixer, with each receiving channel corresponding to a different third mixer. The frequency divider circuit can output a second local oscillator signal applicable to all third mixers to the second mixer, and output a third local oscillator signal with corresponding frequency values to different third mixers, so that each receiving channel can obtain mixing processing at different operating frequencies based on multi-phase clock synthesis and secondary mixing. In this implementation, the second receiving channel can save the filters for image signal filtering in multiple receiving paths, can reuse the same frequency division circuit to obtain the required local oscillator signal, and can also save the device overhead of multiple second mixers, so that the application scenarios of multi-path and multi-frequency receiving channels can greatly reduce device area and power consumption.
[0010] In one possible implementation, the second mixer includes an I-channel second mixer and a Q-channel second mixer. The I-channel and Q-channel second mixers constitute a first synthesizer mixer; the third mixer includes an I-channel third mixer and a Q-channel third mixer. The first synthesizer mixer includes a first switch group and a second switch group; each of the first and second switch groups includes multiple parallel analog switches; the input terminals of the first and second switch groups are used to input a first radio frequency signal; multiple second local oscillator signals correspond one-to-one with the controlled terminals of the multiple analog switches within the first and second switch groups, and each second local oscillator signal is used to control the conduction state of a corresponding analog switch. In the I-channel second mixer, the output terminals of the corresponding first and second switch groups are used to output an I-channel primary down-conversion signal to the I-channel third mixer. In the Q-channel second mixer, the output terminals of the corresponding first and second switch groups are used to output a Q-channel primary down-conversion signal to the Q-channel third mixer. In this embodiment, the second receiving channel adopts an orthogonal I-channel and Q-channel dual-channel radio frequency receiving and processing architecture, which can increase the processing accuracy of the received signal and further suppress interference signals.
[0011] In some possible implementations, the multiple second local oscillator signals have different phases, and the multiple third local oscillator signals have different phases. In the embodiments of this application, the multiple second local oscillator signals have different phases. When the second mixer performs multi-clock synthesis based on the multiple second local oscillator signals, the multi-phase clock synthesis with different phases can more easily synthesize the local oscillator signals required for different frequency bands in different application scenarios. Similarly, the multiple third local oscillator signals also have different phases. The combination of second and third local oscillator signals with different phases can achieve more accurate equivalent simulation of the local oscillator signal, so as to obtain the corresponding sinusoidal signal by equivalent downconversion without the need for a mirror filter.
[0012] In one example, the first switch group and the second switch group together include eight analog switches, and the multiple second local oscillator signals include eight second local oscillator signals with different phases, with each of the eight second local oscillator signals corresponding to one of the eight analog switches.
[0013] In one example, the I-channel third mixer and the Q-channel third mixer constitute a second synthesizer. This second synthesizer includes a first analog switch, a second analog switch, a third analog switch, and a fourth analog switch. The input terminals of the first and second analog switches serve as the first input terminals of the second synthesizer, coupled to the output terminals of their respective first switch groups. The input terminals of the third and fourth analog switches serve as the second input terminals of the second synthesizer, coupled to the output terminals of their respective second switch groups. The output terminals of the first and third analog switches, coupled together, serve as the first output terminal of the second synthesizer. The output terminals of the second and fourth analog switches, coupled together, serve as the second output terminal of the second synthesizer. The controlled terminals of the first, second, third, and fourth analog switches are each used to input a corresponding third local oscillator signal, and each third local oscillator signal controls the conduction state of its corresponding analog switch. In the I-channel third mixer, the first and second input terminals of the corresponding second synthesizer are used to input the I-channel primary down-converted signal, and the first and second output terminals of the corresponding second synthesizer are used to output the I-channel secondary down-converted signal. In the Q-channel third mixer, the first and second input terminals of the corresponding second synthesizer are used to input the Q-channel primary down-converted signal, and the first and second output terminals of the corresponding second synthesizer are used to output the Q-channel secondary down-converted signal.
[0014] In one example, the third local oscillator signal corresponding to the I-channel third mixer and the third local oscillator signal corresponding to the Q-channel third mixer have different phases.
[0015] In one example, in the I-channel third mixer or the Q-channel third mixer, the controlled terminals of the first, second, third, and fourth analog switches of the corresponding second synthesizer are used to input a third local oscillator signal of the same phase. The level changes of the third local oscillator signal at the controlled terminals of the first and fourth analog switches are the same, while the level changes of the third local oscillator signal at the controlled terminals of the second and third analog switches are opposite to the level changes of the third local oscillator signal at the controlled terminal of the first analog switch.
[0016] In one possible implementation, depending on the operating frequency of the second receiving channel, the phase and number of multiple second local oscillator signals can be adjusted, as can the phase and number of multiple third local oscillator signals, to achieve multi-phase frequency synthesis of a local oscillator signal with the required frequency value corresponding to the operating frequency. In addition, the frequency division ratio between the first, second, and third local oscillator signals can also be adjusted. The duty cycle between the multiple second local oscillator signals and the duty cycle between the multiple third local oscillator signals can also be adjusted. Various parameters can be adaptively adjusted according to different application requirements. This application illustrates this with the following embodiment:
[0017] For example, a frequency divider circuit divides a first local oscillator signal with a frequency of 1584MHz into a second local oscillator signal with a frequency of 792MHz, generating eight second local oscillator signals with different phases. Within one cycle, these eight signals have different duty cycles, and are named P1, P2, P3, P4, P5, P6, P7, and P8. Therefore, within one cycle, the duty cycle of these eight signals is 12.5%. The frequency divider circuit also divides the 792MHz second local oscillator signal to obtain a third local oscillator signal with a frequency of 396MHz, generating three third local oscillator signals with two different phases. For example, the frequency divider circuit generates four third local oscillator signals: P9, P10, P9', and P10'. P9 and P9' are in phase, and P10 and P10' are in phase. The voltage levels of P9 and P9' are opposite, and the voltage levels of P10 and P10' are opposite. All four third local oscillator signals have a 50% duty cycle, but the period lengths of the third local oscillator signals P9, P9', P10, and P10' are twice the period lengths of the eight second local oscillator signals P1, P2, P3, P4, P5, P6, P7, and P8. The third local oscillator signals P10 and P10' are output to the I-channel third mixer I2. The third local oscillator signal P10 corresponds to the first and fourth analog switches in the I-channel third mixer, and the third local oscillator signal P10' corresponds to the second and third analog switches in the I-channel third mixer. The third local oscillator signals P9 and P9' are output to the Q-channel third mixer. The third local oscillator signal P9 corresponds to the first and fourth analog switches in the Q-channel third mixer, and the third local oscillator signal P9' corresponds to the second and third analog switches in the Q-channel third mixer. Eight second local oscillator signals P1, P2, P3, P4, P5, P6, P7, and P8 are output to the first synthesizer structures corresponding to the I-channel and Q-channel second mixers, respectively. In the I-channel second mixer, the four second local oscillator signals P1, P4, P7, and P8 correspond to the four analog switches in the first switch group. The four second local oscillator signals P2, P3, P5, and P6 correspond to the four analog switches in the second switch group. In the Q-channel second mixer, the four second local oscillator signals P3, P4, P5, and P8 correspond to the four analog switches in the first switch group, and the four second local oscillator signals P1, P2, P6, and P7 correspond to the four analog switches in the second switch group.In this embodiment, multi-phase clock synthesis is performed by using the second local oscillator signals P1, P2, P3, P4, P5, P6, P7, and P8 during the mixing process of the I-channel second mixer and the Q-channel second mixer. Multi-phase clock synthesis is also performed by using the third local oscillator signals P9, P10, P9', and P10' during the mixing process of the I-channel third mixer and the Q-channel third mixer. By combining the two mixing processes, the multiple second local oscillator signals and the multiple third local oscillator signals can be equivalent to a sinusoidal local oscillator signal with a frequency of 1188MHz, thereby achieving the purpose of suppressing the image signal and down-converting the mixing to obtain the sinusoidal target signal.
[0018] In one possible implementation, the frequency divider circuit includes a first frequency divider and a second frequency divider; a phase-locked loop (PLL) is coupled to the first frequency divider; the first frequency divider is coupled to both the second frequency divider and the second mixer. The second frequency divider is coupled to a third mixer. The PLL is used to: output a first local oscillator signal to the first frequency divider. The first frequency divider is used to: perform frequency division processing on the input first local oscillator signal to obtain multiple second local oscillator signals; and output the second local oscillator signals to both the second frequency divider and the second mixer. The second frequency divider is used to: perform frequency division processing on the input second local oscillator signals to obtain multiple third local oscillator signals; and output the third local oscillator signal to the third mixer. In this embodiment, multiple receivers of the same or different types can reuse a single PLL circuit, greatly reducing the area overhead and power consumption caused by a large number of PLL devices.
[0019] For example, when a second receiving channel includes multiple receiving paths formed by multiple third mixers, multiple second frequency dividers can be configured in the frequency divider circuit, and the multiple second frequency dividers are coupled to the multiple third mixers accordingly. Each third mixer in each receiving path can obtain multiple third local oscillator signals from the corresponding second frequency divider. In this embodiment, when multiple receiving channels are designed within a second receiving channel, the multiple receiving channels can also reuse a single phase-locked loop to generate the corresponding local oscillator signal, greatly reducing the area overhead and power consumption caused by a large number of phase-locked loop devices.
[0020] In one possible implementation, besides the mixing devices within the RF receiver being able to reuse a frequency divider circuit and a phase-locked loop to obtain the local oscillator signal, other related devices can also reuse a frequency divider circuit and a phase-locked loop to obtain the desired clock frequency signal:
[0021] For example, the radio frequency receiver also includes a data processor; the frequency divider circuit is further configured to: divide the first local oscillator signal to obtain a first clock frequency signal, and output the first clock frequency signal to the data processor.
[0022] For example, the second receiving channel further includes an analog-to-digital converter (ADC); the ADC is coupled to a third mixer; and a frequency divider circuit is also coupled to the ADC. The frequency divider circuit is further configured to: divide the first local oscillator signal to obtain a second clock frequency signal, and output the second clock frequency signal to the ADC.
[0023] In the embodiments of this application, a phase-locked loop and a frequency divider circuit can also be reused to provide the required clock frequency signal for the analog-to-digital converter and the data processor.
[0024] In one possible implementation, in addition to the above-described methods of reducing and reusing devices to reduce power consumption, the following methods can also be used to control the operating power of the devices to achieve the purpose of reducing power consumption:
[0025] Exemplarily, the RF receiver further includes a saturated power detector and a state switching circuit. The second receiving channel further includes a low-pass filter and a variable gain amplifier. The output stage of the third mixer is sequentially coupled to the low-pass filter, the variable gain amplifier, and the analog-to-digital converter. The input terminal of the saturated power detector is coupled to the RF input terminal of the second mixer, and the output terminal of the saturated power detector is coupled to the first input terminal of the state switching circuit. The second input terminal of the state switching circuit is coupled to the output terminal of the analog-to-digital converter. The saturated power detector is used to: output a power detection signal to the state controller, the power detection signal indicating the power value of the first RF signal input to the second mixer. The state switching circuit is used to: output a control signal based on the power detection signal; when the power value of the first RF signal is greater than a preset threshold, the control signal controls at least one of the devices among the low-pass filter, the variable gain amplifier, and the analog-to-digital converter to increase its operating power; when the power value of the first RF signal is less than the preset threshold, the control signal controls at least one of the devices among the low-pass filter, the variable gain amplifier, and the analog-to-digital converter to decrease its operating power. In this embodiment, the processed signal of the receiving channel may contain out-of-band (OB) interference signals, which are interference signals whose frequency values deviate significantly from the operating frequency band of the receiving channel. Typically, to combat OB interference, low-pass filters and variable gain amplifiers are designed with fourth-order or higher interference suppression. However, this requires considerable processing accuracy from the low-pass filter and variable gain amplifier, and significantly increases their power consumption. Furthermore, because the low-pass filter and variable gain amplifier employ fourth-order or higher suppression, the analog-to-digital converter (ADC) in the subsequent stage cannot detect the OB interference signals. Typically, this embodiment adds a saturated power detector to detect the power of the input first RF signal. The saturated power detector incorporates relevant nonlinear devices (such as diodes), which have operating frequency regions divided into linear, nonlinear, and saturation regions. When the input signal is located in the OB frequency region, it falls into the saturation operating region of these devices, thereby enabling the detection of OB interference signals. The saturated power detector outputs a relevant power detection signal to the state switching circuit. The state switching circuit, based on the indication of the power detection signal, can output a control signal to control the operating frequency of one or more of the low-pass filter, variable gain amplifier, and analog-to-digital converter. For example, when the saturated power detector detects a far-band interference signal, it can control these devices to increase their operating power to improve anti-interference performance. Conversely, when the saturated power detector does not detect a far-band interference signal, it can control these devices to operate at an appropriate power to reduce unnecessary high power consumption. This embodiment further reduces the power consumption of the RF receiver compared to the above embodiments.
[0026] In one possible implementation, the radio frequency receiver can be used in scenarios such as Global Navigation Satellite System (GNSS), Bluetooth communication, WiFi protocol communication, and satellite communication. It can also be used in applications such as radar scanning.
[0027] For example, when an RF receiver is used in the GNSS field, the operating frequency band of the second receiving channel can be any of the following: L5 band, L2 band, L1 band, E1 band, E5 band, E6 band, B1 band, B2 band, and B3 band. When the RF receiver includes multiple second receiving channels, the different second receiving channels can be the same or different frequency bands among these. Similarly, the operating frequency band of the first receiving channel can also be any of these frequency bands. For example, taking multiple receivers including second receiving channels and first receiving channels as an example, the first receiving channel can operate in the L1 band, and the second receiving channel can operate in the L5 band.
[0028] Secondly, embodiments of this application also provide an electronic device, which includes a circuit board and a radio frequency (RF) receiver as described in the first aspect above. The RF receiver is disposed on the circuit board. The RF receiver is used to receive RF signals and perform down-conversion mixing and digitization processing on the RF signals.
[0029] Regarding the technical principles and beneficial effects of the second aspect mentioned above, please refer to the relevant description of the first aspect mentioned above, which will not be repeated here. Attached Figure Description
[0030] Figure 1 is a schematic diagram of the structure of an electronic device and a radio frequency receiver provided in an embodiment of this application;
[0031] Figure 2 is a schematic diagram of the structure of an RF receiver provided in an embodiment of this application;
[0032] Figure 3 is a schematic diagram of the structure of a first radio frequency receiver provided in an embodiment of this application;
[0033] Figure 4 is a schematic diagram of the structure of a second radio frequency receiver provided in an embodiment of this application;
[0034] Figure 5 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application;
[0035] Figure 6 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application;
[0036] Figure 7 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application;
[0037] Figure 8 is a schematic diagram of the structure of a first synthesizer and a second synthesizer provided in an embodiment of this application;
[0038] Figure 9 is a schematic diagram of the duty cycle distribution of a second local oscillator signal and a third local oscillator signal provided in an embodiment of this application;
[0039] Figure 10 is a schematic diagram showing the correspondence between the second local oscillator signal and the third local oscillator signal and the various analog switches in the secondary mixing structure provided in the embodiment of this application;
[0040] Figure 11 is a waveform simulation diagram of the I-channel equivalent local oscillator signal and the Q-channel equivalent local oscillator signal obtained based on the embodiments of Figures 8 and 9 provided in this application.
[0041] Figure 12 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application;
[0042] Figure 13 is a schematic diagram of a frequency divider circuit provided in an embodiment of this application;
[0043] Figure 14 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application;
[0044] Figure 15 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application;
[0045] Figure 16 is a schematic diagram of the structure of a third radio frequency receiver provided in an embodiment of this application. Detailed Implementation
[0046] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.
[0047] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0048] The terms "connection" and "coupling" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.
[0049] First, some basic concepts involved in this application will be explained:
[0050] Frequency mixing refers to the process of mixing the signal to be processed with the local oscillator signal (also known as the clock frequency signal) generated by a fixed local oscillator (LO). The process of mixing a low-frequency signal to be processed with a high-frequency LO signal to obtain a high-frequency component is called up-conversion. Conversely, the process of mixing a high-frequency signal to be processed with a low-frequency LO signal to obtain a low-frequency component is called down-conversion.
[0051] A mirror signal refers to a signal generated when a radio frequency (RF) signal is mixed using a local oscillator (LO) signal, resulting in two new frequency components. The frequency values of these two components are symmetrical about the LO signal. Typically, the component with the lower frequency value is used as the target signal generated by the mixing process, while the component with the higher frequency value is considered the mirror signal of the target signal, symmetrical about the LO signal in the frequency spectrum.
[0052] Image interference refers to the phenomenon where both the image signal and the useful target signal are superimposed onto the intermediate frequency (IF) signal during down-conversion, causing interference. Furthermore, this interference cannot be removed, resulting in a severe deterioration of the output signal-to-noise ratio (SNR). In practical applications, after down-conversion mixing, the resulting target signal needs to be sinusoidal so that subsequent signal processing can easily demodulate and extract relevant target information. Without filtering out the image signal, it superimposes with the target signal and introduces intermodulation distortion with other interference signals, resulting in a highly chaotic waveform from which useful target information is difficult to extract.
[0053] A standard intermediate frequency (IF) receiver architecture refers to converting the received high-frequency signal to a fixed intermediate frequency (IF) using a mixer, followed by subsequent filtering and signal amplification at that fixed IF frequency. Typically, standard IF receivers are simple in design and commonly used in fixed-frequency satellite television and radio stations. However, they have relatively poor interference resistance and scene adaptability.
[0054] A sliding intermediate frequency (IF) receiver architecture refers to a receiver that operates by changing the intermediate frequency band it processes in response to variations in the input signal frequency. It can dynamically adjust its operating IF range to adapt to different application requirements. Sliding IF receiver architectures are typically used in complex electromagnetic environments, such as high-precision positioning scenarios, radar systems, or multi-channel communication scenarios. In these scenarios, to avoid interfering with other occupied channels or being affected by interfering signals, the IF receiver architecture can flexibly select a specific frequency band.
[0055] Wireless technology is widely used in applications such as communications, target positioning, and radar detection. In wireless applications, electronic devices can transmit radio frequency (RF) signals to a target to complete the transmission of relevant service signals. Simultaneously, electronic devices need to receive RF signals to complete the reception of relevant service signals. To achieve the reception of RF signals, electronic devices typically include a receiver, which enables the reception and processing of target RF signals.
[0056] The following example illustrates its application in satellite positioning scenarios:
[0057] In the application scenarios of Global Navigation Satellite System (GNSS), there are three components: the space segment, the ground segment, and the user segment. The space segment includes GNSS satellites, the ground segment includes master control stations for transmitting data, and the user segment includes all electronic devices that can receive satellite information and output position information.
[0058] Taking a user-side electronic device as an example, as shown in Figure 1, the electronic device 10000 includes a radio frequency (RF) receiver 1000 and an antenna module 2000. The RF receiver 1000 is coupled to the antenna module 2000, and the RF receiver 1000 receives RF signals through the antenna module 2000. The RF receiver 1000 of the electronic device 1000 includes an RF integrated unit 100 and a data processor 200. The RF integrated unit 100 includes a low-noise amplifier (LNA) 110, a down-conversion mixer 120, a low-pass filter (LPF) 130, an intermediate frequency amplifier 140, an analog-to-digital converter (ADC) 150, and a local oscillator phase-locked loop (PLL) 160. The RF integrated unit 100 receives RF signals through the antenna radiator (ANT) within the antenna module 2000. The low-noise amplifier 110 amplifies the received RF signals. The down-conversion mixer 120 obtains the local oscillator signal from the local oscillator phase-locked loop 160 and the amplified radio frequency signal from the low-noise power amplifier 110. Based on the local oscillator signal, it performs down-conversion processing on the amplified radio frequency signal to obtain the down-converted mixed signal. The down-converted mixed signal is filtered by the low-pass filter 130 to obtain the target intermediate frequency signal after filtering out interference signals. The target intermediate frequency signal is then amplified by the intermediate frequency amplifier 140, and the analog-to-digital converter 150 converts the intermediate frequency signal from analog to digital form. Finally, the data processor 200 processes the digital signal to complete the target positioning-related business processing.
[0059] For example, the data processor 200 can be a digital baseband (DBB) chip or a central processor (CPU).
[0060] The structure and principle of the receiver in wireless communication application scenarios are similar to those in positioning scenarios. Please refer to the description of the embodiment in Figure 1 above, which will not be repeated here.
[0061] The embodiment in Figure 1 above briefly illustrates the basic working principle of a receiver using a receiver structure example. However, in wireless positioning or wireless communication scenarios, to improve positioning accuracy or communication accuracy, multiple operating frequencies are typically used for signal transmission and reception. The following explanation uses a positioning application scenario as an example:
[0062] Figure 2 illustrates an exemplary RF receiver architecture based on multiple receivers for receiving multiple operating frequency channels. The RF receiver 1000 may include two or more receive channels RX, each of which includes a corresponding RF integrated unit 100. The input of each receive channel RX is coupled to a different antenna radiator ANT in the antenna module 2000, and the output of each receive channel RX is coupled to a data processor 200.
[0063] For example, taking the RF receiver 1000 in the embodiment of FIG2 as an example, which includes two receiving channels RX, as shown in FIG3, the two receiving channels RX in the first RF receiver 1000A are both architectures including the antenna module 2000 and the internal structure of the RF integrated unit shown in FIG1. The two receiving channels RX are coupled to the antenna module 2000 and the data processor 200, respectively. In the RF receiver 1000 shown in FIG3, each receiving channel RX corresponds to a local oscillator phase-locked loop 160. The two receiving channels RX operate at different frequency points. For example, one receiving channel RX can operate in the L1 frequency band, and the other receiving channel RX can operate in the L5 frequency band. Then, the two local oscillator phase-locked loops 160 provide local oscillator signals of corresponding frequency values to the down-conversion mixer 120 in the corresponding receiving channel RX according to the corresponding operating frequency band. At this time, the first RF receiver 1000A also needs to be equipped with a selector and at least one frequency divider. The two local oscillator phase-locked loops 160 provide local oscillator signals to the selector, respectively. The selector outputs a corresponding local oscillator signal to at least one frequency divider according to the actual application. The input local oscillator signal is divided by at least one selector to obtain a clock frequency signal that meets the operation requirements of the analog-to-digital converter 150 and a clock frequency signal that meets the operation requirements of the data processor 200.
[0064] In the embodiment shown in Figure 3, the architecture of the receiving channel RX within the first RF receiver 1000A, including the internal circuit structure of the RF integrated unit shown in Figure 1, will be described. In this architecture, both receiving channels RX employ a conventional intermediate frequency (IF) receiving architecture. Under this IF receiving architecture, the anti-interference performance between multiple channels and the signal reception and processing performance are poor.
[0065] In multi-channel applications, a sliding intermediate frequency (SIF) receiver architecture can be used for the receiver channel (RX) to achieve higher processing accuracy. However, in this architecture, with a high communication dynamic range, the RX channel faces greater image signal interference during mixing. Therefore, when high performance and high accuracy are required, a double-mixing architecture is typically used in SIF receivers.
[0066] Taking the second RF receiver with a sliding intermediate frequency (IF) receiver architecture employing a double-mixing structure in the RF receiver 1000 shown in Figure 2 as an example, as shown in Figure 4, the second RF receiver 1000B based on the double-mixing structure includes multiple receiver channels RX. Each receiver channel RX includes a low-noise power amplifier 110B, a first down-conversion mixer 121B, a mirror noise filter 180B, a second down-conversion mixer 122B, a low-pass filter 130B, an IF amplifier 140B, an analog-to-digital converter 150B, a first local oscillator (LOP) phase-locked loop (PLL) 161B, and a second LO PLL 162B. The first LO PLL 161B provides the first down-conversion mixer 121B with the local oscillator signal from the first mixing, and the second LO PLL 162B provides the second down-conversion mixer 122B with the local oscillator signal from the second mixing. The local oscillator signals from the first mixing and the second mixing have different frequency values, and both local oscillator signals are signals with fixed frequency and fixed phase.
[0067] In the embodiment shown in Figure 4, the low-noise power amplifier 110B acquires the radio frequency (RF) signal from the antenna module 2000. After amplifying the RF signal, the first down-conversion mixer 121B performs a first down-conversion mixing process on the RF signal based on the local oscillator signal from the first mixing. The RF signal after the first down-conversion mixing process has a target signal and an image signal after the first down-conversion. After filtering the image signal through the image noise filter 180B, the filtered target signal after the first down-conversion is output to the second down-conversion mixer 122B. The second down-conversion mixer 122B performs a down-conversion mixing process on the target signal after the first down-conversion based on the local oscillator signal from the second mixing process to obtain the mixed intermediate frequency (IF) signal. The interference signal on the IF signal is filtered out by the low-pass filter 130B. Then, the IF amplifier 140B and the analog-to-digital converter 150B process the signal sequentially, and the resulting digital signal is transmitted to the data processor 200B.
[0068] The embodiment shown in Figure 4 enables higher-precision multi-frequency reception in multi-channel (RX) reception scenarios. However, in this application, the number of required components increases with the number of receiving channels (e.g., the number of image noise filters 180B, local oscillator phase-locked loops, etc.). This leads to significant increases in component costs, as well as increased equipment area and power consumption. Furthermore, the anti-interference performance requirements of the receiving architecture also increase in multi-channel, multi-frequency applications. These high anti-interference requirements necessitate high power consumption and complex component designs. Therefore, reducing component area and power consumption while improving reception performance remains a major challenge.
[0069] To reduce device area and power consumption while improving the receiving performance of the RF receiver, the RF receiver 1000 shown in Figure 2 can be implemented as a third RF receiver with down-conversion mixing based on a double-mixing structure using multi-phase clock synthesis. In this case, as shown in Figure 5, the third RF receiver 1000C includes a first receiving channel RX1, a second receiving channel RX2, a phase-locked loop 400C, and a frequency divider circuit 300C. The first receiving channel RX1 includes a first mixer 120C1, used to down-convert a first RF signal based on a first local oscillator signal. The phase-locked loop 400C is coupled to both the first mixer 120C1 and the frequency divider circuit 300C, providing the first local oscillator signal to both. The second receiving channel RX2 includes a second mixer 110C2 and a third mixer 120C2, with the second mixer 110C2 coupled to the third mixer 120C2. The frequency divider circuit 300C is coupled to the second mixer 110C2 and the third mixer 120C2, respectively. The frequency divider circuit 300C is used to: divide the first local oscillator signal to obtain multiple second local oscillator signals and multiple third local oscillator signals; provide the multiple second local oscillator signals to the second mixer 110C2; and provide the multiple third local oscillator signals to the third mixer 120C2. The second receiving channel RX2 is used to perform a second down-conversion on the second radio frequency signal based on the multiple second local oscillator signals and the multiple third local oscillator signals.
[0070] In the embodiment shown in FIG5 of this application, the first receiving channel RX1 and the second receiving channel RX2 can multiplex a phase-locked loop 400C and a frequency divider circuit 300C to obtain different local oscillator signals required for their respective down-conversion. The first mixer 120C1 in the first receiving channel RX1 performs down-conversion processing on the first radio frequency signal using the first local oscillator signal provided by the frequency divider circuit 300C. The second mixer 110C2 in the second receiving channel RX2 performs a first down-conversion mixing process on the second radio frequency signal based on multiple second local oscillator signals; the multiple second local oscillator signals can achieve multi-clock synthesis during down-conversion. After obtaining the down-converted signal based on the second local oscillator signals, the third mixer 110C2 further performs down-conversion mixing on the down-converted signal based on multiple third local oscillator signals; the multiple third local oscillator signals can also achieve multi-clock synthesis during down-conversion mixing. Based on multi-clock synthesis and two mixing operations, the effect of down-converting the radio frequency signal using a local oscillator signal equivalent to an approximately sinusoidal signal can be achieved. Under this equivalent mixing process, the image signal generated by the secondary mixing process in the sliding intermediate frequency receiver can be suppressed, thereby achieving the removal of the image signal without the image noise filter 180B shown in the embodiment of Figure 4. This allows the target signal after down-conversion mixing based on the multi-phase synthesis and secondary mixing process to directly exhibit sine-like waveform characteristics. This reduces the area and power consumption overhead caused by setting up the image noise filter while maintaining high performance and accuracy in the second receiving channel RX2. At the same time, suppressing the image signal also facilitates further design of the device to reduce power consumption and area overhead. Furthermore, different receivers reuse the same phase-locked loop 400, thereby reducing the area and power consumption caused by multiple phase-locked loops.
[0071] For example, as shown in FIG6, the second receiving channel RX2 further includes a low-pass filter 130C2, a variable gain amplifier (VGA) 140C2, and an analog-to-digital converter 150C2. The low-pass filter 130C2 is used to filter the signal after the second down-conversion. The variable gain amplifier 140C2 is used to amplify the gain of the filtered signal. After gain amplification, the analog-to-digital converter 150C2 converts the intermediate frequency signal after the second down-conversion into a digital signal and transmits it to the data processor 200C for processing.
[0072] For example, as shown in FIG6, the first receiving channel RX1 is further provided with a low-noise power amplifier 110C1, a low-pass filter 130C1, a variable gain power amplifier 140C1, and an analog-to-digital converter 150C1. The low-noise power amplifier 110C1 amplifies the first radio frequency signal input to the first mixer 120C1. The variable gain power amplifier 140C1 and the analog-to-digital converter 150C1 perform subsequent signal processing on the down-converted output signal of the first mixer 120C1.
[0073] In some possible implementations, the signal after one down-conversion includes an I-channel first down-converted signal and a Q-channel first down-converted signal. Exemplarily, as shown in FIG7, in the third RF receiver 1000C, the second mixer 110C2 includes an I-channel second mixer I1 and a Q-channel second mixer Q1; the I-channel second mixer I1 and the Q-channel second mixer Q1 are a first synthesizer mixer FM1; the third mixer 120C2 includes an I-channel third mixer I2 and a Q-channel third mixer Q2. The low-pass filter 130C2 includes an I-channel low-pass filter 130IC2 and a Q-channel low-pass filter 130QC2; the variable gain amplifier 140C2 includes an I-channel variable gain amplifier 140IC2 and a Q-channel variable gain amplifier 140QC2. The analog-to-digital converter 150C2 includes an I-channel analog-to-digital converter 150IC2 and a Q-channel analog-to-digital converter 150QC2. In the embodiment shown in Figure 7 of this application, the second receiving channel RX adopts an orthogonal I-path and Q-path radio frequency processing architecture, which can increase the processing accuracy of the received signal and further suppress interference signals.
[0074] In some examples, both the I-channel second mixer I1 and the Q-channel second mixer Q1 in Figure 7 adopt the structure of the first synthesizer mixer FM1. As shown in Figure 8, the first synthesizer mixer FM1 includes a first switch group FMS1 and a second switch group FMS2; the first switch group FMS1 and the second switch group FMS2 each include multiple parallel analog switches S; the input terminals of the first switch group FMS1 and the second switch group FMS2 are used to input second RF signals; multiple second local oscillator signals correspond one-to-one with the controlled terminals of multiple analog switches S in the first switch group FMS1 and the second switch group FMS2, and each second local oscillator signal is used to control the conduction state of a corresponding analog switch S. In the I-channel second mixer I1, the output terminals of the corresponding first switch group FMS1 and the second switch group FMS2 are used to output an I-channel primary down-conversion signal to the I-channel third mixer I2. In the second mixer Q1 of the Q-channel, the output terminals of the corresponding first switch group FMS1 and the second switch group FMS2 are used to output the Q-channel primary down-conversion signal to the third mixer Q2 of the Q-channel.
[0075] In some examples, the signal after secondary down-conversion includes an I-channel secondary down-converted signal and a Q-channel secondary down-converted signal. As shown in Figure 8, the I-channel third mixer I2 and the Q-channel third mixer Q2 constitute the second synthesizer FM2. The second synthesizer FM2 includes a first analog switch S1, a second analog switch S2, a third analog switch S3, and a fourth analog switch S4. The input terminals of the first analog switch S1 and the second analog switch S2 serve as the first input terminals of the second synthesizer FM2, coupled to the output terminals of the corresponding first switch group FMS1. The input terminals of the third analog switch S3 and the fourth analog switch S4 serve as the second input terminals of the second synthesizer FM2, coupled to the output terminals of the corresponding second switch group FMS2. The output terminal of the first analog switch S1, coupled with the output terminal of the third analog switch S3, serves as the first output terminal of the second synthesizer FM2. The output terminal of the second analog switch S2, coupled with the output terminal of the fourth analog switch S4, serves as the second output terminal of the second synthesizer FM2. The controlled terminals of the first analog switch S1, the second analog switch S2, the third analog switch S3, and the fourth analog switch S4 are each used to input a corresponding third local oscillator signal. Each third local oscillator signal controls the conduction state of its corresponding analog switch S. In the I-channel third mixer I2, the first and second input terminals of the corresponding second synthesizer FM2 are used to input the I-channel primary down-converted signal, and the first and second output terminals of the corresponding second synthesizer FM2 are used to output the I-channel secondary down-converted signal. In the Q-channel third mixer Q2, the first and second input terminals of the corresponding second synthesizer FM2 are used to input the Q-channel primary down-converted signal, and the first and second output terminals of the corresponding second synthesizer FM2 are used to output the Q-channel secondary down-converted signal.
[0076] For example, the first switch group FMS1 and the second switch group FMS2 together include eight analog switches S, and the multiple second local oscillator signals include eight second local oscillator signals with different phases. Each of the eight second local oscillator signals corresponds one-to-one with one of the eight analog switches S. The third local oscillator signal corresponding to the I-channel third mixer I2 and the third local oscillator signal corresponding to the Q-channel third mixer Q2 have different phases. A specific example is given below:
[0077] For example, the duty cycle distribution of multiple second local oscillator signals and multiple third local oscillator signals can be illustrated in Figure 9. The frequency divider circuit 300C divides the first local oscillator signal with a frequency of 1584MHz into a second local oscillator signal with a frequency of 792MHz, generating eight second local oscillator signals with different phases. As shown in Figure 9, within one cycle, the eight local oscillator signals with different phases have different duty cycles. These eight second local oscillator signals are named P1, P2, P3, P4, P5, P6, P7, and P8. Therefore, within one cycle, the duty cycle of the eight second local oscillator signals is 12.5%. The frequency divider circuit 300C also divides the 792MHz second local oscillator signal to obtain a third local oscillator signal with a frequency of 396MHz, generating three third local oscillator signals with two different phases. For example, the frequency divider circuit 300C generates four third local oscillator signals, namely P9, P10, P9', and P10'. P9 and P9' have the same phase, and P10 and P10' have the same phase. The voltage levels of P9 and P9' change in opposite directions, as do those of P10 and P10'. All four third local oscillator signals have a 50% duty cycle, but the period lengths of the third local oscillator signals P9, P9', P10, and P10' are twice the period lengths of the eight second local oscillator signals P1, P2, P3, P4, P5, P6, P7, and P8.
[0078] For example, in either the I-channel third mixer I2 or the Q-channel third mixer Q2, the controlled terminals of the first analog switch S1, the second analog switch S2, the third analog switch S3, and the fourth analog switch S4 of the corresponding second synthesizer FM2 are used to input a third local oscillator signal of the same phase. The level changes of the third local oscillator signal at the controlled terminals of the first and fourth analog switches S4 are the same, while the level changes of the third local oscillator signal at the controlled terminals of the second and third analog switches S3 are opposite to those at the controlled terminal of the first analog switch S1. For instance, the four third local oscillator signals P9, P10, P9', and P10' shown in the embodiment of Figure 9 are output to the I-channel third mixer I2 and the Q-channel third mixer Q2. For example, as shown in Figure 10, the third local oscillator signals P10 and P10' are output to the I-channel third mixer I2. The third local oscillator signal P10 corresponds to the first analog switch S1 and the fourth analog switch S4 in the I-channel third mixer I2, respectively. The third local oscillator signal P10' corresponds to the second analog switch S3 and the third analog switch S4 in the I-channel third mixer I2, respectively. The third local oscillator signals P9 and P9' are output to the Q-channel third mixer Q2. The third local oscillator signal P9 corresponds to the first analog switch S1 and the fourth analog switch S4 in the Q-channel third mixer Q2, respectively. The third local oscillator signal P9' corresponds to the second analog switch S3 and the third analog switch S4 in the Q-channel third mixer Q2, respectively.
[0079] As shown in Figure 10, the eight second local oscillator signals P1, P2, P3, P4, P5, P6, P7, and P8 shown in the embodiment of Figure 9 are output to the first synthesizer FM1 structure corresponding to the I-channel second mixer I1 and the Q-channel second mixer Q1, respectively. In the I-channel second mixer I1, the four second local oscillator signals P1, P4, P7, and P8 correspond to the four analog switches S of the first switch group FMS1. The four second local oscillator signals P2, P3, P5, and P6 correspond to the four analog switches S of the second switch group FMS2. In the Q-channel second mixer Q1, the four second local oscillator signals P3, P4, P5, and P8 correspond to the four analog switches S of the first switch group FMS1, and the four second local oscillator signals P1, P2, P6, and P7 correspond to the four analog switches S of the second switch group FMS2.
[0080] In the embodiment shown in Figure 10, multi-phase clock synthesis is performed by using the second local oscillator signals P1, P2, P3, P4, P5, P6, P7 and P8 during the mixing process of the I-channel second mixer I1 and the Q-channel second mixer Q1, and multi-phase clock synthesis is performed by using the third local oscillator signals P9, P10, P9' and P10' during the mixing process of the I-channel third mixer I2 and the Q-channel third mixer Q2. By combining the two mixing processes, the multiple second local oscillator signals and the multiple third local oscillator signals can be equivalent to a sinusoidal local oscillator signal with a frequency of 1188MHz.
[0081] Figure 11 shows the simulated waveforms of the equivalent sinusoidal local oscillator signals obtained from the I and Q paths, respectively. Under this multi-phase clock synthesis and two-stage mixing structure, the two-stage mixing process can be equivalent to mixing the second RF signal with the sinusoidal local oscillator signal shown in Figure 11. In this case, the image signal between the two mixing stages is suppressed, eliminating the need for additional filtering devices between the two mixing stages to remove the image signal. This reduces the area and power consumption overhead of related filters. Furthermore, in this implementation, the second receiving channel RX2 exhibits better anti-interference performance, reducing the design requirements for other components and making it easier to design other components with reduced area and power consumption.
[0082] It should be noted that the embodiments shown in Figures 9, 10, and 11 above are only illustrative of obtaining an equivalent 1188MHz sinusoidal local oscillator signal. When the receiving path is at different operating frequencies in practical applications, the phase number, duty cycle, and correspondence with different analog switches of the second and third local oscillator signals can be adjusted accordingly to simulate the equivalent local oscillator signals required for different operating frequencies.
[0083] In the accompanying drawings of the embodiments of this application, the receiving architecture is simplified as a single device for illustration, but it can be expanded into a two-way architecture with I-way and Q-way, which will not be described in detail below.
[0084] In some possible implementations, as shown in FIG12, the second receiving channel RX2 includes a plurality of third mixers 120C2. The second mixer 110C2 is coupled to the plurality of third mixers 120C2 respectively; the frequency divider circuit 300C is coupled to the plurality of third mixers 120C2 respectively. The aforementioned outputting a third local oscillator signal to the third mixers 120C2 includes: outputting a plurality of corresponding third local oscillator signals to each third mixer 120C2, wherein the frequency values of the corresponding third local oscillator signals are different between different third mixers 120C2.
[0085] In the embodiment shown in Figure 12, a single second receiving channel RX2 can be configured with multiple receiving paths, each operating at a different frequency, thereby realizing a multi-path, multi-frequency receiving application. These multiple receiving paths can reuse the second mixer 110C2, with each receiving path corresponding to a different third mixer 120C2. The frequency divider circuit 300C can output a second local oscillator signal suitable for use by the second mixer 110C2, and output a third local oscillator signal with a corresponding frequency value to different third mixers 120C2, allowing each receiving path to obtain mixing processing at different operating frequencies based on multi-phase clock synthesis and secondary mixing. In this embodiment, the second receiving channel RX2 can save on filters for image signal filtering in multiple receiving paths, reuse the same frequency divider circuit 300C to obtain the required local oscillator signal, and also save on the device overhead of multiple second mixers 110C2. Under this implementation, the multi-path, multi-frequency receiving channel application scenario can significantly reduce device area and power consumption.
[0086] In some possible implementations, such as the embodiment shown in FIG12, multiple receive channels in the second receive channel RX2 may reuse a single phase-locked loop device.
[0087] For example, as shown in FIG13, the frequency divider circuit 300C includes a first frequency divider 310C and a second frequency divider 320C. A phase-locked loop 400C is coupled to the first frequency divider 310C. The first frequency divider 310C is coupled to the second frequency divider 320C and the second mixer 110C2. The second frequency divider 320C is coupled to the third mixer 120C2. The phase-locked loop 400C is used to: output a first local oscillator signal to the first frequency divider 310C. The first frequency divider 310C is used to: perform frequency division processing on the input first local oscillator signal to obtain a second local oscillator signal; and output the second local oscillator signal to the second frequency divider 320C and the second mixer 110C2. The second frequency divider 320C is used to: perform frequency division processing on the input second local oscillator signal to obtain a third local oscillator signal; and output the third local oscillator signal to the third mixer 120C2. When the second receiving channel RX2 has multiple receiving channels, multiple second frequency dividers 320C can be configured to provide third local oscillator signals with corresponding frequency values for different third mixers 120C2. In the embodiment shown in Figure 13, a first local oscillator signal is generated by a phase-locked loop 400C, and the first frequency divider 310C in the frequency divider circuit 300C divides the first local oscillator signal into second local oscillator signals with multiple phases. The second frequency divider 320C can also obtain a second local oscillator signal from the first frequency divider 310C and perform frequency division processing on the obtained second local oscillator signal to obtain third local oscillator signals with multiple phases. In the description of the embodiments related to Figures 9 and 10 above, examples are given using the first frequency divider 310C and the second frequency divider 320C as both being frequency divider circuits (for example, the first frequency divider 310C divides the first local oscillator signal with a frequency of 1584MHz into a second local oscillator signal with a frequency of 792MHz, and the first second frequency divider 320C divides the second local oscillator signal with a frequency of 792MHz into a third local oscillator signal with a frequency of 396MHz. Other second frequency dividers 320C can also divide the second local oscillator signal with a frequency of 792MHz into a third local oscillator signal with a frequency other than 396MHz). However, in actual applications, depending on the operating frequency of the receiving channel, in addition to the adjustable phase, quantity, and duty cycle of the second and third local oscillator signals, the ratio of the frequency values between the first, second, and third local oscillator signals can also be adjusted.
[0088] In some possible implementations, as shown in FIG14, multiple second receiving channels RX2 can be configured among multiple receiving channels RX. When multiple second receiving channels RX2 adopt the implementation methods described in the above embodiments, each of the multiple second receiving channels RX2 can achieve a reduction in components and power consumption compared to a conventional sliding intermediate frequency receiver. Furthermore, the multiple second receiving channels RX2 multiplex the local oscillator signal provided by the same frequency divider circuit 300C. The frequency divider circuit 300C obtains the local oscillator signal from a phase-locked loop 400C, which can be divided to obtain the local oscillator signal required for the operation of multiple second receiving channels RX2. Based on the above embodiments, the number of phase-locked loop components and power consumption can also be greatly reduced. The specific technical principles and effects of each second receiving channel among the multiple second receiving channels RX2 can be referred to the description of the above embodiments of the second receiving channel RX2, and will not be repeated here.
[0089] The embodiment in Figure 13 above is an example of extending the frequency divider circuit 300C based on a second receiving channel RX2. When there are multiple second receiving channels RX2, frequency divider devices corresponding to more second receiving channels RX2 can be set in the frequency divider circuit 300C. In addition, in the example shown in Figure 13 where a second receiving channel RX2 includes multiple receiving channels, more frequency divider devices can be adaptively designed for multiple third mixers 120C2 to provide third local oscillator signals with corresponding different frequency values. Meanwhile, the frequency divider architecture in Figure 12 is only a simple example. In practical applications, the design can be adaptively adjusted according to the required frequency value ratio between different local oscillator signals. This application embodiment will not elaborate further. These adaptive adjustment designs all fall within the protection scope of this application.
[0090] In some possible implementations, the clock frequency signal required by other electronic devices in the third RF receiver 1000C can also be provided based on the frequency divider circuit 300C. Exemplarily, as shown in FIG15, the frequency divider circuit 300C is further configured to: divide the first local oscillator signal to obtain a first clock frequency signal, and output the first clock frequency signal to the data processor 200C. Exemplarily, as shown in FIG15, the frequency divider circuit 300C is also coupled to the analog-to-digital converter 150C2. The frequency divider circuit 300C is further configured to: divide the first local oscillator signal to obtain a second clock frequency signal, and output the second clock frequency signal to the analog-to-digital converter 150C2. In the embodiment shown in FIG15, the clock frequency signals required by the data processor 200C and the analog-to-digital converter 150C2 in the third RF receiver 1000C can also be provided using the same phase-locked loop 400C and the frequency divider circuit 300C. Depending on the different frequency values of the clock signals required by the data processor 200C and the analog-to-digital converter 150C2, adaptive adjustments can be made in the frequency divider circuit 300C. Corresponding frequency divider devices can be designed within the frequency divider circuit 300C; specific design methods will not be elaborated here. Similarly, the frequency divider circuit 300C can also provide a clock frequency signal to the analog-to-digital converter 150C1 within the first receiving channel RX1. Through this implementation, multiple electronic devices can reuse a single phase-locked loop device to obtain the clock frequency signal required for operation, thereby further significantly reducing area overhead and power consumption.
[0091] In traditional receiver architectures, numerous interference signals exist, placing significant demands on the architecture's anti-interference performance. Typically, devices are designed to operate at higher performance and precision to avoid the influence of interference signals, but this leads to a substantial increase in the power consumption of individual devices. For example, when high-performance operation is required to reduce the impact of interference signals and improve processing accuracy, devices such as filters, power amplifiers, and analog-to-digital converters located after the mixer in the receiving channel usually require higher operating power, resulting in significant power consumption. In the embodiments of this application, in addition to reducing the number of devices to reduce power consumption, the operating power of relevant devices can also be controlled to achieve the same goal.
[0092] For example, as shown in FIG16, the third RF receiver 1000C further includes a saturation power detector 500C and a state switching circuit 600C. Taking power control of the devices in the second receiving channel RX2 as an example: the output stage of the third mixer 120C2 is sequentially coupled to a low-pass filter 130C2, a variable gain amplifier 140C2, and an analog-to-digital converter 150C2. The input terminal of the saturation power detector 500C is coupled to the RF input terminal of the second mixer 110C2, and the output terminal of the saturation power detector 500C is coupled to the first input terminal of the state switching circuit 600C. The second input terminal of the state switching circuit 600C is coupled to the output terminal of the analog-to-digital converter 150C2. The saturation power detector 500C is used to: output a power detection signal to the state controller, the power detection signal indicating the power value of the second RF signal input to the second mixer 110C2. The state switching circuit 600C is used to: output a control signal based on the power detection signal; when the power value of the second radio frequency signal is greater than a preset threshold, the control signal is used to control at least one of the low-pass filter 130C2, the variable gain amplifier 140C2 and the analog-to-digital converter 150C2 to increase the operating power; when the power value of the second radio frequency signal is less than the preset threshold, the control signal is used to control at least one of the low-pass filter 130C2, the variable gain amplifier 140C2 and the analog-to-digital converter 150C2 to decrease the operating power.
[0093] In the embodiment shown in Figure 16, the processed signal of the receiving channel may have out-of-band (OB) interference signals. OB interference signals are interference signals whose frequency values deviate significantly from the operating frequency band of the receiving channel. Typically, to combat OB interference, the low-pass filter 130C2 and the variable gain amplifier 140C2 are designed with fourth-order or higher interference suppression. However, this requires the low-pass filter 130C2 and the variable gain amplifier 140C2 to have considerable processing accuracy and significantly increases their power consumption. Furthermore, because the low-pass filter 130C2 and the variable gain amplifier 140C2 have fourth-order or higher suppression, the analog-to-digital converter 150C2 located in the subsequent stage cannot detect the OB interference signals. Typically, in this embodiment, a saturated power detector 500C is added to detect the power of the input second RF signal. The saturated power detector 500C incorporates relevant nonlinear devices (such as diodes), which have operating frequency regions divided into linear, nonlinear, and saturation regions. When the input signal is located in the out-of-band frequency region, it will fall into the saturation operating region of these devices, thereby enabling the detection of out-of-band interference signals. The saturation power detector 500C outputs a relevant power detection signal to the state switching circuit 600C. Based on the indication of the power detection signal, the state switching circuit 600C can output a control signal to control the operating frequency of one or more of the low-pass filter 130C2, the variable gain amplifier 140C2, and the analog-to-digital converter 150C2. For example, when the saturation power detector 500C detects an out-of-band interference signal, it can control these devices to increase their operating power to improve anti-interference performance. Conversely, when the saturation power detector 500C does not detect an out-of-band interference signal, it can control these devices to operate at an appropriate power to reduce unnecessary high power consumption. Through the operation of this embodiment, the power consumption of the third RF receiver 1000C can be further reduced based on the above embodiments.
[0094] For example, as shown in FIG16, a saturation power detector 500C and a state switching circuit 600C may also be set for the second receiving channel RX2. The specific implementation principle and beneficial effects of setting the saturation power detector 500C and the state switching circuit 600C for the second receiving channel RX2 can be referred to the relevant description in the above embodiment of the second receiving channel RX2, and will not be repeated here.
[0095] For example, the state switching circuit 600C can be a digital logic control circuit or a microcontroller unit (MCU), etc.
[0096] In some possible implementations, the third radio frequency receiver 1000C can be used in scenarios such as global navigation satellite system (GNSS), Bluetooth communication, WiFi protocol communication, and satellite communication. It can also be used in applications such as radar scanning.
[0097] For example, the electronic device including the third radio frequency receiver 1000C can be a user terminal device, such as a mobile phone, tablet circuit, smart bracelet, and other location-enabled electronic devices. It can also be a wireless communication device, such as a routing node and smart home network. Alternatively, it can be a radar scanning device, such as an in-vehicle radar scanning system.
[0098] For example, when the third RF receiver 1000C is used in the GNSS field, the operating frequency band of the second receiving channel RX2 can be any of the following operating frequency bands: L5 band, L2 band, L1 band, E1 band, E5 band, E6 band, B1 band, B2 band, and B3 band. When the third RF receiver 1000C includes multiple second receiving channels RX2, the different second receiving channels RX2 can be the same or different frequency bands among these bands. Similarly, the operating frequency band of the second receiving channel RX2 can also be any of these frequency bands. For example, taking multiple receiving channels RX including a second receiving channel RX2 and a second receiving channel RX2 as an example, the second receiving channel RX2 can operate in the L1 band, and the second receiving channel RX2 can operate in the L5 band.
[0099] In the embodiments of the third RF receiver 1000C described above, a traditional architecture with an LNA-coupled mixer structure is used for illustration. However, in a mixer architecture that combines two-stage mixing with multi-phase clock synthesis, the third RF receiver 1000C does not necessarily need to place the LNA in the pre-stage of the mixer structure. A mixer-first architecture can also be used, in which the mixer structure is placed before the LNA, or the LNA device can be omitted. Alternatively, a multi-stage RF-IF separation architecture can be adopted, in which the IF signal needs to be down-converted and mixed to generate a baseband signal before relevant digital processing (such as analog-to-digital conversion and related data processing).
[0100] For example, in the antenna module 2000, in addition to the antenna radiator for receiving radio frequency signals, it may also include correlation filtering devices and impedance matching devices. The correlation filtering devices are used to filter out other interference clutter signals received by the antenna radiator of the antenna module 2000 from space. The impedance matching devices are used to realize the transmission impedance between the antenna radiator and the low-noise power amplifier or mixer. The impedance matching devices can be independently configured impedance matching networks (including impedance elements such as capacitors and resistors), or they can be non-separately designed devices that achieve impedance matching functionality using radio frequency signal transmission structures such as transmission lines or auxiliary structures on electronic devices.
[0101] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0102] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0103] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0104] In the embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication coupling shown or discussed between devices or modules can be through some interfaces, or indirect coupling or communication coupling between devices or modules, and can be electrical, mechanical, or other forms.
[0105] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0106] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.
[0107] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).
[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A radio frequency receiver, characterized in that, include: First receiving channel, second receiving channel, phase-locked loop and frequency divider circuit; The first receiving channel includes: a first mixer, used to down-convert the first radio frequency signal based on the first local oscillator signal; The phase-locked loop is coupled to the first mixer and the frequency divider circuit respectively, and the phase-locked loop is used to provide the first local oscillator signal to the first mixer and the frequency divider circuit; The second receiving channel includes a second mixer and a third mixer, wherein the second mixer is coupled to the third mixer; The frequency divider circuit is coupled to the second mixer and the third mixer respectively. The frequency divider circuit is used to: divide the first local oscillator signal to obtain a plurality of second local oscillator signals and a plurality of third local oscillator signals, provide the plurality of second local oscillator signals to the second mixer, and provide the plurality of third local oscillator signals to the third mixer. The second receiving channel is used to perform a second down-conversion on the second radio frequency signal based on the plurality of second local oscillator signals and the plurality of third local oscillator signals.
2. The radio frequency receiver according to claim 1, characterized in that, The second receiving channel includes a plurality of the third mixers; the second mixers are coupled to the plurality of the third mixers respectively; the frequency divider circuit is coupled to the plurality of the third mixers respectively; wherein, providing the plurality of third local oscillator signals to the third mixers includes: Each of the third mixers is provided with a plurality of corresponding third local oscillator signals, and the frequency values of the corresponding third local oscillator signals are different between different third mixers.
3. The radio frequency receiver according to claim 1 or 2, characterized in that, The second mixer includes an I-channel second mixer and a Q-channel second mixer; the I-channel second mixer and the Q-channel second mixer constitute a first combining mixer; the third mixer includes an I-channel third mixer and a Q-channel third mixer; wherein, The first synthesizer includes a first switch group and a second switch group; the first switch group and the second switch group each include a plurality of parallel analog switches; the input terminals of the first switch group and the second switch group are used to input the second radio frequency signal; the plurality of second local oscillator signals correspond one-to-one with the controlled terminals of the plurality of analog switches in the first switch group and the second switch group, and each second local oscillator signal is used to control the conduction state of a corresponding analog switch; In the I-channel second mixer, the output terminals of the corresponding first switch group and the second switch group are used to output an I-channel primary down-conversion signal to the I-channel third mixer; In the Q-channel second mixer, the output terminals of the corresponding first switch group and the second switch group are used to output the Q-channel primary down-conversion signal to the Q-channel third mixer.
4. The radio frequency receiver according to claim 3, characterized in that, The plurality of second local oscillator signals have different phases, and the plurality of third local oscillator signals have different phases.
5. The radio frequency receiver according to claim 4, characterized in that, The first switch group and the second switch group together include eight analog switches, and the plurality of second local oscillator signals include eight second local oscillator signals with different phases, and the eight second local oscillator signals correspond one-to-one with the eight analog switches.
6. The radio frequency receiver according to claim 5, characterized in that, The I-channel third mixer and the Q-channel third mixer are a second synthesizer; wherein... The second synthesizer includes a first analog switch, a second analog switch, a third analog switch, and a fourth analog switch; the input terminals of the first and second analog switches serve as the first input terminals of the second synthesizer and are coupled to the output terminals of the corresponding first switch groups; the input terminals of the third and fourth analog switches serve as the second input terminals of the second synthesizer and are coupled to the output terminals of the corresponding second switch groups; the output terminals of the first and third analog switches, after coupling, serve as the first output terminal of the second synthesizer; the output terminals of the second and fourth analog switches, after coupling, serve as the second output terminal of the second synthesizer; the controlled terminals of the first, second, third, and fourth analog switches are respectively used to input a corresponding third local oscillator signal, and each third local oscillator signal is used to control the conduction state of a corresponding analog switch; In the I-channel third mixer, the first and second input terminals of the corresponding second synthesizer are used to input the I-channel primary down-conversion signal, and the first and second output terminals of the corresponding second synthesizer are used to output the I-channel secondary down-conversion signal. In the Q-channel third mixer, the first and second input terminals of the corresponding second synthesizer are used to input the Q-channel primary down-conversion signal, and the first and second output terminals of the corresponding second synthesizer are used to output the Q-channel secondary down-conversion signal.
7. The radio frequency receiver according to claim 6, characterized in that, The third local oscillator signal corresponding to the I-channel third mixer and the third local oscillator signal corresponding to the Q-channel third mixer have different phases.
8. The radio frequency receiver according to claim 7, characterized in that, In the I-channel third mixer or the Q-channel third mixer, the controlled terminals of the first, second, third, and fourth analog switches of the corresponding second synthesizer are used to input the third local oscillator signal of the same phase. The level changes of the third local oscillator signal at the controlled terminals of the first and fourth analog switches are the same, while the level changes of the third local oscillator signal at the controlled terminals of the second and third analog switches are opposite to the level changes of the third local oscillator signal at the controlled terminal of the first analog switch.
9. The radio frequency receiver according to any one of claims 1-8, characterized in that, The frequency division circuit includes a first frequency divider and a second frequency divider; the phase-locked loop is coupled to the first frequency divider; the first frequency divider is coupled to both the second frequency divider and the second mixer; the second frequency divider is coupled to the third mixer; wherein... The phase-locked loop is used to: output the first local oscillator signal to the first frequency divider; The first frequency divider is used to: divide the input first local oscillator signal to obtain multiple second local oscillator signals; and output the second local oscillator signals to the second frequency divider and the second mixer respectively. The second frequency divider is used to: divide the input second local oscillator signal to obtain multiple third local oscillator signals; and output the third local oscillator signals to the third mixer.
10. The radio frequency receiver according to any one of claims 1-9, characterized in that, The radio frequency receiver further includes a data processor; the frequency divider circuit is also used to: divide the first local oscillator signal to obtain a first clock frequency signal, and output the first clock frequency signal to the data processor.
11. The radio frequency receiver according to any one of claims 1-10, characterized in that, The second receiving channel further includes an analog-to-digital converter; the analog-to-digital converter is coupled to the third mixer; the frequency divider circuit is also coupled to the analog-to-digital converter; wherein, The frequency divider circuit is also used to: divide the first local oscillator signal to obtain a second clock frequency signal, and output the second clock frequency signal to the analog-to-digital converter.
12. The radio frequency receiver according to claim 11, characterized in that, The RF receiver further includes a saturated power detector and a state switching circuit; the second receiving channel further includes a low-pass filter and a variable gain amplifier; the output stage of the third mixer is sequentially coupled to the low-pass filter, the variable gain amplifier, and the analog-to-digital converter; the input terminal of the saturated power detector is coupled to the RF input terminal of the second mixer, and the output terminal of the saturated power detector is coupled to the first input terminal of the state switching circuit; the second input terminal of the state switching circuit is coupled to the output terminal of the analog-to-digital converter; wherein... The saturation power detector is used to: output a power detection signal to the state controller, the power detection signal being used to indicate the power value of the second radio frequency signal input to the second mixer; The state switching circuit is used to: output a control signal according to the power detection signal; when the power value of the second radio frequency signal is greater than a preset threshold, the control signal is used to control at least one of the low-pass filter, the variable gain amplifier and the analog-to-digital converter to increase the operating power; when the power value of the second radio frequency signal is less than the preset threshold, the control signal is used to control at least one of the low-pass filter, the variable gain amplifier and the analog-to-digital converter to decrease the operating power.
13. The radio frequency receiver according to any one of claims 1-12, characterized in that, The operating frequency band of the second receiving channel is any one of the following: L5 band, L2 band, L1 band, E1 band, E5 band, E6 band, B1 band, B2 band, and B3 band.
14. The radio frequency receiver according to any one of claims 1-13, characterized in that, The signal obtained after the second down-conversion process is a sinusoidal signal.
15. An electronic device, characterized in that, It includes an antenna module and a radio frequency receiver as described in any one of claims 1-14; the receiving end of the radio frequency receiver is connected to the antenna module; the radio frequency receiver is used to receive radio frequency signals through the antenna module.