Semiconductor device and preparation method therefor, wafer, chip packaging structure, and electronic device

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a semiconductor device and a preparation method therefor, a wafer, a chip packaging structure, and an electronic device, which are used for optimizing the impedance characteristics of metal silicide layers in the semiconductor device. A transistor in the semiconductor device comprises a first metal silicide layer located on a surface of a gate electrode and a second metal silicide layer located on surfaces of a source electrode and a drain electrode. The first metal silicide layer and the second metal silicide layer are formed by means of different annealing processes. Therefore, on the basis of application scenarios and requirements, the first metal silicide layer and second metal silicide layer, which both have a balanced performance and good resistance, can be formed by controlling factors such as process conditions, materials, and thicknesses. Accordingly, the impedance characteristics of the first metal silicide layer and the second metal silicide layer can be optimized, the line width effect of the first metal silicide layer and the second metal silicide layer can be mitigated, the power consumption of the semiconductor device can be reduced, and the stability of the semiconductor device can be improved.

Description

Semiconductor devices and their fabrication methods, wafers, chip packaging structures, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510365015.6, filed with the State Intellectual Property Office of China on March 25, 2025, entitled "Semiconductor Device and Preparation Method Thereof, Wafer, Chip Packaging Structure, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a semiconductor device and its fabrication method, wafer, chip packaging structure, and electronic equipment. Background Technology

[0003] Complementary metal oxide semiconductor (CMOS) transistors only consume energy when switching on and off, thus having the advantage of low power consumption and are widely used circuit elements in integrated circuits.

[0004] Metal silicides possess conductivity between that of metals and silicon and are typically deposited on the surface of transistor electrodes as an intermediate layer between the back-end metal vias and the transistor electrodes. This effectively reduces the contact resistance between the vias and the electrodes. However, the impedance characteristics of the metal silicide layer in current transistors still require optimization, resulting in relatively high power consumption. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, wafer, chip packaging structure, and electronic device for optimizing the impedance characteristics of the metal silicide layer in the semiconductor device.

[0006] A first aspect of this application provides a semiconductor device, which may be in the form of a bare chip or a chip. The semiconductor device includes a substrate and a transistor disposed on the substrate. The transistor includes a gate, a source, a drain, a first metal silicide layer, and a second metal silicide layer. The gate is disposed on the substrate, and the source and drain are disposed on the substrate, located on opposite sides of the gate. The first metal silicide layer is disposed on the side of the gate away from the substrate, and the first metal silicide layer covers the top surface of the gate. The second metal silicide layer is disposed on the side of the source and drain away from the substrate. The metal included in the first metal silicide layer is different from the metal included in the second metal silicide layer.

[0007] The semiconductor device provided in this application has a first metal silicide layer containing a different metal than the second metal silicide layer. By depositing different types or compositions of metals in the gate region and the source and drain regions, the silicon materials of the gate and the source and drain can be matched with suitable metals. This achieves the formation of a first metal silicide layer above the gate that is matched to the gate, exhibiting balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface. Similarly, a second metal silicide layer is formed above the source and drain that is matched to the source and drain, exhibiting balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface. This optimizes the impedance characteristics of the first and second metal silicide layers, improves the linewidth effect of the first and second metal silicide layers, reduces the power consumption of the semiconductor device, and enhances its stability. Moreover, it is possible to achieve a similar average resistance value between the first metal silicide layer and the second metal silicide layer, thereby improving the performance balance between the first and second metal silicide layers, enhancing the balance between the series resistance of the gate and the back-end metal via, and the series resistance of the source, drain and the back-end metal via, and further improving the stability of the semiconductor device.

[0008] In one possible implementation, the metal comprising the first metal silicide layer has higher thermal stability than the metal comprising the second metal silicide layer. For example, the first metal silicide layer is formed first, followed by the second metal silicide layer. In this case, the thermal budget of the first metal silicide layer is higher than that of the second metal silicide layer. By using a metal with high thermal stability in the first metal silicide layer, the risk of crystal agglomeration defects due to excessive heat in the first metal silicide layer can be reduced.

[0009] In one possible implementation, the metal comprising the first metal silicide layer has lower thermal stability than the metal comprising the second metal silicide layer. For example, the second metal silicide layer is formed first, followed by the first metal silicide layer. In this case, the thermal budget of the second metal silicide layer is higher than that of the first metal silicide layer. By using a metal with high thermal stability in the second metal silicide layer, the risk of crystal agglomeration defects due to excessive heat in the second metal silicide layer can be reduced.

[0010] In one possible implementation, the semiconductor device further includes a gate sidewall and a third metal silicide layer; the side of the gate includes a first region close to the substrate and a second region away from the substrate; the gate sidewall covers the first region; the third metal silicide layer covers the second region; the metal included in the third metal silicide layer is the same as the metal included in the second metal silicide layer. Due to process factors, the third metal silicide layer may be formed simultaneously with the formation of the second metal silicide layer, but the formation of the third metal silicide layer will not affect the uniformity of the resistance values ​​of the first and second metal silicide layers, making it highly feasible.

[0011] In one possible implementation, the thickness of the first metal silicide layer is uniform at all locations. The first and second metal silicide layers are formed separately. Therefore, when forming the first metal silicide layer, only factors such as the metal material, metal layer thickness, and process conditions need to be adjusted to optimize its performance; the performance of the second metal silicide layer does not need to be considered. Thus, a first metal silicide layer with uniform thickness can be formed. Because the first metal silicide layer has uniform thickness, its resistance is also uniform, further improving the linewidth effect of the first metal silicide layer.

[0012] In one possible implementation, the thickness of the second metal silicide layer is uniform at all locations. The first and second metal silicide layers are formed separately. Therefore, when forming the second metal silicide layer, only factors such as the metal material, metal layer thickness, and process conditions need to be adjusted to optimize its performance, without needing to consider the first metal silicide layer. Thus, a second metal silicide layer with uniform thickness can be formed. The uniform thickness of the second metal silicide layer results in uniform resistance, further improving the linewidth effect of the second metal silicide layer.

[0013] In one possible implementation, the sheet resistance of the first metal silicide layer is less than or equal to 20 mΩ / cm. In semiconductor devices, the excellent resistance of the first metal silicide layer, achieving below 20 mΩ / cm, reduces the contact resistance between the gate and the back-end metal vias, decreases the power consumption of the semiconductor device, and improves its stability.

[0014] In one possible implementation, the sheet resistance of the second metal silicide layer is less than or equal to 20 mΩ / cm. In semiconductor devices, the excellent resistance of the second metal silicide layer, achieving values ​​below 20 mΩ / cm, reduces the contact resistance between the source or drain and the back-end metal vias, thereby decreasing power consumption and improving the stability of the semiconductor device.

[0015] In one possible implementation, the difference between the sheet resistance of the first metal silicide layer and the sheet resistance of the second metal silicide layer is less than 10 mΩ / cm. In semiconductor devices, the difference between the sheet resistance of the first metal silicide layer and the second metal silicide layer can be less than 10 mΩ / cm. This performance balance between the first and second metal silicide layers further improves the balance between the series resistance of the first source and first drain and the subsequent metal via, and the series resistance of the first gate and the subsequent metal via.

[0016] In one possible implementation, the metal of the first metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1.5 to 1:2. This can significantly reduce the average resistance of the first metal silicide layer, and even make the first metal silicide layer a low-resistance phase, further reducing the contact resistance of the gate and the subsequent metal via.

[0017] In one possible implementation, the metal of the first metal silicide layer includes Ni; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1 to 2:1. This can significantly reduce the average resistance of the first metal silicide layer, and even make the first metal silicide layer reach a low-resistance phase, further reducing the contact resistance of the gate and the subsequent metal via.

[0018] In one possible implementation, the metal of the second metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the second metal silicide layer ranges from 1:1.5 to 1:2. This can significantly reduce the average resistance of the second metal silicide layer, and even make the second metal silicide layer a low-resistance phase, further reducing the contact resistance of the source or drain and the subsequent metal via.

[0019] In one possible implementation, the metal of the second metal silicide layer includes Ni; the ratio of metal to silicon in the second metal silicide layer ranges from 1:1 to 2:1. This can significantly reduce the average resistance of the second metal silicide layer, and even make the second metal silicide layer a low-resistance phase, further reducing the contact resistance between the source or drain and the subsequent metal via.

[0020] In one possible implementation, the semiconductor device includes multiple transistors; these transistors include N-type transistors and / or P-type transistors. When the semiconductor device includes multiple transistors, the linewidth effect of the metal silicide layer in each transistor can be improved, further reducing power consumption and improving stability. Moreover, when the semiconductor device includes both N-type and P-type transistors, the linewidth effect of the metal silicide layer in both the N-type and P-type transistors can be improved.

[0021] A second aspect of this application provides a semiconductor device, which can be in the form of a bare chip or a chip. The semiconductor device includes a substrate and a transistor disposed on the substrate. The transistor includes a gate, a source, a drain, a first metal silicide layer, and a second metal silicide layer. The gate is disposed on the substrate, and the source and drain are disposed on the substrate, located on opposite sides of the gate. The first metal silicide layer is disposed on the side of the gate away from the substrate, and the first metal silicide layer covers the top surface of the gate. The second metal silicide layer is disposed on the side of the source and drain away from the substrate. The first and second metal silicide layers are formed by different annealing processes.

[0022] The semiconductor device provided in this application embodiment forms a first metal silicide layer above the gate and a second metal silicide layer above the source and drain in steps. The first and second metal silicide layers are formed independently. Therefore, depending on the application scenario and requirements, by controlling factors such as process conditions, materials, and thickness, a first metal silicide layer with balanced performance matching the gate, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface can be formed above the gate. Similarly, a second metal silicide layer with balanced performance matching the source and drain, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface can be formed above the source and drain. This optimizes the impedance characteristics of the first and second metal silicide layers, improves the linewidth effect of the first and second metal silicide layers, reduces the power consumption of the semiconductor device, and enhances the stability of the semiconductor device. Moreover, it is possible to achieve a similar average resistance value between the first metal silicide layer and the second metal silicide layer, thereby improving the performance balance between the first and second metal silicide layers, enhancing the balance between the series resistance of the gate and the back-end metal via, and the series resistance of the source, drain and the back-end metal via, and further improving the stability of the semiconductor device.

[0023] In one possible implementation, the semiconductor device further includes a gate sidewall and a third metal silicide layer; the side of the gate includes a first region close to the substrate and a second region away from the substrate; the gate sidewall covers the first region; and the third metal silicide layer covers the second region. Due to process factors, the third metal silicide layer may be formed simultaneously with the formation of the second metal silicide layer, but the formation of the third metal silicide layer will not affect the uniformity of the resistance values ​​of the first and second metal silicide layers, making it highly feasible.

[0024] In one possible implementation, the first metal silicide layer comprises the same metal as the second metal silicide layer. Even though the first and second metal silicide layers comprise the same metal, since the subsequently formed metal silicide layer (e.g., the second metal silicide layer) only undergoes one annealing process, the thermal budget of the metal silicide layer can be reduced, effectively lowering the risk of high-temperature agglomeration and thus improving the problem of silicide agglomeration formed on different types of silicon surfaces at advanced planar nodes.

[0025] In one possible implementation, the sheet resistance of the first metal silicide layer is less than or equal to 20 mΩ / cm. In semiconductor devices, the excellent resistance of the first metal silicide layer, achieving below 20 mΩ / cm, reduces the contact resistance between the gate and the back-end metal vias, decreases the power consumption of the semiconductor device, and improves its stability.

[0026] In one possible implementation, the sheet resistance of the second metal silicide layer is less than or equal to 20 mΩ / cm. In semiconductor devices, the excellent resistance of the second metal silicide layer, achieving values ​​below 20 mΩ / cm, reduces the contact resistance between the source or drain and the back-end metal vias, thereby decreasing power consumption and improving the stability of the semiconductor device.

[0027] In one possible implementation, the difference between the sheet resistance of the first metal silicide layer and the sheet resistance of the second metal silicide layer is less than 10 mΩ / cm. In semiconductor devices, the difference between the sheet resistance of the first metal silicide layer and the second metal silicide layer can be less than 10 mΩ / cm. This performance balance between the first and second metal silicide layers further improves the balance between the series resistance of the first source and first drain and the subsequent metal via, and the series resistance of the first gate and the subsequent metal via.

[0028] In one possible implementation, the metal of the first metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1.5 to 1:2. This can significantly reduce the average resistance of the first metal silicide layer, and even make the first metal silicide layer a low-resistance phase, further reducing the contact resistance of the gate and the subsequent metal via.

[0029] In one possible implementation, the metal of the first metal silicide layer includes Ni; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1 to 2:1. This can significantly reduce the average resistance of the first metal silicide layer, and even make the first metal silicide layer reach a low-resistance phase, further reducing the contact resistance of the gate and the subsequent metal via.

[0030] In one possible implementation, the metal of the second metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the second metal silicide layer ranges from 1:1.5 to 1:2. This can significantly reduce the average resistance of the second metal silicide layer, and even make the second metal silicide layer a low-resistance phase, further reducing the contact resistance of the source or drain and the subsequent metal via.

[0031] In one possible implementation, the metal of the second metal silicide layer includes Ni; the ratio of metal to silicon in the second metal silicide layer ranges from 1:1 to 2:1. This can significantly reduce the average resistance of the second metal silicide layer, and even make the second metal silicide layer a low-resistance phase, further reducing the contact resistance between the source or drain and the subsequent metal via.

[0032] A third aspect of this application provides a method for fabricating a semiconductor device. The method includes: forming a first gate, a first source, and a first drain on a substrate; the first source and the first drain being located on opposite sides of the first gate; forming a first metal silicide layer; the first metal silicide layer being formed on the side of the first gate away from the substrate; the first metal silicide layer covering the top surface of the first gate; and forming a second metal silicide layer to form a first transistor; the second metal silicide layer being formed on the side of the first source and the first drain away from the substrate.

[0033] The semiconductor device fabrication method provided in this application involves stepwise formation of a first metal silicide layer above a first gate and a second metal silicide layer above a first source and a first drain. The first and second metal silicide layers are formed independently. Therefore, depending on the application scenario and requirements, by controlling factors such as process conditions, materials, and thickness, a first metal silicide layer with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with silicon can be formed above the first gate. Similarly, a second metal silicide layer with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with silicon can be formed above the first source and the first drain. This optimizes the impedance characteristics of the first and second metal silicide layers, improves the linewidth effect of the first and second metal silicide layers, reduces the power consumption of the semiconductor device, and enhances the stability of the semiconductor device. Furthermore, the average resistance of the final fabricated first metal silicide layer can be similar to that of the second metal silicide layer. This improves the performance balance between the first and second metal silicide layers, enhances the balance between the series resistance of the first gate and the back-end metal via, and the series resistance of the first source and the first drain and the back-end metal via, thereby further improving the stability of the semiconductor device.

[0034] In one possible implementation, forming the first metal silicide layer includes: forming a first barrier layer, the first barrier layer exposing a first gate; forming a first metal layer, the first metal layer covering the first gate; and performing a first annealing process to form the first metal silicide layer. Forming the second metal silicide layer includes: patterning the first barrier layer to form a second barrier layer, the second barrier layer exposing a first source and a first drain; forming a second metal layer, the second metal layer covering the first source and the first drain; and performing a second annealing process to form the second metal silicide layer.

[0035] First, a first metal silicide layer is formed on the surface of the first gate electrode, followed by second metal silicide layers on the surfaces of the first source and first drain electrodes. Since there is a natural height difference between the first gate electrode and the first source and drain electrodes, this height difference allows for the step-by-step formation of metal silicide layers in the functional regions (gate, source, and drain) on the substrate. This allows for site-specific application without the need for additional photomasks, resulting in lower costs. Furthermore, the thermal conductivity of the first gate electrode material is typically lower than that of the first source and drain electrodes, requiring a higher thermal budget for forming the first metal silicide layer to achieve a low-resistivity phase. Conversely, a lower thermal budget is needed for forming the second metal silicide layer to achieve the same low-resistivity phase. The thermal budget is related to various factors such as annealing temperature and duration. Forming the first metal silicide layer first effectively involves two annealing processes, and this additional annealing process further enhances the thermal budget for the transformation of the first metal silicide into a low-resistivity phase. The second metal silicide layer only underwent one annealing process, and the thermal budget required for this process is more conducive to reducing the risk of crystal agglomeration defects in the second metal silicide layer. Therefore, it can balance the different thermal budgets required for metal silicide formation in different regions.

[0036] In one possible implementation, the temperature of the second annealing process is higher than that of the first annealing process. The first annealing process is mainly for forming a first metal silicide layer above the first gate, and the second annealing process is mainly for forming a second metal silicide layer above the first source and the first drain. By performing the first annealing of the first metal layer at a lower temperature, followed by the superimposed second annealing, the thermal budget can be sufficient to completely transform the crystal into a low-resistivity phase first metal silicide layer, while also mitigating crystal agglomeration defects in the first metal silicide layer caused by an excessively high thermal budget. By annealing the second metal layer at a higher temperature, the thermal budget of a single annealing process can be sufficient to completely transform the crystal into a low-resistivity phase second metal silicide layer, while also mitigating crystal agglomeration defects in the second metal silicide layer caused by an excessively high thermal budget.

[0037] In one possible implementation, the thicknesses of the first and second metal layers are different. Since the first and second metal layers are formed in stages, considering various factors such as process, product, and application scenario, different thicknesses of the first and second metal layers can be selected. This ensures that the resistance of the final first and second metal silicide layers is relatively uniform, and that their thicknesses meet specific requirements, depending on the application scenario. On one hand, uniform resistance can mitigate the linewidth effect of the first and second metal silicide layers. On the other hand, having different thicknesses meets specific requirements can prevent the first and second metal silicide layers from simultaneously failing to meet requirements, which could lead to problems such as the first being too thin and breaking down in subsequent processes, or the second being too thick and causing leakage current.

[0038] In one possible implementation, the metal comprising the first metal silicide layer has higher thermal stability than the metal comprising the second metal silicide layer. For example, the first metal silicide layer is formed first, followed by the second metal silicide layer. In this case, the thermal budget of the first metal silicide layer is higher than that of the second metal silicide layer. By using a metal with high thermal stability in the first metal silicide layer, the risk of crystal agglomeration defects due to excessive heat in the first metal silicide layer can be reduced.

[0039] In one possible implementation, forming the first barrier layer includes: forming a barrier film covering a first gate, a first source, a first drain, and a substrate; forming an anti-reflective layer covering the barrier film; forming a mask on the surface of the anti-reflective layer, exposing the first gate, the first source, and the first drain; and etching the anti-reflective layer and the barrier film to expose the first gate, thus forming the first barrier layer. Therefore, the first barrier layer can be formed using existing masks in related technologies, eliminating the need for additional mask design, resulting in low cost and ease of implementation.

[0040] In one possible implementation, the fabrication method further includes: forming a first gate sidewall; the side of the first gate includes a first region close to the substrate and a second region away from the substrate; the first gate sidewall covers the first region. A third metal silicide layer is formed simultaneously with the formation of the second metal silicide layer; the third metal silicide layer covers the second region. Due to process factors, the third metal silicide layer may be formed simultaneously with the formation of the second metal silicide layer, but the formation of the third metal silicide layer will not affect the uniformity of the resistance values ​​of the first and second metal silicide layers, making it highly feasible.

[0041] In one possible implementation, forming the second metal silicide layer includes: forming a third barrier layer, the third barrier layer exposing a first source and a first drain; forming a second metal layer, the second metal layer covering the first source and the first drain; and performing a first annealing process to form the second metal silicide layer. Forming the first metal silicide layer includes: patterning the third barrier layer to form a fourth barrier layer, the fourth barrier layer exposing a first gate; forming a first metal layer, the first metal layer covering the first gate; and performing a second annealing process to form the first metal silicide layer. The fabrication method provided in this application can also first form the second metal silicide layer and then form the first metal silicide layer, which can improve the impedance characteristics of the final second metal silicide layer and the first metal silicide layer, and improve the linewidth effect of the second metal silicide layer and the first metal silicide layer.

[0042] In one possible implementation, the temperature of the second annealing process is higher than that of the first annealing process. The first annealing process is primarily for forming a second metal silicide layer above the first source and first drain, while the second annealing process is primarily for forming a first metal silicide layer above the first gate. The second metal silicide layer is equivalent to undergoing two annealing processes, while the first metal silicide layer is equivalent to undergoing one annealing process. Increasing the temperature of the second annealing process helps to achieve a thermal budget sufficient to allow the crystal to completely transform and form a low-resistivity phase first metal silicide layer.

[0043] In one possible implementation, the metal comprising the first metal silicide layer has lower thermal stability than the metal comprising the second metal silicide layer. For example, the second metal silicide layer is formed first, followed by the first metal silicide layer. In this case, the thermal budget of the second metal silicide layer is higher than that of the first metal silicide layer. By using a metal with high thermal stability in the second metal silicide layer, the risk of crystal agglomeration defects due to excessive heat in the second metal silicide layer can be reduced.

[0044] In one possible implementation, the metal included in the first metal silicide layer is different from the metal included in the second metal silicide layer. The metals included in the first metal silicide layer and the second metal silicide layer do not necessarily have to be the same. Therefore, it is possible to match suitable metals to the silicon materials of the first gate, the first source, and the first drain, respectively, based on the application scenario and device characteristics. This helps to form a first metal silicide layer and a second metal silicide layer with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface, thereby improving the linewidth effect of the first and second metal silicide layers.

[0045] In one possible implementation, the fabrication method further includes: forming a second gate, a second source, and a second drain on a substrate. A fourth metal silicide layer is formed concurrently with the formation of a first metal silicide layer; the fourth metal silicide layer is formed on the side of the second gate away from the substrate; the fourth metal silicide layer covers the top surface of the second gate. A fifth metal silicide layer is formed concurrently with the formation of the second metal silicide layer to form a second transistor; the fifth metal silicide layer is formed on the side of the second source and second drain away from the substrate. The first transistor and the second transistor are respectively an N-type transistor and a P-type transistor. When the semiconductor device includes multiple transistors, the multiple transistors can be formed simultaneously to simplify the fabrication process, and the linewidth effect of each formed transistor can be improved. Furthermore, when the semiconductor device includes both N-type and P-type transistors, the linewidth effect of the metal silicide layer in both the N-type and P-type transistors fabricated using the fabrication method provided in this application embodiment can be improved.

[0046] A fourth aspect of this application provides a wafer comprising a plurality of semiconductor devices of any one of the first or second aspects arranged in an array. The wafer provided in the fourth aspect of this application includes the semiconductor devices provided in the embodiments of this application, and its beneficial effects are the same as those of the semiconductor devices, and will not be repeated here.

[0047] A fifth aspect of this application provides a chip packaging structure, comprising: a substrate and a semiconductor device as described in the first or second aspect, wherein the semiconductor device is disposed on one side of the substrate. The chip packaging structure provided in the fifth aspect of this application includes the semiconductor device provided in the embodiments of this application, and its beneficial effects are the same as those of the semiconductor device, and will not be repeated here.

[0048] A sixth aspect of this application provides an electronic device, which includes a circuit board and a semiconductor device as described in either the first or second aspect, wherein the semiconductor device is electrically connected to the circuit board. The electronic device provided in the sixth aspect of this application includes the semiconductor device provided in the embodiments of this application, and its beneficial effects are the same as those of the semiconductor device, which will not be repeated here.

[0049] A seventh aspect of this application provides an electronic device, which includes a circuit board and a chip package structure as described in the fifth aspect, wherein the chip package structure is electrically connected to the circuit board. The electronic device provided in the seventh aspect of this application includes the chip package structure provided in the embodiments of this application, and its beneficial effects are the same as those of the chip package structure, which will not be repeated here. Attached Figure Description

[0050] Figure 1 is an architectural diagram of an electronic device provided in an embodiment of this application;

[0051] Figures 2A-2H are schematic diagrams illustrating the fabrication process of a semiconductor device according to an embodiment of this application;

[0052] Figure 3 is a schematic diagram comparing the thermal conductivity of different materials according to an embodiment of this application;

[0053] Figure 4 is a schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application;

[0054] Figures 5A-5F are schematic diagrams illustrating the fabrication process of another semiconductor device provided in the embodiments of this application;

[0055] Figure 6 is a flowchart illustrating the fabrication process of another semiconductor device provided in an embodiment of this application;

[0056] Figures 7A-7E are schematic diagrams illustrating the fabrication process of another semiconductor device provided in the embodiments of this application;

[0057] Figure 8A is a flowchart illustrating the fabrication process of another semiconductor device provided in an embodiment of this application;

[0058] Figure 8B is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiments of this application;

[0059] Figure 9A is a flowchart illustrating the fabrication process of another semiconductor device provided in an embodiment of this application;

[0060] Figure 9B is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiments of this application;

[0061] Figure 10 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0062] Figure 11 is a schematic diagram of another semiconductor device provided in an embodiment of this application;

[0063] Figure 12 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0064] Figure 13 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application.

[0065] Reference numerals: 10-Cover plate; 20-Display module; 30-Middle frame; 40-Back shell; 61-Substrate; 62-First gate insulating layer; 62'-Second gate insulating layer; 63-Trench; 64-First metal silicide layer; 64'-First metal layer; 65-First barrier layer; 65'-Block film; 65”-Second barrier layer; 65”'-Third barrier layer; 65””-Fourth barrier layer; 66-First mask; 66'-Second mask; 66”-Third mask; 66”'-Fourth mask; 67-Second metal silicide layer; 67'-Second metal layer; 68-Third metal silicide layer; 69-Fourth metal silicide layer; 60-Fifth metal silicide layer; 70-Sixth metal silicide layer; G1 - First gate; G2 - Second gate; S1 - First source; S2 - Second source; D1 - First drain; D2 - Second drain; GW1 - First gate sidewall; GW2 - Second gate sidewall; MOS1 - First transistor; MOS2 - Second transistor; BARC - Anti-reflective layer. Detailed Implementation

[0066] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only one regional embodiment of this application, and not all embodiments.

[0067] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0068] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0069] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0070] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0071] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets, watch faces), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronics products include smart door locks, televisions, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial electronics products include ATMs and self-service electronic devices, etc.

[0072] This application does not impose any special restrictions on the specific form of the above-mentioned electronic device. For the sake of convenience, the following embodiments all use mobile phones as an example for illustration.

[0073] Figure 1 is an architecture diagram of an electronic device provided in an embodiment of this application.

[0074] As shown in Figure 1, the electronic device 1 mainly includes a cover plate 10, a display module 20, a middle frame 30, and a back cover (or battery cover, housing) 40.

[0075] The display module 20 has a light-emitting side from which the displayed image can be seen and a back side opposite to the light-emitting side. The cover plate 10 is located on the light-emitting side of the display module 20, and the rear shell 40 is located on the back side of the display module 20. The display module 20 includes an active area (AA) for displaying images, and the active area includes a plurality of sub-pixels (SPs).

[0076] In one possible embodiment, the display module 20 is a liquid crystal display (LCD). Based on this, the electronic device 1 also includes a backlight unit (BLU) located behind the LCD. The backlight unit can provide a light source to the LCD, enabling each sub-pixel in the LCD to emit light for image display.

[0077] In another possible embodiment, the display module 20 is a self-emissive display module such as an organic light-emitting diode (OLED) display module, an active-matrix organic light-emitting diode (AMOLED) display module, a mini organic light-emitting diode (Mini-OLED) display module, a micro light-emitting diode (Micro-LED) display module, a micro organic light-emitting diode (Micro-OLED) display module, or a quantum dot light-emitting diode (QLED) display module. In this case, the display module 20 can be a rigid display module or a flexible display module.

[0078] The mid-frame 30 is located between the display module 20 and the rear shell 40, forming an installation space to accommodate electronic components such as the printed circuit board (PCB), battery, receiver, speaker, and camera. The PCB can integrate electronic components such as the terminal's main controller, storage unit, antenna module, and power management module, while the battery powers the display module 20, PCB, receiver, speaker, and camera.

[0079] The cover plate 10 is located on the side of the display module 20 away from the middle frame 30. The cover plate 10 has a light-transmitting structure and serves as a protective layer covering the display surface of the display module 20. In this way, the light transmitted from the display surface of the display module 20 can pass through the cover plate 10 and be received by the user. The display surface of the display module 20 involved in this application embodiment is the side of the display module 20 used to display the image to the user. The display surface of the display module 20 and the light-emitting side of the display module 20 are located on the same side, while the back side of the display module 20 refers to the side opposite to the display surface of the display module 20. After the display module 20 and the cover plate 10 and other components are assembled, the display module provided in this application embodiment can be formed.

[0080] In some embodiments, the electronic device 1 further includes a processor (CPU) chip, a microprocessor chip, a static random access memory (DRAM) chip, a logic chip, a dynamic random access memory (DRAM) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuit (PMIC), a memory chip (e.g., high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, flash memory, a graphics processing unit (GPU), and other chips disposed on a PCB. The PCB is used to carry the above-mentioned chips and to complete signal interaction with the above-mentioned chips.

[0081] Metal oxide semiconductor field effect transistors (MOSFETs) only consume energy when switching on and off, thus having the advantage of low power consumption. They are widely used circuit elements in integrated circuits and can be applied to various chips, devices and other semiconductor devices in electronic devices.

[0082] Metal silicides are metal compounds formed by the reaction of metal and silicon. In general processes, they are formed by depositing metal on a silicon surface followed by heat treatment. Metal silicides are typically used as transition layers before the metal-silicon contact; for example, they are widely used in the manufacturing of advanced integrated circuit semiconductor devices. The conductivity of metal silicides lies between that of metal and silicon, allowing them to effectively reduce the contact resistance between metal vias and silicon semiconductors, thus enabling the application of polysilicon electrodes in MOSFETs. Polysilicon electrodes are a technique for growing polysilicon as electrodes in MOSFETs using a deposition method. Examples include polysilicon gate electrode (G), polysilicon source electrode (S), and polysilicon drain electrode (D).

[0083] For planar fabrication processes, titanium silicide (TiSi) is commonly used for metal silicides above the 180nm node. Between the 180nm and 65nm nodes, cobalt silicide (CoSi2) is typically used. However, both TiSi and CoSi2 exhibit significant linewidth effects, meaning the resistivity of metal silicides increases rapidly as device size shrinks. Therefore, below the 65nm node, nickel silicide (NiSi), which does not have a linewidth effect, becomes the preferred choice. NiSi offers advantages such as low formation temperature, low silicon consumption (1nm of nickel consumes 1.83nm of silicon), flat silicide interfaces, and the fact that nickel germanide (NiGe) and NiSi have the same crystal structure and are miscible. However, nickel silicides have poor thermal stability and degrade at temperatures above 500°C, limiting their use in certain high-temperature processes.

[0084] Compared to NiSi, CoSi2 has advantages such as better conductivity and lower mismatch rate with silicon. Furthermore, CoSi2 is the final phase of cobalt silicide, and its thermal stability is approximately 150°C higher than NiSi, making it suitable for applications requiring high-temperature thermal stability. However, compared to NiSi, CoSi2 consumes more silicon (1nm of cobalt consumes 3.61nm of silicon), the resulting silicide interface is rougher, and the cobalt germanide (CoGe2) has a different crystal structure from CoSi2, making them difficult to co-dissolve. In germanium-silicon processes, the cobalt silicide formed leads to germanium agglomeration and precipitation, severely impacting chip performance.

[0085] Therefore, different metal silicides have different advantages and disadvantages, which prevents MOSFET performance from being further improved.

[0086] Figures 2A-2H are schematic diagrams illustrating the fabrication process of a semiconductor device provided in an embodiment of this application.

[0087] In some embodiments, the fabrication process of a semiconductor device includes:

[0088] S1. As shown in Figure 2A, a source, drain, gate, gate insulating layer, and gate sidewall are formed on the substrate. Trenches can also be provided on the side of the gate away from the drain and the side of the drain away from the gate. The trenches are used to isolate different MOSFETs.

[0089] S2. As shown in Figure 2B, a barrier layer comprising silicon oxide (SiO2) and silicon nitride (SiN) is formed, and the barrier layer covers the substrate.

[0090] S3. As shown in Figure 2C, an anti-reflection coating (BARC) and a patterned photoresist are formed. The anti-reflection coating covers SiN, and the photoresist is placed on the side of the anti-reflection coating away from the substrate, exposing the areas where the source, drain, gate and gate sidewall are located.

[0091] S4. As shown in Figure 2D, the silicide block (SAB) is defined by etching process, or in other words, the area where metal silicides will not grow is defined by etching process, part of the anti-reflective layer is removed, and the area where metal silicides grow is exposed.

[0092] The photoresist and remaining antireflective layer were then removed, leaving part of the blocking layer, and the surface on which the metal silicide was grown was pre-cleaned.

[0093] S5. As shown in Figure 2E, a metal layer is deposited in the region where the metal silicide is grown. The metal layer covers the gate, gate sidewall, source, drain and barrier layer.

[0094] S6. As shown in Figure 2F, the first low-temperature rapid thermal annealing (1 st rapid thermal processing, 1 st The RTP forms a high-resistivity metal silicide, with the gate, source, and drain each covered with a high-resistivity metal silicide.

[0095] S7. As shown in Figure 2G, the remaining unreacted metal layer is removed by selective etching.

[0096] S8, As shown in Figure 2H, the second high-temperature rapid thermal annealing (2 ndRTP (Reverse Transformation Technology) transforms high-resistivity metal silicides into low-resistivity metal silicides, forming gate, source, and drain metal silicides. Photoresist and remaining blocking and anti-reflective layers are then removed to form a MOSFET.

[0097] In the case of semiconductor devices including N-type metal oxide semiconductor field effect transistors (NMOSFETs) and P-type metal oxide semiconductor field effect transistors (PMOSFETs), the gate metal silicide, source metal silicide, and drain metal silicide of the NMOSFET are formed synchronously with those of the PMOSFET.

[0098] Figure 3 is a schematic diagram comparing the thermal conductivity of different materials according to an embodiment of this application.

[0099] Metal silicides have attracted much attention due to their excellent low resistance characteristics. However, due to the differences in thermal conductivity of different material systems and the small linewidth effect, when self-aligned metal silicides are formed simultaneously in the gate and source (and drain) regions of the same type of MOSFET using the above process, it is difficult to form metal silicides with uniform performance, low resistance, and no (free) agglomeration defects in different silicon surface regions. This will affect the uniformity of metal silicides and thus affect the contact resistance of the MOSFET.

[0100] For example, as shown in Figure 3, the horizontal axis represents temperature, and the vertical axis represents thermal conductivity. Figure 3 illustrates the thermal conductivity curves of bulk silicon, undoped single-crystal silicon, doped single-crystal silicon, doped polycrystalline silicon, and undoped polycrystalline silicon at different temperatures. Typically, the gate (G) semiconductor of a MOSFET is made of doped polycrystalline silicon, while the source (S) and drain (D) semiconductors are made of doped single-crystal silicon. Doped polycrystalline silicon and doped single-crystal silicon have different thermal conductivities. The gate (G) has low thermal conductivity, while the source (S) and drain (D) have high thermal conductivity. A higher thermal budget is required to form a low-resistivity metal silicide in the gate (G) region. A lower thermal budget is required to form a low-resistivity metal silicide in the source (S) and drain (D) regions.

[0101] The above process cannot balance the heat required for the phase transformation between the source (S) and drain (D) regions and the gate (G) region. Insufficient heat prevents complete transformation, resulting in a high-resistivity phase that affects performance. Excessive heat increases the risk of crystal agglomeration defects. This affects the uniformity of the final metal silicide gate (G) and metal silicide source (S) (and metal silicide drain (D)), leading to an imbalance in the series resistance between the source (S) and drain (D) and the subsequent metal via, as well as the series resistance between the gate (G) and the subsequent metal via.

[0102] In addition, metal silicides have attracted much attention due to their excellent low resistance characteristics. However, the linewidth effect and differences in thermal conductivity can affect the uniformity of metal silicides formed in NMOSFETs and PMOSFETs using the above process, which in turn affects the mismatch characteristics of NMOSFETs and PMOSFETs.

[0103] For example, the doping types of NMOSFETs and PMOSFETs are different, and the corresponding thermal conductivity of the materials is also different, which will affect the uniformity of metal silicides in NMOSFETs and PMOSFETs.

[0104] Based on this, embodiments of this application provide a novel semiconductor device to improve the problem of insufficient metal silicide uniformity in MOSFETs. A method for fabricating a semiconductor device is also provided, for obtaining a MOSFET with relatively superior metal silicide uniformity.

[0105] Figure 4 is a schematic diagram of the fabrication process of a semiconductor device provided in an embodiment of this application; Figures 5A-5F are schematic diagrams of the fabrication process of another semiconductor device provided in an embodiment of this application.

[0106] This application provides a method for fabricating a semiconductor device, used to prepare a semiconductor device with good metal silicide uniformity. The method for fabricating the semiconductor device includes:

[0107] S10, as shown in Figure 5A, a first gate G1, a first source S1 and a first drain D1 are formed on the substrate 61.

[0108] The substrate 61 may be formed of silicon, or it may be formed of other group III, group IV and / or group V elements (e.g., silicon, germanium, gallium, arsenic and combinations thereof). The substrate 61 may also be in the form of silicon-on-insulator (SOI). The SOI substrate may include a silicon substrate body, an insulating layer formed on the silicon substrate body, and a semiconductor layer formed on the insulating layer.

[0109] For example, an N-type well (NW) can be obtained by doping the substrate 61 with group V elements (such as phosphorus, arsenic, antimony, etc.), which can then be used to form an NMOSFET. Alternatively, a P-type well (PW) can be obtained by doping the substrate 61 with trivalent elements (such as boron, indium, gallium, etc.), which can then be used to form a PMOSFET.

[0110] The material of the first gate G1 includes, for example, polysilicon. As an example, the fabrication method further includes forming a first gate sidewall GW1, which is located on the side of the first gate G1, for example, along the gate length direction, with the first gate sidewall GW1 located on both sides of the first gate G1. In subsequent fabrication processes, the semiconductor device is illustrated using the example of the first gate sidewall GW1. If the semiconductor device does not include a gate sidewall, the steps related to the first gate sidewall GW1 may not be performed.

[0111] The first source S1 and the first drain D1 are located within the substrate 61, and along the gate length direction, the first source S1 and the first drain D1 are located on opposite sides of the first gate G1. The material of the first source S1 and the first drain D1 includes, for example, single-crystal silicon. For example, the first source S1 and the first drain D1 can be formed by doping and annealing silicon on the substrate 61.

[0112] For example, the fabrication method further includes forming a trench 63 and a gate insulating layer 62, with trenches 63 respectively formed on the side of the first source S1 away from the first drain D1 and on the side of the first drain D1 away from the first source S1. A gate insulating layer 62 is formed between the first gate G1 and the substrate 61. The specific process of step S10 is not limited in this application embodiment, and methods in related technologies are applicable to this application embodiment.

[0113] In the first implementation, as shown in Figure 4, after step S10 is executed, the following step S20 is executed.

[0114] S20, as shown in Figures 5B and 5C, a first metal silicide layer 64 is formed. The first metal silicide layer 64 is formed on the side of the first gate G1 away from the substrate 61, and the first metal silicide layer 64 covers the top surface of the first gate G1.

[0115] For example, step S20 includes:

[0116] S21. As shown in Figure 5B, a first barrier layer 65 is formed, and the first barrier layer 65 exposes the first gate G1.

[0117] For example, step S21 includes:

[0118] S211, forming a barrier film 65', the barrier film 65' covering the first gate G1, the first source S1, the first gate sidewall GW1, the first drain D1 and the substrate 61.

[0119] The specific structure of the barrier film 65' is not limited in the embodiments of this application, and the structures in related technologies are applicable to the embodiments of this application. For example, as shown in Figure 5B, the barrier film 65' includes a SiO2 layer and a SiN layer.

[0120] S212, Form an anti-reflective layer BARC, the anti-reflective layer BARC covers the barrier film 65'.

[0121] S213. A first mask 66 is formed on the surface of the anti-reflective layer BARC, wherein the first mask 66 exposes at least the first gate G1. For example, the first mask 66 includes an opening that corresponds to the position of the first gate G1, which can be considered as the first mask 66 exposing the first gate G1.

[0122] For example, the first mask 66 exposes the first gate G1.

[0123] Alternatively, for example, the first mask 66 exposes the first gate G1, the first gate sidewall GW1, the first source S1, and the first drain D1.

[0124] Therefore, the first barrier layer 65 can be formed by using a mask in the relevant technology, without the need for additional mask design, which is low-cost and easy to implement.

[0125] S214, Etch the anti-reflective layer BARC and the blocking film 65' to expose the first gate G1, form the first blocking layer 65, and define the silicide metal blocking region.

[0126] The first barrier layer 65 exposes the first gate G1 and covers the first source S1 and the first drain D1. For example, using a dry etching or wet etching process, the etching stops after the first gate G1 is exposed, forming the first barrier layer 65.

[0127] For example, step S21 also includes:

[0128] S215. Remove the first mask 66 and the remaining anti-reflective layer BARC to expose the first barrier layer 65. The first barrier layer 65 can also be understood as a rigid mask, for example.

[0129] S216. Pre-clean the top surface of the first gate G1. The top surface of the first gate G1 can be understood, for example, as the surface of the first gate G1 that is away from the substrate 61 and parallel to the substrate 61.

[0130] S22. As shown in Figure 5C, a first metal layer 64' is formed, which covers the first gate G1.

[0131] For example, the first metal layer 64' also covers the first barrier layer 65.

[0132] For example, the material of the first metal layer 64' includes molybdenum (Mo), tungsten (W), titanium (Ti), nickel (Ni), or cobalt (Co).

[0133] For example, the thickness of the first metal layer 64' is 2nm to 8nm. For instance, the thickness of the first metal layer 64' is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, or 8nm.

[0134] S23. As shown in Figure 5C, the first annealing process is performed to form the first metal silicide layer 64.

[0135] The first gate G1 includes silicon. During the first annealing process, the first metal layer 64' and the first gate G1 recombine to form a metal silicide as the first metal silicide layer 64. The first metal layer 64' does not recombine with the first barrier layer 65; therefore, the first metal layer 64' on the surface of the first barrier layer 65 still exists in the form of a metal layer. The formed metal silicide can be understood as a self-aligned metal silicide.

[0136] For example, a first metal silicide layer 64 with a suitable resistance value for the first gate G1 is formed by low-temperature rapid annealing. For example, the annealing temperature is 380°C to 540°C, and the annealing time is 30s to 120s.

[0137] Alternatively, for example, a first metal silicide layer 64 of metal silicide material is formed by low-temperature rapid annealing, at which point the first metal silicide layer 64 is in a high-resistivity phase.

[0138] In the first annealing process, one annealing process or multiple annealing processes may be performed; this application embodiment does not limit this.

[0139] For example, step S20 also includes S24, removing the uncomposite portion of the first metal layer 64'.

[0140] For example, the portion of the first metal layer 64' that is not combined with the first barrier layer 65 is removed, leaving the metal silicide layer formed by the combination. For example, the remaining unreacted portion of the first metal layer 64' is removed by selective etching, and the selective etching solution can be sulfuric acid.

[0141] After completing step S20, proceed to step S30.

[0142] S30, as shown in Figures 5D-5F, a second metal silicide layer 67 is formed to form the first transistor. The second metal silicide layer 67 is formed on the side of the first source S1 and the first drain D1 away from the substrate 61.

[0143] For example, step S30 includes:

[0144] S31. As shown in Figure 5D, the first barrier layer 65 is patterned to form a second barrier layer 65". The second barrier layer 65 exposes the first source S1, the first drain D1 and the first gate sidewall GW1.

[0145] For example, step S31 includes:

[0146] S311. A second mask 66' is formed, exposing the first source S1 and the first drain D1. For example, the second mask 66' may also expose the first metal silicide layer 64 and the first gate sidewall GW1. Alternatively, for example, the second mask 66' exposes the active area (AA). The source region, drain region, and channel region are collectively referred to as the active area of ​​the MOSFET.

[0147] S312. Pattern the first barrier layer 65, remove the portion of the first barrier layer 65 that covers the first source S1, the first drain D1 and the first gate sidewall GW1, and form a second barrier layer 65". The second barrier layer 65” exposes the first source S1 and the first drain D1, and defines the silicide metal blocking region.

[0148] For example, when patterning the first barrier layer 65, a portion of the first gate sidewall GW1 may be removed, exposing a portion of the sidewall of the first gate G1. Of course, when patterning the first barrier layer 65, a portion of the first gate sidewall GW1 may not be removed, so that the sidewall of the first gate G1 is completely covered by the first gate sidewall GW1.

[0149] For example, step S31 further includes: S313, removing the second mask 66' to expose the second barrier layer 65".

[0150] S32, as shown in Figure 5E, a second metal layer 67' is formed, which covers the first source S1 and the first drain D1.

[0151] For example, the material of the second metal layer 67' includes molybdenum (Mo), tungsten (W), titanium (Ti), nickel (Ni), or cobalt (Co).

[0152] For example, the thickness of the second metal layer 67' is 2nm to 8nm. For instance, the thickness of the second metal layer 67' is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, or 8nm.

[0153] S33. As shown in Figure 5F, a second annealing process is performed to form a second metal silicide layer 67 and a third metal silicide layer 68.

[0154] At this time, the first gate sidewall GW1 covers part of the side surface of the first gate G1. The side surface of the first gate G1 can be, for example, the surface of the first gate G1 facing the first source S1 and the surface of the first gate G1 facing the first drain D1.

[0155] For example, the first gate G1 includes a first region near the substrate 61 and a second region away from the substrate 61, a first gate sidewall GW1 covering the first region, and a third metal silicide layer 68.

[0156] For example, the second metal silicide layer 67 and the third metal silicide layer 68 are formed simultaneously, and the metal included in the third metal silicide layer 68 is the same metal included in the second metal silicide layer 67. For example, the second metal silicide layer 67 and the third metal silicide layer 68 are metal silicides formed from the same metal layer and different silicon atoms.

[0157] The first source S1 and the first drain D1 both contain silicon, as does the first gate G1. The second region of the first gate G1 is not covered by the first sidewall GW1 but is covered by the second metal layer 67'. During the second annealing process, the second metal layer 67' combines with the first source S1 and the first drain D1 to form a metal silicide layer 67. The second metal layer 67' combines with the second region of the first gate G1 to form a third metal silicide layer 68. The second metal layer 67' does not combine with the second barrier layer 65", therefore, the second metal layer 67' on the surface of the second barrier layer 65" still exists in the form of a metal layer. The formed metal silicide can be understood as a self-aligned metal silicide.

[0158] For example, a second metal silicide layer 67 with suitable resistance values ​​for the first source S1 and the first drain D1 is formed by high-temperature rapid annealing. For example, the annealing temperature is 800℃~1300℃ and the annealing time is 100us~1000us.

[0159] Alternatively, for example, a second metal silicide layer 67 is formed by low-temperature rapid annealing, and the second metal silicide layer 67 is in a low-resistivity phase at this time.

[0160] In the second annealing process, one annealing process or multiple annealing processes may be performed; this application embodiment does not limit this.

[0161] The above illustration uses the simultaneous formation of a second metal silicide layer 67 covering the first source S1 and the first drain D1 as an example. Alternatively, a metal silicide layer covering the first source S1 (or the first drain D1) can be formed first, followed by a metal silicide layer covering the first drain D1 (or the first source S1). The fabrication process is the same as described above, except that the mask no longer exposes both the first source S1 and the first drain D1 simultaneously, but only exposes one of them.

[0162] For example, step S30 also includes S34, removing the uncomposite portion of the second metal layer 67' and the second barrier layer 65.

[0163] For example, the portion of the second metal layer 67' that is not composited with the second barrier layer 65" is removed, leaving the composite metal silicide layer. For example, the remaining unreacted portion of the second metal layer 67' is removed by selective etching, and the selective etching solution can be sulfuric acid.

[0164] The semiconductor device fabrication method provided in this application first forms a first metal silicide layer 64 on the surface of a first gate G1, and then forms a second metal silicide layer 67 on the surfaces of a first source S1 and a first drain D1. Since there is a natural height difference between the first gate G1 and the first source S1 and the first drain D1 in their physical structure, the metal silicide layers can be formed stepwise on the functional regions such as the gate region, source region, and drain region on the substrate 61 by utilizing this height difference. This allows for local adaptation, eliminates the need for additional photomasks, and reduces costs. Furthermore, the thermal conductivity of the material of the first gate G1 is typically lower than that of the materials of the first source S1 and the first drain D1, requiring a higher thermal budget when forming the first metal silicide layer 64 to form a low-resistivity metal silicide phase. Conversely, a lower thermal budget is required when forming the second metal silicide layer 67 to form a low-resistivity metal silicide phase. The thermal budget is related to various factors such as annealing temperature and annealing time. If the first metal silicide 64 is formed first, then the first metal silicide layer 64 has essentially undergone two annealing processes. An additional annealing in the thermal budget is more conducive to the transformation of the first metal silicide 64 into the low-resistivity phase. Conversely, the second metal silicide layer 67 only undergoes one annealing process. A thermal budget with only one annealing process is more conducive to reducing the risk of crystal agglomeration defects in the second metal silicide layer 67. Therefore, a balance can be struck regarding the different thermal budgets required for metal silicide formation in different regions.

[0165] In some embodiments, the temperature of the second annealing process is higher than the temperature of the first annealing process.

[0166] The first annealing process is primarily for forming the first metal silicide layer 64 above the first gate G1, and the second annealing process is primarily for forming the second metal silicide layer 67 above the first source S1 and the first drain D1. By performing the first annealing of the first metal layer 64' at a relatively low temperature, followed by a second annealing, the thermal budget is sufficient to ensure complete crystal transformation to form the low-resistivity phase of the first metal silicide layer 64, while also mitigating crystal agglomeration defects in the first metal silicide layer 64 caused by an excessively high thermal budget. By annealing the second metal layer 67' at a higher temperature, the thermal budget of a single annealing process is sufficient to ensure complete crystal transformation to form the low-resistivity phase of the second metal silicide layer 67, while also mitigating crystal agglomeration defects in the second metal silicide layer 67 caused by an excessively high thermal budget.

[0167] Figure 6 is a flowchart of the fabrication process of another semiconductor device provided in the embodiments of this application; Figures 7A-7E are schematic diagrams of the fabrication process of yet another semiconductor device provided in the embodiments of this application.

[0168] In the second implementation, as shown in Figure 6, after step S10 is executed, the following step S20' is executed.

[0169] As shown in Figures 7A and 7B, a second metal silicide layer 67 is formed above the first source S1 and the first drain D1.

[0170] For example, step S20' includes:

[0171] As shown in Figure 7A, a third barrier layer 65”’ is formed in S21’, exposing the first source S1 and the first drain D1.

[0172] For example, step S21' includes:

[0173] S211', forming a barrier film 65', the barrier film 65' covering the first gate G1, the first source S1, the first gate sidewall GW1, the first drain D1 and the substrate 61.

[0174] S212', forming an anti-reflective layer BARC, the anti-reflective layer BARC covering the barrier film 65'.

[0175] S213', A third mask 66" is formed on the surface of the anti-reflective layer BARC. The third mask 66" exposes at least the first source S1 and the first drain D1. For example, the third mask 66" includes an opening that corresponds to the position of the first source S1 and the first drain D1, which can be considered as the third mask 66" exposing the first source S1 and the first drain D1.

[0176] S214' is etched to expose the first source S1 and the first drain D1, forming the third barrier layer 65”'.

[0177] For example, step S21' also includes:

[0178] S215', Remove the first mask 66 and the remaining anti-reflective layer BARC to expose the third barrier layer 65”'. The third barrier layer 65”' can also be understood as a hard mask, for example.

[0179] S216': Pre-clean the surfaces of the first source S1 and the first drain D1.

[0180] As shown in Figure 7B, a second metal layer 67' is formed, which covers the first source S1 and the first drain D1.

[0181] S23', Perform the first annealing treatment to form the second metal silicide layer 67.

[0182] For example, step S20' also includes S24', removing the uncomposite portion of the second metal layer 67'.

[0183] For example, the portion of the second metal layer 67' that is not composited with the third barrier layer 65”' is removed, leaving the composite metal silicide layer.

[0184] After step S20' is completed, step S30' is executed.

[0185] S30', as shown in Figures 7C-7E, forms a first metal silicide layer 64. The first metal silicide layer 64 is formed on the side of the first gate G1 away from the substrate 61, and the first metal silicide layer 64 covers the top surface of the first gate G1.

[0186] For example, step S30' includes:

[0187] S31', as shown in Figure 7C, the third barrier layer 65”' is patterned to form a fourth barrier layer 65”", the fourth barrier layer 65”” exposes the first gate G1.

[0188] For example, step S31' includes:

[0189] S311', forming a fourth mask 66”', the fourth mask 66”' exposing the first gate G1. For example, the fourth mask 66”' may also expose the second metal silicide layer 67 and the first gate sidewall GW1.

[0190] S312', The third barrier layer 65”' is patterned, and the portion of the third barrier layer 65”' covering the first gate G1 is removed to form a fourth barrier layer 65”', the fourth barrier layer 65”' exposes the first gate G1.

[0191] For example, step S31' further includes: S313', removing the fourth mask 66"', exposing the fourth barrier layer 65".

[0192] S32', as shown in Figure 7D, forms a first metal layer 64', which covers the first gate G1.

[0193] S33', as shown in Figure 7E, undergoes a second annealing process to form the first metal silicide layer 64.

[0194] For example, step S33' further includes: removing the uncomposite portion of the first metal layer 64' and the fourth barrier layer 65".

[0195] The semiconductor device fabrication method provided in this application involves forming a first metal silicide layer 64 above a first gate G1 and a second metal silicide layer 67 above a first source S1 and a first drain D1 in steps. The first metal silicide layer 64 and the second metal silicide layer 67 are formed independently. Therefore, depending on the application scenario and requirements, by controlling factors such as process conditions, materials, and thickness, a first metal silicide layer 64 with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with silicon (one or more of the aforementioned characteristics) can be formed above the first gate G1. Similarly, a second metal silicide layer 67 with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with silicon (one or more of the aforementioned characteristics) can be formed above the first source S1 and the first drain D1. This optimizes the impedance characteristics of the first metal silicide layer 64 and the second metal silicide layer 67, improves the first metal silicide layer 64, reduces the power consumption of the semiconductor device, and enhances the stability of the semiconductor device. Furthermore, it allows the average resistance of the final fabricated first metal silicide layer 64 and the average resistance of the second metal silicide layer 67 to reach almost the same level, with significantly reduced resistance dispersion (or a more balanced resistance distribution). This improves the performance balance between the first metal silicide layer 64 and the second metal silicide layer 67, enhances the balance between the series resistance of the first gate G1 and the subsequent metal via, and the series resistance of the first source S1 and the first drain D1 and the subsequent metal via, further improving the stability of the semiconductor device.

[0196] In some embodiments, the temperature of the second annealing process is higher than the temperature of the first annealing process.

[0197] The first annealing process is mainly for forming the second metal silicide layer 67 above the first source S1 and the first drain D1, and the second annealing process is mainly for forming the first metal silicide layer 64 above the first gate G1. The second metal silicide layer 67 is equivalent to undergoing two annealing processes, and the first metal silicide layer 64 is equivalent to undergoing one annealing process. Increasing the temperature of the second annealing process helps to achieve a thermal budget sufficient to allow the crystal to completely transform and form the low-resistivity phase of the first metal silicide layer 64.

[0198] In some embodiments, the thicknesses of the first metal layer 64' and the second metal layer 67' are different.

[0199] Since the first metal layer 64' and the second metal layer 67' are formed in stages, considering various factors such as process, product, and application scenario, different thicknesses of the first metal layer 64' and the second metal layer 67' can be selected. This ensures that the resistance of the final first metal silicide layer 64 and the second metal silicide layer 67 are relatively uniform, and their thicknesses meet the requirements of the application scenario. On the one hand, uniform resistance can improve the linewidth effect of the first metal silicide layer 64 and the second metal silicide layer 67. On the other hand, meeting the thickness requirements of the first metal silicide layer 64 and the second metal silicide layer 67 can avoid the problem that the thickness of the first metal silicide layer 64 and the second metal silicide layer 67 cannot be simultaneously met, resulting in the problem of the first metal silicide layer 64 being too thin and breaking down in subsequent processes, or the first metal silicide layer 67 being too thick and causing leakage current.

[0200] In other embodiments, the first metal layer 64' and the second metal layer 67' have the same thickness.

[0201] In some embodiments, the first metal layer 64' and the second metal layer 67' are made of the same material.

[0202] For example, the materials of the first metal layer 64' and the second metal layer 67' include Mo, W, Ti, or Co. The materials of the first metal layer 64' and the second metal layer 67' are the same, but the thicknesses of the first metal layer 64' and the second metal layer 67' may be different.

[0203] Even if the first metal layer 64' and the second metal layer 67' are made of the same material, since the metal silicide layer formed by the second annealing (e.g., the second metal silicide layer 67) only undergoes one annealing process, the thermal budget of the metal silicide layer can be reduced, effectively reducing the risk of high-temperature agglomeration of the metal silicide layer, thereby improving the problem of silicide agglomeration formed on different types of silicon surfaces in advanced planar nodes.

[0204] In other embodiments, the materials of the first metal layer 64' and the second metal layer 67' are different. The different materials can be due to different metal elements, or the same metal elements but different proportions, etc.

[0205] For example, a first metal silicide layer 64 is formed first, followed by a second metal silicide layer 67. The thermal stability of the material of the first metal layer 64' is higher than that of the material of the second metal layer 67'.

[0206] For example, the material of the first metal layer 64' includes Co, which has high thermal stability, and the material of the second metal layer 67' includes Ni, which has low temperature and low silicon consumption.

[0207] Alternatively, as an example, a second metal silicide layer 67 may be formed first, followed by a first metal silicide layer 64. The material of the second metal layer 67' has higher thermal stability than the material of the first metal layer 64'.

[0208] For example, the material of the first metal layer 64' includes Ni, which has a low temperature and low silicon consumption, and the material of the second metal layer 67' includes Co, which has high thermal stability.

[0209] Different types or compositions of metals can be deposited in the region where the first gate G1 is located, and in the regions where the first source S1 and the first drain D1 are located, so that different silicon materials can be matched with suitable metals according to the application scenario to form a first metal silicide layer 64 and a second metal silicide layer 67 with uniform resistance and balanced performance, so as to improve the linewidth effect of the first metal silicide layer 64 and the second metal silicide layer 67.

[0210] Figure 8A is a flowchart of the fabrication process of another semiconductor device provided in the embodiment of this application, and Figure 8B is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application.

[0211] In the third implementation, in some embodiments, as shown in FIG8A, the preparation method includes:

[0212] S100, as shown in FIG8B, a first gate G1, a first source S1 and a first drain D1, as well as a second gate G2, a second source S2 and a second drain D2 are formed on the substrate 61.

[0213] For example, while forming a first gate G1, a first source S1, and a first drain D1 on the substrate 61, a second gate G2, a second source S2, and a second drain D2 are formed simultaneously. A second gate sidewall GW2 and a second gate insulating layer 62' can also be formed on the substrate 61.

[0214] S200, while forming the first metal silicide layer 64, a fourth metal silicide layer 69 is formed. The fourth metal silicide layer 69 is formed on the side of the second gate G2 away from the substrate 61, and the fourth metal silicide layer 69 covers the top surface of the second gate G2.

[0215] The fourth metal silicide layer 69 and the first metal silicide layer 64 are formed simultaneously in the same annealing process. The formation of the fourth metal silicide layer 69 can be referred to the above description regarding the formation of the first metal silicide layer 64, and will not be repeated here.

[0216] In step S300, while forming the second metal silicide layer 67, a fifth metal silicide layer 60 is formed to form the second transistor. The fifth metal silicide layer 60 is formed on the side of the second source S2 and the second drain D2 away from the substrate 61.

[0217] The fifth metal silicide layer 60 and the second metal silicide layer 67 are formed simultaneously in the same annealing process. The formation of the fifth metal silicide layer 60 can be referred to the above description regarding the formation of the second metal silicide layer 67, and will not be repeated here.

[0218] In some embodiments, the first transistor further includes a third metal silicide layer 68, and the second transistor further includes a sixth metal silicide layer 70, the sixth metal silicide layer 70 covering a portion of the sidewalls of the second gate G2.

[0219] For example, the second metal silicide layer 67, the third metal silicide layer 68, the fifth metal silicide layer 60, and the sixth metal silicide layer 70 are formed simultaneously.

[0220] That is, when a semiconductor device includes multiple transistors, the multiple transistors can be formed simultaneously to simplify the fabrication process. Furthermore, since the first metal silicide layer 64 and the fourth metal silicide layer 69 are formed simultaneously, the mask used to define the metal silicide stop region can directly utilize existing masks in related technologies to reduce costs.

[0221] Figure 9A is a flowchart of the fabrication process of another semiconductor device provided in the embodiment of this application, and Figure 9B is a schematic diagram of the fabrication process of another semiconductor device provided in the embodiment of this application.

[0222] In the fourth implementation, as shown in FIG9A in some embodiments, the preparation method further includes:

[0223] As shown in Figure 9B, a first gate G1, a first source S1, and a first drain D1, as well as a second gate G2, a second source S2, and a second drain D2 are formed on the substrate 61.

[0224] S200', while forming the second metal silicide layer 67, also forms the fifth metal silicide layer 60. The fifth metal silicide layer 60 is formed on the side of the second source S2 and the second drain D2 away from the substrate 61.

[0225] In step S300', while forming the first metal silicide layer 64, a fourth metal silicide layer 69 is formed to form the second transistor. The fourth metal silicide layer 69 is formed on the side of the second gate G2 away from the substrate 61, and the fourth metal silicide layer 69 covers the top surface of the second gate G2.

[0226] That is, when a semiconductor device includes multiple transistors, the multiple transistors can be formed simultaneously to simplify the fabrication process, and the linewidth effect of each formed transistor can be improved.

[0227] In a fifth implementation, in some embodiments, the fabrication method further includes forming a second transistor. After forming the first transistor, the step of forming the first transistor described above is performed again to form the second transistor.

[0228] That is, by first forming a first transistor using the above-mentioned fabrication process, and then forming a second transistor, the final semiconductor device can include multiple transistors with superior performance.

[0229] In some embodiments, both the first transistor and the second transistor are N-type transistors.

[0230] In other embodiments, both the first transistor and the second transistor are P-type transistors.

[0231] In some other embodiments, the first transistor and the second transistor are N-type and P-type transistors, respectively. For example, the first transistor is an N-type transistor and the second transistor is a P-type transistor. Alternatively, for example, the first transistor is a P-type transistor and the second transistor is an N-type transistor. The N-type transistor and the P-type transistor can be isolated, for example, by trench 63.

[0232] When a semiconductor device includes both N-type and P-type transistors, the linewidth effect of the metal silicide layer in both the N-type and P-type transistors prepared by the preparation method provided in this application can be improved, thereby reducing the power consumption of the semiconductor device and improving its stability.

[0233] This application also provides a semiconductor device, which is prepared by the above-described preparation method.

[0234] Figure 10 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0235] This application also provides a semiconductor device, as shown in FIG10, which includes a substrate 61 and a first transistor MOS1 disposed on the substrate 61.

[0236] The first transistor MOS1 includes a first gate G1, a first source S1, a first drain D1, a first metal silicide layer 64, and a second metal silicide layer 67. The first transistor MOS1 can be a PMOSFET or an NMOSFET.

[0237] For example, the first transistor MOS1 may also include a first gate insulating layer 62, a first gate sidewall GW1, and a trench 63. The structure shown in Figure 10 is merely illustrative and is not intended to limit the application; the architectures in related technologies are applicable to the embodiments of this application.

[0238] The first gate G1 is disposed on the substrate 61, the first gate insulating layer 62 is disposed between the first gate G1 and the substrate 61, and the first gate sidewall GW1 is disposed on the side of the first gate G1.

[0239] The first source S1 and the first drain D1 are disposed on the substrate 61, and are disposed on the same side of the substrate 61 as the first gate G1. The first source S1 and the first drain D1 are located on opposite sides of the first gate G1.

[0240] A first metal silicide layer 64 is disposed on the side of the first gate G1 away from the substrate 61, and the first metal silicide layer 64 covers the top surface of the first gate G1. The first metal silicide layer 64 can be prepared, for example, by a self-aligned process.

[0241] A second metal silicide layer 67 is disposed on the side of the first source S1 and the first drain D1 away from the substrate 61. For example, the second metal silicide layer 67 covers the surfaces of the first source S1 and the first drain D1. The second metal silicide layer 67 can be prepared, for example, by a self-aligned process.

[0242] In some embodiments, the first metal silicide layer 64 and the second metal silicide layer 67 are formed by different annealing processes.

[0243] Different annealing processes can lead to different results. For example, it can be understood that when the first metal silicide layer 64 is formed by combining metal and silicon, the second metal silicide layer 67 is not formed. Conversely, when the second metal silicide layer 67 is formed by combining metal and silicon, the first metal silicide layer 64 is not formed. Alternatively, it can be understood that the first metal silicide layer 64 and the second metal silicide layer 67 are silicon metals formed by combining different metal layers and silicon, rather than silicon metals formed by combining the same metal layer and silicon. It can also be understood that the first metal silicide layer 64 and the second metal silicide layer 67 are formed asynchronously. Or, it can be understood that different process parameters such as annealing temperature, annealing time, and number of annealing cycles, or formation in different annealing processes, all fall under the category of different annealing processes.

[0244] The semiconductor device provided in this application embodiment forms a first metal silicide layer 64 above the first gate G1 and a second metal silicide layer 67 above the first source S1 and the first drain D1 in steps. The first metal silicide layer 64 and the second metal silicide layer 67 are formed independently. Therefore, depending on the application scenario and requirements, by controlling factors such as process conditions, materials, and thickness, a first metal silicide layer 64 with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface can be formed above the first gate G1. Similarly, a second metal silicide layer 67 with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight or smooth lattice bonding with the silicon contact interface can be formed above the first source S1 and the first drain D1. This optimizes the impedance characteristics of the first metal silicide layer 64 and the second metal silicide layer 67, improves the linewidth effect of the first metal silicide layer 64 and the second metal silicide layer 67, reduces the power consumption of the semiconductor device, and enhances the stability of the semiconductor device. Furthermore, it allows the average resistance of the final fabricated first metal silicide layer 64 and the average resistance of the second metal silicide layer 67 to reach almost the same level, with significantly reduced resistance dispersion (or a more balanced resistance distribution). This improves the performance balance between the first metal silicide layer 64 and the second metal silicide layer 67, enhances the balance between the series resistance of the first gate G1 and the subsequent metal via, and the series resistance of the first source S1 and the first drain D1 and the subsequent metal via, further improving the stability of the semiconductor device.

[0245] In some embodiments, the metal included in the first metal silicide layer 64 is the same as the metal included in the second metal silicide layer 67.

[0246] For example, the metal of the first metal silicide layer 64 and the metal of the second metal silicide layer 67 may include Mo, W, Ti or Co.

[0247] Even if the metal included in the first metal silicide layer 64 is the same as the metal included in the second metal silicide layer 67, since the later-formed metal silicide layer (e.g., the second metal silicide layer 67) only undergoes one annealing process, the thermal budget of the metal silicide layer can be reduced, effectively reducing the risk of high-temperature agglomeration of the metal silicide layer, thereby improving the problem of silicide agglomeration formed on different types of silicon surfaces in advanced planar nodes.

[0248] In some embodiments, the metal included in the first metal silicide layer 64 is different from the metal included in the second metal silicide layer 67.

[0249] For example, the metal of the first metal silicide layer 64 includes Mo, W, Ti or Co, and the metal of the second metal silicide layer 67 includes Mo, W, Ti or Co.

[0250] For example, the first metal silicide layer 64 comprises Co, and the second metal silicide layer 67 comprises Ti. Alternatively, the first metal silicide layer 64 comprises Co, and the second metal silicide layer 67 comprises Ni. Alternatively, the first metal silicide layer 64 comprises Ni, and the second metal silicide layer 67 comprises Co. Alternatively, the first metal silicide layer 64 comprises Ti, and the second metal silicide layer 67 comprises Co.

[0251] The metal included in the first metal silicide layer 64 does not necessarily have to be the same as the metal included in the second metal silicide layer 67. Therefore, it is possible to match the silicon material of the first gate G1 and the silicon materials of the first source S1 and the first drain D1 with suitable metals according to the application scenario and device characteristics. This helps to form a first metal silicide layer 64 and a second metal silicide layer 67 with balanced performance, uniform morphology, excellent resistance, uniform thickness, and tight lattice bonding with silicon or uniform and smooth interface, so as to improve the linewidth effect of the first metal silicide layer 64 and the second metal silicide layer 67.

[0252] In some embodiments, the metal included in the first metal silicide layer 64 has different thermal stability than the metal included in the second metal silicide layer 67.

[0253] Optionally, the thermal stability of the metal included in the first metal silicide layer 64 is higher than that of the metal included in the second metal silicide layer 67.

[0254] For example, if a first metal silicide layer 64 is formed first, and then a second metal silicide layer 67 is formed, then the thermal budget of the first metal silicide layer 64 is higher than that of the second metal silicide layer 67. By using a metal with high thermal stability in the first metal silicide layer 64, the risk of crystal agglomeration defects in the first metal silicide layer 64 due to excessive heat can be reduced.

[0255] Alternatively, the thermal stability of the metal included in the first metal silicide layer 64 may be lower than that of the metal included in the second metal silicide layer 67.

[0256] For example, if a second metal silicide layer 67 is formed first, followed by a first metal silicide layer 64, then the thermal budget of the second metal silicide layer 67 is higher than that of the first metal silicide layer 64. By using a metal with high thermal stability in the second metal silicide layer 67, the risk of crystal agglomeration defects in the second metal silicide layer 67 due to excessive heat can be reduced.

[0257] Figure 11 is a schematic diagram of another semiconductor device provided in an embodiment of this application.

[0258] In some embodiments, as shown in FIG11, the semiconductor device further includes a third metal silicide layer 68.

[0259] The side of the first gate G1 includes a first region close to the substrate 61 and a second region away from the substrate 61, the first gate sidewall GW1 covers the first region, and the third metal silicide layer 68 covers the second region.

[0260] The third metal silicide layer 68 comprises the same metal as the second metal silicide layer 67, or it can be understood that the third metal silicide layer 68 and the second metal silicide layer 67 are metal silicides formed by combining the same metal layer with different silicon atoms.

[0261] Whether the surface of the third metal silicide layer 68 is flush with the side of the first gate G1 depends on the thickness of the metal layer and the process conditions during recombination. Figure 11 is only an illustration and is not intended to limit anything.

[0262] Due to process factors, the third metal silicide layer 68 may be formed simultaneously with the formation of the second metal silicide layer 67. However, the formation of the third metal silicide layer 68 will not affect the uniformity of the resistance values ​​of the first metal silicide layer 64 and the second metal silicide layer 67, and is highly feasible.

[0263] In some embodiments, the metal of the first metal silicide layer 64 includes Mo, W, Ti, or Co. For example, the ratio of metal to silicon in the first metal silicide layer 64 ranges from 1:1.5 to 1:2.

[0264] For example, the ratio of metal to silicon in the first metal silicide layer 64 can be 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, or 1:2.

[0265] In other embodiments, the metal of the first metal silicide layer 64 includes Ni. For example, the ratio of metal to silicon in the first metal silicide layer 64 ranges from 1:1 to 1.9:1.

[0266] For example, the ratio of metal to silicon in the first metal silicide layer 64 can be 1:1, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, or 1.9:1.

[0267] This can significantly reduce the average resistance of the first metal silicide layer 64, and even make the first metal silicide layer 64 reach a low resistance phase, further reducing the contact resistance between the first gate G1 and the subsequent metal via.

[0268] In some embodiments, the metal of the second metal silicide layer 67 includes Mo, W, Ti, or Co. For example, the ratio of metal to silicon in the second metal silicide layer 67 ranges from 1:1.5 to 1:2.

[0269] For example, the ratio of metal to silicon in the second metal silicide layer 67 can be 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, or 1:2.

[0270] In other embodiments, the metal of the second metal silicide layer 67 includes Ni. For example, the ratio of metal to silicon in the second metal silicide layer 67 ranges from 1:1 to 1.9:1.

[0271] For example, the ratio of metal to silicon in the second metal silicide layer 67 can be 1:1, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, or 1.9:1.

[0272] This can significantly reduce the average resistance of the second metal silicide layer 67, and even make the second metal silicide layer 67 reach a low resistance phase, further reducing the contact resistance between the first source S1 or the first drain D1 and the subsequent metal via.

[0273] In some embodiments, the thickness of the first metal silicide layer 64 is the same at all locations.

[0274] The first metal silicide layer 64 and the second metal silicide layer 67 are formed separately. Therefore, when forming the first metal silicide layer 64, only factors such as the metal material, metal layer thickness, and process conditions need to be adjusted to optimize the performance of the first metal silicide layer 64, without needing to consider the second metal silicide layer 67. Thus, a first metal silicide layer 64 with uniform thickness can be formed. The uniform thickness of the first metal silicide layer 64 results in a uniform resistance, further improving the linewidth effect of the first metal silicide layer 64.

[0275] In some embodiments, the thickness of the second metal silicide layer 67 is the same at all locations.

[0276] The first metal silicide layer 64 and the second metal silicide layer 67 are formed separately. Therefore, when forming the second metal silicide layer 67, only factors such as the metal material, metal layer thickness, and process conditions need to be adjusted to optimize the performance of the second metal silicide layer 67, without needing to consider the first metal silicide layer 64. Thus, a second metal silicide layer 67 with uniform thickness can be formed. The uniform thickness of the second metal silicide layer 67 results in uniform resistance, further improving the linewidth effect of the second metal silicide layer 67.

[0277] In some embodiments, the sheet resistance of the first metal silicide layer 64 is less than or equal to 20 mΩ / cm. For example, the sheet resistance of the first metal silicide layer 64 is less than or equal to 20 mΩ / cm, 19 mΩ / cm, 18 mΩ / cm, 17 mΩ / cm, 16 mΩ / cm, 15 mΩ / cm, 14 mΩ / cm, 10 mΩ / cm, 5 mΩ / cm, etc.

[0278] Sheet resistance refers to the resistance between two opposite sides of a square conductive film when its thickness is uniform and much smaller than its side length. It does not change with the size of the square, but only depends on the properties of the material itself and the thickness of the film.

[0279] In the semiconductor device provided in this application embodiment, the first metal silicide layer 64 has excellent resistance, which can be below 20mΩ / cm, thereby reducing the contact resistance between the first gate G1 and the subsequent metal via, reducing the power consumption of the semiconductor device, and improving the stability of the semiconductor device.

[0280] In some embodiments, the sheet resistance of the second metal silicide layer 67 is less than or equal to 20 mΩ / cm. For example, the sheet resistance of the second metal silicide layer 67 is less than or equal to 20 mΩ / cm, 19 mΩ / cm, 18 mΩ / cm, 17 mΩ / cm, 16 mΩ / cm, 15 mΩ / cm, 14 mΩ / cm, 10 mΩ / cm, 5 mΩ / cm, etc.

[0281] In the semiconductor device provided in this application embodiment, the second metal silicide layer 67 has excellent resistance, which can be below 20mΩ / cm, thereby reducing the contact resistance between the first source S1 or the first drain D1 and the subsequent metal via, so as to reduce the power consumption of the semiconductor device and improve the stability of the semiconductor device.

[0282] In some embodiments, the difference between the sheet resistance of the first metal silicide layer 64 and the sheet resistance of the second metal silicide layer 67 is less than or equal to 10 mΩ / cm.

[0283] For example, the difference between the sheet resistance of the first metal silicide layer 64 and the sheet resistance of the second metal silicide layer 67 is less than or equal to 10 mΩ / cm, 9 mΩ / cm, 8 mΩ / cm, 7 mΩ / cm, 6 mΩ / cm, 5 mΩ / cm, etc.

[0284] In the semiconductor device provided in this application embodiment, the difference between the sheet resistance of the first metal silicide layer 64 and the sheet resistance of the second metal silicide layer 67 can be less than 10mΩ / cm. The performance balance between the first metal silicide layer 64 and the second metal silicide layer 67 improves the balance between the series resistance of the first source S1 and the first drain D1 and the back-end metal via and the series resistance of the first gate G1 and the back-end metal via.

[0285] Figures 12 and 13 are schematic diagrams of the structure of another semiconductor device provided in the embodiments of this application.

[0286] In some embodiments, the semiconductor device includes a plurality of transistors. For example, as shown in FIG12, the plurality of transistors includes the first transistor MOS1 and the second transistor MOS2 described above.

[0287] As shown in Figure 12, the second transistor MOS2 includes a second gate G2, a second source S2, a second drain D2, a second gate insulating layer 62', and a second gate sidewall GW2. The second transistor MOS2 may also include a fourth metal silicide 69 and a fifth metal silicide 60. As shown in Figure 13, the second transistor MOS2 may also include a seventh metal silicide 70.

[0288] The structure of the second transistor MOS2 can be the same as that of the first transistor MOS1, and will not be described again here. Both the first transistor MOS1 and the second transistor MOS2 can be N-type transistors. Alternatively, both the first transistor MOS1 and the second transistor MOS2 can be P-type transistors.

[0289] The first transistor MOS1 and the second transistor MOS2 can also be N-type and P-type transistors, respectively. In this case, the first transistor MOS1 and the second transistor MOS2 have the same architecture but different doping types. For example, the first transistor MOS1 is an N-type transistor and the second transistor MOS2 is a P-type transistor. Or, for example, the first transistor MOS1 is a P-type transistor and the second transistor MOS2 is an N-type transistor.

[0290] The semiconductor device provided in this application can be in the form of a semiconductor structure, a bare chip, or a chip, etc. This application does not limit the specific form of the semiconductor structure.

[0291] This application also provides a wafer including a plurality of the above-described semiconductor devices arranged in an array.

[0292] This application also provides a chip packaging structure, which includes a substrate and any of the aforementioned semiconductor devices, with the semiconductor devices disposed on one side of the substrate. The chip packaging structure may contain only the aforementioned semiconductor devices, or it may contain multiple semiconductor devices with different performance characteristics.

[0293] This application also provides an electronic device, which includes a circuit board and any of the aforementioned semiconductor devices, wherein the semiconductor devices are electrically connected to the circuit board. Alternatively, the electronic device includes a circuit board and any of the aforementioned chip package structures, wherein the chip package structure is electrically connected to the circuit board.

[0294] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a substrate and a transistor disposed on the substrate; The transistor includes: A gate is disposed on the substrate; The source and drain are disposed on the substrate, located on opposite sides of the gate; A first metal silicide layer is disposed on the side of the gate away from the substrate; the first metal silicide layer covers the top surface of the gate; A second metal silicide layer is disposed on the side of the source and drain electrodes away from the substrate. The metal included in the first metal silicide layer is different from the metal included in the second metal silicide layer.

2. The semiconductor device according to claim 1, characterized in that, The thermal stability of the metal included in the first metal silicide layer is higher than that of the metal included in the second metal silicide layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes a gate sidewall and a third metal silicide layer; The sidewall of the gate includes a first region close to the substrate and a second region away from the substrate; the gate sidewall covers the first region; The third metal silicide layer covers the second region; the metal included in the third metal silicide layer is the same as the metal included in the second metal silicide layer.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The thickness of the first metal silicide layer is the same at all locations; And / or, The thickness of the second metal silicide layer is the same at all locations.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The sheet resistance of the first metal silicide layer is less than or equal to 20 mΩ / cm; And / or, The sheet resistance of the second metal silicide layer is less than or equal to 20 mΩ / cm.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The difference between the sheet resistance of the first metal silicide layer and the sheet resistance of the second metal silicide layer is less than 10 mΩ / cm.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The metal in the first metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1.5 to 1:

2. And / or, The metal in the second metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the second metal silicide layer ranges from 1:1.5 to 1:

2.

8. The semiconductor device according to any one of claims 1-6, characterized in that, The metal in the first metal silicide layer includes Ni; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1 to 1.9:

1. And / or, The metal in the second metal silicide layer includes Ni; the ratio of metal to silicon in the second metal silicide layer ranges from 1:1 to 1.9:

1.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The semiconductor device includes a plurality of transistors; the plurality of transistors include N-type transistors and / or P-type transistors.

10. A semiconductor device, characterized in that, The semiconductor device includes: a substrate and a transistor disposed on the substrate; The transistor includes: A gate is disposed on the substrate; The source and drain are disposed on the substrate, located on opposite sides of the gate; A first metal silicide layer is disposed on the side of the gate away from the substrate; the first metal silicide layer covers the top surface of the gate; A second metal silicide layer is disposed on the side of the source and drain electrodes away from the substrate. The first metal silicide layer and the second metal silicide layer are formed by different annealing processes.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes a gate sidewall and a third metal silicide layer; The sidewall of the gate includes a first region close to the substrate and a second region away from the substrate; the gate sidewall covers the first region; and the third metal silicide layer covers the second region.

12. The semiconductor device according to claim 10 or 11, characterized in that, The first metal silicide layer comprises the same metal as the second metal silicide layer.

13. The semiconductor device according to any one of claims 10-12, characterized in that, The sheet resistance of the first metal silicide layer is less than or equal to 20 mΩ / cm; And / or, The sheet resistance of the second metal silicide layer is less than or equal to 20 mΩ / cm.

14. The semiconductor device according to any one of claims 10-13, characterized in that, The metal in the first metal silicide layer includes Mo, W, Ti, or Co; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1.5 to 1:

2. or, The metal in the first metal silicide layer includes Ni; the ratio of metal to silicon in the first metal silicide layer ranges from 1:1 to 2:

1.

15. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A first gate, a first source, and a first drain are formed on a substrate; the first source and the first drain are located on opposite sides of the first gate; A first metal silicide layer is formed; the first metal silicide layer is formed on the side of the first gate away from the substrate; the first metal silicide layer covers the top surface of the first gate; A second metal silicide layer is formed to form a first transistor; the second metal silicide layer is formed on the side of the first source and the first drain away from the substrate.

16. The preparation method according to claim 15, characterized in that, Forming a first metal silicide layer includes: A first barrier layer is formed, the first barrier layer exposing the first gate; A first metal layer is formed, which covers the first gate. The first annealing process is performed to form the first metal silicide layer; Forming a second metal silicide layer includes: The first barrier layer is patterned to form a second barrier layer, the second barrier layer exposing the first source and the first drain; A second metal layer is formed, which covers the first source and the first drain. A second annealing process is performed to form the second metal silicide layer.

17. The preparation method according to claim 16, characterized in that, The thickness of the first metal layer is different from the thickness of the second metal layer.

18. The preparation method according to claim 16 or 17, characterized in that, Forming the first barrier layer includes: A barrier film is formed, the barrier film covering the first gate, the first source, the first drain, and the substrate; An anti-reflective layer is formed, which covers the barrier film; A mask is formed on the surface of the anti-reflection layer, the mask exposing the first gate, the first source, and the first drain. The anti-reflective layer and the barrier film are etched to expose the first gate, forming the first barrier layer.

19. The preparation method according to any one of claims 15-18, characterized in that, The preparation method further includes: A first gate sidewall is formed; the side of the first gate includes a first region close to the substrate and a second region away from the substrate; the first gate sidewall covers the first region; A third metal silicide layer is formed simultaneously with the formation of the second metal silicide layer; the third metal silicide layer covers the second region.

20. The preparation method according to any one of claims 15-19, characterized in that, The thermal stability of the metal included in the first metal silicide layer is higher than that of the metal included in the second metal silicide layer.

21. The preparation method according to claim 15, characterized in that, Forming a second metal silicide layer includes: A third barrier layer is formed, which exposes the first source and the first drain. A second metal layer is formed, which covers the first source and the first drain. The first annealing process is performed to form the second metal silicide layer; Forming a first metal silicide layer includes: The third barrier layer is patterned to form a fourth barrier layer, the fourth barrier layer exposing the first gate; A first metal layer is formed, which covers the first gate. A second annealing process is performed to form the first metal silicide layer.

22. The preparation method according to any one of claims 15-21, characterized in that, The temperature of the second annealing process is higher than the temperature of the first annealing process.

23. The preparation method according to any one of claims 15-22, characterized in that, The metal included in the first metal silicide layer is different from the metal included in the second metal silicide layer.

24. The preparation method according to any one of claims 15-23, characterized in that, The preparation method further includes: A second gate, a second source, and a second drain are formed on the substrate; While forming the first metal silicide layer, a fourth metal silicide layer is formed; the fourth metal silicide layer is formed on the side of the second gate away from the substrate; the fourth metal silicide layer covers the top surface of the second gate. While forming the second metal silicide layer, a fifth metal silicide layer is formed to form the second transistor; the fifth metal silicide layer is formed on the side of the second source and the second drain away from the substrate; The first transistor and the second transistor are respectively an N-type transistor and a P-type transistor.

25. A wafer, characterized in that, It includes a plurality of semiconductor devices arranged in an array as described in any one of claims 1-14.

26. A chip packaging structure, characterized in that, The chip packaging structure includes: a substrate and a semiconductor device as described in any one of claims 1-14, wherein the semiconductor device is disposed on one side of the substrate.

27. An electronic device, characterized in that, The electronic device includes: Circuit board; The semiconductor device as described in any one of claims 1-14, wherein the semiconductor device is electrically connected to the circuit board; or, The chip packaging structure as described in claim 26 is electrically connected to the circuit board.

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