Chip stack structure, manufacturing method therefor, chip package structure, and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a chip stack structure, a manufacturing method therefor, a chip package structure, and an electronic device, for use in improving hybrid bonding quality and improving yield of the chip stack structure. In the chip stack structure, between a first chip and a second chip, in addition to a sixth dielectric layer for filling a gap, a fourth dielectric layer and a fifth dielectric layer are further comprised. The fourth dielectric layer covers a side surface of a first circuit layer in the first chip, and the fifth dielectric layer covers a side surface of a second circuit layer in the second chip. The fourth dielectric layer and the fifth dielectric layer can cover molten slag debris on the side surfaces of the circuit layers, preventing the molten slag debris from scattering, and improving cleanliness of a bonding surface between a first bonding layer and a third bonding layer and a bonding surface between a second bonding layer and the third bonding layer, thereby improving the bonding effect of hybrid bonding and improving product yield.

Description

Chip stacking structures and their fabrication methods, chip packaging structures, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510393363.4, filed with the State Intellectual Property Office of China on March 28, 2025, entitled "Chip Stacking Structure and Preparation Method Thereof, Chip Packaging Structure, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a chip stacking structure and its fabrication method, a chip packaging structure, and an electronic device. Background Technology

[0003] With the development of electronic technology, electronic devices are constantly moving towards miniaturization, integration, and ultra-thinness, and the chip packaging structure in electronic devices also has to develop towards miniaturization.

[0004] When interconnect pin pitch shrinks to 10µm, conventional microbump (uBump) processes face significant challenges. For applications with pitches smaller than 10µm, the industry commonly employs hybrid bonding (HB) for interconnection. Hybrid bonding uses planar soldering and interconnects via smaller pads to achieve higher vertical interconnect density, greater bandwidth, and lower power consumption. Therefore, hybrid bonding is one of the key technologies for realizing high-density 3D stacked packaging and architecture integration design.

[0005] However, hybrid bonding requires extremely high cleanliness. If the bonding interface is contaminated, it will affect the quality of hybrid bonding and cause a loss of yield. Summary of the Invention

[0006] This application provides a chip stacking structure and its fabrication method, a chip packaging structure, and an electronic device, which are used to improve the quality of hybrid bonding and increase the yield of chip stacking structures.

[0007] A first aspect of this application provides a chip stacking structure, comprising a first chip, a second chip, a third chip, a first bonding layer, a second bonding layer, a third bonding layer, a fourth dielectric layer, a fifth dielectric layer, and a sixth dielectric layer. The first chip includes a first substrate and a first circuit layer disposed on one side of the first substrate. The first bonding layer is electrically connected to the first circuit layer and includes a first dielectric layer and a first pad, the first pad penetrating the first dielectric layer. The second chip includes a second substrate and a second circuit layer disposed on one side of the second substrate. A first gap exists between the first substrate and the second substrate, and a second gap exists between the first circuit layer and the second circuit layer. The second bonding layer is electrically connected to the second circuit layer and includes a second dielectric layer and a second pad, the second pad penetrating the second dielectric layer. The third bonding layer is electrically connected to the third chip and includes a third dielectric layer and a plurality of third pads, the plurality of third pads penetrating the third dielectric layer and spaced apart. The first dielectric layer and the second dielectric layer are respectively bonded to the third dielectric layer, and the first pad and the second pad are electrically connected to different third pads. That is, the first bonding layer and the second bonding layer are respectively mixed and bonded with the third bonding layer. The fourth dielectric layer covers the side of the first circuit layer, the fifth dielectric layer covers the side of the second circuit layer, and the sixth dielectric layer fills the first gap and extends between the fourth and fifth dielectric layers, filling the second gap.

[0008] The chip stacking structure provided in this application embodiment includes a fourth dielectric layer and a fifth dielectric layer between the first chip and the second chip, in addition to a sixth dielectric layer used to fill the gap. The fourth dielectric layer covers the side of the first circuit layer, and the fifth dielectric layer covers the side of the second circuit layer. The fourth and fifth dielectric layers can cover the molten slag residue on the side of the circuit layer, preventing molten slag residue from scattering and improving the cleanliness of the bonding surfaces of the first and second bonding layers with the third bonding layer. This improves the bonding effect of the first and second dielectric layers with the third dielectric layer, as well as the electrical connection effect of the first and second pads with the third pad, i.e., improving the bonding effect of hybrid bonding, thereby improving product yield. Moreover, when the bonding yield of the first chip and the second chip with the third chip is guaranteed, the bonding chips can be stacked and bonded on the back of the first chip and the second chip in the same manner, which is beneficial to realizing a high-density three-dimensional stacking structure.

[0009] In one possible implementation, the surface of the first bonding layer facing the third bonding layer is flat. In the chip stacking structure, the flat surface of the first bonding layer, without obvious protrusions, can improve the adhesion between the surfaces of the first and third bonding layers, thereby enhancing the bonding effect between the first and third bonding layers.

[0010] In one possible implementation, the surface of the second bonding layer facing the third bonding layer is flat. In the chip stacking structure, the flat surface of the second bonding layer, without obvious protrusions, can improve the adhesion between the surfaces of the second and third bonding layers, thereby enhancing the bonding effect between the two layers.

[0011] In one possible implementation, the flatness of the surface of the first bonding layer facing the third bonding layer is less than 0.2 μm. In this case, the bonding yield of the small-sized first and third bonding layers can also be relatively high.

[0012] In one possible implementation, the flatness of the surface of the second bonding layer facing the third bonding layer is less than 0.2 μm. In this case, the bonding yield of the small-sized second and third bonding layers is higher.

[0013] In one possible implementation, the fourth dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, with the first sub-dielectric layer disposed close to the first circuit layer. The density of the first sub-dielectric layer is greater than that of the second sub-dielectric layer. The first sub-dielectric layer is disposed close to the first circuit layer, for example, directly covering the slag on the side of the first circuit layer. By increasing the density of the first sub-dielectric layer, its anti-diffusion capability can be improved, reducing the probability of diffusion of exposed metal during the cutting process to form the first circuit layer. This also reduces the probability of residue scattering and improves product yield.

[0014] In one possible implementation, the fourth dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, with the first sub-dielectric layer disposed close to the first circuit layer. The first sub-dielectric layer has a higher hydrophobicity than the second sub-dielectric layer. By placing the first sub-dielectric layer close to the first circuit layer and increasing its hydrophobicity, the adhesion of the second sub-dielectric layer can be improved, reducing the risk of the fourth dielectric layer detaching and increasing product yield.

[0015] In one possible implementation, along the direction from the first chip to the second chip, the size of the portion of the sixth dielectric layer located within the first gap is equal to the size of the portion located within the second gap. That is, the sixth dielectric layer has a columnar structure. After forming the fourth dielectric layer, the surface of the fourth dielectric layer facing the fifth dielectric layer needs to be planar. After forming the fifth dielectric layer, the surface of the fifth dielectric layer facing the fourth dielectric layer needs to be planar to form the columnar structure of the sixth dielectric layer. Therefore, the thickness of both the fourth and fifth dielectric layers needs to be relatively thick, and a thicker dielectric layer can reduce the risk of breakage of the fourth and fifth dielectric layers during film deposition. Moreover, the sixth dielectric layer does not need to be deposited along the recessed surface trajectory, which can also reduce the risk of breakage during the deposition of the sixth dielectric layer, thereby improving the yield.

[0016] In one possible implementation, along the direction from the first chip to the second chip, the dimension of the end of the sixth dielectric layer located within the second gap is larger than the dimension of the end of the sixth dielectric layer located within the first gap. With a fixed size of the second gap, a larger dimension at the end of the sixth dielectric layer near the third bonding layer results in a thinner fourth and / or fifth dielectric layer. During chip fabrication, the substrate of the wafer is diced only after the dielectric film used to fabricate the fourth (or fifth) dielectric layer has been formed. Therefore, the dielectric film also needs to be diced at this point. The diced dielectric film needs to be subsequently filled by the sixth dielectric layer. Therefore, reducing the thickness of the fourth (or fifth) dielectric layer can, on the one hand, reduce the dielectric material wasted during dicing, thereby reducing material consumption and lowering costs. On the other hand, it can reduce the difficulty of dicing, thereby reducing dicing costs.

[0017] In one possible implementation, the fourth, fifth, and sixth dielectric layers are located on the side of the first bonding layer facing the first substrate; the first and second bonding layers are integrally formed. The integrally formed first and second bonding layers simplify the manufacturing process.

[0018] In one possible implementation, a fourth dielectric layer is located on the side of the first bonding layer facing the first substrate; a third gap exists between the first and second bonding layers, and a sixth dielectric layer extends into and fills the third gap. This is one possible structure.

[0019] In one possible implementation, the chip stack structure further includes a first interconnect layer and a second interconnect layer stacked between the first chip and the first bonding layer. The first interconnect layer is electrically connected to the first chip, and the second interconnect layer is electrically connected to the first bonding layer. A fourth dielectric layer also covers the side of the first interconnect layer and is attached to the second interconnect layer. One or more interconnect layers can be disposed between the first chip and the first bonding layer as needed to meet signal extraction requirements.

[0020] In one possible implementation, a third gap exists between the first and second bonding layers, and a fourth and sixth dielectric layers extend into the third gap, with the fourth dielectric layer also covering the side surface of the first bonding layer. Covering the side surface of the first bonding layer with the fourth dielectric layer prevents molten slag from randomly scattering from the side surface of the first bonding layer, thereby improving the bonding effect.

[0021] In one possible implementation, the size of the third gap is larger than the size of the second gap along the direction from the first chip to the second chip. Since the third gap is larger than the second gap, the third gap and the second gap can be formed asynchronously. Therefore, the slag generated during the formation of the second gap may not cover the third gap, allowing the slag to be kept away from the first and second bonding layers, thereby improving the bonding effect.

[0022] In one possible implementation, the chip stack structure further includes a first interconnect layer disposed between the first chip and the first bonding layer, the first interconnect layer being electrically connected to both the first chip and the first bonding layer; a fourth dielectric layer also covers the sides of the first interconnect layer. One or more interconnect layers may be disposed between the first chip and the first bonding layer as needed to meet signal extraction requirements.

[0023] In one possible implementation, the fifth dielectric layer is located on the side of the second bonding layer facing the second substrate. In the chip stacking structure, the structures of the fourth and fifth dielectric layers can be different, and the corresponding first and second chips can be different to meet different application requirements.

[0024] In some embodiments, the chip stack structure further includes a first slag located between the first circuit layer and the fourth dielectric layer, the first slag being flush with the surface of the fourth dielectric layer facing the third bonding layer. In this chip stack structure, the first slag being flush with the fourth dielectric layer prevents the first bonding layer from protruding. This improves the surface flatness of the first bonding layer, thereby enhancing the bonding effect of hybrid bonding.

[0025] In some embodiments, the chip stack structure further includes a second slag located between the second circuit layer and the fifth dielectric layer, the second slag being flush with the surface of the fifth dielectric layer facing the third bonding layer. In this chip stack structure, the second slag being flush with the fifth dielectric layer prevents the second bonding layer from protruding. This improves the surface flatness of the second bonding layer, thereby enhancing the bonding effect of hybrid bonding.

[0026] In one possible implementation, the chip stacking structure further includes a fourth chip and a fifth chip; the fourth chip is disposed on the side of the first chip away from the third chip and is electrically connected to the first chip; the fifth chip is disposed on the side of the second chip away from the third chip and is electrically connected to the first chip. One layer of the first chip and the second chip, and one layer of the fourth chip and the fifth chip can be stacked in the thickness direction of the chip stacking structure. Stacking multiple layers of chips can meet different performance requirements.

[0027] In one possible implementation, the chip stack structure further includes a fourth pad, which is located on the side of the third chip away from the third bonding layer and is electrically connected to the third chip. The chip stack structure can be a three-dimensional stacked chip including pads, which is electrically connected to the packaging substrate through the pads to achieve encapsulation with other chips.

[0028] A second aspect of this application provides a method for fabricating a chip stack structure. The method includes: forming multiple sets of first chips, a first bonding layer, a fourth dielectric layer, second chips, a second bonding layer, and a fifth dielectric layer; the first chip includes a first substrate and a first circuit layer disposed on one side of the first substrate; the first bonding layer is electrically connected to the first circuit layer, and the first bonding layer includes a first dielectric layer and a first pad, the first pad penetrating the first dielectric layer; the second chip includes a second substrate and a second circuit layer disposed on one side of the second substrate; the second bonding layer is electrically connected to the second circuit layer, and the second bonding layer includes a second dielectric layer and a second pad, the second pad penetrating the second dielectric layer; a first gap exists between the first substrate and the second substrate, and a second gap exists between the first circuit layer and the second circuit layer; the fourth dielectric layer covers the first circuit layer. The fifth dielectric layer covers the side of the second circuit layer; a third bonding layer is prepared in each first chip region of the first wafer; the first wafer includes multiple first chip regions defined by first dicing channels; the third bonding layer is electrically connected to the first wafer; the third bonding layer includes a third dielectric layer and multiple third pads, the multiple third pads respectively penetrate the third dielectric layer and are spaced apart; the first bonding layer and the second bonding layer in the same group are mixed and bonded with the same third bonding layer; the first dielectric layer and the second dielectric layer are respectively bonded to the third dielectric layer; the first pads and the second pads are electrically connected to different third pads; a sixth dielectric layer is formed; the sixth dielectric layer fills the first gap and extends to the space between the fourth dielectric layer and the fifth dielectric layer, filling the second gap; separation is performed along the first dicing channel to obtain a multiple chip stack structure.

[0029] The chip stacking structure fabrication method provided in this application requires the formation of a fourth dielectric layer covering the side of the first circuit layer and a fifth dielectric layer covering the side of the second circuit layer before the first chip and the second chip are bonded to the third bonding layer via the first bonding layer and the second bonding layer. The fourth dielectric layer and the fifth dielectric layer can cover the molten residue on the side of the circuit layer, preventing the molten residue from scattering, improving the cleanliness of the mixed bonding surface, thereby improving the bonding effect of the mixed bonding and increasing the product yield.

[0030] In one possible implementation, forming a first chip includes: providing a second wafer; the second wafer including a substrate and a circuit layer disposed on the substrate; laser-cutting the circuit layer to form a first circuit layer; and plasma-cutting the substrate to form a first substrate, thereby forming the first chip. This application uses laser cutting to cut the circuit layer and plasma cutting to cut the substrate, which solves the problem that plasma cutting cannot cut metal, necessitating a metal clearance design in the cutting area for the circuit layer if plasma cutting is used. The fabrication method of this application, by using laser cutting to cut the circuit layer, effectively creates a metal clearance area to accommodate the plasma cutting process. Therefore, the fabrication method is generally applicable to various circuit layer structures and has a wide range of applications. Furthermore, plasma cutting of the substrate provides higher flatness and cleanliness than rotary cutting, further adapting to the surface cleanliness requirements of hybrid bonding.

[0031] In one possible implementation, forming the fourth dielectric layer includes: forming a fourth dielectric base film before plasma cutting the substrate to form the first substrate; the fourth dielectric base film covering the groove between the first circuit layer and adjacent first circuit layers; removing the portion of the fourth dielectric base film above the first circuit layer using a grinding process to form the fourth dielectric film; and simultaneously plasma cutting the fourth dielectric film and the substrate to form the fourth dielectric layer. After forming the first circuit layer using laser cutting, the fourth dielectric base film is formed, and then processed using grinding and cutting processes to form the fourth dielectric layer. When the grinding process removes the fourth dielectric base film above the first circuit layer, it simultaneously removes the copper slag protrusions generated by laser cutting, making the surface of the subsequently formed first bonding layer flat, thereby improving the bonding effect of hybrid bonding. Furthermore, before cutting the substrate, a fourth dielectric film covering the sides of the first circuit layer is formed first. The fourth dielectric film covers the molten slag generated by laser cutting to prevent molten slag from falling and causing contamination. Furthermore, forming a fourth dielectric film before plasma cutting the substrate can cover the exposed metal structure during the cutting of the circuit base layer, reducing the risk of metal ions in the metal structure diffusing into the substrate after subsequent substrate cutting, and improving product yield.

[0032] In one possible implementation, forming multiple sets of first chips, a first bonding layer, a fourth dielectric layer, a second chip, a second bonding layer, a fifth dielectric layer, and a sixth dielectric layer includes: providing a second wafer; the second wafer includes a substrate and a circuit base layer disposed on the substrate, the circuit base layer being defined by a plurality of second chip regions by intersecting second dicing lines; using a laser cutting process to cut the circuit base layer along the second dicing lines to form a first circuit layer; forming a fourth dielectric film; using a plasma cutting process to cut the substrate and the fourth dielectric film along the second dicing lines to form a first substrate and a fourth dielectric layer to form the first chip; forming the second chip and the fifth dielectric layer; placing the first chip and the second chip on a carrier board and forming the sixth dielectric layer; the first circuit layer and the second circuit layer facing the carrier board; transferring the first chip and the second chip onto a support layer, exposing the first circuit layer and the second circuit layer, and forming an integral structure of the first bonding layer and the second bonding layer.

[0033] After dicing to form the first and second chips, they are transferred to a carrier substrate to form the sixth dielectric layer. During the chip transfer process, defective chips can be discarded, or defective chips can be placed as dummy chips in a special area and aligned with defective chips in the first wafer for subsequent bonding. This ensures that good chip positions in the first wafer correspond to good chips, avoiding bonding to defective chips, thus achieving a yield of the final bonded structure equal to the yield of the first wafer, thereby improving product yield. Furthermore, using a C2W process to bond the first and second chips to the carrier substrate, forming a structure after the sixth dielectric layer, resembles the wafer structure. Then, a W2W process is used to co-bond the first and second chips with the first wafer, resulting in a simple process with high yield.

[0034] In one possible implementation, forming multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers includes: providing a second wafer; the second wafer includes a substrate and a circuit base layer disposed on the substrate, the circuit base layer being defined by a plurality of second chip regions by intersecting second dicing lines; using a laser cutting process to cut the circuit base layer along the second dicing lines to form first circuit layers, with grooves between adjacent first circuit layers; forming a fourth dielectric film covering the surface of the grooves; forming a bonding base layer; the bonding base layer covering the fourth dielectric film and electrically connected to the circuit base layer; using a plasma cutting process to cut the bonding base layer, fourth dielectric film, and substrate along the second dicing lines to form the first bonding layer, fourth dielectric layer, and first substrate to form the first chip; and forming the second chip, fifth dielectric layer, and second bonding layer.

[0035] In the fabrication process, after the second wafer arrives, it is first laser-cut to form a fourth dielectric film covering the sides of the first circuit layer, and then the substrate is plasma-cut. The fourth dielectric film can cover the molten slag generated during laser cutting, preventing it from falling and causing contamination. Furthermore, the fourth dielectric film can cover the exposed metal structure during the cutting of the circuit base layer, reducing the risk of metal ions diffusing from the metal structure to the first substrate after subsequent substrate cutting, thus improving product yield. Moreover, laser cutting and plasma cutting are separate and not continuous operations, allowing for flexible and adaptable processes suitable for a wider range of product structures; C2W and W2W processes can be appropriately integrated and combined. Furthermore, the entire fabrication process involves fewer steps, lower costs, and higher efficiency.

[0036] In one possible implementation, forming multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers includes: providing a second wafer; the second wafer includes a substrate and a circuit substrate disposed on the substrate, the circuit substrate defining multiple second chip regions by intersecting second dicing lines; fabricating a bonding substrate electrically connected to the circuit substrate on the second wafer; using a laser cutting process to cut the bonding substrate and the circuit substrate along the second dicing lines to form a first bonding layer and a first circuit layer, with grooves between adjacent first circuit layers; forming a fourth dielectric film covering the surface of the grooves and the sidewalls of the first bonding layers; using a plasma cutting process to cut the fourth dielectric film and the substrate along the second dicing lines to form a fourth dielectric layer and a first substrate to form a first chip; and forming a second chip, a fifth dielectric layer, and a second bonding layer.

[0037] In the fabrication process, after the second wafer arrives, it is first laser-cut to form a fourth dielectric film covering the sides of the first circuit layer, and then the substrate is plasma-cut. The fourth dielectric film can cover the molten slag generated during laser cutting, preventing it from falling and causing contamination. Furthermore, the fourth dielectric film can cover the exposed metal structure during the cutting of the circuit base layer, reducing the risk of metal ions diffusing from the metal structure to the first substrate after subsequent substrate cutting, thus improving product yield. Moreover, laser cutting and plasma cutting are separate and not continuous operations, allowing for flexible and adaptable processes suitable for a wider range of product structures; C2W and W2W processes can be appropriately integrated. Furthermore, the entire fabrication process involves fewer steps, lower costs, and higher efficiency. Additionally, since the laser cutting and grinding of the fourth dielectric base film are performed after the bonding base layer is formed, the surface flatness after grinding has a smaller impact on the flatness of the bonding base layer. Therefore, the requirements for surface flatness after grinding can be reduced, lowering costs.

[0038] In one possible implementation, forming multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers includes: providing a second wafer; the second wafer includes a substrate and a circuit base layer disposed on the substrate, the circuit base layer being defined by intersecting second dicing lines that delineate multiple second chip regions. A bonding base layer electrically connected to the circuit base layer is fabricated on the second wafer. A plasma dicing process is used to cut the bonding base layer along the second dicing lines to form a first bonding layer. A laser dicing process is used to cut the circuit base layer along the second dicing lines to form a first circuit layer, with grooves between adjacent first circuit layers. A fourth dielectric film is formed, covering the surface of the grooves and the sides of the first bonding layers. A plasma dicing process is used to cut the fourth dielectric film and the substrate along the second dicing lines to form a fourth dielectric layer and a first substrate, thereby forming the first chip. A second chip, a fifth dielectric layer, and a second bonding layer are then formed.

[0039] During the fabrication process, after the second wafer arrives, a bonding base layer is formed, and a plasma cutting process is used to cut the bonding base layer to form the first bonding layer. Then, a laser cutting process is used to cut the circuit base layer to form the first circuit layer. At this point, the slag generated by the laser cutting process is mainly concentrated on the sides of the first circuit layer and does not completely cover the sides of the first bonding layer. The slag is relatively far from the first bonding layer, which reduces the impact of the slag on the flatness and cleanliness of the first bonding layer, thereby improving product yield. Furthermore, after the laser cutting of the circuit base layer forms slag, a fourth dielectric film is first formed to cover the sides of the first circuit layer before plasma cutting of the substrate. The fourth dielectric film can cover the slag generated by laser cutting, preventing slag from falling everywhere and causing contamination. Moreover, the fourth dielectric film can cover the exposed metal structure during the cutting of the circuit base layer, reducing the risk of metal ions from the metal structure diffusing into the first substrate after subsequent substrate cutting, further improving product yield. Furthermore, the laser cutting and plasma cutting are separate, not continuous operations, allowing for flexible and adaptable processes suitable for a wider range of product structures. Furthermore, the entire preparation process involves fewer steps, lower costs, and higher efficiency. Additionally, the laser cutting and grinding of the fourth dielectric substrate film are performed only after the bonding base layer is formed, minimizing the impact of the post-grinding surface smoothness on the overall smoothness of the bonding base layer. Therefore, the requirements for post-grinding surface smoothness can be reduced, thus lowering costs.

[0040] A third aspect of the present application provides a chip packaging structure, which includes a packaging substrate and a chip stacking structure according to any one of the first aspects; the chip stacking structure is disposed on the packaging substrate.

[0041] The chip packaging structure provided in the third aspect of the embodiments of this application includes the chip stacking structure of the first aspect, and its beneficial effects are the same as those of the chip stacking structure, which will not be repeated here.

[0042] A fourth aspect of this application provides an electronic device, which includes a circuit board and a chip packaging structure as described in the third aspect; the chip packaging structure is electrically connected to the circuit board. Attached Figure Description

[0043] Figure 1 is an architectural diagram of an electronic device provided in an embodiment of this application;

[0044] Figure 2 is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0045] Figure 3A is a schematic diagram of the chip fabrication process provided in an embodiment of this application;

[0046] Figure 3B is a schematic diagram of an uneven chip edge provided in an embodiment of this application;

[0047] Figure 4A is a schematic diagram of the fabrication process of a chip stacking structure provided in an embodiment of this application;

[0048] Figure 4B is a schematic diagram of a chip stacking structure provided in an embodiment of this application;

[0049] Figure 5 is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0050] Figure 6 is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0051] Figures 7A and 7B are schematic diagrams of another chip stacking structure provided in the embodiments of this application;

[0052] Figure 8 is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0053] Figure 9A is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0054] Figure 9B is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0055] Figure 9C is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0056] Figure 10 is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0057] Figures 11A and 11B are schematic diagrams of another chip stacking structure provided in the embodiments of this application;

[0058] Figure 12 is a schematic diagram of the fabrication process of a chip stacking structure provided in an embodiment of this application;

[0059] Figure 13 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiment of this application;

[0060] Figures 14A-14M are schematic diagrams illustrating the fabrication process of another chip stacking structure provided in the embodiments of this application;

[0061] Figure 15 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiment of this application;

[0062] Figures 16A-16K are schematic diagrams illustrating the fabrication process of another chip stacking structure provided in the embodiments of this application;

[0063] Figure 17 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiment of this application;

[0064] Figures 18A-18H are schematic diagrams illustrating the fabrication process of another chip stacking structure provided in the embodiments of this application;

[0065] Figure 19 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiment of this application;

[0066] Figures 20A-20I are schematic diagrams illustrating the fabrication process of another chip stacking structure provided in the embodiments of this application;

[0067] Figures 21A and 21B are schematic diagrams of another chip packaging structure provided in the embodiments of this application.

[0068] Reference numerals: 1-Electronic device; 2-Display module; 3-Middle frame; 4-Housing; 5-Cover plate; 10-Chip packaging structure; 100-Chip stacking structure; 21′-Substrate; 22′-Circuit base layer; 23′-Interconnect base layer; 24′-Bonding base layer; 211-First substrate; 212-Second substrate; 221-First circuit layer; 222-Second circuit layer; 231-First interconnect layer; 233-Third interconnect layer; 241-First bonding layer; 242-Second bonding layer; 26-Third bonding layer; 26′-Third bonding base layer; 27-Dielectric layer; 28-Support layer; 29-Connection layer; 31-First substrate; 31′-Base; 32-First circuit layer; 32′-Circuit base layer; 41-Second substrate; 42-Second circuit layer; 60-Interconnect layer; 61-First interconnect layer; 61′-First interconnect base layer; 62-Second interconnect layer; 62′-Second interconnect base layer; 63-Third interconnect layer; 64-Fourth interconnect layer; 65-Fifth interconnect layer; 66-Sixth interconnect layer; 67-Seventh interconnect layer; 70-Connection layer; 80-Support layer; 90-Cut protection layer; 91-Protective layer; 92-Sacrificial layer; 93-Protective layer; 94-Protective layer; 95-Protective layer; 96-Protective layer; W1 - First wafer; W2 - Second wafer; D1 - First chip; D2 - Second chip; D3 - Third chip; D4 - Fourth chip; D5 - Fifth chip; L1 - First dielectric layer; L2 - Second dielectric layer; L3 - Third dielectric layer; L4 - Fourth dielectric layer; L4″ - Fourth dielectric base film; L4′ - Fourth dielectric film; L41 - First sub-dielectric layer; L41′ - First sub-dielectric film; L41″ - First sub-dielectric base film; L42 - Second sub-dielectric layer; L42′ - Second sub-dielectric film; L42″ - Second sub-dielectric base film; L5 - Fifth chip Dielectric layer; L6 - Sixth dielectric layer; L61′ - Sixth sub-dielectric film; L61 - Sixth sub-dielectric layer; L62′ - Seventh sub-dielectric film; L62 - Seventh sub-dielectric layer; HB1 - First bonding layer; HB2 - Second bonding layer; HB3 - Third bonding layer; HB4 - Fourth bonding layer; HB5 - Fifth bonding layer; HB6 - Sixth bonding layer; TV - Through-hole; P - Pad; P1 - First pad; P2 - Second pad; P3 - Third pad; P4 - Fourth pad; B - Solder ball; PR - Photoresist coating; BV - Bonding hole; BL - Bonding wire; 200 - Sixth chip; 300 - Seventh chip; 500 - Adapter board; 600 - Redistribution layer; 700 - Packaging layer; 800 - Bridge chip. Detailed Implementation

[0069] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0070] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0071] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0072] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0073] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0074] This application provides an electronic device, which can be a terminal device with a display interface such as a mobile phone, television, monitor, tablet computer, or in-vehicle computer; a smart wearable device such as a smartwatch or smart bracelet; a communication device such as a server, network device, or base station; or a smart car. This application does not impose any special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following embodiments all use a mobile phone as an example for illustration.

[0075] Figure 1 is an architecture diagram of an electronic device provided in an embodiment of this application.

[0076] As shown in Figure 1, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing 4 (or battery cover, back cover) and a cover plate 5.

[0077] The display module 2 has a light-emitting side from which the display image can be seen and a back side opposite to the light-emitting side. The back side of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0078] Display module 2 can be a self-emissive display module such as an organic light-emitting diode (OLED) display module, an active-matrix organic light-emitting diode (AMOLED) display module, a mini organic light-emitting diode (Mini-OLED) display module, a micro light-emitting diode (Micro-LED) display module, a micro organic light-emitting diode (Micro-OLED) display module, or a quantum dot light-emitting diode (QLED) display module. In this case, display module 2 can be a rigid display module or a flexible display module.

[0079] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0080] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0081] The aforementioned electronic device 1 also includes a motherboard, a system-on-chip (SOC), a chip package structure 10, and other electronic components mounted on a PCB. The PCB is used to carry the aforementioned electronic components and to perform signal interaction with them.

[0082] Taking chip packaging structure as an example, the smaller the size of the chip packaging structure, the faster the internal signal transmission speed and the higher the bandwidth of electronic device 1, so as to improve the processing power and processing speed of cloud computing, artificial intelligence (AI) computing and servers.

[0083] Figure 2 is a schematic diagram of a chip packaging structure provided in an embodiment of this application.

[0084] In some embodiments, as shown in FIG2, the chip package structure 10 includes a first type of chip, a second type of chip, a package substrate, a package layer, pads, and solder balls. The first type of chip and the second type of chip are disposed on the same side of the package substrate, and the package layer covers the first type of chip and the second type of chip. The pads and solder balls are disposed on the side of the package substrate away from the first type of chip and the second type of chip. The chip package structure 10 is bonded to the PCB, for example, by solder balls.

[0085] The first and second types of chips can be chips of any function and any type. For example, the first type of chip is a chip stacking structure 100, such as a three-dimensional (3D) stacked chip. The resulting chip package structure is a three-dimensional package on package (3D POP package).

[0086] When interconnect pin pitch shrinks to 10µm, conventional microbump (uBump) processes face significant challenges. For applications with pitches smaller than 10µm, the industry commonly employs hybrid bonding (HB) for interconnection. Hybrid bonding uses planar soldering and interconnects via smaller pads to achieve higher vertical interconnect density, greater bandwidth, and lower power consumption. Therefore, in the chip stack structure 100, hybrid bonding can be used to bond chips to each other.

[0087] Figure 3A is a schematic diagram of the chip fabrication process provided in an embodiment of this application, and Figure 3B is a schematic diagram of an uneven chip edge provided in an embodiment of this application.

[0088] Before stacking and bonding chips together, the wafer needs to be diced to form the chips. As shown in Figure 3A, in some embodiments, the second wafer W2 includes a substrate 21′ and a circuit layer 22′. First, the circuit layer 22′ is diced using laser grooving (LG) technology, with the dicing depth exceeding the circuit layer 22′, thus dividing the circuit layer 22′ into multiple circuit layers 22. Then, the substrate 21′ is diced using a blade saw process to form a substrate 21, achieving chip separation and forming multiple chips.

[0089] However, laser cutting generates a significant amount of molten slag, and the cutting wheel produces a large amount of silicon chip spatter. As shown in Figure 3B, this results in uneven edges on the active surface of the chip, with molten slag accumulating and protruding.

[0090] Figure 4A is a schematic diagram of the fabrication process of a chip stacking structure provided in an embodiment of this application, and Figure 4B is a schematic diagram of a chip stacking structure provided in an embodiment of this application.

[0091] In some embodiments, as shown in FIG4A, the fabrication process of the chip stack structure 100 includes:

[0092] S10. A second wafer W2 is provided, the second wafer W2 including a substrate 21' and a circuit base layer 22'.

[0093] S11. An interconnect layer 23' and a bonding layer 24' are formed on the circuit layer 22'.

[0094] S12, forming a cutting protective layer 25, which covers the bonding base layer 24′.

[0095] S13. Laser cutting is performed on the interconnect base layer 23′, the bonding base layer 24′ and the circuit base layer 22′ to form the first interconnect layer 231, the third interconnect layer 233, the first bonding layer 241, the second bonding layer 242, the first circuit layer 221 and the second circuit layer 222.

[0096] S14. Cut the substrate 21′ with a cutting wheel.

[0097] S15. Thin the substrate 21′ to form a first substrate 211 and a second substrate 212, so as to form a first chip D1 including the first substrate 211 and a first circuit layer 221 and a second chip D2 including the second substrate 212 and the second circuit layer 222.

[0098] S16. A third bonding layer 26' is formed on the active surface of the first wafer W1, and the first bonding layer 241 and the second bonding layer 242 are mixed and bonded to the third bonding layer 26', for example, chip to wafer bonding is performed.

[0099] S17. Fill the gap between the first chip D1 and the second chip D2 to form a dielectric layer 27.

[0100] S18. A support layer 28 is placed on the back side of the first chip D1 and the second chip D2, a via TV is formed in the first wafer W1, and a pad P and a solder ball B are formed on the back side of the first wafer W1. For example, the support layer 28 is connected to the first chip D1 and the second chip D2 through a connection layer 29.

[0101] S19. The first wafer W1 is cut to form the chip stacking structure 100 shown in Figure 4B. The first chip D1 and the second chip D2 are bonded to the third chip D3 respectively.

[0102] After the bonding base layer 24' is formed, a protective layer 25 is formed, which serves as a protective layer for laser cutting and rotary cutting. Chip cutting is achieved through continuous laser cutting and rotary cutting operations. Then, after the hybrid bonding chip is mounted with the third bonding base layer 26', a dielectric layer 27 is deposited. As shown in Figure 4B, in the formed chip stack structure 100, slag and a rough, loose structure remain on the sidewalls of the first chip D1 and the second chip D2. The slag is covered by the dielectric layer 27 only after the first chip D1 and the second chip D2 are bonded to the first wafer W1, respectively. The formed dielectric layer 27 directly contacts the third bonding layer 26 and may contact the pads in the third bonding layer 26.

[0103] In the above scheme, after laser cutting the second wafer W2 to form the first chip D1 and the second chip D2, the first chip D1 and the second chip D2 have uneven surface edges and slag accumulation protrusions as shown in Figure 3B. This causes problems when bonding the first chip D1 and the second chip D2 with other chips or the first wafer W1, as the surface flatness of the mixed bonding plane cannot be guaranteed, affecting the bonding quality of the first chip D1 and the second chip D2 with the first wafer W1 and resulting in yield loss. Moreover, during the fabrication of the chip stack structure 100, the dielectric layer covering the sides of the first chip D1 and the second chip D2 is formed only after step S16 is performed to mix and bond the first chip D1 and the second chip D2 with the first wafer W1. At this time, metal ion diffusion is prone to problems.

[0104] Figure 5 is a schematic diagram of another chip stacking structure provided in an embodiment of this application.

[0105] This application provides a chip stacking structure 100, as shown in FIG5. The chip stacking structure 100 includes a first chip D1, a second chip D2, a third chip D3, a first bonding layer HB1, a second bonding layer HB2, a third bonding layer HB3, a fourth dielectric layer L4, a fifth dielectric layer L5, and a sixth dielectric layer L6.

[0106] The first chip D1 includes a first substrate 31 and a first circuit layer 32 disposed on one side of the first substrate 31. The first chip D1 can be, for example, a bare chip cut from a wafer, such as the portion from the front-end process to the back-end process pads, which can be understood as part of the first circuit layer 32 in this embodiment. That is, the active device portion of the front-end process and the interconnect traces and pads of the back-end process all belong to the structure of the first circuit layer 32. Alternatively, the first circuit layer 32 can be understood as the portion from the surface of the first substrate 31 to the aluminum pads on the surface of the first chip D1. The black trapezoidal filling pattern covered by the first interconnect layer 61 in FIG. 5 can be understood, for example, as the pads of the first chip D1. Even when the first chip D1 does not include pads, the active device portion of the front-end process and the interconnect traces of the back-end process belong to the structure of the first circuit layer 32.

[0107] The material of the first substrate 31 may include, for example, silicon wafers (Si), glass plates, etc., and this embodiment of the application does not limit this. The first chip D1 may be a chip with any function, for example, the first chip D1 includes a memory chip, a control chip, etc.

[0108] The first bonding layer HB1 is electrically connected to the first circuit layer 32. The first bonding layer HB1 includes a first dielectric layer L1 and a first pad P1, with the first pad P1 penetrating through the first dielectric layer L1. For example, the first pad P1 is electrically connected to a pad in the first circuit layer 32. The first bonding layer HB1 may, for example, include a plurality of spaced-apart first pads P1.

[0109] The material of the first dielectric layer L1 may include insulating dielectric materials such as silicon oxide and silicon nitride. The material of the first pad P1 may include metallic materials such as copper.

[0110] For example, the chip stack structure 100 also includes a first interconnect layer 61 and a second interconnect layer 62. The first interconnect layer 61 is electrically connected to the first circuit layer 32, and the second interconnect layer 62 is electrically connected to the first bonding layer HB1. The first interconnect layer 61 and the second interconnect layer 62 are electrically connected to achieve the electrical connection between the first bonding layer HB1 and the first circuit layer 32.

[0111] The first interconnect layer 61 may include interconnect lines and conductive posts, for example, to facilitate the transfer of signals in the first circuit layer 32. The first interconnect layer 61 may be electrically connected to the traces in the first circuit layer 32, or it may be electrically connected to the pads in the first circuit layer 32. Figure 5 is only one illustration.

[0112] The second interconnect layer 62, for example, protects metal pillars, electrically connecting the first circuit layer 32 to the first bonding layer HB1. This application embodiment does not limit the specific structure of the first interconnect layer 61 and the second interconnect layer 62. The chip stack structure 100 may not include interconnect layers, may include only one interconnect layer, or may include two or more interconnect layers. This application embodiment is merely illustrative and does not impose any limitations.

[0113] The second chip D2 includes a second substrate 41 and a second circuit layer 42 disposed on one side of the second substrate 41.

[0114] The second chip D2 can be, for example, a bare chip cut from a wafer, such as the portion from the front-end process to the back-end process pads, which can all be understood as part of the second circuit layer 42 in this embodiment. That is, the active device portion of the front-end process and the interconnect traces and pads of the back-end process all belong to the structure of the second circuit layer 42. Alternatively, the second circuit layer 42 can be understood as the portion from the surface of the second substrate 41 to the aluminum pads on the surface of the second chip D2. The black trapezoidal fill pattern covered by the third interconnect layer 63 in FIG5 can be understood as, for example, the pads of the second chip D2.

[0115] The second chip D2 can be a chip with any function; for example, the second chip D2 may include a memory chip, a control chip, etc. The first chip D1 and the second chip D2 can be chips with the same function, or they can be chips with different functions.

[0116] The second bonding layer HB2 is electrically connected to the second circuit layer 42. The second bonding layer HB2 includes a second dielectric layer L2 and a second pad P2, with the second pad P2 penetrating through the second dielectric layer L2. For example, the second pad P2 is electrically connected to a pad in the second circuit layer 42. The second bonding layer HB2 may, for example, include a plurality of spaced-apart second pads P2.

[0117] The material of the second dielectric layer L2 includes insulating dielectric materials such as silicon oxide and silicon nitride. The material of the second pad P2 includes metallic materials such as copper.

[0118] In some embodiments, the first bonding layer HB1 and the second bonding layer HN2 are, for example, integrally formed structures and are formed simultaneously in the same manufacturing process.

[0119] For example, the chip stack structure 100 also includes a third interconnect layer 63 and a fourth interconnect layer 64. The third interconnect layer 63 is electrically connected to the second circuit layer 42, and the fourth interconnect layer 64 is electrically connected to the second bonding layer HB2. The third interconnect layer 63 and the fourth interconnect layer 64 are electrically connected to achieve the electrical connection between the second bonding layer HB2 and the second circuit layer 42.

[0120] The third interconnect layer 63 may include interconnect lines and conductive posts, for example, to transfer signals in the second circuit layer 42. The third interconnect layer 63 may be electrically connected to the traces in the second circuit layer 42, or it may be electrically connected to the pads in the second circuit layer 42. Figure 5 is only one illustration.

[0121] The fourth interconnect layer 64, for example, protects metal pillars, electrically connecting the second circuit layer 42 to the second bonding layer HB2. This application embodiment does not limit the specific structure of the third interconnect layer 63 and the fourth interconnect layer 64. The chip stack structure 100 may not include interconnect layers, may include only one interconnect layer, or may include two or more interconnect layers. This application embodiment is merely illustrative and does not impose any limitations.

[0122] The third bonding layer HB3 is electrically connected to the third chip D3. The third bonding layer HB3 includes a third dielectric layer L3 and multiple third pads P3. The multiple third pads P3 pass through the third dielectric layer L3 and are spaced apart.

[0123] The material of the third dielectric layer L3 may include insulating dielectric materials such as silicon oxide and silicon nitride. The material of the third pad P3 may include metallic materials such as copper.

[0124] The first bonding layer HB1 and the third bonding layer HB3 are mixed and bonded to achieve the bonding of the first chip D1 and the third chip D3. The second bonding layer HB2 is also mixed and bonded with the third bonding layer HB3 to achieve the bonding of the second chip D2 and the third chip D3.

[0125] For example, the first dielectric layer L1 and the second dielectric layer L2 are respectively bonded to the third dielectric layer L3, and the first pad P1 and the second pad P2 are electrically connected to different third pads P3. For instance, the first dielectric layer L1 and the second dielectric layer L2 are fused bonded to the third dielectric layer L3, and the pads P1 and P2 are atomically diffuse bonded to different third pads P3.

[0126] After the first chip D1 and the second chip D2 are bonded to the third chip D3 respectively, there is a first gap between the first substrate 31 and the second substrate 41, and a second gap between the first circuit layer 32 and the second circuit layer 42.

[0127] A fourth dielectric layer L4 is disposed within the second gap, covering the side surface of the first circuit layer 32. For example, the fourth dielectric layer L4 covers the slag left during wafer dicing.

[0128] The fifth dielectric layer L5 is disposed within the second gap, covering the side surface of the second circuit layer 42. For example, the fifth dielectric layer L5 covers the slag left during wafer dicing.

[0129] The sixth dielectric layer L6 fills the first gap and extends between the fourth dielectric layer L4 and the fifth dielectric layer L5, filling the second gap. For example, the fourth dielectric layer L4, the fifth dielectric layer L5, and the sixth dielectric layer L6 together fill the second gap. The sixth dielectric layer L6 fills the first gap alone.

[0130] The dielectric layers filling the first and second gaps are different.

[0131] The chip stacking structure provided in this application embodiment includes a fourth dielectric layer L4 and a fifth dielectric layer L5 between the first chip D1 and the second chip D2, in addition to a sixth dielectric layer L6 used to fill the gap. The fourth dielectric layer L4 covers the side of the first circuit layer 32, and the fifth dielectric layer L5 covers the side of the second circuit layer 42. The fourth dielectric layer L4 and the fifth dielectric layer L5 can cover the molten slag residue on the side of the circuit layer, preventing molten slag residue from scattering, improving the cleanliness of the bonding surfaces of the first bonding layer HB1 and the second bonding layer HB2 with the third bonding layer HB3, thereby improving the bonding effect of the first dielectric layer L1 and the second dielectric layer L2 with the third dielectric layer L3, as well as the electrical connection effect of the first pad P1 and the second pad P2 with the third pad P3, that is, improving the bonding effect of hybrid bonding, so as to improve the product yield. Furthermore, if the bonding yield of the first chip D1, the second chip D2, and the third chip D3 is guaranteed, the bonding chips can be stacked and bonded on the back of the first chip D1 and the second chip D2 in the same way, which is beneficial to realizing a high-density three-dimensional stacked structure.

[0132] In some embodiments, the surface of the first bonding layer HB1 facing the third bonding layer HB3 is flat. For example, the flatness of the surface of the first bonding layer HB1 facing the third bonding layer HB3 is less than or equal to 0.2 μm. For example, the flatness of the surface of the first bonding layer HB1 facing the third bonding layer HB3 is 0.2 μm, 0.18 μm, 0.15 μm, 0.13 μm, 0.1 μm, 0.08 μm, 0.05 μm, etc.

[0133] In some embodiments, the surface of the second bonding layer HB2 facing the third bonding layer HB3 is flat. For example, the flatness of the surface of the second bonding layer HB2 facing the third bonding layer HB3 is less than or equal to 0.2 μm. For instance, the flatness of the surface of the second bonding layer HB2 facing the third bonding layer HB3 is 0.2 μm, 0.18 μm, 0.15 μm, 0.13 μm, 0.1 μm, 0.08 μm, 0.05 μm, etc.

[0134] Flatness refers to the degree to which the surface of an object or a specific plane deviates geometrically from an ideal plane. It is a quantitative description of the smoothness and evenness of an object's surface. Flatness is an indicator used to measure the difference between an actual surface and an ideal plane; the smaller the difference, the higher the flatness. The greater the difference, the lower the flatness, and the more pronounced the unevenness of the surface.

[0135] In the chip stacking structure 100, the surfaces of the first bonding layer HB1 and the second bonding layer HB2 are flat and without obvious protrusions, which can improve the adhesion between the first bonding layer HB1 and the second bonding layer HN2 and the surface of the third bonding layer HB3, thereby improving the bonding effect between the first bonding layer HB1 and the second bonding layer HN2 and the third bonding layer HB3.

[0136] In some embodiments, as shown in FIG5, the dimension of one end of the sixth dielectric layer L6 located within the second gap is larger than the dimension of one end of the sixth dielectric layer L6 located within the first gap. For example, the sixth dielectric layer has a funnel-shaped structure.

[0137] For example, the dimensions of the fourth dielectric layer L4 and / or the fifth dielectric layer L5 are equal at each location, and the remaining portion within the second gap is to be filled by the sixth dielectric layer L6. The dimension of the second end of the sixth dielectric layer L6 within the second gap is larger than the dimension of the first end of the sixth dielectric layer L6 within the first gap. For example, along the direction from the first chip D1 to the second chip D2, the dimension of the second end of the sixth dielectric layer L6 within the second gap is larger than the dimension of the first end of the sixth dielectric layer L6 within the first gap.

[0138] With the second gap size fixed, the sixth dielectric layer L6 has a larger dimension at the end near the third bonding layer HB3, resulting in a thinner fourth dielectric layer L4 and / or fifth dielectric layer L5. During chip fabrication, the wafer substrate is diced only after the dielectric film used to fabricate the fourth dielectric layer L4 (or fifth dielectric layer L5) is formed. Therefore, the dielectric film also needs to be diced at this point. The diced dielectric film needs to be refilled by the sixth dielectric layer L6. Therefore, reducing the thickness of the fourth dielectric layer L4 (or fifth dielectric layer L5) can reduce the dielectric material wasted during dicing, thus reducing material consumption and costs. Furthermore, it can reduce the difficulty of dicing, thereby reducing dicing costs.

[0139] Figure 6 is a schematic diagram of another chip stacking structure provided in an embodiment of this application.

[0140] In other embodiments, as shown in FIG6, the dimensions of the portion of the sixth dielectric layer L6 located within the first gap and the portion located within the second gap are equal along the direction from the first chip D1 to the second chip D2. For example, the sixth dielectric layer L6 has a columnar structure.

[0141] For example, the fourth dielectric layer L4 and the fifth dielectric layer L5 are disposed after the second gap, and the gap size of the remaining portion of the second gap is the same as the gap size of the first gap. Along the direction from the first chip D1 to the second chip D2, the size of the sixth dielectric layer L6 within the second gap is equal to the size of the sixth dielectric layer L6 within the first gap.

[0142] After forming the fourth dielectric layer L4, the surface of the fourth dielectric layer L4 facing the fifth dielectric layer L5 needs to be planar. Similarly, after forming the fifth dielectric layer L5, the surface of the fifth dielectric layer L5 facing the fourth dielectric layer L4 needs to be planar to form the columnar structure of the sixth dielectric layer L6. Therefore, both the fourth and fifth dielectric layers L4 and L5 need to be relatively thick. Thicker dielectric layers reduce the risk of breakage during film deposition. Furthermore, the sixth dielectric layer L6 does not need to be deposited along the recessed surface, further reducing the risk of breakage during film deposition and thus improving yield.

[0143] Since the second gap contains a fourth dielectric layer L4, a fifth dielectric layer L5, and a sixth dielectric layer L6, the size of the sixth dielectric layer L6 is smaller than the size of the second gap along the direction from the first chip D1 to the second chip D2.

[0144] Figures 7A and 7B are schematic diagrams of another chip stacking structure provided in the embodiments of this application.

[0145] In some embodiments, as shown in Figures 7A and 7B, the fourth dielectric layer L4 includes a first sub-dielectric layer L41 and a second sub-dielectric layer L42. For example, the first sub-dielectric layer L41 is disposed near the first circuit layer 32, and the second sub-dielectric layer L42 is disposed near the sixth dielectric layer L6.

[0146] For example, the density of the first sub-dielectric layer L41 is greater than that of the second sub-dielectric layer L42. Density refers to the compactness and uniformity of the internal structure of a dielectric material.

[0147] The first sub-dielectric layer L41 is disposed close to the first circuit layer 32, for example, directly covering the slag on the side of the first circuit layer 32. By increasing the density of the first sub-dielectric layer L41, the anti-diffusion capability of the first sub-dielectric layer L41 can be improved, reducing the probability of diffusion of exposed metal during the cutting process to form the first circuit layer 32, and improving product yield.

[0148] Alternatively, for example, the first sub-dielectric layer L41 is more hydrophobic than the second sub-dielectric layer L42. Hydrophobicity refers to the property of a material to be either not wetted by water or to repel water.

[0149] The first sub-dielectric layer L41 is disposed close to the first circuit layer 32. By improving the hydrophobicity of the first sub-dielectric layer L41, the adhesion of the second sub-dielectric layer L42 can be improved, the risk of the fourth dielectric layer L4 falling off can be reduced, and the product yield can be improved.

[0150] In some embodiments, the fourth dielectric layer L4 further includes a third sub-dielectric layer disposed between the second sub-dielectric layer L42 and the sixth dielectric layer L6. For example, the surface of the third sub-dielectric layer facing the sixth dielectric layer L6 may be perpendicular to the third bonding layer HB3, so that the surface of the fourth dielectric layer L4 facing the sixth dielectric layer L6 is planar.

[0151] The third dielectric layer mainly serves to fill the gaps. It can be made of lower-cost materials, which can reduce costs on the one hand and improve product yield on the other, thus solving the problem of the incompatibility between yield and cost.

[0152] In some embodiments, the fifth dielectric layer L5 includes a fourth sub-dielectric layer L51 and a fifth sub-dielectric layer L52. For example, the fourth sub-dielectric layer L51 is disposed near the second circuit layer 42, and the fifth sub-dielectric layer L52 is disposed near the sixth dielectric layer L6.

[0153] For example, the density of the fourth sub-dielectric layer L51 is greater than that of the fifth sub-dielectric layer L52.

[0154] The fourth sub-dielectric layer L51 is disposed close to the second circuit layer 42, for example, directly covering the slag on the side of the second circuit layer 42. By increasing the density of the fourth sub-dielectric layer L51, the anti-diffusion capability of the fourth sub-dielectric layer L51 can be improved, reducing the probability of diffusion of exposed metal when cutting to form the second circuit layer 42, and improving product yield.

[0155] Alternatively, for example, the fourth sub-dielectric layer L51 is more hydrophobic than the fifth sub-dielectric layer L52.

[0156] In some embodiments, the sixth dielectric layer L6 includes a sixth sub-dielectric layer L61 and a seventh sub-dielectric layer L62. For example, the sixth sub-dielectric layer L61 is disposed close to the fourth dielectric layer L4, and the seventh sub-dielectric layer L62 is disposed away from the fourth dielectric layer L4. For example, the sixth sub-dielectric layer L61 forms a groove, and the seventh sub-dielectric layer L62 is disposed within the groove.

[0157] For example, the compactness of the sixth sub-dielectric layer L61 is greater than that of the seventh sub-dielectric layer L62. Or, for example, the hydrophobicity of the sixth sub-dielectric layer L61 is greater than that of the seventh sub-dielectric layer L62.

[0158] In some embodiments, as shown in FIG7A, the third chip D3 includes a third substrate 51 and a third circuit layer 52. The third circuit layer 52 is disposed on the third substrate 51, and the side where the third circuit layer 52 is located is the active side of the third chip D3. The third circuit layer 52 is bonded to the third bonding layer HB3.

[0159] The third chip D3 also includes a through-hole TV, which penetrates the third substrate 51 and is electrically connected to the third circuit layer 52. For example, the through-hole TV is a silicon via or a glass via, which is related to the material of the third substrate 51.

[0160] The chip stack structure 100 also includes a fourth pad P4, which is located on the side of the third chip D3 away from the third bonding layer HB3, and is electrically connected to the third chip D3. For example, the fourth pad P4 is electrically connected to the third circuit layer 52 through a via TV. The chip stack structure 100 can be packaged on a package substrate together with other chips via the fourth pad P4.

[0161] In some embodiments, the chip stack structure 100 further includes a fifth interconnect layer 65, which is disposed between the third chip D3 and the fourth pad P4. The fifth interconnect layer 65 is used, for example, to implement the electrical connection between the fourth pad P4 and the via TV. The fifth interconnect layer 65 may be, for example, a re-distribution layer (RDL).

[0162] In some embodiments, as shown in FIG7B, the chip stack structure 100 further includes solder balls B, which are electrically connected to the fourth pad P4. That is, the chip stack structure 100 provided in this application embodiment may include solder balls B or may not include pad B.

[0163] In some embodiments, the chip stack structure 100 further includes a support layer 80, and a connection layer 70 is disposed between the support layer 80 and the first chip D1 and the second chip D2.

[0164] In some embodiments, the fourth dielectric layer L4, the fifth dielectric layer L5, and the sixth dielectric layer L6 are located on the side of the first bonding layer HB1 facing the first substrate 31, and the first bonding layer HB1 and the second bonding layer HB2 are integrally formed structures.

[0165] For example, the fourth dielectric layer L4, the fifth dielectric layer L5, and the sixth dielectric layer L6 are formed first, and then the first bonding layer HB1 and the second bonding layer HB2 are formed together.

[0166] For example, the chip stack structure 100 also includes a first interconnect layer 61 and a second interconnect layer 62 stacked between the first chip D1 and the first bonding layer HB1, and a fourth dielectric layer L4 also covers the side of the first interconnect layer 61 and is attached to the second interconnect layer 62.

[0167] For example, the chip stack structure 100 also includes a third interconnect layer 63 and a fourth interconnect layer 64 stacked between the second chip D2 and the second bonding layer HB2, and a fifth dielectric layer L5 also covers the side of the third interconnect layer 63 and is attached to the fourth interconnect layer 64.

[0168] The second interconnect layer 62 and the fourth interconnect layer 64 can, for example, be integrally formed and formed simultaneously.

[0169] Figure 8 is a schematic diagram of another chip stacking structure provided in the embodiments of this application.

[0170] In some embodiments, as shown in FIG8, a fourth dielectric layer L4 is located on the side of the first bonding layer HB1 facing the first substrate 31, a third gap is formed between the first bonding layer HB1 and the second bonding layer HB2, and a sixth dielectric layer L6 extends to and fills the third gap. For example, the fourth dielectric layer L4 is formed before the first bonding layer HB1 is formed. The sixth dielectric layer L6 is formed after the first bonding layer HB1 is formed.

[0171] The fifth dielectric layer L5 can also be located on the side of the second bonding layer HB2 facing the second substrate 41. For example, the fifth dielectric layer L5 has been formed before the second bonding layer HB2 is formed.

[0172] For example, the chip stack structure 100 also includes a first interconnect layer 61 and a second interconnect layer 62 stacked between the first chip D1 and the first bonding layer HB1, and a fourth dielectric layer L4 covering the side of the first interconnect layer 61 and adhering to the second interconnect layer 62. For example, the fourth dielectric layer L4 is formed before the second interconnect layer 62 is formed.

[0173] Figures 9A-9C are schematic diagrams of another chip stacking structure provided in the embodiments of this application.

[0174] In some embodiments, as shown in FIG9A, a third gap is provided between the first bonding layer HB1 and the second bonding layer HB2, and the fourth dielectric layer L4 and the sixth dielectric layer L6 extend to the third gap respectively, with the fourth dielectric layer L4 also covering the side surface of the first bonding layer HB1. For example, the fourth dielectric layer L4 and the sixth dielectric layer L6 are formed after the first bonding layer HB1 is formed.

[0175] For example, as shown in Figure 9A, the chip stack structure 100 further includes a first interconnect layer 61 disposed between the first chip D1 and the first bonding layer HB1, the first interconnect layer 61 being electrically connected to both the first chip D1 and the first bonding layer HB1. A fourth dielectric layer L4 also covers the sides of the first interconnect layer 61.

[0176] Alternatively, as shown in Figure 9B, the chip stack structure 100 further includes a first interconnect layer 61 and a second interconnect layer 62 stacked between the first chip D1 and the first bonding layer HB1, and a fourth dielectric layer L4 also covers the sides of the first interconnect layer 61 and the sides of the second interconnect layer 62.

[0177] Optionally, the fifth dielectric layer L5 may also extend to the third gap, and the fifth dielectric layer L5 may also cover the side of the second bonding layer HB2. For example, the fifth dielectric layer L5 may be formed after the second bonding layer HB2 is formed.

[0178] For example, the chip stack structure 100 also includes a third interconnect layer 63 and a fourth interconnect layer 64 stacked between the second chip D2 and the second bonding layer HB2, and a fifth dielectric layer L5 also covers the sides of the third interconnect layer 63 and the sides of the fourth interconnect layer 64.

[0179] In some embodiments, as shown in FIG9C, along the direction from the first chip D1 to the second chip D2, the size d3 of the third gap is greater than the size d2 of the second gap.

[0180] Alternatively, this can be understood as follows: the dimension d3 from the side of the first bonding layer HB1 to the side of the second bonding layer HB2 is greater than the dimension d2 from the side of the first circuit layer 32 to the side of the second circuit layer 42. It can also be understood as follows: the sum of the dimensions of the portions of the fourth dielectric layer L4, the fifth dielectric layer L5, and the sixth dielectric layer L6 located within the third gap is greater than the sum of the dimensions of the portions of the fourth dielectric layer L4, the fifth dielectric layer L5, and the sixth dielectric layer L6 located within the second gap.

[0181] For example, at this time, the slag covers the side of the first circuit layer 32 and the side of the second circuit layer 42, but does not cover the side of the first bonding layer HB1 and the side of the second bonding layer HB2.

[0182] Figure 10 is a schematic diagram of another chip stacking structure provided in the embodiments of this application.

[0183] Alternatively, as shown in Figure 10, the fifth dielectric layer L5 is located on the side of the second bonding layer HB2 facing the second substrate 41.

[0184] For example, the chip stack structure 100 also includes a third interconnect layer 63 and a fourth interconnect layer 64 stacked between the second chip D2 and the second bonding layer HB2, and a fifth dielectric layer L5 also covers the side of the third interconnect layer 63 and is attached to the fourth interconnect layer 64.

[0185] In the chip stack structure 100, the structure of the fourth dielectric layer L4 and the structure of the fifth dielectric layer L5 can be the same or different.

[0186] In some embodiments, the chip stack structure 100 further includes a first slag, which is located between the first circuit layer 32 and the fourth dielectric layer L4, and the first slag is flush with the surface of the fourth dielectric layer L4 facing the third bonding layer HB3.

[0187] In some embodiments, the chip stack structure 100 further includes a second slag located between the second circuit layer 42 and the fifth dielectric layer L5, with the second slag flush with the surface of the fifth dielectric layer L5 facing the third bonding layer HB3.

[0188] In the chip stack structure 100, the first molten slag is flush with the fourth dielectric layer L4, and the first molten slag will not cause the first bonding layer HB1 to protrude. The second molten slag is flush with the fifth dielectric layer L5, and the second molten slag will not cause the second bonding layer HB2 to protrude. This can improve the surface flatness of the first bonding layer HB1 and the second bonding layer HB2, thereby improving the bonding effect of hybrid bonding.

[0189] Figures 11A and 11B are schematic diagrams of another chip stacking structure provided in the embodiments of this application.

[0190] Based on any of the above structures, in some embodiments, as shown in FIG11A, the chip stack structure 100 further includes a fourth chip D4 and a fifth chip D5, with a fourth gap between the fourth chip D4 and the fifth chip D5. The types of the fourth chip D4, the fifth chip D5, the first chip D1, and the second chip D2 may be the same or different. The dimensions of the fourth chip D4, the fifth chip D5, the first chip D1, and the second chip D2 may be the same or different. For example, the fourth chip D4 and the fifth chip D5 are disposed on the support layer 80 facing the first chip D1 and the second chip D2.

[0191] The fourth bonding layer HB4 is bonded to the fourth chip D4. For example, one or more interconnect layers 60 may be disposed between the fourth bonding layer HB4 and the fourth chip D4. The structure of the fourth bonding layer HB4 and the interconnect layer 60 can be referred to the above description of the first bonding layer HB1 and the fourth chip D4.

[0192] The fifth bonding layer HB5 is bonded to the fifth chip D5. For example, one or more interconnect layers 60 may be disposed between the fifth bonding layer HB5 and the fifth chip D5. The structure of the fifth bonding layer HB5 and the interconnect layer 60 can be referred to the above description of the second bonding layer HB2 and the second chip D2.

[0193] The sixth bonding layer HB6 is located on the side of the first chip D1 and the second chip D2 away from the third chip D3, and is bonded to the first chip D1, the second chip D2, the fourth bonding layer HB4, and the fifth bonding layer HB5, respectively.

[0194] For example, a sixth interconnect layer 66 is provided between the sixth bonding layer HB6 and the first chip D1 and the second chip D2. Through holes TV are respectively provided in the first substrate 31 of the first chip D1 and the second substrate 41 of the second chip D2. The sixth bonding layer HB6 is electrically connected to the first circuit layer 32 of the first chip D1 and the second circuit layer 42 of the second chip D2 through the sixth interconnect layer 66 and through the through holes TV.

[0195] The chip stack structure 100 also includes a filling portion that fills a fourth gap between the fourth chip D4 and the fifth chip D5. The filling portion includes, for example, a fourth dielectric layer L4, a fifth dielectric layer L5, and a sixth dielectric layer L6.

[0196] In some embodiments, the chip stack structure 100 may further include a via TV penetrating the sixth dielectric layer L6 to enable electrical connection between the fourth chip D4 and / or the fifth chip D5 and the third chip D3.

[0197] In some embodiments, as shown in FIG11B, the chip stacking structure 100 can stack multiple layers of chips, and adjacent chips in different layers are provided with filling portions. The structures of the filling portions in different layers can be the same or different.

[0198] By stacking multiple layers of chips in the thickness direction of the chip stack structure 100, different performance requirements can be met. For example, stacking multiple layers of memory chips can increase the storage capacity of the chip stack structure 100. Or, for example, stacking multiple layers of processing chips can increase the processing power of the chip stack structure 100.

[0199] Figure 12 is a schematic diagram of the fabrication process of a chip stacking structure provided in an embodiment of this application.

[0200] This application embodiment also provides a method for fabricating a chip stacking structure, as shown in FIG12, the fabrication method including:

[0201] S21, forming multiple sets of first chip D1, first bonding layer HB1, fourth dielectric layer L4, second chip D2, second bonding layer HB2 and fifth dielectric layer L5.

[0202] The first chip D1, the first bonding layer HB1, the fourth dielectric layer L4, the second chip D2, the second bonding layer HB2, and the fifth dielectric layer L5 in the same group will be subsequently cut into the same chip stack structure 100.

[0203] S22. Prepare a third bonding layer HB3 in each first chip region of the first wafer W1.

[0204] The first wafer W1 includes multiple first chip regions defined by first dicing channels that intersect horizontally and vertically, and the third bonding layer HB3 in the multiple first chip regions can be a monolithic structure.

[0205] S23. Bond the first bonding layer HB1 and the second bonding layer HB2 in the same group to the same third bonding layer HB3.

[0206] Step S23 can bond multiple sets of first chips D1 and second chips D2 to the first wafer W1. The bonding of multiple sets of first chips D1 and second chips D2 to the first wafer W1 can be understood as realizing wafer-to-wafer (W2W) hybrid bonding.

[0207] S24, forming the sixth dielectric layer L6.

[0208] After the sixth dielectric layer L6 is fabricated, the gap between the first chip D1 and the second chip D2 is completely filled. Subsequently, metal addition layers of the top bonding pad can be fabricated through wafer-level packaging to achieve bonding between the chip stack structure and the packaging substrate.

[0209] S25. Separate along the first cutting path to obtain multiple chip stacked structures 100.

[0210] The chip stacking structure fabrication method provided in this application requires the formation of a fourth dielectric layer L4 covering the side of the first circuit layer 32 and a fifth dielectric layer L5 covering the side of the second circuit layer 42 before the first chip D1 and the second chip D2 are bonded to the third bonding layer HB3 via the first bonding layer HB1 and the second bonding layer HB2. The fourth dielectric layer L4 and the fifth dielectric layer L5 can cover the molten residue on the side of the circuit layer, preventing the molten residue from scattering, improving the cleanliness of the mixed bonding surface, thereby improving the bonding effect of the mixed bonding and increasing the product yield.

[0211] In some embodiments, forming the first chip D1 includes:

[0212] A second wafer is provided, the second wafer including a substrate and a circuit layer disposed on the substrate.

[0213] The circuit substrate is laser-cut to form the first circuit layer 32, and the substrate is plasma-cut to form the first substrate 31.

[0214] This application employs laser cutting to cut the circuit substrate and plasma cutting to cut the base layer. This solves the problem that plasma cutting cannot cut metal, necessitating a metal clearance design in the cutting area for the circuit substrate if plasma cutting is used. The fabrication method of this application, by using laser cutting to cut the circuit substrate, effectively creates a metal clearance area to accommodate plasma cutting. Therefore, this fabrication method is universally applicable to various circuit substrate structures and has a wide range of uses. Furthermore, plasma cutting of the base layer provides higher flatness and cleanliness than rotary cutting, further adapting to the surface cleanliness requirements of hybrid bonding.

[0215] In some embodiments, a fourth dielectric layer L4 is formed, including:

[0216] A fourth dielectric base film is formed, which covers the groove between the first circuit layer and the adjacent first circuit layer.

[0217] The portion of the fourth dielectric base film located above the first circuit layer is removed by a grinding process to form the fourth dielectric film.

[0218] The fourth dielectric film is cut to form the fourth dielectric layer L4.

[0219] After forming the first circuit layer 32 by laser cutting, a fourth dielectric base film is formed, and then the fourth dielectric layer L4 is formed by grinding and cutting processes. When the grinding process removes the fourth dielectric base film located above the first circuit layer 32, the copper slag protrusions generated by laser cutting are removed simultaneously, so that the surface of the subsequently formed first bonding layer HB1 is flat, thereby improving the bonding effect of hybrid bonding.

[0220] In some embodiments, a fourth dielectric base film is formed before plasma cutting of the substrate to form the first substrate 31. Then, a fourth dielectric film is formed. Subsequently, the substrate and the fourth dielectric film are simultaneously plasma cut to form the first substrate 31 and the fourth dielectric layer L4.

[0221] The chip stacking structure fabrication method provided in this application requires forming a fourth dielectric film covering the sides of the first circuit layer 32 before cutting the substrate. The fourth dielectric film covers the molten slag generated during laser cutting to prevent it from falling and causing contamination. Furthermore, forming the fourth dielectric film before plasma cutting the substrate can cover the exposed metal structure during the cutting of the circuit base layer 32', reducing the risk of metal ions diffusing from the metal structure to the first substrate 31 after subsequent substrate cutting, thus improving product yield.

[0222] The following examples illustrate the method for fabricating the chip stacking structure provided in the embodiments of this application.

[0223] Figure 13 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiments of this application; Figures 14A-14M are schematic diagrams of the fabrication process of another chip stacking structure provided in the embodiments of this application.

[0224] In some embodiments, as shown in FIG13, the method for fabricating a chip stacking structure includes:

[0225] A sixth dielectric layer L6 is formed, along with multiple sets of first chips D1, first bonding layer HB1, fourth dielectric layer L4, second chips D2, second bonding layer HB2, and fifth dielectric layer L5.

[0226] For example, the steps above include:

[0227] S211, as shown in Figure 14A, a second wafer W2 is provided. The second wafer W2 includes a substrate 31' and a circuit base layer 32' disposed on the substrate 31'. The circuit base layer 32' is defined by a plurality of second chip regions by intersecting second dicing channels.

[0228] S212. As shown in Figure 14B, the circuit base layer 32′ is cut along the second cutting path using laser cutting technology to form the first circuit layer 32.

[0229] For example, step S212 includes:

[0230] S2121, Form the first interconnection base layer 61′.

[0231] For example, a dielectric film layer is deposited using chemical vapor deposition (CVD), followed by processes such as copper electroplating followed by chemical mechanical polishing (CMP) to form vias, wiring layers, or pads, thereby forming the interconnect substrate 61'. The first interconnect substrate 61' can also be referred to as a metal addition layer. The dielectric film layer can include one or more of silicon oxide (SiO2), silicon nitride (SiN), and silicon carbonitride (SiCN) materials. For example, the first interconnect substrate 61' includes bonding vias (BV) and bonding lines (BL).

[0232] The first interconnect base layer 61' can be electrically connected to the pads in the circuit base layer 32', and the first interconnect base layer 61' can also be electrically connected to the traces in the circuit base layer 32'. Figure 14B is only one illustration.

[0233] S2122, Form a cutting protective layer 90.

[0234] For example, the cutting protective layer 90 includes a protective layer 91 and a sacrificial layer 92. The protective layer 91 is used for cleanliness protection, and the material of the protective layer 91 includes, for example, SiCN. The material of the sacrificial layer 92 includes, for example, tetraethoxysilane (TEOS). For example, the thickness of the protective layer 91 is 0.1 μm, and the thickness of the sacrificial layer 92 is 0.5 μm.

[0235] S2123. Using laser cutting technology, the circuit base layer 32′, the first interconnect base layer 61′ and the cutting protective layer are cut along the second cutting path to cut out the first groove, forming the first circuit layer 32 and the first interconnect layer 61.

[0236] Due to the limitations of the laser cutting and ablation principle, slag will inevitably be present on the side of the first circuit layer 32 after laser cutting. That is, the slag is generated during the laser cutting process. At this time, the slag will be distributed on the side of the circuit base layer 32', or it may also be distributed on the side of the first interconnect base layer 61'.

[0237] It should be understood that a first interconnect base layer 61' may or may not be formed before laser cutting. The bottom of the first groove may be located within the substrate 31' or on the surface of the substrate 31', as long as the circuit base layer 32' is divided. To clearly illustrate the fabrication process, slag is not shown in the fabrication process diagram.

[0238] S213, as shown in Figure 14C, forms the fourth dielectric film L4′.

[0239] For example, step S213 includes:

[0240] S2131. Remove sacrificial layer 92. For example, CMP process is used to remove sacrificial layer 92, with protective layer 91 serving as a grinding stop layer. Removing sacrificial layer 92 removes some slag, but slag will still form protrusions.

[0241] S2132, First gap filling (GF) to form the fourth dielectric base film L4″.

[0242] When the fourth dielectric layer L4 is a single-layer structure, a dielectric layer is filled during the first gap filling. For example, the material of the fourth dielectric base film L4″ includes TEOS or aluminum oxide (AlO).

[0243] When the fourth dielectric layer L4 has a multilayer structure, multiple dielectric layers are filled during the first gap filling. For example, the fourth dielectric layer L4 includes a first sub-dielectric layer L41 and a second sub-dielectric layer L42. The material of the first sub-dielectric layer L41 includes SiCN, and the material of the second sub-dielectric layer L42 includes TEOS or a thermoplastic material, etc. At this time, the fourth dielectric base film L4″ includes, for example, a first sub-dielectric base film L41″ and a second sub-dielectric base film L42″. The first gap filling is, for example, filling a first sub-dielectric base film L41″ with a thickness of 0.1µm and a second sub-dielectric base film L42″ with a thickness of 1µm.

[0244] The initial gap filling can fill the first groove, and the subsequently formed fourth dielectric layer L4 can be as shown in Figure 7A. For example, the thickness of the fourth dielectric film L4′ is greater than 20 μm. For instance, the thickness of the fourth dielectric film L4′ is greater than 25 μm, 30 μm, 35 μm, etc.

[0245] The first gap filling may not be necessary to completely fill the first groove, in which case the subsequently formed fourth dielectric layer L4 can be as shown in Figure 7B. For example, the thickness of the base film L4″ is 1µm to 2µm. For instance, the thickness of the fourth dielectric base film L4″ is 1µm, 1.3µm, 1.5µm, 1.7µm, or 2µm, etc.

[0246] S2133. Using CMP, remove part or all of the fourth dielectric base film L4″ located on the surface of the first interconnect layer 61 to form the fourth dielectric film L4′.

[0247] For example, in step S2141, the second sub-dielectric base film L42″ located on the front side is removed, and then the first sub-dielectric base film L41″ and the protective layer 91 are removed by wet etching. The fourth dielectric film L4′ includes, for example, the first sub-dielectric film L41′ and the second sub-dielectric film L42′.

[0248] Depending on the depth of the first groove, the fourth dielectric film L4′ can cover only the side surface of the first circuit layer 32, or it can extend into the substrate 31′, covering a portion of the substrate 31′. In other words, the fourth dielectric film L4′ can also cover a portion of the side surface of the first substrate 31. The fourth dielectric film L4′ covers the molten slag, and the molten slag is flush with the fourth dielectric film L4′.

[0249] S214. As shown in Figure 14D, a plasma dicing (PD) process is used to cut the substrate 31′ and the fourth dielectric film L4′ along the second dicing path to form the first substrate 31 and the fourth dielectric layer L4, thereby forming the first chip D1.

[0250] For example, step S214 includes:

[0251] S2141. A protective layer 93 is deposited using a physical vapor deposition (PVD) process. The material of the protective layer 93 includes, for example, titanium (Ti) or titanium nitride (TiN), for cleanliness protection.

[0252] S2142, Form a photoresist coating (PR).

[0253] S2143. Expose and develop the photoresist coating.

[0254] The above-mentioned use of photoresist as a mask layer can also use a hard mask (HD) as a layer, and this application does not limit this.

[0255] S2144. Using plasma cutting technology, the substrate 31′ and the fourth dielectric film L4′ are cut to form the fourth dielectric layer L4.

[0256] For example, the substrate 31' can be completely cut off to directly form the first substrate 31, thus achieving chip separation. Alternatively, a half-cut can be performed without cutting off the substrate 31', and then step S2146 can be executed to achieve chip separation.

[0257] S2145, Remove photoresist coating PR.

[0258] S2146. The back side of the substrate 31′ is thinned by a grinding process to form a first substrate 31, thereby forming a first chip D1.

[0259] For example, step S146 includes:

[0260] S21461. Place the side containing the protective layer 93 on the polishing carrier film and polish the substrate 31′ to form the first substrate 31, thereby forming the first chip D1.

[0261] S21462. Remove the abrasive film and perform surface cleaning.

[0262] S21463, Remove protective layer 93.

[0263] S215, forming the second chip D2 and the fifth dielectric layer L5.

[0264] When the second chip D2 is the same as the first chip D1, the first chip D1 is formed simultaneously with the formation of the second chip D2. When the second chip D2 is different from the first chip D1, the steps for forming the second chip D2 and the fifth dielectric layer L5 are the same as those for forming the first chip D1 and the fourth dielectric layer L4, and will not be repeated here.

[0265] S216, As shown in Figure 14E, the first chip D1 and the second chip D2 are placed on the carrier board to form the sixth dielectric layer L6. The first circuit layer 32 and the second circuit layer 42 face the carrier board.

[0266] For example, step S216 includes:

[0267] S2161. Using a chip bonding machine, the separated first chip D1 and second chip D2 are mounted and bonded to the carrier board in a chip-to-wafer (C2W) manner.

[0268] S2162, Form the sixth sub-dielectric film L61′. The sixth sub-dielectric film L61′ can also serve as a protective film for subsequent mask cleanliness protection. The material of the sixth sub-dielectric film L61′ includes, for example, titanium nitride (SiN).

[0269] S2163. Perform backside grinding (BG) on the first substrate 31 of the first chip D1 and the second substrate 41 of the second chip D2 to remove the sixth sub-dielectric film L61′ located on the surface of the first substrate 31 and the second substrate 41, and form the sixth sub-dielectric layer L61.

[0270] S2164. Perform a second gap filling to form the seventh dielectric film L62′, in order to form the sixth dielectric film L6′.

[0271] After mounting, there is a gap between the first chip D1 and the second chip D2. A second gap filling process is performed to fill this gap. The material of the seventh sub-dielectric film L62′ includes, for example, TEOS, thermoplastic molding materials, etc.

[0272] S2165. Grind and flatten the sixth dielectric film L6′ to form the seventh sub-dielectric layer L62, thus forming the sixth dielectric layer L6.

[0273] The sixth dielectric layer L6 and the fourth dielectric layer L4 are both disposed on the surface of the carrier board. The surfaces of the sixth dielectric layer L6 and the fourth dielectric layer L4 are flush with the surface of the first circuit layer 32 or the first interconnect layer 61.

[0274] When placing the first chip D1 and the second chip D2 on the carrier board, the chips on the carrier board can be rearranged. For example, if the chip to be bonded is a good chip, the good first chip D1 and the second chip D2 are placed in the corresponding positions. If the chip to be bonded is a defective chip, the defective first chip D1 and the second chip D2 are placed in the corresponding positions, avoiding waste of the good first chip D1 and the second chip D2.

[0275] S217. As shown in Figure 14F, the first chip D1 and the second chip D2 are transferred to the support layer 80, exposing the first circuit layer 32 and the second circuit layer 42, and forming an integral structure of the first bonding layer HB1 and the second bonding layer HB2.

[0276] For example, step S217 includes:

[0277] S2171, Transfer the first chip D1 and the second chip D2 onto the support layer 80.

[0278] The first chip D1 and the second chip D2 are connected to the support layer, for example, through a connecting layer 70, which may be a bonding film transferred onto the support layer in a W2W manner.

[0279] S2172, Remove the carrier board to expose the first circuit layer 32 and the second circuit layer 42. For example, the carrier board can be removed by back-side grinding thinning and dry / wet etching technique (ET).

[0280] S2173, forming a second interconnect layer 62 and a fourth interconnect layer 64 with an integral structure. The second interconnect layer 62 and the fourth interconnect layer 64 include, for example, bonding vias.

[0281] S2174. A first bonding layer HB1 and a second bonding layer HB2 are formed into an integral structure. The first bonding layer HB1 and the second bonding layer HB2, for example, include a first pad P1 and a second pad P2, respectively.

[0282] S22. As shown in Figure 14G, a third bonding layer HB3 is prepared in each first chip region of the first wafer W1.

[0283] For example, step S22 includes:

[0284] S221, A seventh interconnect layer 67 is formed on the active surface of each first chip region of the first wafer W1.

[0285] S222, A third bonding layer HB3 is formed on the surface of the seventh interconnect layer 67.

[0286] S23. As shown in Figure 14H, the support layer 80 and the first wafer W1 are aligned and bonded. The first bonding layer HB1 and the second bonding layer HB2 in the same group are bonded to the same third bonding layer HB3. For example, it can be W2W bonding.

[0287] For example, prior to performing step S25, the preparation method further includes:

[0288] S20, as shown in Figures 14I-14L, solder balls B are prepared on the back side of the first wafer W1.

[0289] For example, step S20 includes:

[0290] S201, as shown in Figure 14I, the substrate of the first wafer W1 is thinned. For example, the substrate of the first wafer W1 is thinned by processes such as grinding, dry / wet etching, etc.

[0291] S202, as shown in Figure 14J, forms a protective layer 94, the material of which includes, for example, SiO2.

[0292] S203, as shown in Figure 14K, a via TV is formed on the first wafer W1.

[0293] For example, step S203 includes:

[0294] S2031, Form a photoresist coating PR, and expose and develop the photoresist coating PR.

[0295] S2032, An opening is formed on the substrate and protective layer 94 of the first wafer W1.

[0296] S2033, A through hole TV is formed inside the opening.

[0297] S204, as shown in Figure 14L, forms the fourth wafer-level pad P4.

[0298] For example, step S204 includes:

[0299] S2041. Form a fifth interconnect layer 65, which may be, for example, a rerouting layer.

[0300] S2042, Form the fourth pad P4.

[0301] S2043, Form solder balls B. The chip stack structure 100 formed after subsequent dicing is assembled with an interposer or substrate, for example, via solder balls B.

[0302] Step S2043 may also not form solder ball B, but instead form a long bump or C4 bump structure.

[0303] S25. As shown in Figure 14M, the chips are separated along the first cutting path to obtain a stacked chip structure.

[0304] During the fabrication process, after the second wafer W2 arrives, it is first laser-cut to form a fourth dielectric film L4′ covering the sides of the first circuit layer 32, and then the substrate 31′ is plasma-cut. The fourth dielectric film L4′ can cover the molten slag generated by laser cutting to prevent slag from falling everywhere and causing contamination. Moreover, the fourth dielectric film L4′ can cover the exposed metal structure when cutting the circuit base layer 32′, reducing the risk of metal ions in the metal structure diffusing into the first substrate 31 after subsequent cutting of the substrate 31′, thus improving product yield. Furthermore, after cutting to form the first chip D1 and the second chip D2, the first chip D1 and the second chip D2 are transferred to a carrier to form the sixth dielectric layer L6. During the chip transfer process, defective chips can be discarded, or defective chips can be placed as dummy chips in a special area for alignment and bonding with defective chips in the first wafer W1 that are subsequently bonded. This ensures that the bonding locations at the good chip positions in the first wafer W1 are all good chips, and not defective chips, thus making the yield of the final bonded structure equal to the yield of the first wafer W1, thereby improving product yield. Furthermore, using the C2W process to bond the first chip D1 and the second chip D2 to the carrier substrate, forming the sixth dielectric layer L6, results in a structure similar to a wafer. Then, the W2W process is used to co-bond the first chip D1 and the second chip D2 with the first wafer W1, resulting in a simple process with high yield.

[0305] Figure 15 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiments of this application; Figures 16A-16K are schematic diagrams of the fabrication process of another chip stacking structure provided in the embodiments of this application.

[0306] In some embodiments, as shown in FIG15, the method for fabricating a chip stacking structure includes:

[0307] Multiple sets of first chip D1, first bonding layer HB1, fourth dielectric layer L4, second chip D2, second bonding layer HB2 and fifth dielectric layer L5 are formed.

[0308] For example, the steps above include:

[0309] S211' provides a second wafer W2, the second wafer W2 including a substrate 31' and a circuit base layer 32' disposed on the substrate 31', the circuit base layer 32' being defined by a plurality of second chip regions by intersecting second dicing channels.

[0310] As shown in Figure 16A, S212′ is formed by using laser cutting technology to cut the circuit base layer 32′ along the second cutting path to form the first circuit layer 32.

[0311] For example, step S212' includes:

[0312] S2121′, A protective layer 95 is formed on the surface of the circuit substrate 32′. For example, the material of the protective layer 95 includes SiN, TEOS, or AlO.

[0313] S2122′: Using laser cutting technology, the circuit base layer 32′ and the cutting protective layer are cut along the second cutting path to form the first circuit layer 32, and a second groove is provided between adjacent first circuit layers 32.

[0314] S213′, as shown in Figure 16B, forms the fourth dielectric film L4′.

[0315] For example, the fourth dielectric film L4′ covers the surface of the second groove.

[0316] For example, step S213' includes:

[0317] S2131′, First gap filling, forming the fourth dielectric base film L4″, the fourth dielectric base film L4″ covers the surface of the cutting protective layer and the second groove.

[0318] S2132′: Using CMP and / or etching processes, the fourth dielectric base film L4″ located on the surface of the cutting protective layer is removed to form a fourth dielectric film L4′ located within the second groove. The fourth dielectric film L4′ can fill the second groove, and the thickness of the fourth dielectric base film L4″ can be, for example, greater than 30 μm. The fourth dielectric film L4′ can also only cover the inner surface of the second groove. Different fourth dielectric films L4′ can be used to prepare different fourth dielectric layers L4.

[0319] The material of the fourth dielectric base film L4″ includes, for example, TEOS, AlO or thermoplastic materials, or the fourth dielectric base film L4″ includes a stacked SiN film and a TEOS film.

[0320] S214′, as shown in Figure 16C, forms a bonding substrate HB1′, which covers the fourth dielectric film L4′ and is electrically connected to the circuit substrate 32′.

[0321] For example, step S214' includes:

[0322] S2141′, A second interconnect base layer 62′ is formed on the surface of the SiN film. The second interconnect base layer 62′ is electrically connected to the first circuit layer 32 through the first interconnect layer 61.

[0323] The second interconnect base layer 62' may include structures such as vias, wiring, and pads. For example, it may require processes such as deposition, etching, electroplating, and CPM. The conductive structures in the second interconnect base layer 62' may penetrate the SiN film and be electrically connected to the first circuit layer 32. In this case, the SiN film and the conductive structures located within it can serve as the structure of the first interconnect layer 61 in the embodiments of this application.

[0324] S2142′, a bonding base layer HB1′ is formed on the surface of the second interconnect base layer 62′.

[0325] As shown in Figure 16D, S215′ is formed by using plasma cutting technology to cut the bonding layer HB1′, the fourth dielectric film L4′ and the substrate 31′ along the second cutting path to form the first bonding layer HB1, the fourth dielectric layer L4 and the first substrate 31, thereby forming the first chip D1.

[0326] For example, step S125' includes:

[0327] S2151′ uses plasma cutting technology to cut the bonding base layer HB1′, the fourth dielectric film L4′ and the substrate 31′ along the second cutting path.

[0328] For example, the entire substrate 31' can be cut off to directly form the first substrate 31, achieving chip separation. Alternatively, the substrate 31' can be partially cut off without cutting it off, and then step 2152' can be performed to achieve chip separation.

[0329] S2152', The back side of the substrate 31' is thinned by a grinding process to form the first substrate 31, thereby forming the first chip D1.

[0330] S216′, forming the second chip D2, the fifth dielectric layer L5, and the second bonding layer HB2.

[0331] When the second chip D2 is the same as the first chip D1, the first chip D1 is formed simultaneously with the formation of the second chip D2. When the second chip D2 is different from the first chip D1, the steps for forming the second chip D2 and the fifth dielectric layer L5 are the same as those for forming the first chip D1 and the fourth dielectric layer L4, and will not be repeated here.

[0332] S22′, Prepare a third bonding layer HB3 in each first chip region of the first wafer W1.

[0333] S23′, as shown in Figure 16E, the first bonding layer HB1 and the second bonding layer HB2 in the same group are bonded to the same third bonding layer HB3. For example, it can be C2W bonding or surface mounting.

[0334] S24′, as shown in Figure 16F, forms the sixth dielectric layer L6.

[0335] For example, the sixth dielectric layer L6 can be formed through film formation and polishing processes.

[0336] For example, prior to performing step S25′, the preparation method further includes:

[0337] S20′, solder ball B is prepared on the back side of the first wafer W1.

[0338] For example, step S20' includes:

[0339] S201′, as shown in Figure 16G, a support layer 80 is formed on the back side of the first chip D1 and the second chip D2. For example, the support layer 80 and the chip are connected by a connection layer 70.

[0340] S202′, as shown in Figure 16H, thins the substrate of the first wafer W1.

[0341] S203′, as shown in Figure 16I, a through-hole TV is formed on the first wafer W1.

[0342] S204′, as shown in Figure 16J, forms solder ball B.

[0343] For example, step S204' includes:

[0344] S2041′, forming the fifth interconnect layer 65.

[0345] S2042′, forming the fourth pad P4 and solder ball B.

[0346] S25′, as shown in Figure 16K, is separated along the first cutting path to obtain a stacked structure of multiple chips.

[0347] In the fabrication process, after the second wafer W2 arrives, it is first laser-cut to form a fourth dielectric film L4′ covering the side of the first circuit layer 32. Then, the substrate 31′ is plasma-cut. The fourth dielectric film L4′ covers the molten slag generated during laser cutting, preventing it from falling and causing contamination. Furthermore, the fourth dielectric film L4′ covers the exposed metal structure during the cutting of the circuit substrate 32′, reducing the risk of metal ions diffusing from the metal structure to the first substrate 31 after subsequent cutting of the substrate 31′, thus improving product yield. Moreover, the laser cutting and plasma cutting are separate and not continuous operations, allowing for flexible and adaptable processes suitable for a wider range of product structures. The C2W and W2W processes can be appropriately integrated and combined. Furthermore, the entire fabrication process involves fewer steps, lower costs, and higher efficiency.

[0348] Figure 17 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiments of this application; Figures 18A-18H are schematic diagrams of the fabrication process of another chip stacking structure provided in the embodiments of this application.

[0349] In some embodiments, as shown in FIG17, the method for fabricating a chip stacking structure includes:

[0350] Multiple sets of first chip D1, first bonding layer HB1, fourth dielectric layer L4, second chip D2, second bonding layer HB2 and fifth dielectric layer L5 are formed.

[0351] For example, the steps above include:

[0352] S211″ provides a second wafer W2, the second wafer W2 including a substrate 31′ and a circuit base layer 32′ disposed on the substrate 31′, the circuit base layer 32′ being defined by a plurality of second chip regions by intersecting second dicing channels.

[0353] S212″, as shown in Figure 18A, a bonding layer HB1′ electrically connected to the circuit base layer 32′ is prepared on the second wafer W2.

[0354] For example, step S212″ includes:

[0355] S2121″, A first interconnect base layer 61′ is formed on the surface of the circuit base layer 32′, and the first interconnect base layer 61′ is electrically connected to the circuit base layer 32′.

[0356] The first interconnect base layer 61' may include structures such as vias, wiring, and pads. For example, it may require processes such as deposition, etching, electroplating, and CPM.

[0357] S2122″, forming a bonding base layer HB1′ on the surface of the first interconnect base layer 61′.

[0358] S213″, as shown in Figure 18B, uses laser cutting technology to cut the bonding layer HB1′ and the circuit layer 32′ along the second cutting path to form the first bonding layer HB1 and the first circuit layer 32.

[0359] For example, step S213″ includes:

[0360] S2131″, A protective layer 96 is formed on the surface of the bonding base layer HB1′. For example, the material of the protective layer 96 includes SiN, SiO2 or SiCN.

[0361] S2132″: Using laser cutting technology, the circuit base layer 32′, bonding base layer HB1′, first interconnect base layer 61′ and protective layer 96 are cut along the second cutting path to form the first bonding layer HB1, the first interconnect layer 61 and the first circuit layer 32, with a third groove between adjacent first circuit layers 32.

[0362] S214″, as shown in Figure 18C, forms the fourth dielectric film L4′.

[0363] For example, the fourth dielectric film L4′ covers the surface of the third groove and the side of the first bonding layer HB1.

[0364] For example, step S214″ includes:

[0365] S2141″, the first gap filling, forms the fourth dielectric base film L4″, the fourth dielectric base film L4″ covers the protective layer 96 and the surface of the third groove.

[0366] S2142″, using CMP and / or etching processes, remove the protective layer 96 and the fourth dielectric base film L4″ located on the surface of the protective layer 96, exposing the first bonding layer HB1, and forming the fourth dielectric film L4′.

[0367] The fourth dielectric film L4′ can fill the third groove, in which case the thickness of the fourth dielectric base film L4″ can be greater than 30 μm, for example. Alternatively, the fourth dielectric film L4′ can only cover the inner surface of the third groove, in which case the thickness of the fourth dielectric base film L4″ can be less than 2 μm, for example.

[0368] The fourth dielectric base film L4″ can be a single-layer structure or a multilayer structure; Figure 18C is only one illustration.

[0369] As shown in Figure 18D, S215″ uses a plasma cutting process to cut the fourth dielectric film L4′ and the substrate 31′ along the second cutting path to form the fourth dielectric layer L4 and the first substrate 31, thereby forming the first chip D1.

[0370] For example, step S215″ includes:

[0371] S2151″: Using plasma cutting technology, the fourth dielectric film L4′ and the substrate 31′ are cut along the second cutting path to form the fourth dielectric layer L4.

[0372] For example, the entire substrate 31' can be cut off to directly form the first substrate 31, achieving chip separation. Alternatively, the substrate 31' can be partially cut off without cutting it off, and then step 2152″ can be performed to achieve chip separation.

[0373] S2152″, The back side of the substrate 31′ is thinned by a grinding process to form the first substrate 31, thereby forming the first chip D1.

[0374] S2153″, Place the first chip D1 on the carrier film. The carrier film material may include, for example, a washable film that can be removed by a subsequent washing process.

[0375] S216″, forming the second chip D2, the fifth dielectric layer L5, and the second bonding layer HB2.

[0376] When the second chip D2 is the same as the first chip D1, the first chip D1 is formed simultaneously with the formation of the second chip D2. When the second chip D2 is different from the first chip D1, the steps for forming the second chip D2 and the fifth dielectric layer L5 are the same as those for forming the first chip D1 and the fourth dielectric layer L4, and will not be repeated here.

[0377] S22″, a third bonding layer HB3 is prepared in each first chip region of the first wafer W1.

[0378] S23″, as shown in Figure 18E, the first bonding layer HB1 and the second bonding layer HB2 in the same group are bonded to the same third bonding layer HB3. For example, it can be C2W bonding or mounting.

[0379] S24″, as shown in Figure 18F, forms the sixth dielectric layer L6.

[0380] For example, the sixth dielectric layer L6 can be formed through film formation and polishing processes.

[0381] For example, prior to performing step S25″, the preparation method further includes:

[0382] S20″, as shown in Figure 18G, solder balls B are prepared on the back side of the first wafer W1.

[0383] S25″, as shown in Figure 18H, is separated along the first cutting path to obtain a stacked structure of multiple chips.

[0384] In the fabrication process, after the second wafer W2 arrives, it is first laser-cut to form a fourth dielectric film L4′ covering the side of the first circuit layer 32. Then, the substrate 31′ is plasma-cut. The fourth dielectric film L4′ covers the molten slag generated during laser cutting, preventing it from falling and causing contamination. Furthermore, the fourth dielectric film L4′ covers the exposed metal structure during the cutting of the circuit substrate 32′, reducing the risk of metal ions diffusing from the metal structure to the first substrate 31 after subsequent cutting of the substrate 31′, thus improving product yield. Moreover, the laser cutting and plasma cutting are separate and not continuous operations, allowing for flexible and adaptable processes suitable for a wider range of product structures. The C2W and W2W processes can be appropriately integrated and combined. Furthermore, the entire fabrication process involves fewer steps, lower costs, and higher efficiency. Furthermore, since the laser cutting and grinding of the fourth dielectric substrate film L4″ are performed only after the bonding base layer HB1′ is formed, the total thickness variation (TTV) of the ground surface has a smaller impact on the flatness of the bonding base layer HB1′. Therefore, the requirements for the flatness of the ground surface can be reduced, thus lowering costs.

[0385] Figure 19 is a schematic diagram of the fabrication process of another chip stacking structure provided in the embodiments of this application; Figures 20A-20I are schematic diagrams of the fabrication process of another chip stacking structure provided in the embodiments of this application.

[0386] In some embodiments, as shown in FIG19, the method for fabricating a chip stacking structure includes:

[0387] Multiple sets of first chip D1, first bonding layer HB1, fourth dielectric layer L4, second chip D2, second bonding layer HB2 and fifth dielectric layer L5 are formed.

[0388] For example, the steps above include:

[0389] S211″′, a second wafer W2 is provided, the second wafer W2 includes a substrate 31′ and a circuit base layer 32′ disposed on the substrate 31′, the circuit base layer 32′ is defined by a plurality of second chip regions by intersecting second dicing channels.

[0390] As shown in Figure 20A, a bonding substrate HB1′ electrically connected to the circuit substrate 32′ is prepared on the second wafer W2.

[0391] For example, step S212″′ includes:

[0392] S2121″′, A first interconnecting substrate 61′ and a second interconnecting substrate 62′ are formed on the surface of the circuit substrate 32′. The first interconnecting substrate 61′ is electrically connected to the circuit substrate 32′, and the second interconnecting substrate 62′ is electrically connected to the first interconnecting substrate 61′.

[0393] The first interconnect substrate 61' and the second interconnect substrate 62' may include structures such as vias, wiring, and pads. For example, processes such as deposition, etching, electroplating, and CPM may be required. This application embodiment does not limit the number of interconnect substrate layers and their structure on the surface of the circuit substrate 32'; Figure 20A is merely an illustration.

[0394] S2122″′, a bonding base layer HB1′ is formed on the surface of the second interconnect base layer 62′.

[0395] As shown in Figure 20B, S213″′ is cut along the second cutting path of the bonding base layer HB1′ using plasma cutting technology to form the first bonding layer HB1.

[0396] For example, if an interconnect base layer is also formed during the fabrication process, a plasma cutting process can be used to cut part or all of the interconnect base layer. For instance, if a first interconnect base layer 61′ and a second interconnect base layer 62′ are formed, when the bonding base layer HB1′ is cut using a plasma cutting process, the second interconnect base layer 62′ is cut simultaneously to form a second interconnect layer 62.

[0397] Plasma cutting cannot cut metal. Therefore, when forming the bonding base layer HB1′ and the first interconnect base layer 61′, no metal structure is formed at the position corresponding to the second cutting path.

[0398] As shown in Figure 20C, S214″′ is cut along the second cutting path to form the first circuit layer 32 using laser cutting technology.

[0399] For example, if an uncut interconnect layer is still provided on the surface of the circuit substrate 32′ during the fabrication process, the remaining interconnect layer is cut simultaneously when the circuit substrate 32′ is cut using a laser cutting process. For instance, when the circuit substrate 32′ is cut using a laser cutting process, the first interconnect layer 61′ is cut simultaneously to form the first interconnect layer 61.

[0400] At this time, the slag generated by the laser cutting process covers, for example, the sides of the first circuit layer 32 and the first interconnect layer 61, but does not completely cover the sides of the first bonding layer HB1 and the second interconnect layer 62.

[0401] S215″′, as shown in Figure 20D, forms the fourth dielectric film L4′.

[0402] For example, the fourth dielectric film L4′ covers the side of the first bonding layer HB1, the side of the second interconnect layer 62, the side of the first interconnect layer 61, and the side of the first circuit layer 32.

[0403] The fourth dielectric base film L4″ can fill the gap formed by the above cutting, and the fourth dielectric film L4′ can also only cover the surface of the gap formed by cutting. The fourth dielectric base film L4″ can be a single-layer structure or a multilayer structure; Figure 20D is only one illustration.

[0404] As shown in Figure 20E, S216″′ is cut along the second cutting path using a plasma cutting process to form the fourth dielectric layer L4 and the first substrate 31, thereby forming the first chip D1.

[0405] S217″′, forming the second chip D2, the fifth dielectric layer L5, and the second bonding layer HB2.

[0406] When the second chip D2 is the same as the first chip D1, the first chip D1 is formed simultaneously with the formation of the second chip D2. When the second chip D2 is different from the first chip D1, the steps for forming the second chip D2 and the fifth dielectric layer L5 are the same as those for forming the first chip D1 and the fourth dielectric layer L4, and will not be repeated here.

[0407] S22″′, a third bonding layer HB3 is prepared in each first chip region of the first wafer W1.

[0408] S23″′, as shown in Figure 20F, the first bonding layer HB1 and the second bonding layer HB2 in the same group are bonded to the same third bonding layer HB3. For example, it can be C2W bonding or mounting.

[0409] S24″′, as shown in Figure 20G, forms the sixth dielectric layer L6.

[0410] For example, the sixth dielectric layer L6 can be formed through film formation and polishing processes.

[0411] For example, prior to performing step S25″, the preparation method further includes:

[0412] S20″′, as shown in Figure 20H, solder balls B are prepared on the back side of the first wafer W1.

[0413] S25″′, as shown in Figure 20I, separation is performed along the first cutting path to obtain a stacked structure of multiple chips.

[0414] During the fabrication process, after the second wafer W2 arrives, a bonding substrate HB1′ is formed. Plasma dicing is then used to cut the bonding substrate HB1′ to form the first bonding layer HB1. Next, laser dicing is used to cut the circuit substrate 32′ to form the first circuit layer 32. At this stage, the slag generated by the laser dicing process is mainly concentrated on the sides of the first circuit layer 32 and does not completely cover the sides of the first bonding layer HB1. The slag is relatively far from the first bonding layer HB1, which reduces its impact on the flatness and cleanliness of the first bonding layer HB1, thereby improving product yield. Furthermore, after laser dicing the circuit substrate 32′ to form slag, a fourth dielectric film L4′ is first formed to cover the sides of the first circuit layer 32 before plasma dicing of the substrate 31′. The fourth dielectric film L4′ can cover the slag generated by laser dicing to prevent slag from falling everywhere and causing contamination. Furthermore, the fourth dielectric film L4′ can cover the exposed metal structure during the cutting of the circuit substrate 32′, reducing the risk of metal ions diffusing from the metal structure to the first substrate 31 after subsequent cutting of the substrate 31′, thus further improving product yield. Moreover, laser cutting and plasma cutting are separate and not continuous operations, allowing for flexible and adaptable processes suitable for a wider range of product structures; C2W and W2W processes can be appropriately integrated. Furthermore, the entire fabrication process involves fewer steps, lower costs, and higher efficiency. Additionally, the laser cutting and grinding of the fourth dielectric film L4″ are performed only after the bonding substrate HB1′ is formed, minimizing the impact of the surface flatness after grinding on the flatness of the bonding substrate HB1′. Therefore, the requirements for surface flatness after grinding can be reduced, lowering costs.

[0415] In some embodiments, when other chips are stacked on the first chip D1 and the second chip D2, the other chips can be bonded to the first chip D1 and the second chip D2 before the support layer 80 is formed.

[0416] Figures 21A and 21B are schematic diagrams of another chip packaging structure provided in the embodiments of this application.

[0417] The chip stacking structure 100 provided in this application embodiment, or the chip stacking structure prepared by the above-described chip stacking structure preparation method, can be applied to the chip packaging structure 10 provided in this application embodiment to improve the yield and density of the chip packaging structure 10.

[0418] As shown in Figure 21A, the chip package structure 10 includes any of the above-described chip stack structure 100 and the sixth chip 200, and the package layer 700 covers the chip stack structure 100 and the sixth chip 200. For example, the package layer 700 may expose the top of the chip stack structure 100 and the sixth chip 200 to improve heat dissipation.

[0419] The chip package structure 10 may further include a seventh chip 300. The chip stack structure 100, the sixth chip 200, and the seventh chip 300 may be different types of chips. For example, the sixth chip 200 may be an input / output (I / O) chip, and the seventh chip 300 may be a high bandwidth memory (HBM) chip. The chip stack structure 100, the sixth chip 200, and the seventh chip 300 are electrically connected to the package substrate.

[0420] For example, as shown in Figure 21A, the packaging substrate includes an adapter board 500, and the chip stack structure 100, the sixth chip 200 and the seventh chip 300 are electrically connected to the adapter board 500.

[0421] Alternatively, for example, as shown in Figure 21B, the packaging substrate includes a bridging chip 800, and the chip stack structure 100, the sixth chip 200 and the seventh chip 300 are electrically connected to the bridging chip 800.

[0422] The chip package structure 10 may also include a redistribution layer 600, which covers the package substrate and is electrically connected to the solder ball B.

[0423] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip stacking structure, characterized in that, The chip stacking structure includes: The first chip includes a first substrate and a first circuit layer disposed on one side of the first substrate; A first bonding layer is electrically connected to the first circuit layer; the first bonding layer includes a first dielectric layer and a first pad, the first pad penetrating the first dielectric layer. The second chip includes a second substrate and a second circuit layer disposed on one side of the second substrate; a first gap is provided between the first substrate and the second substrate, and a second gap is provided between the first circuit layer and the second circuit layer. The second bonding layer is electrically connected to the second circuit layer; the second bonding layer includes a second dielectric layer and a second pad, the second pad penetrating the second dielectric layer. The third chip; The third bonding layer is electrically connected to the third chip; the third bonding layer includes a third dielectric layer and a plurality of third pads, the plurality of third pads respectively penetrate the third dielectric layer and are spaced apart; the first dielectric layer and the second dielectric layer are respectively bonded to the third dielectric layer, and the first pad and the second pad are electrically connected to different third pads; A fourth dielectric layer, a fifth dielectric layer, and a sixth dielectric layer; the fourth dielectric layer covers the side of the first circuit layer, the fifth dielectric layer covers the side of the second circuit layer, and the sixth dielectric layer fills the first gap and extends between the fourth and fifth dielectric layers, filling the second gap.

2. The chip stacking structure according to claim 1, characterized in that, The surface of the first bonding layer facing the third bonding layer is flat; And / or, The surface of the second bonding layer is flat toward the surface of the third bonding layer.

3. The chip stacking structure according to claim 2, characterized in that, The flatness of the surface of the first bonding layer facing the third bonding layer is less than 0.2 μm; And / or, The flatness of the surface of the second bonding layer facing the third bonding layer is less than 0.2 μm.

4. The chip stacking structure according to any one of claims 1-3, characterized in that, The fourth dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, wherein the first sub-dielectric layer is disposed close to the first circuit layer. The density of the first sub-dielectric layer is greater than that of the second sub-dielectric layer; And / or, The hydrophobicity of the first sub-dielectric layer is greater than that of the second sub-dielectric layer.

5. The chip stacking structure according to claim 4, characterized in that, Along the direction from the first chip to the second chip, the size of the portion of the sixth dielectric layer located within the first gap is equal to the size of the portion located within the second gap.

6. The chip stacking structure according to claim 4, characterized in that, Along the direction from the first chip to the second chip, the dimension of the end of the sixth dielectric layer located within the second gap is larger than the dimension of the end of the sixth dielectric layer located within the first gap.

7. The chip stacking structure according to any one of claims 1-6, characterized in that, The fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer are located on the side of the first bonding layer facing the first substrate; The first bonding layer and the second bonding layer are integrally formed.

8. The chip stacking structure according to any one of claims 1-6, characterized in that, The fourth dielectric layer is located on the side of the first bonding layer facing the first substrate; A third gap exists between the first bonding layer and the second bonding layer, and the sixth dielectric layer extends into and fills the third gap.

9. The chip stacking structure according to claim 7 or 8, characterized in that, The chip stacking structure further includes a first interconnect layer and a second interconnect layer stacked between the first chip and the first bonding layer, wherein the first interconnect layer is electrically connected to the first chip and the second interconnect layer is electrically connected to the first bonding layer; The fourth dielectric layer also covers the side of the first interconnect layer and is attached to the second interconnect layer.

10. The chip stacking structure according to any one of claims 1-6, characterized in that, A third gap exists between the first bonding layer and the second bonding layer, and the fourth dielectric layer and the sixth dielectric layer extend to the third gap respectively, with the fourth dielectric layer also covering the side of the first bonding layer.

11. The chip stacking structure according to claim 10, characterized in that, Along the direction from the first chip to the second chip, the size of the third gap is larger than the size of the second gap.

12. The chip stacking structure according to claim 10 or 11, characterized in that, The chip stacking structure further includes a first interconnect layer disposed between the first chip and the first bonding layer, wherein the first interconnect layer is electrically connected to the first chip and the first bonding layer respectively; The fourth dielectric layer also covers the sides of the first interconnect layer.

13. The chip stacking structure according to any one of claims 10-12, characterized in that, The fifth dielectric layer is located on the side of the second bonding layer facing the second substrate.

14. The chip stacking structure according to any one of claims 1-13, characterized in that, The chip stacking structure also includes: a fourth chip and a fifth chip; The fourth chip is disposed on the side of the first chip away from the third chip and is electrically connected to the first chip; The fifth chip is located on the side of the second chip away from the third chip and is electrically connected to the first chip.

15. A method for fabricating a chip stacking structure, characterized in that, The preparation method includes: Multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers are formed. The first chip includes a first substrate and a first circuit layer disposed on one side of the first substrate. The first bonding layer is electrically connected to the first circuit layer and includes a first dielectric layer and a first pad, with the first pad penetrating the first dielectric layer. The second chip includes a second substrate and a second circuit layer disposed on one side of the second substrate. The second bonding layer is electrically connected to the second circuit layer and includes a second dielectric layer and a second pad, with the second pad penetrating the second dielectric layer. A first gap exists between the first substrate and the second substrate, and a second gap exists between the first circuit layer and the second circuit layer. The fourth dielectric layer covers the side surface of the first circuit layer, and the fifth dielectric layer covers the side surface of the second circuit layer. A third bonding layer is fabricated in each first chip region of a first wafer; the first wafer includes a plurality of first chip regions defined by first dicing channels that intersect horizontally and vertically; the third bonding layer is electrically connected to the first wafer; the third bonding layer includes a third dielectric layer and a plurality of third pads, the plurality of third pads respectively penetrating the third dielectric layer and being spaced apart; The first bonding layer and the second bonding layer in the same group are mixed and bonded with the same third bonding layer; the first dielectric layer and the second dielectric layer are respectively bonded to the third dielectric layer; the first pad and the second pad are electrically connected to different third pads; A sixth dielectric layer is formed; the sixth dielectric layer fills the first gap and extends between the fourth dielectric layer and the fifth dielectric layer, filling the second gap; Separate along the first cutting path to obtain multiple chip stack structures.

16. The method for fabricating a chip stacking structure according to claim 15, characterized in that, Forming the first chip includes: A second wafer is provided; the second wafer includes a substrate and a circuit layer disposed on the substrate; The first circuit layer is formed by laser cutting the circuit substrate. The substrate is plasma-cut to form the first substrate, thereby forming the first chip.

17. The method for fabricating a chip stacked structure according to claim 16, characterized in that, Forming a fourth dielectric layer, including: Before plasma cutting the substrate to form the first substrate, a fourth dielectric base film is formed, which covers the first circuit layer and the groove between adjacent first circuit layers. A grinding process is used to remove the portion of the fourth dielectric base film located above the first circuit layer to form the fourth dielectric film. The fourth dielectric film and the substrate are simultaneously subjected to plasma cutting to form the fourth dielectric layer.

18. The method for fabricating a chip stacked structure according to any one of claims 15-17, characterized in that, Forming multiple sets of a first chip, a first bonding layer, a fourth dielectric layer, a second chip, a second bonding layer, a fifth dielectric layer, and a sixth dielectric layer, including: A second wafer is provided; the second wafer includes a substrate and a circuit layer disposed on the substrate, the circuit layer being defined by a plurality of second chip regions by intersecting second dicing lines; The circuit substrate is cut along the second cutting path using laser cutting technology to form the first circuit layer; Form the fourth dielectric film; The substrate and the fourth dielectric film are cut along the second cutting path using a plasma cutting process to form the first substrate and the fourth dielectric layer, thereby forming the first chip; The second chip and the fifth dielectric layer are formed; The first chip and the second chip are placed on a carrier board to form the sixth dielectric layer; the first circuit layer and the second circuit layer face the carrier board; The first chip and the second chip are transferred onto the support layer, exposing the first circuit layer and the second circuit layer, and forming an integral first bonding layer and second bonding layer.

19. The method for fabricating a chip stacked structure according to any one of claims 15-17, characterized in that, Forming multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers, including: A second wafer is provided; the second wafer includes a substrate and a circuit layer disposed on the substrate, the circuit layer being defined by a plurality of second chip regions by intersecting second dicing lines; The circuit substrate is cut along the second cutting path using laser cutting technology to form the first circuit layer, and there are grooves between adjacent first circuit layers. A fourth dielectric film is formed, which covers the surface of the groove; A bonding substrate is formed; the bonding substrate covers the fourth dielectric film and is electrically connected to the circuit substrate. The bonding layer, the fourth dielectric film, and the substrate are cut along the second cutting path using a plasma cutting process to form the first bonding layer, the fourth dielectric layer, and the first substrate, thereby forming the first chip; The second chip, the fifth dielectric layer, and the second bonding layer are formed.

20. The method for fabricating a chip stacked structure according to any one of claims 15-17, characterized in that, Forming multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers, including: A second wafer is provided; the second wafer includes a substrate and a circuit layer disposed on the substrate, the circuit layer being defined by a plurality of second chip regions by intersecting second dicing lines; A bonding substrate electrically connected to the circuit substrate is fabricated on the second wafer; Using laser cutting technology, the bonding substrate and the circuit substrate are cut along the second cutting path to form the first bonding layer and the first circuit layer, with grooves between adjacent first circuit layers; A fourth dielectric film is formed, which covers the surface of the groove and the side surface of the first bonding layer; The fourth dielectric film and the substrate are cut along the second cutting path using a plasma cutting process to form the fourth dielectric layer and the first substrate, thereby forming the first chip; The second chip, the fifth dielectric layer, and the second bonding layer are formed.

21. The method for fabricating a chip stacked structure according to any one of claims 15-17, characterized in that, Forming multiple sets of first chips, first bonding layers, fourth dielectric layers, second chips, second bonding layers, and fifth dielectric layers, including: A second wafer is provided; the second wafer includes a substrate and a circuit layer disposed on the substrate, the circuit layer being defined by a plurality of second chip regions by intersecting second dicing lines; A bonding substrate electrically connected to the circuit substrate is fabricated on the second wafer; The bonding substrate is cut along the second cutting path using a plasma cutting process to form the first bonding layer; The circuit substrate is cut along the second cutting path using laser cutting technology to form the first circuit layer, and there are grooves between adjacent first circuit layers. A fourth dielectric film is formed, which covers the surface of the groove and the side surface of the first bonding layer; The fourth dielectric film and the substrate are cut along the second cutting path using a plasma cutting process to form the fourth dielectric layer and the first substrate, thereby forming the first chip; The second chip, the fifth dielectric layer, and the second bonding layer are formed.

22. A chip packaging structure, characterized in that, The chip packaging structure includes a packaging substrate and a chip stacking structure as described in any one of claims 1-14; the chip stacking structure is disposed on the packaging substrate.

23. An electronic device, characterized in that, The electronic device includes a circuit board and a chip package structure as described in claim 22; the chip package structure is electrically connected to the circuit board.

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