Preparation method for non-volatile two-terminal memory cell and product thereof

Abstract

A preparation method for a non-volatile two-terminal memory cell and a product thereof. The preparation method comprises: providing a lower dielectric layer (120) which surrounds a first-region lower electrode metal connection layer (111) and exposes an upper surface of the first-region lower electrode metal connection layer; forming an isolation stack layer (130) at least covering the first-region lower electrode metal connection layer; etching, on the basis of a patterned photomask layer, the isolation stack layer to form a first-region lower electrode interconnection via hole (141), wherein the bottom of the first-region lower electrode interconnection via hole is at least partially in contact with the first-region lower electrode metal connection layer; and forming, in the first-region lower electrode interconnection via hole, a first stack layer (250) comprising a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253). In the preparation method, the first stack layer is formed in the first-region lower electrode interconnection via hole, and the preparation of the first lower electrode metal layer and the first upper electrode metal layer is realized by using only a single patterned photomask layer, thereby reducing the production costs, simplifying the preparation process, avoiding the problem of aligning an upper electrode and a lower electrode, and reducing the preparation difficulty.

Description

Fabrication method and products of non-volatile two-terminal memory cells Cross-references to related applications

[0001] This application claims priority to Chinese patent application filed on March 25, 2025, with application number 202510363276.4 and entitled "Method for fabricating non-volatile two-terminal memory cells and products thereof". Technical Field

[0002] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a method for fabricating a non-volatile two-terminal memory cell and the product thereof. Background Technology

[0003] Resistive Random Access Memory (RRAM) is a non-volatile two-terminal memory cell that stores information based on changes in the resistance of a material. It typically consists of a lower electrode, a switching layer, and a upper electrode. In existing technologies, the fabrication of RRAM requires two separate photolithography steps to fabricate the lower and upper electrodes. Due to the manufacturing process, the fabrication of the lower and upper electrodes usually requires a different patterned photomask layer, significantly increasing production costs and complicating the fabrication process. Furthermore, this method involves aligning the lower and upper electrodes during fabrication, further complicating the fabrication of RRAM.

[0004] In view of this, there is an urgent need to provide a method for fabricating non-volatile two-sided memory cells. This method can fabricate the lower and upper electrodes of the non-volatile two-sided memory cells while reducing the number of patterned photomask layers used, thereby reducing the production cost of non-volatile two-sided memory cells, simplifying the fabrication process, and avoiding the problem of mutual alignment between the lower and upper electrodes, thus reducing the fabrication difficulty of non-volatile two-sided memory cells. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, this disclosure proposes a method for fabricating non-volatile two-ended memory cells and a solution for their products in several aspects.

[0006] In a first aspect, this disclosure provides a method for fabricating a non-volatile two-terminal memory cell, the method comprising: providing a lower dielectric layer 120 surrounding a first region lower electrode metal interconnect layer 111 and exposing its upper surface; forming an isolation stack layer 130 at least covering the first region lower electrode metal interconnect layer 111; etching a first region lower electrode interconnect via 141 in the isolation stack layer 130 based on a patterned photomask layer, the bottom of the first region lower electrode interconnect via 141 at least partially contacting the first region lower electrode metal interconnect layer 111; and forming a first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 in the first region lower electrode interconnect via 141.

[0007] In some embodiments, the upper surface of the first stacked layer 250 is flush with the upper surface of the isolation stacked layer 130.

[0008] In some embodiments, forming a first stacked layer 250 flush with the upper surface of the isolation stacked layer 130 in the first region lower electrode interconnect via 141 includes: depositing a first lower electrode metal layer 251 and a first switching layer 252 covering the first lower electrode metal layer 251 at least on the inner wall and bottom of the first region lower electrode interconnect via 141; forming a sacrificial layer 270 on the first switching layer 252 such that the sacrificial layer 270 at least fills the remaining space of the first region lower electrode interconnect via 141; removing the first lower electrode metal layer 251, the first switching layer 252 and the sacrificial layer 270 outside the region of the first region lower electrode interconnect via 141, and removing the sacrificial layer 270 in the region of the first region lower electrode interconnect via 141; forming a first upper electrode metal layer 253 in the region of the first region lower electrode interconnect via 141 where the sacrificial layer 270 has been removed, such that the upper surface of the first upper electrode metal layer 253 is flush with the upper surface of the isolation stacked layer 130.

[0009] In some embodiments, the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532, wherein the first upper electrode metal layer 2531 is located between the first switching layer 252 and the first upper electrode metal layer 2532; a first stacked layer 250 flush with the upper surface of the isolation stacked layer 130 is formed in the first region lower electrode interconnect via 141, including: depositing and forming at least the first lower electrode metal layer 251, the first switching layer 252 covering the first lower electrode metal layer 251, and the first upper electrode metal layer 2531 covering the first switching layer 252 at the inner wall and bottom of the first region lower electrode interconnect via 141; A sacrificial layer 270 is formed on the first upper electrode metal layer 2531, such that the sacrificial layer 270 at least fills the remaining space of the first region lower electrode interconnect via 141; the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 2531 and the sacrificial layer 270 outside the region of the first region lower electrode interconnect via 141 are removed, and the sacrificial layer 270 in the region of the first region lower electrode interconnect via 141 is also removed; a first upper electrode metal layer 2532 is formed in the region of the first region lower electrode interconnect via 141 where the sacrificial layer 270 has been removed, such that the upper surface of the first upper electrode metal layer 2532 is flush with the upper surface of the isolation stack layer 130.

[0010] In some embodiments, after the first stacked layer 250 is formed, a barrier layer 230 is formed that at least covers the upper surface of the first stacked layer 250.

[0011] In some embodiments, after the barrier layer 230 is formed, a first region upper electrode metal connection layer 191 is formed that penetrates the barrier layer 230 and whose bottom contacts the upper surface of the first upper electrode metal layer 253.

[0012] In a second aspect, this disclosure provides a non-volatile two-terminal memory cell, the non-volatile two-terminal memory cell comprising: a lower dielectric layer 120 surrounding a first region lower electrode metal interconnect layer 111 and exposing its upper surface; an isolation stack layer 130 at least covering the first region lower electrode metal interconnect layer 111; a first region lower electrode interconnect via 141 disposed in the isolation stack layer 130, and the bottom of the first region lower electrode interconnect via 141 at least partially contacting the first region lower electrode metal interconnect layer 111; and a first stack layer 250 located within the first region lower electrode interconnect via 141, the first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253.

[0013] In some embodiments, the non-volatile end-to-end storage cell further includes: a blocking layer 230 covering at least the upper surface of the first stacked layer 250, and a first region upper electrode metal connection layer 191 penetrating the blocking layer 230, wherein the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253.

[0014] In a third aspect, this disclosure provides a memory comprising one or more non-volatile end-to-end memory cells according to embodiments of this disclosure.

[0015] In a fourth aspect, this disclosure provides an electronic device that includes the memory described in the embodiments of this disclosure.

[0016] By utilizing the fabrication scheme of the non-volatile two-terminal memory cell provided above, this disclosed embodiment forms a first stacked layer in the interconnect via of the lower electrode in the first region, thereby enabling the fabrication of the first lower electrode metal layer and the first upper electrode metal layer of the non-volatile two-terminal memory cell using only one patterned photomask layer. This reduces production costs, simplifies the fabrication process, avoids the problem of mutual alignment between the lower and upper electrodes, and reduces the fabrication difficulty. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0018] Figures 1A-1F show schematic diagrams of semiconductor cross-sectional structures fabricated using existing technology for non-volatile two-terminal memory cells;

[0019] Figure 2 shows an exemplary structural block diagram of a method for fabricating a non-volatile two-ended memory cell according to some embodiments of this application;

[0020] Figures 3A-3N show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to some embodiments of this disclosure;

[0021] Figures 4A-4N show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to other embodiments of this disclosure;

[0022] Figures 5A-5H show schematic diagrams of semiconductor cross-sectional structures of methods for fabricating non-volatile two-terminal memory cells according to further embodiments of this disclosure.

[0023] Figure label name:

[0024] 111-Lower electrode metal connection layer of the first region, 112-Lower electrode metal connection layer of the second region, 120-Lower dielectric layer, 130-Isolation stack layer, 131-Isolation stack layer 1, 132-Isolation stack layer 2, 141-Interconnect via of the lower electrode of the first region, 151-Second lower electrode metal layer, 1511-Second lower electrode metal layer 1, 1512-Second lower electrode metal layer 2, 152-Second switching layer, 153-Second upper electrode metal layer, 154-Upper electrode hard mask layer, 159-Sidewall, 170-Upper dielectric layer, 191-Upper electrode metal connection layer of the first region, 192-Upper electrode metal connection layer of the second region;

[0025] 230 - Barrier layer, 250 - First stacked layer, 251 - First lower electrode metal layer, 2511 - First lower electrode metal layer 1, 2512 - First lower electrode metal layer 2, 252 - First switching layer, 253 - First upper electrode metal layer, 2531 - First upper electrode metal layer 1, 2532 - First upper electrode metal layer 2, 270 - Sacrificial layer. Detailed Implementation

[0026] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0028] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0029] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0030] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0031] Figures 1A-1F show schematic diagrams of semiconductor cross-sectional structures for fabricating non-volatile two-terminal memory cells using existing technology.

[0032] Figure 1A shows a schematic diagram of a semiconductor cross-sectional structure in the prior art for forming a second lower electrode metal layer 1511.

[0033] As shown in Figure 1A, a lower dielectric layer 120 is provided surrounding the first region lower electrode metal interconnect layer 111, with its upper surface exposed. An isolation stack layer 130 is deposited on the upper surface of the first region lower electrode metal interconnect layer 111 and the upper surface of the lower dielectric layer 120 using a thin-film deposition process. The isolation stack layer 130 may include an isolation stack first layer 131 and an isolation stack second layer 132, with the isolation stack second layer 132 covering the upper surface of the isolation stack first layer 131. A first region lower electrode interconnect via 141 is formed in the isolation stack layer 130 using photolithography and etching processes. A second lower electrode metal first layer 1511 is formed within the first region lower electrode interconnect via 141 using thin-film deposition, chemical mechanical polishing, and other processes.

[0034] Figure 1B shows a schematic diagram of a semiconductor cross-sectional structure in the prior art, comprising a second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154.

[0035] As shown in Figure 1B, a second lower electrode metal layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154 are sequentially deposited over the isolation stack layer 130 and the second lower electrode metal layer 1511 using a thin-film deposition process. The second lower electrode metal layer 1511 and the second lower electrode metal layer 1512 covering the second lower electrode metal layer 1511 form the second lower electrode metal layer 151. The upper electrode hard mask layer 154 can be a conductive hard mask layer or a non-conductive hard mask layer.

[0036] Figure 1C shows a schematic diagram of a semiconductor cross-sectional structure in the prior art for etching the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154.

[0037] As shown in Figure 1C, photolithography and etching processes are used to etch a portion of the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 to form a stacked structure.

[0038] Figure 1D shows a schematic diagram of the semiconductor cross-sectional structure of the deposited sidewall 159 in the prior art.

[0039] As shown in Figure 1D, sidewalls 159 are deposited in the exposed areas of the etched second lower electrode metal layer 1512, second switching layer 152, second upper electrode metal layer 153, and upper electrode hard mask layer 154. The sidewalls 159 can be single-layered or multi-layered, covering all sides of the second switching layer 152, second upper electrode metal layer 153, and upper electrode hard mask layer 154, as well as at least a portion of the sides of the second lower electrode metal layer 1512.

[0040] Figure 1E shows a schematic diagram of a semiconductor cross-sectional structure in the prior art where the sidewall 159 and the second lower electrode metal layer 1512 are etched.

[0041] As shown in Figure 1E, the deposited sidewalls 159 and the second lower electrode metal layer 1512 are etched, and the etching stops at the upper surface of the isolation stack layer 130, so that the sidewalls 159 cover all sides of the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154.

[0042] Figure 1F shows a schematic diagram of the semiconductor cross-sectional structure in the prior art for forming the upper electrode metal interconnect layer 191 of the first region.

[0043] As shown in Figure 1F, an upper dielectric layer 170 is deposited in the exposed area of ​​the above-formed structure. A first region upper electrode interconnect via is formed in the upper dielectric layer 170 using photolithography and etching processes, and a first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnect via. When the upper electrode hard mask layer 154 is a conductive hard mask layer, the first region upper electrode interconnect via can partially penetrate the upper electrode hard mask layer 154, making the first region upper electrode metal connection layer 191, the upper electrode hard mask layer 154, and the second upper electrode metal layer 153 conductive. When the upper electrode hard mask layer 154 is a non-conductive hard mask layer, the first region upper electrode interconnect via can penetrate the upper electrode hard mask layer 154, making the first region upper electrode metal connection layer 191 and the second upper electrode metal layer 153 conductive. The second lower electrode metal layer 151, the second lower electrode metal layer 1511, and the second lower electrode metal layer 1512 are in contact with each other. The second lower electrode metal layer 151 and the first lower electrode metal connection layer 111 are in contact with each other, so that the second lower electrode metal layer 151 and the first lower electrode metal connection layer 111 are connected.

[0044] In the existing technology for fabricating non-volatile two-terminal memory cells, during the formation of the second lower electrode metal layer 1511, a first region lower electrode interconnect via 141 is formed in the isolation stack layer 130 using photolithography and etching processes, and the second lower electrode metal layer 1511 is deposited within the first region lower electrode interconnect via 141. During the formation of the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154, photolithography and etching processes are required to etch these layers. Therefore, the formation of the second lower electrode metal layer 1511 and the formation of the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 all require patterned photomask layers formed by corresponding photomasks. Due to the manufacturing process, the fabrication of the lower and upper electrodes of a non-volatile two-ended memory cell typically requires a separate patterned photomask layer, which significantly increases production costs and complicates the fabrication process. Furthermore, this method involves aligning the lower and upper electrodes during fabrication, making the fabrication of non-volatile two-ended memory cells extremely difficult.

[0045] In view of this, the present disclosure provides a fabrication scheme for a non-volatile two-terminal memory cell, which forms a first stacked layer 250 in the first region lower electrode interconnect via 141, thereby achieving the formation of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 of the non-volatile two-terminal memory cell using only one patterned photomask layer, reducing fabrication costs, shortening the fabrication process of the non-volatile two-terminal memory cell, and reducing fabrication difficulty.

[0046] Figure 2 shows an exemplary structural block diagram of a method 200 for fabricating a non-volatile two-terminal memory cell according to some embodiments of this application.

[0047] As shown in Figure 2, in step S210, a lower dielectric layer 120 is provided surrounding the first region lower electrode metal interconnect layer 111 and exposing its upper surface. In step S220, an isolation stack layer 130 is formed that at least covers the first region lower electrode metal interconnect layer 111. In step S230, a first region lower electrode interconnect via 141 is formed in the isolation stack layer 130 based on a patterned photomask layer, the bottom of the first region lower electrode interconnect via 141 being at least partially in contact with the first region lower electrode metal interconnect layer 111. In step S240, a first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 is formed in the first region lower electrode interconnect via 141.

[0048] The following describes in detail the exemplary process flow of the fabrication method 200 for the non-volatile two-ended memory cell based on the fabrication method of Figure 2, in conjunction with the semiconductor cross-sectional structure schematic diagrams shown in Figures 3A-3N.

[0049] Figure 3A shows a schematic diagram of the semiconductor cross-sectional structure of the lower dielectric layer 120 according to an embodiment of this application.

[0050] As shown in Figure 3A, a lower dielectric layer 120 is provided surrounding the lower electrode metal connection layer 111 of the first region under the array region and exposing its upper surface.

[0051] Specifically, the material used for the lower electrode metal connection layer 111 in the first region can be copper. The main advantages of copper compared to other metals are its high electrical and thermal conductivity, corrosion resistance, suitable strength, and ease of processing and forming. In the embodiments of this application, other metals may also be used for the lower electrode metal connection layer 111 as needed, and this is not limited here.

[0052] The lower dielectric layer 120 can be made of materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, or low-k materials. More specifically, the low-k material can be porous silicon dioxide, silicon fluoride glass, etc. In the embodiments of this application, the lower dielectric layer 120 can also be made of other materials according to the actual application scenario and process requirements, and is not limited here.

[0053] In providing the lower dielectric layer 120 surrounding the lower electrode metal interconnect layer 111 of the first region and exposing its upper surface, various known processes can be used to fabricate it, and the embodiments of this application are not limited in this respect. For example, the process of providing the lower dielectric layer 120 surrounding the lower electrode metal interconnect layer 111 of the first region and exposing its upper surface includes: first, providing the lower dielectric layer 120, forming a photoresist layer on the lower dielectric layer 120, selectively exposing the photoresist using an exposure machine, developing to remove the exposed or unexposed portions of the photoresist, etching or depositing patterns in the exposed areas, removing the remaining photoresist, continuing to form the desired grooves by dry etching or wet etching, and forming the remaining portion after etching as the lower dielectric layer 120. Then, depositing a metal material in the grooves. Finally, planarizing the metal material to form the lower electrode metal interconnect layer 111 of the first region, such that the upper surface of the lower electrode metal interconnect layer 111 of the first region is flush with the upper surface of the lower dielectric layer 120. Thus, a lower dielectric layer 120 is obtained, which surrounds the lower electrode metal connection layer 111 of the first region and exposes its upper surface.

[0054] By providing a lower dielectric layer 120 surrounding the first lower electrode metal interconnect layer 111 and exposing its upper surface, the first lower electrode metal interconnect layer 111 and the subsequently formed first lower electrode metal layer 251 are isolated from other unrelated parts in the multilayer metal interconnect structure. This prevents current from flowing in unwanted paths and avoids short circuits and leakage.

[0055] Figure 3B shows a schematic diagram of the semiconductor cross-sectional structure of the deposited isolation stacked layer 130 according to an embodiment of this application.

[0056] As shown in Figure 3B, an isolation stack layer 130 is deposited on the upper surface of the lower electrode metal connection layer 111 and the upper surface of the lower dielectric layer 120 in the first region by a thin film deposition process. The isolation stack layer 130 may include an isolation stack layer 131 and an isolation stack layer 132, and the isolation stack layer 132 covers the upper surface of the isolation stack layer 131.

[0057] In some embodiments of this application, during the formation of the isolation stack 130, the deposited isolation stack 130 must at least cover the first region lower electrode metal interconnect layer 111.

[0058] Specifically, the first layer 131 of the isolation stack can be made of silicon nitride (SiN) thin film or nitro-doped silicon carbide (NDC) thin film, and the second layer 132 of the isolation stack can be made of low-temperature oxide (LTO), silicon dioxide (SiO2), or silicon-rich oxide (SRO), etc. In the embodiments of this application, the first layer 131 and the second layer 132 of the isolation stack can also be made of other materials according to the actual application scenario and process requirements, which are not limited here.

[0059] By depositing an isolation stack 131 and an isolation stack 22, the lower electrode metal connection layer 111 of the first region can be protected to prevent damage to the lower electrode metal connection layer 111 of the first region in subsequent steps.

[0060] Figure 3C shows a schematic cross-sectional view of the semiconductor structure forming the first region lower electrode interconnect via 141 according to an embodiment of this application.

[0061] As shown in Figure 3C, a first region lower electrode interconnect via 141 is etched in the isolation stack layer 130.

[0062] In the embodiments of this application, the first region lower electrode interconnect via 141 is mainly formed by photolithography and can be fabricated using various known processes; the embodiments of this application are not limited in this respect. For example, the fabrication process of the first region lower electrode interconnect via 141 includes: forming photoresist on the upper surface of the isolation stack layer 130, selectively exposing the photoresist using an exposure machine, developing to remove the exposed or unexposed portions of the photoresist, and forming a patterned photomask layer. Then, the first region lower electrode interconnect via 141 is formed by dry etching or wet etching of the isolation stack layer 130 not covered by the patterned photomask layer, and the bottom of the first region lower electrode interconnect via 141 is at least partially in contact with the first region lower electrode metal interconnect layer 111. After forming the first region lower electrode interconnect via 141, the patterned photomask layer is removed.

[0063] In the embodiments of this application, the lower electrode interconnect via 141 in the first region can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum-shaped structure or a trapezoidal structure. Designing the lower electrode interconnect via 141 in the first region as a frustum-shaped structure determines the cross-sectional shape of each layer of the stacked layer subsequently deposited in the lower electrode interconnect via 141 in the first region. This not only ensures the required contact area between each layer of the stacked layer subsequently deposited in the lower electrode interconnect via 141 in the first region, but also effectively reduces the overall volume of the stacked layer.

[0064] In the embodiments of this application, the first region lower electrode interconnect via 141 can also be selected with other structural shapes according to the actual application scenario and process requirements, which are not limited here.

[0065] In the embodiments of this application, the cross-sectional shape of the lower electrode interconnect via 141 in the first region is an inverted trapezoid.

[0066] In the embodiments of this application, the width of the upper base of the inverted trapezoid is greater than the width of the lower base, and the width of the upper base of the inverted trapezoid is greater than... The width of the lower base of the inverted trapezoid is greater than

[0067] In the embodiments of this application, the angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

[0068] In other embodiments of this application, the size of the first region lower electrode interconnect via 141 may also be set based on the size of the first stacked layer 250 that needs to be formed in the first region lower electrode interconnect via 141 and the process used in the deposition of the first stacked layer 250.

[0069] Figure 3D shows a schematic diagram of the semiconductor cross-sectional structure of the deposited first lower electrode metal layer 251 and first switching layer 252 according to an embodiment of this application.

[0070] As shown in Figure 3D, a first lower electrode metal layer 251 and a first switching layer 252 covering the first lower electrode metal layer 251 are sequentially deposited on the upper surface of the isolation stack layer 130, the inner wall of the first region lower electrode interconnect via 141, and the bottom.

[0071] In the embodiments of this application, during the deposition of the first lower electrode metal layer 251, the deposited first lower electrode metal layer 251 and the first switching layer 252 must at least cover the inner wall and bottom of the first region lower electrode interconnect via 141.

[0072] In the embodiments of this application, the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 are electrically connected through the first region lower electrode interconnect via 141.

[0073] In the embodiments of this application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure, and the material used may be one of TiN (titanium nitride), Ti (titanium), Ta (tantalum), W (tungsten), etc. Alternatively, the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 may use the same metal material, thereby ensuring close contact between the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 and avoiding the formation of voids.

[0074] In a preferred embodiment of this application, the first lower electrode metal layer 251 adopts a two-layer structure.

[0075] Figure 3E shows a schematic diagram of the semiconductor cross-sectional structure of the deposited first lower electrode metal layer 251 and first switching layer 252 in a preferred embodiment.

[0076] As shown in Figure 3E, the first lower electrode metal layer 251 includes a first lower electrode metal layer 1 2511 and a first lower electrode metal layer 2512 covering the upper surface of the first lower electrode metal layer 1 2511.

[0077] Specifically, the first lower electrode metal layer 2511 can be made of TiN (titanium nitride), and the first lower electrode metal layer 2512 can be made of W (tungsten). The first lower electrode metal layer 2512 can serve as a connecting layer between the first lower electrode metal layer 2511 and the first switching layer 252. By using W (tungsten) as the material for the first lower electrode metal layer 2512, not only can the thermal conductivity of the first lower electrode metal layer 2512 be ensured, but its resistance can also be kept low, thereby enabling rapid heat conduction, promoting heat dissipation, and reducing heat generation, thus minimizing thermal damage to the fabricated non-volatile two-sided memory cell. Furthermore, using W (tungsten) as the material for the first lower electrode metal layer 2512 also ensures that it has higher inertness, preventing chemical reactions between the first lower electrode metal layer 2512 and the first switching layer 252, and ensuring the thermal stability of the fabricated non-volatile two-sided memory cell.

[0078] In the embodiments of this application, the material of the aforementioned first switching layer 252 may be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), or tantalum oxide (TaO), which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 may also be selected from other materials according to the actual application scenario and process requirements, which are not limited here.

[0079] Figure 3F shows a schematic cross-sectional view of a semiconductor structure in which a sacrificial layer 270 is filled in the first region lower electrode interconnect via 141 according to an embodiment of this application.

[0080] As shown in Figure 3F, a sacrificial layer 270 is filled on the first switching layer 252, and the sacrificial layer 270 covers the upper surface of the first switching layer 252.

[0081] In embodiments of this application, during the formation of the sacrificial layer 270, the formed sacrificial layer 270 is at least made to fill the remaining space of the lower electrode interconnect via 141 in the first region.

[0082] Specifically, the sacrificial layer 270 can be made of carbon coating (SOC, spin on carbon) material. Due to the good fluidity of carbon coating material, the surface of the sacrificial layer 270 is flat, and the sacrificial layer 270 can accurately cover every corner of the remaining space of the lower electrode interconnect via 141 in the first region. It not only effectively isolates the interference of the external environment on the lower electrode interconnect via 141 in the first region, but also acts as a solid barrier to protect the first lower electrode metal layer 251 and the first switching layer 252 in the lower electrode interconnect via 141 in the first region from damage.

[0083] Figure 3G shows a schematic diagram of the semiconductor cross-sectional structure of the etched first lower electrode metal layer 251, first switching layer 252 and sacrificial layer 270 according to an embodiment of this application.

[0084] As shown in Figure 3G, the first lower electrode metal layer 251, the first switching layer 252 and the sacrificial layer 270 outside the region of the first lower electrode interconnect via 141 are etched, and the remaining first lower electrode metal layer 251, the first switching layer 252 and the sacrificial layer 270 stacked in sequence fill the first lower electrode interconnect via 141.

[0085] In the embodiments of this application, a blank etching process is used to etch the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 outside the region of the first lower electrode interconnect via 141. A blank etching process refers to the process of removing all or part of the thin film from the surface of a semiconductor layer. This etching process is in contrast to the aforementioned etching process using a patterned photomask layer, where the pattern of the patterned photomask layer is transferred to the isolation stack layer 130. However, the blank etching process for etching the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 does not involve the use of a patterned photomask layer.

[0086] Specifically, during the etching process of the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 outside the region of the first lower electrode interconnect via 141 using the Blanket Etch process, the entire plane of the structure formed above is etched back without a mask on the etching machine until the first lower electrode metal layer 251 and the first switching layer 252 in the first lower electrode interconnect via 141 are exposed. The etching is then stopped, and the exposed portions of the remaining first lower electrode metal layer 251, the exposed portions of the first switching layer 252, and the upper surface of the sacrificial layer 270 are flush.

[0087] Because the sacrificial layer 270 protects the first lower electrode metal layer 251 and the first switching layer 252, damage to the first lower electrode metal layer 251 and the first switching layer 252 in the first region lower electrode interconnect via 141 can be avoided during the etching process.

[0088] Figure 3H shows a schematic diagram of the semiconductor cross-sectional structure after removing the remaining sacrificial layer 270 according to an embodiment of this application.

[0089] As shown in Figure 3H, the sacrificial layer 270 in the region of the lower electrode interconnect via 141 in the first region is removed.

[0090] In the embodiments of this application, the sacrificial layer 270 in the region of the lower electrode interconnect via 141 in the first region is removed by etching using the Asher process, causing the etching to stop at the surface of the first switching layer 252. The Asher process utilizes plasma reaction etching to precisely etch the corresponding semiconductor material layer while avoiding damage to adjacent structures. The Asher process can etch only specific materials based on the chemical reaction kinetics parameters of different semiconductor materials without affecting other materials, thereby reducing damage to the surface of the corresponding semiconductor material layer.

[0091] Compared to the Blanket Etch process, the Asher process is characterized by its high dependence on material chemical differences. It is not limited to etching in the vertical direction and usually does not require photoresist or hard mask to define patterns or similar methods. It also causes less damage to non-target surfaces and is often used for sacrificial layer removal, surface cleaning and pretreatment. It is especially suitable for advanced processes below 5nm where atomic-level precision is required.

[0092] The sacrificial layer 270 in the region of the lower electrode interconnect via 141 in the first region is removed by etching using the Asher process, so as to avoid damage to the surface of the first switching layer 252.

[0093] Figure 3I shows a schematic diagram of the semiconductor cross-sectional structure of the deposited first upper electrode metal layer 253 according to an embodiment of this application.

[0094] As shown in Figure 3I, a first upper electrode metal layer 253 is deposited on the upper surface of the isolation stack layer 130, the exposed area of ​​the first lower electrode metal layer 251, and the exposed area of ​​the first switching layer 252.

[0095] In the embodiments of this application, during the deposition of the first upper electrode metal layer 253 material, the formed first upper electrode metal layer 253 material must at least fill the remaining space of the first region lower electrode interconnect via 141.

[0096] Figure 3J shows a schematic diagram of a semiconductor cross-sectional structure with a portion of the material removed from the first upper electrode metal layer 253 according to an embodiment of this application.

[0097] As shown in Figure 3J, a planarization process is used to remove part of the material of the first upper electrode metal layer 253, and to make the upper surface of the first upper electrode metal layer 253 in the region of the first lower electrode interconnect via 141 flush with the upper surface of the isolation stack layer 130, thereby forming a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252 and the first upper electrode metal layer 253 in the first lower electrode interconnect via 141.

[0098] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0099] In summary, in the embodiments of this application, after forming the first lower electrode interconnect via 141, it is necessary to deposit a first lower electrode metal layer 251, deposit a first switching layer 252, deposit a sacrificial layer 270, etch using a patternless etching (Blanket ETCH) process, etch using an Asher process, deposit a first upper electrode metal layer 253, and perform planarization, so as to achieve that the upper surface of the first stacked layer 250 is flush with the upper surface of the isolation stacked layer 130.

[0100] In the embodiments of this application, when the first region lower electrode interconnect via 141 is designed as a mesa structure, since the first lower electrode metal layer 251 covers the inner wall and bottom of the first region lower electrode interconnect via 141, the first switching layer 252 covers the first lower electrode metal layer 251, and the first upper electrode metal layer 253 covers the first switching layer 252, the contact area between the layers of the first stacked layer 250 is increased. This improves the contact stability between the first lower electrode metal layer 251 and the first upper electrode metal layer 253 and the first switching layer 252, thereby improving device performance and facilitating the formation of conductive filaments in the fabricated non-volatile two-terminal memory cells.

[0101] In the embodiments of this application, the aforementioned first upper electrode metal layer 253 may be a single-layer or multi-layer structure.

[0102] In a preferred embodiment of this application, the first upper electrode metal layer 253 adopts a two-layer structure.

[0103] Figure 3K shows a schematic diagram of a semiconductor cross-sectional structure in a preferred embodiment of this application, where both the first lower electrode metal layer 251 and the first upper electrode metal layer 253 are two layers.

[0104] As shown in Figure 3K, the first lower electrode metal layer 251 includes a first lower electrode metal layer 2511 and a first lower electrode metal layer 2512 covering the surface of the first lower electrode metal layer 2511, and the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2531.

[0105] Specifically, the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532. The material used in the first upper electrode metal layer 2531 can be AlN (aluminum nitride), and the material used in the first upper electrode metal layer 2532 can be TiN (titanium nitride). Other materials can also be used for the first upper electrode metal layer 2531 and the first upper electrode metal layer 2532; no restrictions are placed here.

[0106] The material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532. The purpose is that, as the upper electrode of the non-volatile two-sided memory cell, the first upper electrode metal layer 2531 provides metal ions to the first switching layer 252, but also prevents the first upper electrode metal layer 2531 from being oxidized and causing adverse effects, such as reduced conductivity. Therefore, the first upper electrode metal layer 2532, which is less prone to oxidation than the first upper electrode metal layer 2531, needs to cover the first upper electrode metal layer 2531, thereby reducing the possibility of the first upper electrode metal layer 2531 being oxidized and ensuring that the characteristics of the non-volatile two-sided memory cell are not affected.

[0107] In one embodiment of this application, after the formation of the first stacked layer 250, a first region upper electrode metal connection layer 191 is formed over the first stacked layer 250.

[0108] Figure 3L shows a schematic cross-sectional view of the semiconductor structure forming the upper dielectric layer 170 and the first region upper electrode metal interconnect layer 191 according to an embodiment of this application.

[0109] As shown in Figure 3L, an upper dielectric layer 170 is deposited on the upper surface of the structure formed above. First region upper electrode interconnect vias are formed in the upper dielectric layer 170 using photolithography and etching processes. A first region upper electrode metal interconnect layer 191 is filled into the first region upper electrode interconnect vias. The bottom of the first region upper electrode metal interconnect layer 191 contacts the upper surface of the first upper electrode metal layer 253. The entire lower surface of the bottom of the first region upper electrode metal interconnect layer 191 contacts the upper surface of the first upper electrode metal layer 253, ensuring sufficient contact between the first region upper electrode metal interconnect layer 191 and the first upper electrode metal layer 253, and preventing a short circuit caused by partial contact between the bottom of the first region upper electrode metal interconnect layer 191 and the upper surface of the first lower electrode metal layer 251.

[0110] Specifically, the upper dielectric layer 170 may be made of silicon nitride (Si3N4). In the embodiments of this application, the upper dielectric layer 170 may also be made of other materials depending on the actual application scenario and process requirements, and no limitation is made here.

[0111] The upper dielectric layer 170 can isolate the first upper electrode metal layer 253 and the first region upper electrode metal connection layer 191 from other parts, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0112] Specifically, the upper electrode metal connection layer 191 of the first region can be made of copper. In the embodiments of this application, the upper electrode metal connection layer 191 of the first region can also be made of other metals as needed, and there is no limitation here.

[0113] In a preferred embodiment of this application, the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2531. When the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532, the bottom of the first region upper electrode interconnect via is in contact with the upper surface of the first upper electrode metal layer 2532.

[0114] Figure 3M shows a schematic cross-sectional view of the semiconductor structure forming the upper dielectric layer 170 and the first region upper electrode metal interconnect layer 191 in a preferred embodiment of this application.

[0115] As shown in Figure 3M, the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2532. When the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532, the bottom of the first region upper electrode metal connecting layer 191 is in contact with the upper surface of the first upper electrode metal layer 2532. The entire lower surface of the bottom of the first region upper electrode metal connecting layer 191 is in contact with the upper surface of the first upper electrode metal layer 2532, ensuring sufficient contact between the first region upper electrode metal connecting layer 191 and the first upper electrode metal layer 2532, and preventing a short circuit caused by partial contact between the bottom of the first region upper electrode metal connecting layer 191 and the upper surface of the first lower electrode metal layer 251.

[0116] By having the bottom of the first upper electrode metal connection layer 191 in contact with the upper surface of the second layer of the first upper electrode metal 2532, it is possible to prevent the first upper electrode metal layer 2531 from being easily oxidized to produce high-limit oxides when it comes into contact with the first upper electrode metal layer 2531, which would affect the conductivity between the first upper electrode metal connection layer 191 and the first upper electrode metal layer 253.

[0117] Figure 3N shows a schematic cross-sectional view of the semiconductor structure forming the non-volatile two-terminal memory cell region and the peripheral circuit region according to an embodiment of this application.

[0118] As shown in Figure 3N, during the fabrication process of the non-volatile two-terminal memory cell of this application embodiment, a second lower electrode metal connection layer 112 and a second upper electrode metal connection layer 192 of the peripheral circuit region can also be generated.

[0119] Specifically, in providing a lower dielectric layer 120 surrounding the first region lower electrode metal connection layer 111 and exposing its upper surface, a second region lower electrode metal connection layer 112 for the peripheral circuit region is also provided. The second region lower electrode metal connection layer 112 for the peripheral circuit region is also surrounded by the lower dielectric layer 120, and its upper surface is exposed.

[0120] The structure, materials and preparation process of the second lower electrode metal connection layer 112 in the peripheral circuit area can be the same as those of the first lower electrode metal connection layer 111, and will not be described in detail here.

[0121] Specifically, the isolation stack layer 130 and the upper dielectric layer 170 can be etched in the peripheral circuit region, stopping the etching at the upper surface of the second region lower electrode metal interconnect layer 112 in the peripheral circuit region, forming a second region upper electrode interconnect via in the peripheral circuit region. Then, a second region upper electrode metal interconnect layer 192 is formed in the second region upper electrode interconnect via in the peripheral circuit region, connecting the second region upper electrode metal interconnect layer 192 and the second region lower electrode metal interconnect layer 112. This completes the fabrication of the semiconductor structure in the peripheral circuit region.

[0122] The structure, materials and preparation process of the second upper electrode metal connection layer 192 in the peripheral circuit area can be the same as those of the first upper electrode metal connection layer 191, and will not be described in detail here.

[0123] Next, based on the fabrication process of the non-volatile two-ended memory cell in FIG2, and in conjunction with the semiconductor cross-sectional structure schematic diagrams shown in FIG4A-FIG4N, an exemplary process flow of the fabrication method 200 of the non-volatile two-ended memory cell using other embodiments of this application will be described in detail.

[0124] The fabrication steps of the non-volatile two-terminal memory cell shown in Figures 4A-4D are the same as those shown in Figures 3A-3D, so they will not be described in detail here.

[0125] Figure 4E shows a schematic diagram of the semiconductor cross-sectional structure of the deposited first upper electrode metal layer 2531 according to an embodiment of this application.

[0126] In embodiments of this application, at least the deposited first upper electrode metal layer 2531 must cover the inner wall and bottom of the first region lower electrode interconnect via 141.

[0127] Figure 4F shows a schematic cross-sectional view of a semiconductor structure in which a sacrificial layer 270 is filled in the first region lower electrode interconnect via 141 according to an embodiment of this application.

[0128] As shown in Figure 4F, a sacrificial layer 270 is formed on the first upper electrode metal layer 2531, such that the sacrificial layer 270 covers the upper surface of the first upper electrode metal layer 2531.

[0129] In embodiments of this application, during the formation of the sacrificial layer 270, the formed sacrificial layer 270 must at least fill the remaining space of the lower electrode interconnect via 141 in the first region.

[0130] Specifically, the sacrificial layer 270 can be made of carbon coating (SOC, spin on carbon) material. Due to the good fluidity of carbon coating material, the surface of the sacrificial layer 270 is flat, and the sacrificial layer 270 can accurately cover every corner of the remaining space of the lower electrode interconnect via 141 in the first region. It not only effectively isolates the interference of the external environment to the lower electrode interconnect via 141 in the first region, but also acts as a solid barrier to protect the first lower electrode metal layer 251, the first switching layer 252 and the first upper electrode metal layer 2531 in the lower electrode interconnect via 141 in the first region from damage.

[0131] Figure 4G shows a schematic diagram of the semiconductor cross-sectional structure of the etched first lower electrode metal layer 251, first switching layer 252, first upper electrode metal layer 2531 and sacrificial layer 270 according to an embodiment of this application.

[0132] As shown in Figure 4G, the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 2531, and the sacrificial layer 270 outside the region of the first lower electrode interconnect via 141 are etched, and the remaining sequentially stacked first lower electrode metal layer 251, first switching layer 252, first upper electrode metal layer 2531, and sacrificial layer 270 fill the first lower electrode interconnect via 141.

[0133] In the embodiments of this application, a blank etching process is used to etch the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 2531, and the sacrificial layer 270 outside the region of the first lower electrode interconnect via 141. A blank etching process refers to the process of removing all or part of the thin film from the surface of a semiconductor layer. This etching process is in contrast to the aforementioned patterned photomask etching process, which transfers the pattern of the photomask to the isolation stack layer 130. In contrast, the blank etching process for etching the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 2531, and the sacrificial layer 270 does not involve the use of a photomask.

[0134] Specifically, during the etching process of the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 2531, and the sacrificial layer 270 outside the region of the lower electrode interconnect via 141 in the first region using a patternless etching process, the entire plane of the structure formed above is etched back without a mask on the etching machine until the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 2531 in the lower electrode interconnect via 141 in the first region are exposed, the etching is stopped, and the upper surfaces of the remaining first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 2531, and the sacrificial layer 270 are flush.

[0135] Because the sacrificial layer 270 protects the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 2531, damage to the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 2531 in the first region lower electrode interconnect via 141 can be avoided during the etching process.

[0136] Figure 4H shows a schematic diagram of the semiconductor cross-sectional structure after removing the remaining sacrificial layer 270 according to an embodiment of this application.

[0137] As shown in Figure 4H, the sacrificial layer 270 in the region of the lower electrode interconnect via 141 in the first region is removed.

[0138] In the embodiments of this application, the Asher process is used to remove the sacrificial layer 270 in the region of the lower electrode interconnect via 141 in the first region, so that the etching stops at the surface of the first upper electrode metal layer 2531. The Asher process utilizes plasma reaction for etching to precisely etch the corresponding semiconductor material layer while avoiding damage to adjacent structures. The Asher process can etch only specific materials based on the chemical reaction kinetics parameters of different semiconductor materials without affecting other materials, thereby reducing damage to the surface of the corresponding semiconductor material layer.

[0139] By using the Asher process to etch and remove the sacrificial layer 270 in the region of the lower electrode interconnect via 141 in the first region, damage to the surface of the first upper electrode metal layer 2531 is avoided.

[0140] Figure 4I shows a schematic diagram of the semiconductor cross-sectional structure of the deposited first upper electrode metal two-layer 2532 according to an embodiment of this application.

[0141] As shown in Figure 4I, a first upper electrode metal layer 2532 is deposited on the upper surface of the isolation stack layer 130, the exposed area of ​​the first lower electrode metal layer 251, the exposed area of ​​the first switching layer 252, and the exposed area of ​​the first upper electrode metal layer 2531.

[0142] In the embodiments of this application, during the deposition of the first upper electrode metal layer 2532, the formed first upper electrode metal layer 2532 must at least fill the remaining space of the first region lower electrode interconnect via 141.

[0143] Figure 4J shows a schematic diagram of the semiconductor cross-sectional structure of an embodiment of this application with a portion of the material removed from the first upper electrode metal layer 2532.

[0144] As shown in Figure 4J, a planarization process is used to remove part of the material of the first upper electrode metal layer 2532, and to make the upper surface of the first upper electrode metal layer 2532 in the region of the first lower electrode interconnect via 141 flush with the upper surface of the isolation stack layer 130. Thus, a first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, a first upper electrode metal layer 2531, and a first upper electrode metal layer 2532 is formed in the first lower electrode interconnect via 141. Furthermore, the first upper electrode metal layer 2531 and the first upper electrode metal layer 2532 form the first upper electrode metal layer 253.

[0145] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0146] In summary, in the embodiments of this application, after forming the first lower electrode interconnect via 141, it is necessary to deposit the first lower electrode metal layer 251, deposit the first switching layer 252, deposit the first upper electrode metal layer 2531, deposit the sacrificial layer 270, etch using a patternless etching (Blanket ETCH) process, etch using an Asher process, deposit the first upper electrode metal layer 2532, and perform planarization, so as to achieve that the upper surface of the first stacked layer 250 is flush with the upper surface of the isolation stacked layer 130.

[0147] In the embodiments of this application, when the first region lower electrode interconnect via 141 is designed as a mesa structure, since the first lower electrode metal layer 251 covers the inner wall and bottom of the first region lower electrode interconnect via 141, the first switching layer 252 covers the first lower electrode metal layer 251, the first upper electrode metal layer 1 2531 covers the first switching layer 252, and the first upper electrode metal layer 2532 covers the first upper electrode metal layer 1 2531, the contact area between the layers of the first stacked layer 250 is increased. This improves the contact stability between the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal layer 1 2531, and the first upper electrode metal layer 2532, thereby improving device performance and facilitating the formation of conductive filaments in the fabricated non-volatile two-terminal memory cells.

[0148] In the embodiments of this application, the aforementioned first lower electrode metal layer 251 may be a multilayer structure.

[0149] In a preferred embodiment of this application, the first lower electrode metal layer 251 adopts a two-layer structure.

[0150] Figure 4K shows a schematic diagram of a semiconductor cross-sectional structure in a preferred embodiment of this application, where both the first lower electrode metal layer 251 and the first upper electrode metal layer 253 are two layers.

[0151] As shown in Figure 4K, the first lower electrode metal layer 251 includes a first lower electrode metal layer 2511 and a first lower electrode metal layer 2512 covering the surface of the first lower electrode metal layer 2511, and the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2531.

[0152] Specifically, the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532. The material used in the first upper electrode metal layer 2531 can be AlN (aluminum nitride), and the material used in the first upper electrode metal layer 2532 can be TiN (titanium nitride). Other materials can also be used for the first upper electrode metal layer 2531 and the first upper electrode metal layer 2532; no restrictions are placed here.

[0153] The material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532. The purpose is that, as the upper electrode of the non-volatile two-sided memory cell, the first upper electrode metal layer 2531 provides metal ions to the first switching layer 252, but also prevents the first upper electrode metal layer 2531 from being oxidized and causing adverse effects, such as reduced conductivity. Therefore, the first upper electrode metal layer 2532, which is less prone to oxidation than the first upper electrode metal layer 2531, needs to cover the first upper electrode metal layer 2531, thereby reducing the possibility of the first upper electrode metal layer 2531 being oxidized and ensuring that the characteristics of the non-volatile two-sided memory cell are not affected.

[0154] In one embodiment of this application, after the formation of the first stacked layer 250, a first region upper electrode metal connection layer 191 is formed over the first stacked layer 250.

[0155] Figure 4L shows a schematic cross-sectional view of the semiconductor structure forming the upper dielectric layer 170 and the first region upper electrode metal interconnect layer 191 according to an embodiment of this application.

[0156] As shown in Figure 4L, an upper dielectric layer 170 is deposited on the upper surface of the structure formed above. First region upper electrode interconnect vias are formed in the upper dielectric layer 170 using photolithography and etching processes. A first region upper electrode metal interconnect layer 191 is then filled into the first region upper electrode interconnect vias. The entire lower surface of the bottom of the first region upper electrode metal interconnect layer 191 contacts the upper surface of the first upper electrode metal layer 253, ensuring sufficient contact between the first region upper electrode metal interconnect layer 191 and the first upper electrode metal layer 253, and preventing a short circuit caused by partial contact between the bottom of the first region upper electrode metal interconnect layer 191 and the upper surface of the first lower electrode metal layer 251.

[0157] Specifically, the upper dielectric layer 170 may be made of silicon nitride (Si3N4). In the embodiments of this application, the upper dielectric layer 170 may also be made of other materials depending on the actual application scenario and process requirements, and no limitation is made here.

[0158] The upper dielectric layer 170 can isolate the first upper electrode metal layer 253 and the first region upper electrode metal connection layer 191 from other parts, thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0159] Specifically, the upper electrode metal connection layer 191 of the first region can be made of copper. In the embodiments of this application, the upper electrode metal connection layer 191 of the first region can also be made of other metals as needed, and there is no limitation here.

[0160] In a preferred embodiment of this application, the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2531. When the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532, the bottom of the first region upper electrode interconnecting via is in contact with the upper surface of the first upper electrode metal layer 2532, that is, the bottom of the first region upper electrode metal connecting layer 191 is in contact with the upper surface of the first upper electrode metal layer 2532.

[0161] Figure 4M shows a schematic diagram of the semiconductor cross-sectional structure of the upper dielectric layer 170 and the first region upper electrode metal connection layer 191 in a preferred embodiment of this application.

[0162] As shown in Figure 4M, the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2531. When the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532, the bottom of the first region upper electrode metal connecting layer 191 is in contact with the upper surface of the first upper electrode metal layer 2532. The entire lower surface of the bottom of the first region upper electrode metal connecting layer 191 is in contact with the upper surface of the first upper electrode metal layer 2532, ensuring sufficient contact between the first region upper electrode metal connecting layer 191 and the first upper electrode metal layer 2532, and preventing a short circuit caused by contact between a portion of the lower surface of the bottom of the first region upper electrode metal connecting layer 191 and the upper surface of the first lower electrode metal layer 251.

[0163] By having the bottom of the first upper electrode metal connection layer 191 in contact with the upper surface of the second layer of the first upper electrode metal 2532, it is possible to prevent the first upper electrode metal layer 2531 from being easily oxidized to produce high-limit oxides when it comes into contact with the first upper electrode metal layer 2531, which would affect the conductivity between the first upper electrode metal connection layer 191 and the first upper electrode metal layer 253.

[0164] Figure 4N shows a schematic diagram of the semiconductor cross-sectional structure forming the non-volatile two-terminal memory cell region and the peripheral circuit region according to an embodiment of this application.

[0165] As shown in Figure 4N, during the fabrication process of the non-volatile two-terminal memory cell of this application embodiment, a second lower electrode metal connection layer 112 and a second upper electrode metal connection layer 192 of the peripheral circuit region can also be fabricated.

[0166] Specifically, in providing a lower dielectric layer 120 surrounding the first region lower electrode metal connection layer 111 and exposing its upper surface, a second region lower electrode metal connection layer 112 for the peripheral circuit region is also provided. The second region lower electrode metal connection layer 112 for the peripheral circuit region is also surrounded by the lower dielectric layer 120, and its upper surface is exposed.

[0167] The structure, materials and preparation process of the second lower electrode metal connection layer 112 in the peripheral circuit area can be the same as those of the first lower electrode metal connection layer 111, and will not be described in detail here.

[0168] Specifically, the isolation stack layer 130 and the upper dielectric layer 170 can be etched in the peripheral circuit region, stopping the etching at the upper surface of the second region lower electrode metal interconnect layer 112 in the peripheral circuit region, forming a second region upper electrode interconnect via in the peripheral circuit region. Then, a second region upper electrode metal interconnect layer 192 is formed in the second region upper electrode interconnect via in the peripheral circuit region, connecting the second region upper electrode metal interconnect layer 192 and the second region lower electrode metal interconnect layer 112. This completes the fabrication of the semiconductor structure in the peripheral circuit region.

[0169] The structure, materials and preparation process of the second upper electrode metal connection layer 192 in the peripheral circuit area can be the same as those of the first upper electrode metal connection layer 191, and will not be described in detail here.

[0170] Finally, based on the fabrication process of the non-volatile two-ended memory cell in Figure 2, and in conjunction with the schematic diagrams of semiconductor cross-sectional structures shown in Figures 5A-5H, an exemplary process flow of the fabrication method 200 of the non-volatile two-ended memory cell using some embodiments of this application will be described in detail.

[0171] The fabrication steps of the non-volatile two-terminal memory cell shown in Figures 5A-5C are the same as those of the non-volatile two-terminal memory cell shown in Figures 3A-3C, so they will not be described in detail here.

[0172] Figure 5D shows a schematic diagram of the semiconductor cross-sectional structure of the deposited first lower electrode metal layer 251, first switching layer 252, and first upper electrode metal layer 253 according to an embodiment of this application.

[0173] As shown in Figure 5D, a first lower electrode metal layer 251, a first switching layer 252 covering the first lower electrode metal layer 251, and a first upper electrode metal layer 253 covering the first switching layer 252 are sequentially deposited on the upper surface of the isolation stack layer 130, the inner wall of the first region lower electrode interconnect via 141, and the bottom. During the deposition of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253, the deposition must at least cover the inner wall and the bottom of the first region lower electrode interconnect via 141.

[0174] When depositing multilayer materials, due to uneven deposition rates in different regions, the amount of material deposited in some regions may be insufficient, resulting in depressions. As shown in Figure 5D, above the lower electrode interconnect via 141 in the first region, the first upper electrode metal layer 253 has a depression facing the lower electrode interconnect via 141 in the first region.

[0175] Figure 5E shows a schematic cross-sectional view of a semiconductor structure with some material removed from the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 according to an embodiment of this application.

[0176] As shown in Figure 5E, a planarization process is used to remove part of the material of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253, so that the exposed portion of the first lower electrode metal layer 251, the exposed portion of the first switching layer 252, and the upper surface of the first upper electrode metal layer 253 are flush with the upper surface of the isolation stack layer 130. As a result, a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 is formed in the first region lower electrode interconnect via 141.

[0177] Specifically, chemical mechanical polishing (CMP) can be used during the planarization process.

[0178] When a portion of the deposit is sunken, planarization is generally used because if etching is used, it is difficult to control the etching progress and other useful parts are easily etched away.

[0179] In summary, in the embodiments of this application, after depositing the first lower electrode metal layer 251, the first switching layer 252 and the first upper electrode metal layer 253, a planarization process is adopted to achieve that the upper surface of the first stacked layer 250 is flush with the upper surface of the isolation stacked layer 130.

[0180] In one embodiment of this application, after the formation of the first stacked layer 250 and before the formation of the first region upper electrode metal connection layer 191 above the first stacked layer 250, a barrier layer 230 is formed on the upper surface of the first stacked layer 250 and the upper surface of the isolation stacked layer 130.

[0181] Figure 5F shows a schematic diagram of the semiconductor cross-sectional structure of the forming barrier layer 230 according to an embodiment of this application.

[0182] As shown in Figure 5F, a barrier layer 230 is formed on the upper surface of the first stacked layer 250 and the upper surface of the isolation stacked layer 130.

[0183] Specifically, the barrier layer may be formed only on the upper surface of the first stacked layer 250, or the barrier layer 230 may be formed on the upper surface of the first stacked layer 250 and a portion of the upper surface of the isolation stacked layer 130. The barrier layer 230 may be a single-layer structure or a multi-layer structure, and may be formed by a thin film deposition process.

[0184] The barrier layer 230 may be made of at least one material selected from amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0185] During the planarization process of the first lower electrode metal layer 251, the first switching layer 252 and the first upper electrode metal layer 253, atoms in each layer may become free and come into contact with other materials in subsequent steps, which may lead to short circuits or leakage. The above-mentioned operation of forming the barrier layer 230 can effectively avoid such risks.

[0186] Figure 5G shows a schematic cross-sectional view of a semiconductor structure in which a first region upper electrode metal interconnect layer 191 is formed after the formation of the barrier layer 230, according to an embodiment of this application.

[0187] As shown in Figure 5G, after forming the barrier layer 230, during the formation of the first region upper electrode metal interconnect layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stacked layer 250 and the upper surface of the isolation stacked layer 130. First region upper electrode interconnect vias are formed in the upper dielectric layer 170 and the barrier layer 230 using photolithography and etching processes, and the first region upper electrode metal interconnect layer 191 is filled into the first region upper electrode interconnect vias. That is, the formed first region upper electrode metal interconnect layer 191 penetrates the barrier layer 230 and its bottom contacts the first upper electrode metal layer 253. The entire lower surface of the bottom of the first region upper electrode metal interconnect layer 191 contacts the upper surface of the first upper electrode metal layer 253, ensuring sufficient contact between the first region upper electrode metal interconnect layer 191 and the first upper electrode metal layer 253, and preventing a short circuit caused by partial contact between the lower surface of the bottom of the first region upper electrode metal interconnect layer 191 and the upper surface of the first lower electrode metal layer 251.

[0188] In some embodiments of this application, the first upper electrode metal layer 253 includes a first upper electrode metal layer 2531 and a first upper electrode metal layer 2532 covering the surface of the first upper electrode metal layer 2531, and the material used in the first upper electrode metal layer 2531 is more easily oxidized than the material used in the first upper electrode metal layer 2532. After the barrier layer 230 is formed, the first region upper electrode metal connecting layer 191 penetrates the barrier layer 230, and its bottom contacts the upper surface of the first upper electrode metal layer 2532.

[0189] Figure 5H shows a schematic cross-sectional view of a semiconductor structure in which a first region upper electrode metal interconnect layer 191 is formed after the formation of the barrier layer 230, according to an embodiment of this application.

[0190] As shown in Figure 5H, after forming the barrier layer 230, during the formation of the first region upper electrode metal interconnect layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stacked layer 250 and the upper surface of the isolation stacked layer 130. First region upper electrode interconnect vias are formed in the upper dielectric layer 170 and the barrier layer 230 using photolithography and etching processes. The first region upper electrode metal interconnect layer 191 is then filled into these vias, ensuring that the formed first region upper electrode metal interconnect layer 191 penetrates the barrier layer 230, and its bottom contacts the upper surface of the first upper electrode metal layer 2532. The entire lower surface of the bottom of the first region upper electrode metal interconnect layer 191 contacts the upper surface of the first upper electrode metal layer 2532, ensuring sufficient contact between the first region upper electrode metal interconnect layer 191 and the first upper electrode metal layer 2532, and preventing a short circuit caused by partial contact between the lower surface of the bottom of the first region upper electrode metal interconnect layer 191 and the upper surface of the first lower electrode metal layer 251.

[0191] Similarly, in the process of preparing the non-volatile two-terminal memory cell of the present application embodiment, a second lower electrode metal connection layer 112 and a second upper electrode metal connection layer 192 of the peripheral circuit region can also be generated.

[0192] Specifically, in providing a lower dielectric layer 120 surrounding the first region lower electrode metal connection layer 111 and exposing its upper surface, a second region lower electrode metal connection layer 112 for the peripheral circuit region is also provided. The second region lower electrode metal connection layer 112 under the peripheral circuit region is also surrounded by the lower dielectric layer 120, and its upper surface is exposed.

[0193] The structure, materials and preparation process of the second lower electrode metal connection layer 112 in the peripheral circuit area can be the same as those of the first lower electrode metal connection layer 111, and will not be described in detail here.

[0194] Specifically, the isolation stack layer 130, the stop layer 230, and the upper dielectric layer 170 can be etched in the peripheral circuit region, penetrating the stop layer 230 and stopping at the upper surface of the second region lower electrode metal interconnect layer 112 in the peripheral circuit region, forming a second region upper electrode interconnect via in the peripheral circuit region. Then, a second region upper electrode metal interconnect layer 192 is formed in the second region upper electrode interconnect via in the peripheral circuit region, connecting the second region upper electrode metal interconnect layer 192 and the second region lower electrode metal interconnect layer 112. Thus, the semiconductor structure fabrication of the peripheral circuit region is completed.

[0195] The structure, materials and preparation process of the second upper electrode metal connection layer 192 in the peripheral circuit area can be the same as those of the first upper electrode metal connection layer 191, and will not be described in detail here.

[0196] In summary, by utilizing the fabrication scheme for the non-volatile two-sided memory cell provided above, this disclosed embodiment, through forming the first stacked layer 250 in the first region's lower electrode interconnect via 141, can achieve the fabrication of the first lower electrode metal layer 251 and the first upper electrode metal layer 253 of the non-volatile two-sided memory cell using only one patterned photomask layer. This shortens the fabrication time, reduces the cost of the non-volatile two-sided memory cell, and simplifies the process flow. Furthermore, since only one patterned photomask layer is used, i.e., alignment is only required when forming the first region's lower electrode interconnect via 141, and alignment is not required when forming the second stacked layer (i.e., the stacking of the second lower electrode metal layer 1511, the second lower electrode metal layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154). This reduces the complexity of the process, avoids problems such as contact resistance changes caused by misalignment, and improves the stability and reliability of the fabricated non-volatile two-sided memory cell. Furthermore, by forming a first stacked layer 250 in the first region lower electrode interconnect via 141, the height of the first stacked layer 250 is reduced compared to the second stacked layer in the prior art. This makes it easier for the first stacked layer 250 formed in this application to be embedded between the first region lower electrode metal interconnect layer 111 and the first region upper electrode metal interconnect layer 191. As a result, the integration density of the formed non-volatile two-terminal memory cell can be improved, the current path can be shortened, the resistance can be reduced, and the performance of the formed non-volatile two-terminal memory cell can be improved.

[0197] This embodiment provides a non-volatile two-terminal memory cell, which includes: a lower dielectric layer 120 surrounding a first region lower electrode metal interconnect layer 111 and exposing its upper surface; an isolation stack layer 130 at least covering the first region lower electrode metal interconnect layer 111; a first region lower electrode interconnect via 141 formed in the isolation stack layer 130, and the bottom of the first region lower electrode interconnect via 141 at least partially contacting the first region lower electrode metal interconnect layer 111; and a first stack layer 250 located within the first region lower electrode interconnect via 141, the first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253.

[0198] This embodiment also provides a non-volatile two-ended memory cell, which includes: a barrier layer 230 covering at least the upper surface of the first stacked layer 250, and a first region upper electrode metal connection layer 191 penetrating the barrier layer 230, with the bottom of the first region upper electrode metal connection layer 191 contacting the upper surface of the first upper electrode metal layer 253. The entire lower surface of the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, ensuring sufficient contact between the first region upper electrode metal connection layer 191 and the first upper electrode metal layer 253, and preventing a short circuit caused by partial contact between the bottom of the first region upper electrode metal connection layer 191 and the upper surface of the first lower electrode metal layer 251.

[0199] In one embodiment of this application, the aforementioned non-volatile two-terminal storage cell can be prepared using the preparation method 200 of the non-volatile two-terminal storage cell of any of the preceding embodiments.

[0200] After obtaining the non-volatile two-terminal memory cell, a second lower electrode metal connection layer 112 and a second upper electrode metal connection layer 192 of the peripheral circuit region can be fabricated to obtain a further semiconductor device.

[0201] For specific structural diagrams, please refer to Figures 3A-3N, 4A-4N, and 5A-5H, which will not be described further here.

[0202] The aforementioned non-volatile two-ended memory cell saves on patterned photomask layers, and the manufacturing method facilitates the formation and alignment of the lower electrode interconnect vias and upper electrode interconnect vias of the non-volatile two-ended memory cell. Therefore, it can shorten the fabrication process of the non-volatile two-ended memory cell, reduce the fabrication difficulty, and thus reduce the fabrication cost.

[0203] This embodiment provides a memory that includes one or more non-volatile dual-ended memory cells from any of the foregoing embodiments. These non-volatile dual-ended memory cells can be arranged in a specific manner to store instructions or data. By employing the aforementioned non-volatile dual-ended memory cells, the memory yield can be improved, and the manufacturing cost of the memory can be reduced.

[0204] This embodiment provides an electronic device that includes the memory of this application embodiment. The electronic device may also include a processor; wherein the processor is configured to execute program instructions, and the memory is configured to store the program instructions. When the program instructions are loaded and executed by the processor, the electronic device performs execution according to a specific method. By employing the aforementioned memory, the possibility of memory quality problems in the electronic device can be reduced, and the hardware cost of the electronic device can be lowered.

[0205] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for fabricating a non-volatile two-terminal storage cell, characterized in that, The preparation method includes: A lower dielectric layer (120) is provided surrounding the lower electrode metal connection layer (111) of the first region and having its upper surface exposed; An isolation stack layer (130) is formed that at least covers the lower electrode metal connection layer (111) of the first region; Based on the patterned photomask layer forming a first region lower electrode interconnect via (141) in the isolation stack layer (130), the bottom of the first region lower electrode interconnect via (141) is at least partially in contact with the first region lower electrode metal connection layer (111); A first stacked layer (250) comprising a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) is formed in the lower electrode interconnect via (141) of the first region.

2. The preparation method according to claim 1, characterized in that, The upper surface of the first stacked layer (250) is flush with the upper surface of the isolation stacked layer (130).

3. The preparation method according to claim 2, characterized in that, A first stacked layer (250) flush with the upper surface of the isolation stacked layer (130) is formed in the lower electrode interconnect via (141) of the first region, comprising: At least the inner wall and bottom of the lower electrode interconnect via (141) in the first region are formed the first lower electrode metal layer (251) and the first switching layer (252) covering the first lower electrode metal layer (251); A sacrificial layer (270) is formed on the first switching layer (252) such that the sacrificial layer (270) at least fills the remaining space of the lower electrode interconnect via (141) in the first region; Remove the first lower electrode metal layer (251), the first switching layer (252) and the sacrificial layer (270) outside the region of the first lower electrode interconnect via (141), and remove the sacrificial layer (270) in the region of the first lower electrode interconnect via (141). A first upper electrode metal layer (253) is formed in the region of the first region lower electrode interconnect via (141) where the sacrificial layer (270) has been removed, such that the upper surface of the first upper electrode metal layer (253) is flush with the upper surface of the isolation stack layer (130).

4. The preparation method according to claim 3, characterized in that, During the removal of the first lower electrode metal layer (251), the first switching layer (252), and the sacrificial layer (270) outside the region of the first lower electrode interconnect via (141), a patternless etching process or a CMP process is employed.

5. The preparation method according to claim 3, characterized in that, The Asher process is used in the process of removing the sacrificial layer (270) in the region of the lower electrode interconnect via (141) of the first region.

6. The preparation method according to claim 3, characterized in that, After the first upper electrode metal layer (253) is formed, a first region upper electrode metal connection layer (191) is formed with its bottom in contact with the upper surface of the first upper electrode metal layer (253).

7. The preparation method according to claim 2, characterized in that, The first upper electrode metal layer (253) includes a first upper electrode metal layer 1 (2531) and a first upper electrode metal layer 2 (2532), wherein the first upper electrode metal layer 1 (2531) is located between the first switching layer (252) and the first upper electrode metal layer 2 (2532); A first stacked layer (250) flush with the upper surface of the isolation stacked layer (130) is formed in the lower electrode interconnect via (141) of the first region, comprising: At least on the inner wall and bottom of the lower electrode interconnect via (141) in the first region, a first lower electrode metal layer (251), a first switching layer (252) covering the first lower electrode metal layer (251), and a first upper electrode metal layer (2531) covering the first switching layer (252) are formed. A sacrificial layer (270) is formed on the first upper electrode metal layer (2531) such that the sacrificial layer (270) at least fills the remaining space of the lower electrode interconnect via (141) in the first region; Remove the first lower electrode metal layer (251), the first switching layer (252), the first upper electrode metal layer (2531) and the sacrificial layer (270) outside the region of the first lower electrode interconnect via (141), and remove the sacrificial layer (270) in the region of the first lower electrode interconnect via (141). The first upper electrode metal layer (2532) is formed in the region of the first region lower electrode interconnect via (141) where the sacrificial layer (270) has been removed, such that the upper surface of the first upper electrode metal layer (2532) is flush with the upper surface of the isolation stack layer (130).

8. The preparation method according to claim 7, characterized in that, During the removal of the first lower electrode metal layer (251), the first switching layer (252), the first upper electrode metal layer (2531), and the sacrificial layer (270) outside the region of the first lower electrode interconnect via (141), a patternless etching process or a CMP process is used.

9. The preparation method according to claim 7, characterized in that, The Asher process is used in the process of removing the sacrificial layer (270) in the region of the lower electrode interconnect via (141) of the first region.

10. The preparation method according to claim 7, characterized in that, After the first upper electrode metal layer (2532) is formed, a first region upper electrode metal connection layer (191) is formed with its bottom in contact with the upper surface of the first upper electrode metal layer (2532).

11. The preparation method according to claim 2, characterized in that, After the first stacked layer (250) is formed, a barrier layer (230) is formed that at least covers the upper surface of the first stacked layer (250).

12. The preparation method according to claim 11, characterized in that, After the barrier layer (230) is formed, a first region upper electrode metal connection layer (191) is formed that penetrates the barrier layer (230) and whose bottom contacts the upper surface of the first upper electrode metal layer (253).

13. The preparation method according to claim 1, characterized in that, The first upper electrode metal layer (253) includes a first upper electrode metal layer 1 (2531) and a first upper electrode metal layer 2 (2532) covering the surface of the first upper electrode metal layer 1 (2531), wherein the material used in the first upper electrode metal layer 1 (2531) is more easily oxidized than the material used in the first upper electrode metal layer 2 (2532).

14. The preparation method according to claim 1, characterized in that, The first lower electrode metal layer (251) includes a first lower electrode metal layer 1 (2511) and a first lower electrode metal layer 2 (2512) covering the surface of the first lower electrode metal layer 1 (2511).

15. The preparation method according to claim 1, characterized in that, The cross-sectional shape of the lower electrode interconnect via (141) in the first region is an inverted trapezoid.

16. The preparation method according to claim 15, characterized in that, The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than... The width of the lower base of the inverted trapezoid is greater than 17. The preparation method according to claim 15, characterized in that, The angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

18. A non-volatile two-ended storage cell, characterized in that, The non-volatile two-end storage unit includes: A lower dielectric layer (120) surrounds the first region lower electrode metal connection layer (111) and exposes its upper surface; An isolation stack layer (130) is provided, which at least covers the lower electrode metal connection layer (111) of the first region; A first region lower electrode interconnect via (141) is formed in the isolation stack layer (130), and the bottom of the first region lower electrode interconnect via (141) is at least partially in contact with the first region lower electrode metal connection layer (111). The first stacked layer (250) is located within the lower electrode interconnect via (141) of the first region. The first stacked layer (250) includes a first lower electrode metal layer (251), a first switching layer (252), and a first upper electrode metal layer (253).

19. The non-volatile two-terminal storage unit according to claim 18, characterized in that, The non-volatile two-ended storage unit also includes: A barrier layer (230) at least covers the upper surface of the first stacked layer (250), and The first region upper electrode metal connection layer (191) penetrates the barrier layer (230), and the bottom of the first region upper electrode metal connection layer (191) is in contact with the upper surface of the first upper electrode metal layer (253).

20. A memory, characterized in that, The memory includes one or more non-volatile two-ended memory cells as described in claim 18 or 19.

21. An electronic device, characterized in that, The electronic device includes the memory of claim 20.

Images