Memory connector, motherboard, and server

Abstract

A memory connector, a motherboard, and a server. The memory connector comprises: a first memory slot (1), a side wall of the first memory slot (1) being provided with a plurality of first memory connection pins (11) electrically connected to a memory module; a second memory slot (2), a side wall of the second memory slot (2) being provided with a plurality of second memory connection pins (21) electrically connected to the memory module; and a plurality of soldering pins (3) located on a bottom surface (A) of the memory connector and configured to be electrically connected to pads of a printed circuit board. The soldering pins (3) comprise first soldering pins (31) and second soldering pins (32). First memory connection pins (11) and second memory connection pins (21) transmitting a same signal are electrically connected to a same first soldering pin (31). First memory connection pins (11) and second memory connection pins (21) transmitting different signals are respectively electrically connected to different second soldering pins (32) in a one-to-one correspondence. The bottom surface (A) of the memory connector comprises at least one soldering pin vacant region (S1), the area of the soldering pin vacant region (S1) being larger than the area of at least two soldering pins (3).

Description

A memory connector, motherboard, and server

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510382532.4, filed on March 28, 2025, entitled “A memory connector, motherboard and server”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of server technology, and in particular to a memory connector, a motherboard, and a server. Background Technology

[0004] In the development of electronic products, memory modules are indispensable components in large-scale storage and intelligent computing products. As the computing power of electronic products gradually increases, the number of memory modules used will further increase, and the scale of operations will expand. Furthermore, the functionality of the main processing unit is enhanced, enabling it to support an increasing number of memory channels. To meet the enormous demand for memory capacity, the use of two memory modules per channel is becoming increasingly common in related technologies.

[0005] As computing speed and storage capacity increase, the number of slots on the connector for inserting memory modules will further increase. Data signal traces shared by two memory modules need to be connected through traces on the printed circuit board, which increases the number of pads, traces and vias on the printed circuit board, occupies more surface space on the printed circuit board, and the connector also needs twice the number of pins.

[0006] Application content

[0007] This application provides a memory connector, motherboard, and server that reduces the number of first solder pins, as well as the number of pads, traces, and vias on the printed circuit board, improving signal quality and freeing up design space for the printed circuit board and memory connector.

[0008] In a first aspect, this application provides a memory connector, including: a first memory slot; the side wall of the first memory slot is provided with a plurality of first memory connection pins electrically connected to a memory module;

[0009] The second memory slot; the side wall of the second memory slot is provided with multiple second memory connection pins that are electrically connected to the memory module; multiple solder pins; located on the bottom surface of the memory connector, for electrical connection with the solder pads on the printed circuit board;

[0010] The soldering pins include a first soldering pin and a second soldering pin. The first memory connection pin and the second memory connection pin that transmit the same signal are electrically connected to the same first soldering pin. The first memory connection pin and the second memory connection pin that transmit different signals are electrically connected to different second soldering pins respectively.

[0011] The bottom surface of the memory connector includes at least one solder pin gap area, the area of ​​which is larger than the area of ​​at least two solder pins.

[0012] In a second aspect, this application also provides a printed circuit board, including: a printed circuit board including a plurality of pads, the plurality of pads being located on the top surface of the printed circuit board, the pads being used for electrical connection one-to-one with the solder pins of the memory connector as in the first aspect;

[0013] The pads include multiple first pads and multiple second pads, the first pads being electrically connected to first solder pins, and the second pads being electrically connected to second solder pins;

[0014] The top surface of the printed circuit board includes a pad void area, the area of ​​which is larger than the area of ​​at least two pads; wherein, the first memory connection pin and the second memory connection pin that transmit the same signal are electrically connected to the same first solder pin, and the first memory connection pin and the second memory connection pin that transmit different signals are electrically connected to different second solder pins respectively.

[0015] Thirdly, this application also provides a server, including the memory connector provided in the first aspect and the printed circuit board provided in the second aspect.

[0016] The memory connector, motherboard, and server provided in this application embodiment electrically connect the first memory connection pin and the second memory connection pin that transmit the same signal to the same first solder pin. This eliminates the need to set separate first solder pins for the first memory connection pin and the second memory connection pin that transmit the same signal on the bottom surface of the memory connector, reducing the number of first solder pins. The positions of the deleted first solder pins serve as solder pin vacancy areas on the bottom surface of the memory connector, leaving more space on the bottom surface of the memory connector. The number of pads on the top surface of the printed circuit board also decreases with the reduction in the number of first solder pins, thereby reducing the number of vias and trace density on the printed circuit board, increasing the design space on the printed circuit board, and improving signal quality. The area of ​​the solder pin gap is larger than that of at least two solder pins. By expanding the area of ​​the solder pin gap, it can serve as a heat dissipation channel, facilitating airflow around the memory connector, improving heat dissipation, preventing heat buildup on the memory connector, and providing more space for wiring. This reduces crossovers and overlaps, simplifies wiring, and consequently lowers the current density on the memory connector, preventing burnout and improving its reliability and safety, ensuring stable operation. Furthermore, merging two independent memory connectors on a channel into a single unit results in a single connector occupying the same area as the two individual connectors. This eliminates the need for memory module adjustments, maintaining compatibility with existing installation methods, and keeping the connector height unchanged. In single-channel dual-memory-module applications, this integrated connector design helps differentiate the memory from single-channel single-memory-module applications, facilitating correct memory module insertion for users. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a bottom view of a memory connector provided in an embodiment of this application;

[0019] Figure 2 is a cross-sectional structural diagram of the memory connector shown in Figure 1;

[0020] Figure 3 is a bottom view of another memory connector provided in an embodiment of this application;

[0021] Figure 4 is a cross-sectional structural diagram of the memory connector shown in Figure 3;

[0022] Figure 5 is a bottom view of another memory connector provided in an embodiment of this application;

[0023] Figure 6 is a cross-sectional structural diagram of the memory connector shown in Figure 5;

[0024] Figure 7 is a schematic diagram of another cross-sectional structure of the memory connector shown in Figure 1;

[0025] Figure 8 is a schematic diagram of another cross-sectional structure of the memory connector shown in Figure 3;

[0026] Figure 9 is a schematic diagram of another cross-sectional structure of the memory connector shown in Figure 5;

[0027] Figure 10 is a top view of a printed circuit board according to an embodiment of this application;

[0028] Figure 11 is a top view of another printed circuit board structure provided in an embodiment of this application;

[0029] Figure 12 is a top view of another printed circuit board provided in an embodiment of this application.

[0030] The correspondence between the reference numerals and the structural names in the attached drawings is as follows: 1. First memory slot; 2. Second memory slot; 3. Solder pin; 4. Connecting lead; 5. Gating device; 6. Pad; 11. First memory connection pin; 21. Second memory connection pin; 31. First solder pin; 32. Second solder pin; 41. First connecting lead; 42. Second connecting lead; 43. Third connecting lead; 44. Fourth connecting lead; 61. First pad; 62. Second pad; 101. First sidewall; 102. Second sidewall; 201. Third sidewall; 202. Fourth sidewall; 111, First sub-pin; 112, Second sub-pin; 211, Third sub-pin; 212, Fourth sub-pin; 311, First common solder pin; 312, Second common solder pin; S1, Solder pin void area; S2, Pad void area; S11, First sub-solder pin void area; S12, Second sub-solder pin void area; S13, Third sub-solder pin void area; S14, Fourth sub-solder pin void area; S21, First sub-pad void area; S22, Second sub-pad void area; S23, Third sub-pad void area; S24, Fourth sub-pad void area. Detailed Implementation

[0031] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0032] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0033] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] In related technologies, as the computing speed and storage capacity increase, the number of slots on the connector for inserting memory modules will further increase. Data signal traces shared by two memory modules need to be connected through traces on the printed circuit board, which increases the pin density, number of traces and vias on the printed circuit board, occupies more surface space on the printed circuit board, and the connector also needs twice the number of pins.

[0035] To address the aforementioned problems, this application provides a memory connector. Figure 1 is a bottom view of a memory connector provided in this application embodiment; Figure 2 is a cross-sectional view of the memory connector shown in Figure 1; Figure 3 is a bottom view of another memory connector provided in this application embodiment; Figure 4 is a cross-sectional view of the memory connector shown in Figure 3; Figure 5 is a bottom view of another memory connector provided in this application embodiment; and Figure 6 is a cross-sectional view of the memory connector shown in Figure 5. Referring to Figures 1 to 6, the memory connector includes: a first memory slot 1; the side wall of the first memory slot 1 is provided with a plurality of first memory connection pins 11 electrically connected to the memory module; a second memory slot 2; the side wall of the second memory slot 2 is provided with a plurality of second memory connection pins 21 electrically connected to the memory module; a plurality of solder pins 3, located on the bottom surface A of the memory connector, for electrically connecting to the pads of the printed circuit board; the solder pins 3 include first solder pins 31 and second solder pins 32, the first memory connection pins 11 and second memory connection pins 21 transmitting the same signal are electrically connected to the same first solder pin 31, the first memory connection pins 11 and second memory connection pins 21 transmitting different signals are respectively electrically connected to different second solder pins 32 in a one-to-one correspondence; the bottom surface A of the memory connector includes at least one solder pin vacancy area S1, the area of ​​the solder pin vacancy area S1 is larger than the area of ​​at least two solder pins 3.

[0036] Figures 1 to 6 distinguish the first solder pin 31 and the second solder pin 32 using different filling patterns. Figure 1 shows four solder pin vacancy areas S1, while Figures 3 and 5 show two solder pin vacancy areas S1.

[0037] It should be noted that the number of the first solder pin 31, the second solder pin 32, and the solder pin gap area S1 is not limited in this embodiment of the application, as long as it can meet the usage requirements of the memory connector.

[0038] In some embodiments, referring to Figures 2, 4, and 6, a memory module (not shown in the figures) inserted into the first memory slot 1 is electrically connected to the first memory connection pin 11 provided on the side wall of the first memory slot 1 via the gold fingers on the memory module, and / or, a memory module (not shown in the figures) inserted into the second memory slot 2 is electrically connected to the second memory connection pin 21 provided on the side wall of the second memory slot 2 via the gold fingers on the memory module.

[0039] The bottom surface A of the memory connector may include, for example, multiple solder pins 3. These solder pins 3 are used for electrical connection to pads on the printed circuit board. The common signal, including the data signal and the corresponding ground signal, is the same signal transmitted by the first memory connection pin 11 and the second memory connection pin 21. In this embodiment, the first memory connection pin 11 and the second memory connection pin 21, which transmit the same signal, are electrically connected to the same first solder pin 31 to achieve the transmission of the same signal on the first memory connection pin 11 and the second memory connection pin 21. Therefore, it is unnecessary to provide separate first solder pins 31 for the first memory connection pin 11 and the second memory connection pin 21 that transmit the same signal, thus reducing the number of first solder pins 31. The position of the removed first solder pins 31 serves as the solder pin vacancy area S1 on the bottom surface A of the memory connector.

[0040] Figure 1 shows the first and second sub-soldering pin vacancy areas S11 and S12, which overlap with the orthographic projection of the second soldering pin 32 in the second row on the bottom surface A of the memory connector. The third and fourth sub-soldering pin vacancy areas S13 and S14 overlap with the orthographic projection of the second soldering pin 32 in the third row on the bottom surface A of the memory connector, thus expanding the area of ​​the soldering pin vacancy area S1. The area of ​​the soldering pin vacancy area S1 is larger than the area of ​​at least two soldering pins 3. By expanding the area of ​​the soldering pin vacancy area S1, it can serve as a heat dissipation channel, facilitating airflow around the memory connector, improving heat dissipation, preventing heat accumulation on the memory connector, and providing more space for wiring on the memory connector. This reduces the crossing and overlap between wirings, lowers wiring difficulty, and consequently reduces the current density on the memory connector, preventing problems such as memory connector burnout. This improves the reliability and safety of the memory connector and ensures its stable operation.

[0041] Furthermore, the overall memory connector occupies the same device area as two separate memory connectors, eliminating the need for adjustments to the memory modules and maintaining compatibility with existing installation methods. The height of the memory connector remains unchanged, preventing any new height-related issues. In applications with dual memory modules connected in a single channel, the integrated memory connector helps differentiate the application from one with a single memory module connected in a single channel, facilitating correct insertion of the memory module by the user.

[0042] In some embodiments, non-common signals such as address signals and control signals are different signals transmitted by the first memory connection pin 11 and the second memory connection pin 21. In this case, the first memory connection pin 11 and the second memory connection pin 21 that transmit different signals are respectively electrically connected to different second solder pins 32 in a one-to-one correspondence, so as to realize the transmission of different signals on the first memory connection pin 11 and the second memory connection pin 21.

[0043] It should be noted that the memory module can be a DIMM (Dual Inline Memory Module) memory module, or other types of memory modules. This application embodiment does not limit this.

[0044] In this embodiment, the first memory connection pin 11 and the second memory connection pin 21, which transmit the same signal, are electrically connected to the same first solder pin 31 to achieve the transmission of the same signal on the first memory connection pin 11 and the second memory connection pin 21. This eliminates the need to provide separate first solder pins 31 for the first memory connection pin 11 and the second memory connection pin 21, reducing the number of first solder pins 31. The location of the removed first solder pins 31 serves as the solder pin vacancy area S1 on the bottom surface A of the memory connector. The area of ​​the solder pin vacancy area S1 is greater than at least The area of ​​the two solder pins 3 is expanded by extending the area of ​​the solder pin gap S1, allowing S1 to serve as a heat dissipation channel. This facilitates airflow around the memory connector, improving heat dissipation and preventing heat buildup. Furthermore, the solder pin gap S1 provides more space for wiring on the memory connector, reducing crossovers and overlaps, simplifying wiring, and consequently lowering the current density. This helps prevent connector burnout and improves reliability and safety, ensuring stable operation. In addition, integrating two independent memory connectors into a single unit results in a single connector occupying the same area as the two individual connectors. This eliminates the need for adjustments to the memory module, maintaining compatibility with existing installation methods, and keeping the connector height unchanged. In single-channel dual-memory-module applications, this integrated connector design helps differentiate the memory from single-channel single-memory-module applications, facilitating correct memory module insertion.

[0045] In some embodiments, in conjunction with Figures 2, 4 and 6, the memory connector further includes: multiple connecting leads 4; and a first solder pin 31 is electrically connected to a corresponding first memory connection pin 11 and a second memory connection pin 21 via the connecting leads 4.

[0046] In some embodiments, referring to Figures 2, 4, and 6, the memory connector may further include multiple connecting leads 4, with the first solder pin 31 electrically connected to the corresponding first memory connection pin 11 and second memory connection pin 21 via the connecting leads 4. This transfers the traces connecting pads transmitting the same signal on the printed circuit board to the memory connector, thereby saving trace density and via count on the printed circuit board, increasing design space on the printed circuit board, and improving signal quality.

[0047] In some embodiments, as shown in FIG1, the welding pin vacancy area S1 is located on both sides of the first welding pin 31.

[0048] In some embodiments, as shown in FIG1, the solder pin vacancy area S1 can be distributed on the upper and lower sides of the first solder pin 31, thereby reducing the pin density on both sides of the first solder pin 31 and leaving design space for the positions of the first solder pin 31 of the memory connector.

[0049] In some embodiments, referring to Figures 1 and 2, the first memory slot 1 includes opposing first sidewalls 101 and second sidewalls 102; the second memory slot 2 includes opposing third sidewalls 201 and fourth sidewalls 202; a plurality of first memory connection pins 11 are disposed on the first sidewalls 101 and second sidewalls 102; a plurality of second memory connection pins 21 are disposed on the third sidewalls 201 and fourth sidewalls 202; the second sidewall 102 is located between the first sidewall 101 and the third sidewall 201; a plurality of first solder pins 31 are located on the bottom surface A of the memory connector between the second sidewall 102 and the third sidewall 201.

[0050] In some embodiments, referring to Figures 1 and 2, by setting the first solder pin 31 on the bottom surface A of the memory connector between the second sidewall 102 and the third sidewall 201, the solder pin vacancy area S1 is located on both sides of the first solder pin 31, reducing the pin density on both sides of the first solder pin 31 and leaving design space for the bottom surface A of the memory connector on both sides of the first solder pin 31 of the memory connector.

[0051] In some embodiments, as shown in FIG2, the connecting leads 4 electrically connected to the same first welding pin 31 are of equal length.

[0052] In some embodiments, as shown in FIG2, by setting the lengths of the connecting leads 4 electrically connected to the same first solder pin 31 to be equal, a symmetrical connection of the first memory connection pin 11 and the second memory connection pin 21 is realized inside the memory connector. In scenarios where memory modules are inserted into the first memory slot 1 and the second memory slot 2, the signal quality of the first memory connection pin 11 and the signal quality of the second memory connection pin 21 are made as equal as possible. That is, the signal quality of the memory module inserted into the first memory slot 1 and the signal quality of the memory module inserted into the second memory slot 2 are made as equal as possible, so as to avoid signal deviation problems and ensure the consistency of signal quality of the two memory modules.

[0053] It is understood that the equal connection lengths referred to in the embodiments of this application mean equal connection lengths within the process error range. In some embodiments, the process error range can be set according to the actual use of the memory connector, and the embodiments of this application do not limit this.

[0054] In some embodiments, referring to Figures 3 and 5, the weld pin vacancy area S1 is located on the same side of the first weld pin 31.

[0055] Figure 3 shows that the solder pin vacancy area S1 is located on the lower side of the first solder pin 31, and Figure 5 shows that the solder pin vacancy area S1 is located on the upper side of the first solder pin 31. This helps to concentrate the solder pin vacancy area S1 on one side, leaving more design space on the other side of the first solder pin 31 and reducing the design density of the solder pins 3 of the memory connector.

[0056] In some embodiments, referring to Figures 3 and 4, the length of the connection lead 4 electrically connected to the first memory connection pin 11 is less than the length of the connection lead 4 electrically connected to the second memory connection pin 21.

[0057] In some embodiments, referring to Figures 3 and 4, the length of the connecting lead 4 electrically connected to the first memory connection pin 11 is less than the length of the connecting lead 4 electrically connected to the second memory connection pin 21. The first memory slot 1 can be located close to the main processing unit (CPU (Center Processing Unit), GPU (Graphics Processing Unit), DPU (Data Processing Unit), etc.) in the server. The distance from which the main processing unit transmits signals to the memory module in the first memory slot 1 is less than the distance from which the main processing unit transmits signals to the memory module in the second memory slot 2. In the case of a partial memory configuration, the memory module can be preferentially inserted into the first memory slot 1 to shorten the signal transmission distance and reduce signal loss during transmission.

[0058] In some embodiments, referring to Figures 5 and 6, the length of the connection lead 4 electrically connected to the second memory connection pin 21 is less than the length of the connection lead 4 electrically connected to the first memory connection pin 11.

[0059] In some embodiments, referring to Figures 5 and 6, the length of the connecting lead 4 electrically connected to the second memory connection pin 21 is less than the length of the connecting lead 4 electrically connected to the first memory connection pin 11. The second memory slot 2 can be set close to the main processing unit (CPU, GPU, DPU, etc.) in the server. The distance from which the main processing unit transmits signals to the memory module in the second memory slot 2 is less than the distance from which the main processing unit transmits signals to the memory module in the first memory slot 1. In the case of a partial memory configuration, the memory module can be preferentially inserted into the second memory slot 2 to shorten the signal transmission distance and reduce signal loss during transmission.

[0060] In some embodiments, referring to Figures 2, 4, and 6, the plurality of first memory connection pins 11 of the first memory slot 1 include a plurality of first sub-pins 111 and a plurality of second sub-pins 112; the plurality of first sub-pins 111 are located on the first sidewall 101 of the first memory slot 1; the plurality of second sub-pins 112 are located on the second sidewall 102 of the first memory slot 1; the plurality of second memory connection pins 21 of the second memory slot 2 include a plurality of third sub-pins 211 and a plurality of fourth sub-pins 212; the plurality of third sub-pins 211 are located on the third sidewall 201 of the second memory slot 2; the plurality of fourth sub-pins 212 are located on the fourth sidewall 202 of the second memory slot 2; the first solder pin 31 includes a first common solder pin 311 and a second common solder pin 312. 12. The connecting lead 4 includes a first connecting lead 41, a second connecting lead 42, a third connecting lead 43, and a fourth connecting lead 44. The first connecting lead 41 and the second connecting lead 42 are located on both sides of the first common solder pin 311, and the third connecting lead 43 and the fourth connecting lead 44 are located on both sides of the second common solder pin 312. The first common solder pin 311 is electrically connected to the first sub-pin 111 through the first connecting lead 41, the first common solder pin 311 is electrically connected to the third sub-pin 211 through the second connecting lead 42, the second common solder pin 312 is electrically connected to the second sub-pin 112 through the third connecting lead 43, and the second common solder pin 312 is electrically connected to the fourth sub-pin 212 through the fourth connecting lead 44.

[0061] Figures 2, 4 and 6 distinguish the first common solder pin 311 and the second common solder pin 312 using different filling patterns.

[0062] The first common solder pin 311 in Figure 2 can be, for example, the first solder pin 31 in the second row of Figure 1; the second common solder pin 312 in Figure 2 can be, for example, the first solder pin 31 in the third row of Figure 1. The first common solder pin 311 in Figure 4 can be, for example, the first solder pin 31 in the first row of Figure 3; the second common solder pin 312 in Figure 4 can be, for example, the first solder pin 31 in the second row of Figure 3. The first common solder pin 311 in Figure 6 can be, for example, the first solder pin 31 in the third row of Figure 5; the second common solder pin 312 in Figure 6 can be, for example, the first solder pin 31 in the fourth row of Figure 5.

[0063] Figure 2 shows that the first common solder pin 311 is electrically connected to the first sub-pin 111 via the first connecting lead 41. The first common solder pin 311 is electrically connected to the third sub-pin 211 via the second connecting lead 42 (the second connecting lead 42 is not shown in Figure 2 due to perspective obstruction, and the third connecting lead 43 also partially obscures the connection between the first common solder pin 311 and the first connecting lead 41; it can be understood that the first connecting lead 41 and the first common solder pin 311, which are obscured by the third connecting lead 43, are electrically connected). The distance between the first connecting lead 41 and the second connecting lead 42 is equal. The second common solder pin 312 is electrically connected to the second sub-pin 112 via the third connecting lead 43, and the second common solder pin 312 is electrically connected to the fourth sub-pin 212 via the fourth connecting lead 44. The distance between the third connecting lead 43 and the fourth connecting lead 44 is equal.

[0064] This achieves a symmetrical connection between the first sub-pin 111 and the third sub-pin 211, as well as a symmetrical connection between the second sub-pin 112 and the fourth sub-pin 212 inside the memory connector. This minimizes the problem of signal quality deviation between the first memory slot 1 and the second memory slot 2, ensuring the consistency of signal quality between the memory modules in the first memory slot 1 and the second memory slot 2.

[0065] Figure 4 shows that the first common solder pin 311 is electrically connected to the third sub-pin 211 via the second connecting lead 42, and the second common solder pin 312 is electrically connected to the fourth sub-pin 212 via the fourth connecting lead 44. It is understood that, due to the short lengths of the first connecting lead 41 and the third connecting lead 43, the electrical connection between the first common solder pin 311 and the first sub-pin 111 via the first connecting lead 41, and the electrical connection between the second common solder pin 312 and the second sub-pin 112 via the third connecting lead 43, are not shown in Figure 4. Furthermore, the fourth connecting lead 44 in Figure 4 obscures the connection position between the second connecting lead 42 and the third sub-pin 211; it is understood that the second connecting lead 42, obscured by the fourth connecting lead 44, is electrically connected to the third sub-pin 211. In this embodiment, the length of the first connecting lead 41 is less than the length of the second connecting lead 42, and the length of the third connecting lead 43 is less than the length of the fourth connecting lead 44. This allows the memory module to be inserted into the first memory slot 1 preferentially when the memory configuration is partially configured, thereby shortening the signal transmission distance and reducing signal loss during transmission.

[0066] Figure 6 shows that the first common solder pin 311 is electrically connected to the first sub-pin 111 via the first connecting lead 41, and the second common solder pin 312 is electrically connected to the second sub-pin 112 via the third connecting lead 43. It is understood that, due to the short lengths of the second connecting lead 42 and the fourth connecting lead 44, the electrical connection between the first common solder pin 311 and the third sub-pin 211 via the second connecting lead 42, and the electrical connection between the second common solder pin 312 and the fourth sub-pin 212 via the fourth connecting lead 44, are not shown in Figure 6. Furthermore, the third connecting lead 43 in Figure 6 obscures the connection position between the first common solder pin 311 and the first connecting lead 41; it is understood that the first common solder pin 311 and the first connecting lead 41, which are obscured by the third connecting lead 43, are electrically connected.

[0067] The length of the second connecting lead 42 is less than the length of the first connecting lead 41, and the length of the fourth connecting lead 44 is less than the length of the third connecting lead 43. This allows the memory module to be inserted into the second memory slot 2 first when the memory configuration is partially configured, thereby shortening the signal transmission distance and reducing signal loss during transmission.

[0068] Figure 7 is a schematic cross-sectional view of another memory connector shown in Figure 1, Figure 8 is a schematic cross-sectional view of another memory connector shown in Figure 3, and Figure 9 is a schematic cross-sectional view of another memory connector shown in Figure 5. In some embodiments, in conjunction with Figures 7 to 9, the memory connector further includes: a gating device 5; the gating device 5 is used to open or close the path between the first solder pin 31 and the first memory connection pin 11, and / or, the gating device 5 is used to open or close the path between the first solder pin 31 and the second memory connection pin 21.

[0069] In related technologies, when a memory connector with a first memory slot and a second memory slot is used, if the memory is configured as a partial configuration and the slot where no memory module is inserted is empty, but the connection traces still exist, the connection leads connected to the pins of the slot where no memory module is inserted will cause signal reflection, resulting in invalid stubs (or residual stubs), which will adversely affect the signal quality.

[0070] To address the aforementioned issues, this embodiment of the application includes a gating device 5 in the memory connector. When a memory module is inserted into the first memory slot 1 and no memory module is inserted into the second memory slot 2, the gating device 5 can, for example, open the path between the first solder pin 31 and the first memory connection pin 11, and close the path between the first solder pin 31 and the second memory connection pin 21. This not only enables signal transmission to the memory module in the first memory slot 1 but also minimizes the signal reflection caused by the path between the first solder pin 31 and the second memory connection pin 21, reducing invalid stubs and improving signal quality.

[0071] When a memory module is inserted into the second memory slot 2 and no memory module is inserted into the first memory slot 1, the gating device 5 can, for example, open the path between the first solder pin 31 and the second memory connection pin 21, and close the path between the first solder pin 31 and the first memory connection pin 11. This can enable signal transmission to the memory module in the second memory slot 2, and also minimize the signal reflection caused by the path between the first solder pin 31 and the first memory connection pin 11, reduce invalid stubs, and improve signal quality.

[0072] When memory modules are inserted into both the first memory slot 1 and the second memory slot 2, the gate device 5 can, for example, open the path between the first solder pin 31 and the first memory connection pin 11, and open the path between the first solder pin 31 and the second memory connection pin 21, thereby enabling signal transmission to the memory modules in the first memory slot 1 and the memory modules in the second memory slot 2.

[0073] In some embodiments, referring to FIG7, the gating device 5 may include, for example, a first gating device, a second gating device, a third gating device 53, and a fourth gating device 54. Due to viewing angle obstruction, the first gating device and the second gating device are not shown in some embodiments in FIG7. The arrangement of the first gating device and the second gating device can be understood with reference to the arrangement of the third gating device 53 and the fourth gating device 54, and is not limited here. The first gating device is used to open or close the passage between the first common solder pin 311 and the first sub-pin 111, the second gating device is used to open or close the passage between the first common solder pin 311 and the third sub-pin 211, the third gating device 53 is used to open or close the passage between the second common solder pin 312 and the second sub-pin 112, and the fourth gating device 54 is used to open or close the passage between the second common solder pin 312 and the fourth sub-pin 212.

[0074] Referring to Figure 7, when a memory module is inserted into the first memory slot 1 and no memory module is inserted into the second memory slot 2, the first gating device opens the path between the first common solder pin 311 and the first sub-pin 111, the third gating device opens the path between the second common solder pin 312 and the second sub-pin 112, the second gating device closes the path between the first common solder pin 311 and the third sub-pin 211, and the fourth gating device 54 closes the path between the second common solder pin 312 and the fourth sub-pin 212.

[0075] When a memory module is inserted into the second memory slot 2 and no memory module is inserted into the first memory slot 1, the second gating device opens the path between the first common solder pin 311 and the third sub-pin 211, the fourth gating device 54 opens the path between the second common solder pin 312 and the fourth sub-pin 212, the first gating device closes the path between the first common solder pin 311 and the first sub-pin 111, and the third gating device closes the path between the second common solder pin 312 and the second sub-pin 112.

[0076] When a memory module is inserted into the first memory slot 1 and the second memory slot 2, the first gating device opens the path between the first common solder pin 311 and the first sub-pin 111, the third gating device opens the path between the second common solder pin 312 and the second sub-pin 112, the second gating device opens the path between the first common solder pin 311 and the third sub-pin 211, and the fourth gating device 54 opens the path between the second common solder pin 312 and the fourth sub-pin 212.

[0077] In other embodiments, referring to FIG8, the gating device 5 may include, for example, a fifth gating device 55 and a sixth gating device 56. The fifth gating device 55 is used to open or close the passage between the first common solder pin 311 and the third sub-pin 211, and the sixth gating device 56 is used to open or close the passage between the second common solder pin 312 and the fourth sub-pin 212.

[0078] Referring again to Figure 8, the path between the first common solder pin 311 and the first sub-pin 111 is always conductive, and the path between the second common solder pin 312 and the second sub-pin 112 is also always conductive. When the memory configuration is half-full, a memory module can be inserted first into the first memory slot 1, and no memory module is inserted into the second memory slot 2. The fifth gating device 55 shuts off the path between the first common solder pin 311 and the third sub-pin 211, and the sixth gating device 56 shuts off the path between the second common solder pin 312 and the fourth sub-pin 212. When the memory configuration is full, memory modules are inserted into both the first memory slot 1 and the second memory slot 2. The fifth gating device 55 opens the path between the first common solder pin 311 and the third sub-pin 211, and the sixth gating device 56 opens the path between the second common solder pin 312 and the fourth sub-pin 212.

[0079] In other embodiments, referring to FIG9, the gating device 5 may include, for example, a seventh gating device 57 and an eighth gating device 58. The seventh gating device 57 is used to open or close the passage between the first common solder pin 311 and the first sub-pin 111, and the eighth gating device 58 is used to open or close the passage between the second common solder pin 312 and the second sub-pin 112.

[0080] Referring again to Figure 9, the path between the first common solder pin 311 and the first sub-pin 111 is always conductive, and the path between the second common solder pin 312 and the second sub-pin 112 is also always conductive. When the memory configuration is half-full, a memory module can be inserted first into the second memory slot 2, and no memory module is inserted into the first memory slot 1. The seventh gating device 57 shuts off the path between the first common solder pin 311 and the first sub-pin 111, and the eighth gating device 58 shuts off the path between the second common solder pin 312 and the second sub-pin 112. When the memory configuration is full, memory modules are inserted into both the first memory slot 1 and the second memory slot 2. The seventh gating device 57 conducts the path between the first common solder pin 311 and the first sub-pin 111, and the eighth gating device 58 conducts the path between the second common solder pin 312 and the second sub-pin 112.

[0081] In some embodiments, referring to Figures 7 to 9, the gating device 5 includes an elastic structure and a conductive element, which are connected; when the elastic structure is in a first elastic state, the conductive element opens the path between the first solder pin 31 and the first memory connection pin 11; when the elastic structure is in a second elastic state, the conductive element closes the path between the first solder pin 31 and the first memory connection pin 11; and / or, when the elastic structure is in the first elastic state, the conductive element opens the path between the first solder pin 31 and the second memory connection pin 21; when the elastic structure is in the second elastic state, the conductive element closes the path between the first solder pin 31 and the second memory connection pin 21.

[0082] In some embodiments, the gating device 5 may include an elastic structure and a conductive element, which are connected together. The elastic structure may be, for example, a spring, and the conductive element may be, for example, a metal conductive sheet.

[0083] In some embodiments, based on the insertion of a memory module into the first memory slot 1, the elastic structure can be compressed to a first elastic state, such as a compressed state. The compressed elastic structure causes the conductive element to open the passage between the first solder pin 31 and the first memory connection pin 11. When no memory module is inserted into the first memory slot 1, the elastic structure can be released to a second elastic state, such as a relaxed or stretched state. The elastic structure in the relaxed or stretched state causes the conductive element to close the passage between the first solder pin 31 and the first memory connection pin 11.

[0084] In other embodiments, when a memory module is inserted into the second memory slot 2, the elastic structure can be compressed to a first elastic state, such as a compressed state. The compressed elastic structure causes the conductive element to open the path between the first solder pin 31 and the second memory connection pin 21. When no memory module is inserted into the second memory slot 2, the elastic structure can be released to a second elastic state, such as a relaxed or stretched state. The relaxed or stretched elastic structure causes the conductive element to close the path between the first solder pin 31 and the second memory connection pin 21.

[0085] This application also provides a motherboard. Figure 10 is a top view of a printed circuit board provided in this application, Figure 11 is a top view of another printed circuit board provided in this application, and Figure 12 is a top view of yet another printed circuit board provided in this application. Referring to Figures 1 to 12, the motherboard includes: a printed circuit board, which includes multiple pads 6 located on the top surface B of the printed circuit board. The pads 6 are electrically connected one-to-one with the soldering pins 3 of the memory connector provided in the above embodiment; the pads 6 include multiple first pads 61 and multiple second pads 62, the first pads 61 being electrically connected to the first soldering pin 31, and the second pads 62 being electrically connected to the second soldering pin 32; the top surface B of the printed circuit board includes a pad vacancy area S2, the area of ​​which is larger than the area of ​​at least two pads 6. The first memory connection pin 11 and the second memory connection pin 21 that transmit the same signal are electrically connected to the same first solder pin 31, and the first memory connection pin 11 and the second memory connection pin 21 that transmit different signals are electrically connected to different second solder pins 32 respectively.

[0086] In some embodiments, referring to Figures 1 to 12, a plurality of pads 6 are provided on the top surface B of the printed circuit board. The pads 6 are electrically connected one-to-one with the solder pins 3 of the memory connector. The first memory connection pin 11 and the second memory connection pin 21 that transmit the same signal are connected to the same first solder pin 31. The first solder pin 31 and the first pad 61 are electrically connected to realize the transmission of the same signal on the first memory connection pin 11 and the second memory connection pin 21. Thus, it is not necessary to provide a first pad 61 for the first memory connection pin 11 and the second memory connection pin 21 that transmit the same signal, reducing the number of first pads 61, and consequently reducing the number of vias and the trace density on the printed circuit board. The position of the deleted first pad 61 is designated as the pad void area S2 on the top surface B of the printed circuit board.

[0087] Figure 10 shows, in some embodiments, a first sub-pad vacancy area S21 and a second sub-pad vacancy area S22, which overlap with the orthographic projection of the second pad 62 in the second row on the bottom surface B of the printed circuit board. A third sub-pad vacancy area S23 and a fourth sub-pad vacancy area S24 overlap with the orthographic projection of the second pad 62 in the third row on the bottom surface B of the printed circuit board, thereby also expanding the area of ​​the pad vacancy area S2, which is larger than the area of ​​at least two pads 6. By expanding the area of ​​the pad void area S2, the pad void area S2 can serve as a heat dissipation channel for the printed circuit board, which helps air circulate around the printed circuit board and improves the heat dissipation effect. The larger area of ​​the pad void area S2 can increase the spacing between the traces on the printed circuit board, reduce the possibility of electromagnetic interference, and improve signal integrity and stability. The pad void area S2 makes the routing space on the printed circuit board more spacious, reduces the crossing and overlap between traces, reduces the routing difficulty, and can also reduce the current density on the printed circuit board, thereby improving the reliability and safety of the printed circuit board.

[0088] The second pad 62 is used to electrically connect to the second solder pin 32. The second pad 62 and the second solder pin 32 are used to transmit address signals and control signals to the first memory connection pin 11 and the second memory connection pin 21, which transmit different signals, so as to realize the transmission of different signals on the first memory connection pin 11 and the second memory connection pin 21.

[0089] In some embodiments, referring to Figures 1 and 10, taking the four rows of solder pins 3 in Figure 1 and the four rows of pads 6 in Figure 10 as examples, the first solder pin 31 in the second row of Figure 1 serves as the first common solder pin 311, and the first pad 61 in the second row of Figure 10 serves as the first common pad 611, with the first common solder pin 311 electrically connected to the first common pad 611. Similarly, the first solder pin 31 in the third row of Figure 1 serves as the second common solder pin 312, and the first pad 61 in the third row of Figure 10 serves as the second common pad 612, with the second common solder pin 312 electrically connected to the second common pad 612.

[0090] Referring to Figures 3 and 11, taking the four rows of solder pins 3 in Figure 3 and the four rows of pads 6 in Figure 11 as examples, the first solder pin 31 in the first row of Figure 3 serves as the first common solder pin 311, and the first pad 61 in the first row of Figure 11 serves as the first common pad 611. The first common solder pin 311 is electrically connected to the first common pad 611. The first solder pin 31 in the second row of Figure 3 serves as the second common solder pin 312, and the first pad 61 in the second row of Figure 11 serves as the second common pad 612. The second common solder pin 312 is electrically connected to the second common pad 612.

[0091] Referring to Figures 5 and 12, taking the four rows of solder pins 3 in Figure 5 and the four rows of pads 6 in Figure 12 as examples, the first solder pin 31 in the third row of Figure 5 serves as the first common solder pin 311, and the first pad 61 in the third row of Figure 12 serves as the first common pad 611. The first common solder pin 311 is electrically connected to the first common pad 611. The first solder pin 31 in the fourth row of Figure 5 serves as the second common solder pin 312, and the first pad 61 in the fourth row of Figure 12 serves as the second common pad 612. The second common solder pin 312 is electrically connected to the second common pad 612.

[0092] The motherboard provided in this application embodiment includes a printed circuit board. On the top surface B of the printed circuit board, it is not necessary to set the first pad 61 for the first memory connection pin 11 and the second memory connection pin 21 that transmit the same signal, thereby reducing the number of first pads 61 and thus reducing the number of vias and the trace density on the printed circuit board. The position of the deleted first pads 61 is used as the pad void area S2 on the top surface B of the printed circuit board, leaving more space on the top surface B of the printed circuit board, increasing the design space on the printed circuit board, and improving the signal quality. The area of ​​the pad vacancy area S2 is larger than the area of ​​at least two pads 6. By expanding the area of ​​the pad vacancy area S2, it can serve as a heat dissipation channel for the printed circuit board, which helps air to circulate around the printed circuit board and improves its heat dissipation. The larger area of ​​the pad vacancy area S2 can increase the spacing between the traces on the printed circuit board, reduce the possibility of electromagnetic interference, and improve signal integrity and stability. The pad vacancy area S2 provides more space for the traces on the printed circuit board, reduces the crossing and overlap between traces, reduces the difficulty of wiring, and can also reduce the current density on the printed circuit board, thereby improving the reliability and safety of the printed circuit board.

[0093] In some embodiments, as shown in FIG10, the pad vacancy area S2 is located on both sides of the first pad 61.

[0094] In some embodiments, as shown in FIG10, the pad vacancy area S2 may be located on both sides of the first pad 61, thereby reducing the pin density on both sides of the first pad 61 and leaving design space for the position of the first pad 61 on both sides of the printed circuit board.

[0095] In some embodiments, referring to Figures 11 and 12, the pad vacancy area S2 is located on the same side of the first pad 61.

[0096] Figure 11 shows that the pad vacancy area S2 is located on the lower side of the first pad 61, and Figure 12 shows that the pad vacancy area S2 is located on the upper side of the first pad 61. This helps to concentrate the pad vacancy area S2 on one side, leaving more design space on the other side of the first pad 61 and improving the design density of the pads 6 on the printed circuit board.

[0097] This application also provides a server, including any of the memory connectors and motherboards provided in the above embodiments. Therefore, it can also solve the same technical problems as the memory connector embodiments and motherboards provided in the above embodiments and achieve the same technical effects, which will not be repeated here.

[0098] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0099] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory connector, characterized in that, include: First memory slot; The side wall of the first memory slot is provided with a plurality of first memory connection pins that are electrically connected to the memory module; Second memory slot; The side wall of the second memory slot is provided with multiple second memory connection pins that are electrically connected to the memory module; Multiple solder pins, located on the bottom surface of the memory connector, are configured to be electrically connected to the solder pads on the printed circuit board; The soldering pins include a first soldering pin and a second soldering pin. The first memory connection pin and the second memory connection pin that transmit the same signal are electrically connected to the same first soldering pin. The first memory connection pin and the second memory connection pin that transmit different signals are respectively electrically connected to different second soldering pins. The bottom surface of the memory connector includes at least one solder pin gap area, the area of ​​which is larger than the area of ​​at least two solder pins.

2. The memory connector according to claim 1, characterized in that, The memory connector further includes: multiple connecting leads; the first solder pin is electrically connected to the corresponding first memory connection pin and the second memory connection pin via the connecting leads.

3. The memory connector according to claim 2, characterized in that, The weld pin gap area is located on both sides of the first weld pin.

4. The memory connector according to claim 3, characterized in that, The first memory slot includes opposing first and second sidewalls; the second memory slot includes opposing third and fourth sidewalls. Multiple first memory connection pins are disposed on the first sidewall and the second sidewall; multiple second memory connection pins are disposed on the third sidewall and the fourth sidewall; The second sidewall is located between the first sidewall and the third sidewall; a plurality of the first solder pins are located on the bottom surface of the memory connector between the second sidewall and the third sidewall.

5. The memory connector according to claim 4, characterized in that, The lengths of the connecting leads electrically connected to the same first welded pin are equal.

6. The memory connector according to claim 2, characterized in that, The welded pin gap is located on the same side as the first welded pin.

7. The memory connector according to claim 6, characterized in that, The length of the connection lead electrically connected to the first memory connection pin is less than the length of the connection lead electrically connected to the second memory connection pin.

8. The memory connector according to claim 6, characterized in that, The length of the connection lead electrically connected to the second memory connection pin is less than the length of the connection lead electrically connected to the first memory connection pin.

9. The memory connector according to any one of claims 2-8, characterized in that, The plurality of first memory connection pins include a plurality of first sub-pins and a plurality of second sub-pins; the plurality of first sub-pins are located on the first sidewall of the first memory slot; the plurality of second sub-pins are located on the second sidewall of the first memory slot.

10. The memory connector according to claim 9, characterized in that, The plurality of second memory connection pins include a plurality of third sub-pins and a plurality of fourth sub-pins; the plurality of third sub-pins are located on the third sidewall of the second memory slot; the plurality of fourth sub-pins are located on the fourth sidewall of the second memory slot.

11. The memory connector according to claim 10, characterized in that, The first welding pin includes a first common welding pin and a second common welding pin. The connecting lead includes a first connecting lead, a second connecting lead, a third connecting lead, and a fourth connecting lead. The first connecting lead and the second connecting lead are located on both sides of the first common welding pin, and the third connecting lead and the fourth connecting lead are located on both sides of the second common welding pin. The first common solder pin is electrically connected to the first sub-pin via the first connecting lead, the first common solder pin is electrically connected to the third sub-pin via the second connecting lead, the second common solder pin is electrically connected to the second sub-pin via the third connecting lead, and the second common solder pin is electrically connected to the fourth sub-pin via the fourth connecting lead.

12. The memory connector according to claim 11, characterized in that, Between the first memory connection pin and the second memory connection pin that are electrically connected to the first common solder pin, there is a first memory connection pin or the second memory connection pin that is electrically connected to the second common solder pin, and the distance between the first common solder pin and the second common solder pin is less than the distance between the two second solder pins.

13. The memory connector according to claim 1, characterized in that, The memory connector further includes: a gating device; the gating device is configured to open or close the path between the first solder pin and the first memory connection pin, and / or the gating device is configured to open or close the path between the first solder pin and the second memory connection pin.

14. The memory connector according to claim 13, characterized in that, The gating device includes an elastic structure and a conductive element, and the elastic structure and the conductive element are connected. When the elastic structure is in the first elastic state, the conductive element opens the path between the first solder pin and the first memory connection pin; when the elastic structure is in the second elastic state, the conductive element closes the path between the first solder pin and the first memory connection pin. And / or, when the elastic structure is in a first elastic state, the conductive element opens the path between the first solder pin and the second memory connection pin; when the elastic structure is in a second elastic state, the conductive element closes the path between the first solder pin and the second memory connection pin.

15. A motherboard, characterized in that, include: A printed circuit board, the printed circuit board including a plurality of pads located on the top surface of the printed circuit board, the pads being configured to be electrically connected one-to-one with the solder pins of the memory connector as described in any one of claims 1-14.

16. The motherboard according to claim 15, characterized in that, The pads include a plurality of first pads and a plurality of second pads, wherein the first pads are electrically connected to a first soldering pin and the second pads are electrically connected to a second soldering pin.

17. The motherboard according to claim 16, characterized in that, The top surface of the printed circuit board includes a pad void area, the area of ​​which is larger than the area of ​​at least two pads; wherein, a first memory connection pin and a second memory connection pin that transmit the same signal are electrically connected to the same first solder pin, and a first memory connection pin and a second memory connection pin that transmit different signals are respectively electrically connected to different second solder pins.

18. The motherboard according to claim 17, characterized in that, The vacant pad area is located on both sides of the first pad.

19. The motherboard according to claim 17, characterized in that, The missing area of ​​the pad is located on the same side of the first pad.

20. A server, characterized in that, Includes the memory connector as described in any one of claims 1-14 and the motherboard as described in any one of claims 15-19.

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