Power conversion apparatus and control method
Patent Information
- Application Number
- PCT/CN2026/077099
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-28
- Filing Date
- 2026-02-04
- Publication Date
- 2026-10-01
Smart Images
Figure CN2026077099_01102026_PF_FP_ABST
Abstract
Description
A power conversion device and control method
[0001] Cross-reference to related applications
[0002] This application claims priority to Chinese Patent Application No. 202510382964.5, filed on March 28, 2025, entitled "A Power Conversion Device and Control Method", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This application relates to the field of energy storage technology, and in particular to a power conversion device and control method. Background Technology
[0004] A photovoltaic system typically includes photovoltaic modules and a power conversion device. The photovoltaic modules can convert solar energy into electrical energy, and the power conversion device can convert the direct current generated by the photovoltaic modules into alternating current and output it to energy storage devices or electrical devices. The power conversion device usually includes a boost circuit, which can adjust the output voltage of the photovoltaic modules to adapt to different lighting conditions, thereby improving the overall efficiency.
[0005] Power conversion devices typically include an arc fault detection circuit to detect the current output from the photovoltaic modules to the boost circuit, thereby determining whether arcing has occurred. The arc fault detection circuit can stop arc detection when the boost circuit is in hiccup mode. That is, once the boost circuit enters hiccup mode, the arc fault detection circuit stops arc detection; when the boost circuit exits hiccup mode, the arc fault detection circuit restarts arc detection. This reduces the chance of false alarms in hiccup mode. However, this shortens the arc detection time, making it impossible to provide long-term arc monitoring. If arcing occurs during the period when arc detection is stopped, it can lead to more serious damage. Summary of the Invention
[0006] This application provides a power conversion device and control method that can extend the arc detection time of the arc fault detection circuit, enabling longer arc monitoring and thus improving the safety of the power conversion device.
[0007] In a first aspect, embodiments of this application provide a power conversion device, which may include: an arc fault detection circuit, a first boost circuit, a controller, and an inverter circuit. The first boost circuit is connected between a first DC power supply and the inverter circuit, and the arc fault detection circuit is connected to the input terminal of the first boost circuit. The first boost circuit includes a switching transistor and an inductor, with the switching transistor connected to the controller and the inductor respectively. The controller is configured to: control the switching frequency of the switching transistor in the first boost circuit to decrease from a first frequency to a second frequency when the average value of the inductor current in the first boost circuit is less than a frequency reduction threshold; and control the first boost circuit to enter a hiccup mode when the average value of the inductor current in the first boost circuit is less than a hiccup threshold. The hiccup threshold is less than the frequency reduction threshold, and the hiccup mode is a mode in which the switching transistor in the first boost circuit operates discontinuously.
[0008] Based on the relationship that the hiccup threshold decreases as the switching frequency decreases, the hiccup threshold is the first hiccup threshold before frequency reduction and the second hiccup threshold after frequency reduction, which is lower than the first hiccup threshold. In the prior art, the first boost circuit enters hiccup mode when the average inductor current is less than the first hiccup threshold, thus stopping arc detection when the average inductor current is less than the first hiccup threshold. In this embodiment, the first boost circuit only enters hiccup mode when the average inductor current is less than the second hiccup threshold, thus stopping arc detection only when the average inductor current is less than the second hiccup threshold. Compared to the prior art, arc detection can still be performed during the period when the average inductor current is greater than or equal to the second hiccup threshold but less than the first hiccup threshold, extending the arc detection time of the arc fault detection circuit and enabling longer-term arc monitoring, thereby improving the safety of the power conversion device.
[0009] Furthermore, when the average inductor current in the first boost circuit is less than the frequency reduction threshold, it indicates that the average inductor current is not high. In this case, the inverter circuit, acting as the load of the first boost circuit, may be in a state of half-load or below. Frequency reduction can reduce the number of switching cycles of the switching transistors, reducing additional control losses and thus improving the efficiency of the power conversion device and reducing switching losses. It should be understood that when the equipment's operating load reaches approximately 50% of its rated capacity, it can be considered to be in a "half-load" state; when it is less than 50%, it can be considered to be in a state below half-load.
[0010] Optionally, the difference between the first frequency and the second frequency is negatively correlated with the hiccup threshold. A larger difference indicates a higher degree of frequency reduction, thus a smaller second hiccup threshold; conversely, a smaller difference indicates a lower degree of frequency reduction, thus a larger second hiccup threshold. Furthermore, a smaller second hiccup threshold results in a smaller average inductor current when entering hiccup mode, leading to a longer arc detection time; conversely, a larger second hiccup threshold results in a larger average inductor current when entering hiccup mode, leading to a shorter arc detection time. Therefore, the second frequency can be designed according to the arc detection duration requirements, thereby improving design flexibility and meeting the application needs of various scenarios.
[0011] Optionally, the power conversion device further includes a second boost circuit, which is connected between the second DC power supply and the inverter circuit. An arc fault detection circuit is connected to the input terminal of the second boost circuit. In the prior art, when the first boost circuit enters hiccup mode, the arc fault detection circuit stops arc detection. If arcing occurs in the path between the second DC power supply and the second boost circuit, the arc fault detection circuit will be unable to detect the arcing phenomenon due to the cessation of arc detection, leading to a potential hazard. In this embodiment, by reducing the hiccup threshold of the first boost circuit through frequency reduction processing, the probability of the first boost circuit entering hiccup mode is reduced, allowing arc detection to continue during the extended period. This solves the problem in the prior art where arc detection of the path between the second DC power supply and the second boost circuit cannot be performed during the extended period, achieving longer-term arc monitoring and thus improving the safety of the power conversion device. The extended period refers to the period during which the average value of the inductor current is greater than or equal to the second hiccup threshold and less than the first hiccup threshold.
[0012] Optionally, the first frequency corresponds to the first cycle, and the second frequency corresponds to the second cycle. Within the first cycle, the switching transistor in the first boost circuit has a first on-time, and within the second cycle, it has a second on-time. The difference between the first and second on-times is within a preset range, with the lower limit being -5% of the first cycle and the upper limit being 5% of the first cycle. In other words, the first and second on-times are essentially the same, thus ensuring that the on-time remains essentially unchanged within one cycle before and after the frequency reduction process. This allows for more accurate control of the second hiccup threshold, which helps extend the arc detection duration. Furthermore, it meets the load requirements, such as preventing the load from being insufficient when the on-time is shorter, and preventing an increase in load burden when the on-time is longer.
[0013] Optionally, the controller is also configured to: upon reaching the end of at least one second cycle, control the switching frequency of the switching transistor in the first boost circuit to return to the first frequency; the second cycle is the reciprocal of the second frequency. Exiting the frequency reduction process upon reaching the end of one second cycle allows for adjustment of the conduction time to meet load requirements even when the load changes. Exiting the frequency reduction process upon reaching the end of multiple second cycles can be applied to various scenarios, improving design flexibility.
[0014] Furthermore, the controller is also used to: restore the switching frequency of the switching transistor to the first frequency when the exit condition is met and at least one second cycle has ended; the exit condition includes: the average value of the inductor current in the first boost circuit is greater than or equal to the frequency reduction threshold. If the controller exits without checking whether the exit condition is met, a hiccup phenomenon may occur. In this case, when exiting the frequency reduction process, the switching frequency will first be restored to the first frequency, and then the trigger condition will be checked again. If the result is yes, the frequency reduction process will continue. In this case, exiting the frequency reduction process may require executing three more steps. If the controller checks whether the exit condition is met, and does not exit the frequency reduction process when the exit condition is not met, the frequency reduction process can continue directly. This reduces the number of operation steps, the amount of computation of the controller, and the power consumption.
[0015] Specifically, the controller is used to: the duration of the second cycle includes the duration of the first cycle corresponding to a first frequency; when the duration of the first cycle is reached, the exit condition is met; and when at least one end time of the second cycle is reached, the switching frequency of the control switch is restored to the first frequency.
[0016] Alternatively, the controller can be specifically configured to: The duration of the second cycle includes the duration of multiple first cycles corresponding to the first frequencies; when the exit condition is met at each first cycle duration, and the exit condition is met consecutively for a preset number of times, and at the end of at least one second cycle, the switching frequency of the control transistor is restored to the first frequency. This increases the accuracy of the judgment result and avoids repeated switching of the frequency reduction process due to an inaccurate judgment result.
[0017] Optionally, the controller is specifically used to: when the average value of the inductor current in the first boost circuit is less than the frequency reduction threshold, control the switching frequency of the switching transistor in the first boost circuit to decrease from a first frequency to a second frequency based on the difference between the average value of the inductor current in the first boost circuit and the frequency reduction threshold. Here, a mapping table between the difference between the average value of the inductor current in the first boost circuit and the frequency reduction threshold and the switching frequency can be determined based on practical experience. In the mapping table, different differences correspond to different switching frequencies, or different difference ranges correspond to different switching frequencies. This mapping table can be pre-configured in the controller. When the controller determines the current difference between the average value of the inductor current and the frequency reduction threshold, it can find the corresponding switching frequency from the mapping table and use the switching frequency found in the table as the second frequency. This allows the second frequency to be determined according to the current actual needs, reducing the probability of hiccups after frequency reduction processing, thereby helping to extend the arc detection time.
[0018] Alternatively, a second frequency can be pre-configured in the controller. When the triggering conditions are met, the controller performs frequency reduction based on the pre-configured second frequency. This eliminates the need for table lookup operations, reduces the amount of computation by the controller, and thus reduces the power consumption of the power conversion device.
[0019] Secondly, embodiments of this application also provide a control method for a boost circuit in a power conversion device. The control method may include: receiving the inductor current in a first boost circuit; when the average value of the inductor current in the first boost circuit is less than a frequency reduction threshold, controlling the switching frequency of the switching transistor in the first boost circuit to decrease from a first frequency to a second frequency; when the average value of the inductor current in the first boost circuit is less than a hiccup threshold, controlling the first boost circuit to enter a hiccup mode; wherein, the hiccup threshold is less than the frequency reduction threshold, and the hiccup mode is a mode in which the switching transistor in the first boost circuit operates discontinuously.
[0020] Optionally, the difference between the first and second frequencies is negatively correlated with the hiccup threshold.
[0021] Optionally, the first frequency corresponds to the first cycle, the second frequency corresponds to the second cycle, the switching transistor in the first boost circuit has a first conduction time in the first cycle, and the switching transistor in the first boost circuit has a second conduction time in the second cycle. The difference between the first conduction time and the second conduction time is within a preset range, the lower limit of the preset range is -5% of the first cycle, and the upper limit of the preset range is 5% of the first cycle.
[0022] Optionally, the control method further includes: when the end of at least one second cycle is reached, controlling the switching frequency of the switching transistor in the first boost circuit to return to the first frequency; the second cycle is the reciprocal of the second frequency.
[0023] It should be understood that since the principle of this control method in solving the problem is similar to that of the aforementioned power conversion device, the implementation and technical effects of this control method can be found in the implementation and technical effects of the aforementioned power conversion device, and the repetition will not be repeated.
[0024] Thirdly, embodiments of this application also provide a photovoltaic system, which may include: a photovoltaic module and a power conversion device as described in the first aspect and any one of the embodiments of the first aspect above. The power conversion device is connected to the photovoltaic module and is used to convert the direct current generated by the photovoltaic module into alternating current.
[0025] It should be understood that since the principle of this photovoltaic system in solving the problem is similar to that of the aforementioned power conversion device, the implementation and technical effects of this photovoltaic system can be found in the implementation and technical effects of the aforementioned power conversion device, and the repetition will not be repeated. Attached Figure Description
[0026] Figure 1 is a schematic diagram of a photovoltaic system provided in an embodiment of this application;
[0027] Figure 2 is a schematic diagram of a power conversion device provided in an embodiment of this application;
[0028] Figure 3 is a schematic diagram of the discontinuous current mode provided in the embodiment of this application;
[0029] Figure 4 is a schematic diagram of the frequency reduction method provided in the embodiments of this application;
[0030] Figure 5 is a schematic diagram of another power conversion device provided in an embodiment of this application.
[0031] Reference numerals: 100-Photovoltaic module, 200-Power conversion device, 300-Energy storage device, 11-First boost circuit, 12-Second boost circuit, 20-Controller, 30-Inverter circuit, 40-Arc fault detection circuit, 51-First DC power supply, 52-Second DC power supply, 61-First positive bus, 62-First negative bus, 63-Second positive bus, 64-Second negative bus, U c - Input voltage of the first boost circuit, U bus - Output voltage of the first boost circuit, L0 - Inductor, Q1 - Switch, D - Diode, C - Filter capacitor, GND - Ground, T1 - First cycle, T2 - Second cycle. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.
[0033] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.
[0034] It should be noted that, in this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner. In the embodiments of this application, the words "first," "second," etc., do not limit the number or order.
[0035] To facilitate understanding of the technical solutions provided in the embodiments of this application, their application scenarios are first described below. The power conversion device provided in the embodiments of this application can be applied to photovoltaic systems. Photovoltaic systems generate electricity based on solar energy, which can supply power to the AC grid, base station equipment (e.g., base station equipment in remote areas without mains power or with poor mains power), batteries, or various types of electrical appliances such as household appliances (e.g., refrigerators, air conditioners) in the AC grid. The specific application scenario can be determined according to the actual application scenario. Of course, in addition to photovoltaic systems, the power conversion device can also be applied to non-photovoltaic systems. In this case, the power conversion device can be any device that includes a boost circuit and has voltage conversion power. Therefore, this application does not limit the application scenario of the power conversion device. The following descriptions all use the application to photovoltaic systems as an example.
[0036] Figure 1 is a schematic diagram of the application scenario of the photovoltaic system provided in the embodiment of this application. As shown in Figure 1, the photovoltaic system includes a photovoltaic module 100 and a power conversion device 200. The photovoltaic module 100, also known as a photovoltaic array, may include multiple photovoltaic strings, each of which may include multiple photovoltaic panels connected in series. The photovoltaic panels are used to convert solar energy into electrical energy. The power conversion device 200 is connected to the photovoltaic module 100. The power conversion device 200 can monitor, safely shut down, or optimize the power of the photovoltaic module 100. It can also convert the direct current generated by the photovoltaic module 100 into alternating current and output it to an energy storage device 300 or an electrical appliance. The energy storage device 300 can be a battery or an AC power grid. In some embodiments, the power conversion device 200 can be a photovoltaic optimizer with maximum power point tracking (MPPT) functionality, meaning the photovoltaic optimizer can perform maximum power point tracking on the photovoltaic module 100, allowing the photovoltaic module 100 to maintain a high output power.
[0037] For example, the power conversion device 200 generally includes a boost circuit, an inverter circuit, an arc fault detection circuit, and a controller. The boost circuit is connected between the photovoltaic module 100 and the inverter circuit. The controller is connected to the boost circuit. The arc fault detection circuit is connected to the output terminal of the photovoltaic module 100. The arc fault detection circuit can detect the current output by the photovoltaic module 100. When the current output by the photovoltaic module 100 is detected to be greater than the preset current, it can be determined that an arcing phenomenon has occurred.
[0038] A boost circuit typically includes an inductor, a switching transistor, a diode, and a filter capacitor. During operation, the inductor is charged and discharged by controlling the switching transistor's on and off states, thus achieving voltage boosting. When the switching transistor is on, the power supply charges the inductor; when it is off, the inductor releases energy, supplying power to the inverter circuit through the diode and simultaneously charging the filter capacitor, making the output voltage higher than the input voltage, thus achieving voltage boosting. When the average inductor current drops to the hiccup threshold, the boost circuit enters hiccup mode. In hiccup mode, the signal collected by the arc fault detection circuit is similar to the signal when an actual arc occurs. Therefore, even if no arcing occurs, the arc fault detection circuit may mistakenly identify it as arcing, leading to a false alarm.
[0039] To avoid false alarms, the arc fault detection circuit can stop arc detection when the boost circuit is in hiccup mode. In other words, once the boost circuit enters hiccup mode, the arc fault detection circuit stops arc detection; it resumes when the boost circuit exits hiccup mode. This reduces the chance of false alarms in hiccup mode. However, this shortens the arc detection time, making it impossible to provide long-term arc monitoring. If arcing occurs during the stopped arc detection phase, it can lead to more serious damage.
[0040] Based on this, embodiments of this application provide a power conversion device that can extend the arc detection time of the arc fault detection circuit, enabling longer arc monitoring and thus improving the safety of the power conversion device. Exemplarily, the power conversion device provided in this application includes: an arc fault detection circuit, a first boost circuit, a controller, and an inverter circuit. The first boost circuit is connected between a first DC power supply and the inverter circuit, and the arc fault detection circuit is connected to the input terminal of the first boost circuit. The first boost circuit includes a switching transistor and an inductor, with the switching transistor connected to the controller and the inductor respectively. The controller is used to: when the average value of the inductor current in the first boost circuit is less than a frequency reduction threshold, control the switching frequency of the switching transistor in the first boost circuit to decrease from a first frequency to a second frequency; when the average value of the inductor current in the first boost circuit is less than a hiccup threshold, control the first boost circuit to enter a hiccup mode; the hiccup threshold is less than the frequency reduction threshold, and the hiccup mode is a mode in which the switching transistor in the first boost circuit operates discontinuously. Based on the relationship that the hiccup threshold decreases as the switching frequency decreases, the hiccup threshold is the first hiccup threshold before frequency reduction and the second hiccup threshold after frequency reduction, which is lower than the first hiccup threshold. In the prior art, the first boost circuit enters hiccup mode when the average inductor current is less than the first hiccup threshold, thus stopping arc detection when the average inductor current is less than the first hiccup threshold. In this embodiment, the first boost circuit only enters hiccup mode when the average inductor current is less than the second hiccup threshold, thus stopping arc detection only when the average inductor current is less than the second hiccup threshold. Compared to the prior art, arc detection can still be performed during the period when the average inductor current is greater than or equal to the second hiccup threshold but less than the first hiccup threshold, extending the arc detection time of the arc fault detection circuit and enabling longer-term arc monitoring, thereby improving the safety of the power conversion device.
[0041] Figure 2 exemplarily illustrates a structural schematic diagram of a power conversion device 200 provided in this application. Referring to Figure 2, the power conversion device 200 may include: an arc fault detection circuit 40, a first boost circuit 11, a controller 20, and an inverter circuit 30. The positive input terminal of the first boost circuit 11 is connected to the positive terminal of the first DC power supply 51 via a first positive bus 61, and the negative input terminal of the first boost circuit 11 is connected to the negative terminal of the first DC power supply 51 via a first negative bus 62. When the power conversion device 200 is applied to a photovoltaic system, the first DC power supply 51 can be a photovoltaic module; when the power conversion device 200 is applied to a non-photovoltaic system, the first DC power supply 51 can be any power source capable of outputting DC power. The arc fault detection circuit 40 is connected to both the first positive bus 61 and the first negative bus 62, therefore the arc fault detection circuit... Arc fault detection circuit 40 is connected to the input terminal of the first boost circuit 11. Arc fault detection circuit 40 can be used to detect arcing in the current output from the first DC power supply 51 to the first boost circuit 11. The positive output terminal of the first boost circuit 11 is connected to the positive input terminal of the inverter circuit 30, and the negative output terminal of the first boost circuit 11 is connected to the negative input terminal of the inverter circuit 30. The first boost circuit 11 is used to boost the first DC signal output from the first DC power supply 51 under the control of the controller 20, and output the second DC signal to the inverter circuit 30. The inverter circuit 30 is used to convert the second DC signal into an AC signal. When the inverter circuit 30 is connected to the power grid, the AC signal output by the inverter circuit 30 can be fed into the power grid. When the inverter circuit 30 is connected to the load, the AC signal output by the inverter circuit 30 can be used to supply power to the load.
[0042] The first boost circuit 11 may include: a switching transistor Q1, an inductor L0, a diode D, and a filter capacitor C. The control terminal of the switching transistor Q1 is connected to the controller 20. The first terminal of the switching transistor Q1 is connected to the first terminal of the inductor L0 and the positive terminal of the diode D. The second terminal of the switching transistor Q1 is connected to the first negative bus 62, the first terminal of the filter capacitor C, and the negative input terminal of the inverter circuit 30. The first terminal of the filter capacitor C is also connected to the ground terminal GND. The second terminal of the inductor L0 is connected to the first positive bus 61. The negative terminal of the diode D is connected to the second terminal of the filter capacitor C and the positive input terminal of the inverter circuit 30. The input voltage of the first boost circuit 11 is represented by U. c This indicates that the output voltage of the first boost circuit 11 is represented by U. bus express.
[0043] When the switching transistor Q1 is turned on, the two ends of the inductor L0 are directly connected to the first positive bus 61 and the first negative bus 62, that is, the two ends of the inductor L0 are directly connected to the first DC power supply 51. The diode D is reverse-biased and cut off. The output voltage U of the first boost circuit 11 is...bus The power is supplied by the electrical energy stored in the filter capacitor C; and when the switch Q1 is turned on, the input voltage U of the first boost circuit 11 is... c The driving current flows through inductor L0, and the voltage across inductor L0 is the input voltage U of the first boost circuit 11. c As the current in inductor L0 gradually increases, it stores energy during this phase, thus charging itself with the power supplied by the power source. The percentage of time that the switching transistor Q1 is on in each cycle is called the duty cycle. A larger duty cycle means more time for inductor L0 to store energy, resulting in a larger inductor current.
[0044] When the switch Q1 is turned off, the first terminal of inductor L0 is disconnected from the first negative bus 62, so the current no longer flows to ground through inductor L0. The current in inductor L0 flows through diode D to inverter circuit 30 and filter capacitor C, so the inductor current begins to decrease, and inductor L0 begins to discharge. At this time, the inductor current flows to inverter circuit 30 and charges filter capacitor C. Since the self-induced electromotive force voltage generated by inductor L0 is superimposed on the input voltage U of the first boost circuit 11... c Therefore, the output voltage U of the first boost circuit 11 is... bus The voltage released by inductor L0 and the input voltage U of the first boost circuit 11 c The sum of these values, and consequently the output voltage U of the first boost circuit 11. bus The input voltage U of the first boost circuit 11 is greater than c This achieves the effect of boosting pressure.
[0045] The first boost circuit 11 can operate in two modes: continuous current mode and discontinuous current mode. In continuous current mode, the current in inductor L0 is never zero, and current flows through inductor L0 throughout the entire cycle. Therefore, the output ripple is small and the efficiency is high in this continuous current mode, making it suitable for high-power applications. In discontinuous current mode, as shown in Figure 3, at time t1, switch Q1 is turned off, and the energy stored in inductor L0 is completely released. By time t2, the current in inductor L0 is close to zero, and this near-zero current state is maintained until time t3. When switch Q1 is turned on again (i.e., at time t3), inductor L0 starts charging again, and the current in inductor L0 increases again. Thus, the current in inductor L0 drops to zero at some point in each cycle. This discontinuous current mode is suitable for low-power or load-varying scenarios.
[0046] In discontinuous current mode, when the average value of the inductor current is less than the hiccup threshold, the required duty cycle of the switch Q1 may be less than the pre-configured duty cycle (i.e., the threshold duty cycle). This will cause the conduction time of the switch Q1 to fail to meet the requirements, which will result in the switch Q1 being unable to work continuously, thus causing the hiccup phenomenon. For example, referring to the pulse signal before frequency reduction shown in Figure 4, in this pulse signal, the switch Q1 is turned on when the level is high and turned off when the level is low. The period of the switch Q1 is represented by T1. From time t4 to time t5, the switch Q1 will be turned on in each period T1. This mode in which the switch Q1 is turned on in each period T1 is called the continuous operation mode. At time t5, if the required duty cycle of the switch Q1 is less than the threshold duty cycle, then the switch Q1, which should have been turned on, is not turned on. Therefore, the pulse signal before frequency reduction does not change from low level to high level at time t5, but continues to remain at low level. This means that the switch Q1 continues to be turned off at time t5. At this time, the first boost circuit 11 breaks the original continuous operation mode, or in other words, the first boost circuit 11 enters the discontinuous operation mode from time t5, that is, the hiccup mode. This phenomenon can be called the hiccup phenomenon. It should be understood that the high levels indicated by dashed lines 1 and 2 refer to the pulse signals corresponding to the continuous operation mode, while the discontinuous operation mode refers to the mode in which the pulse signal used to control the switching transistor Q1 remains unchanged for at least one cycle T1. Specifically, in hiccup mode, the signal collected by the arc fault detection circuit 40 is similar to the signal when an actual arc occurs. In this case, even if no arc occurs, the arc fault detection circuit 40 may mistakenly identify it as an arc, leading to a misjudgment.
[0047] Assume T pwm The period of switch Q1 is used to represent the period of switch Q1, and the duty cycle of switch Q1 is used to represent the duty cycle of switch Q1. peak i is used to represent the peak current in inductor L0. avg The value of inductance (L) is used to represent the average current in inductor L0 during each cycle of switch Q1 (i.e., the average value of the inductor current). Referring to Figure 3, t... on This is used to represent the increase in current in inductor L0 to the peak current i. peak The time, and t on It can also be used to represent the on-time of the switching transistor Q1 in each cycle, t off1 The current in inductor L0 is represented by the peak current i. peak The time t to decrease to zero off2 The value of S represents the time during which the current in inductor L0 remains zero, and S represents the area of the triangle shown in Figure 3. The following calculation process can then be performed: Tpwm =t on +t off1 +t off2
[0048] Therefore, based on the above calculation process, the following relationship 1 can be summarized:
[0049] Equation 1 above is the equation for calculating the average value of the inductor current in the first boost circuit 11 under discontinuous current mode. In Equation 1 above, if t... on / T pwm When representing the duty cycle (Duty), the above relationship 1 can be transformed to obtain the following relationship 2:
[0050] In relation 2 above, if t is kept on The input voltage U of the first boost circuit 11 remains unchanged. c and the output voltage U of the first boost circuit 11 bus When maintaining stability and keeping L constant, the period T of switch Q1 is... pwm When changes occur, the calculated i avg It will change; if the duty cycle (Duty) is set to the threshold duty cycle, the calculated i... avg As the hiccup threshold, the period T of the switching transistor Q1 pwm When changes occur, the hiccup threshold also changes; and the period T pwm The larger the frequency, the smaller the hiccup threshold. Since frequency and period are inversely related, the lower the switching frequency of switch Q1, the smaller the hiccup threshold, and vice versa. Therefore, by reducing the switching frequency of switch Q1, the hiccup threshold can be reduced.
[0051] Based on this, the controller 20 is configured to: when the average value of the inductor current in the first boost circuit 11 is less than the frequency reduction threshold, control the switching frequency of the switching transistor Q1 in the first boost circuit 11 to decrease from a first frequency to a second frequency; when the average value of the inductor current in the first boost circuit 11 is less than the hiccup threshold, control the first boost circuit 11 to enter a hiccup mode; when the hiccup threshold is less than the frequency reduction threshold, the hiccup mode is a mode in which the switching transistor Q1 in the first boost circuit 11 operates discontinuously. It should be understood that the hiccup threshold in this paragraph is also the second hiccup threshold mentioned later, and will be used to describe it from now on.
[0052] Based on the conclusion drawn from Equation 2 above, "the smaller the switching frequency of the switching transistor Q1, the smaller the hiccup threshold," when the hiccup threshold is the first hiccup threshold before frequency reduction and the hiccup threshold is the second hiccup threshold after frequency reduction, the second hiccup threshold will be less than the first hiccup threshold. Since in the prior art, when the average inductor current is less than the first hiccup threshold, the first boost circuit 11 will enter hiccup mode, and arc detection will stop when the average inductor current is less than the first hiccup threshold. In this embodiment, the first boost circuit 11 will only enter hiccup mode when the average inductor current is less than the second hiccup threshold, and arc detection will stop when the average inductor current is less than the second hiccup threshold. Compared with the prior art, arc detection can still be performed during the period when the average inductor current is greater than or equal to the second hiccup threshold and less than the first hiccup threshold (hereinafter referred to as the extended period), extending the arc detection time of the arc fault detection circuit 40, enabling longer arc monitoring, thereby improving the safety of the power conversion device 200.
[0053] The frequency reduction threshold can be determined based on the second hiccup threshold, for example, but not limited to: when the structure of the first boost circuit 11 is fixed, the second hiccup threshold will vary with the output voltage U of the first boost circuit 11. bus Fluctuations occur due to the fluctuations in voltage, but the output voltage U of the first boost circuit 11... bus It usually stabilizes within a certain range, so the output voltage U of the first boost circuit 11 bus If the frequency reduction threshold is relatively stable within a certain range, then the second hiccup threshold will also stabilize within a certain range, making the second hiccup threshold (i.e., the threshold range) relatively stable as well. In this case, the frequency reduction threshold can be the sum of the upper limit of the threshold range and a constant. The constant can be any value set according to actual needs, without specific limitations here. If the constant is set relatively large, frequency reduction can be performed when the inductor current exceeds the larger value of the second hiccup threshold. This helps ensure that the average value of the inductor current is always greater than the second hiccup threshold, effectively preventing hiccups. Therefore, this approach is suitable for scenarios with strict requirements for avoiding hiccups. If the constant is set relatively small, frequency reduction can be performed when the inductor current is slightly higher than the second hiccup threshold. This also reduces the probability of hiccups and avoids frequent frequency reduction processes, reducing the computational load of the controller 20 and thus reducing power consumption. Therefore, this approach is suitable for scenarios with certain requirements for both avoiding hiccups and power consumption.
[0054] Furthermore, when the average inductor current in the first boost circuit 11 is less than the frequency reduction threshold, it indicates that the average inductor current is not high. In this case, the inverter circuit 30, acting as the load of the first boost circuit 11, may be in a state of half-load or below. Frequency reduction can reduce the number of switching cycles of the switching transistor Q1, reducing additional control losses and thus improving the efficiency of the power conversion device 200 and reducing switching losses. It should be understood that when the operating load of a device reaches approximately 50% of its rated capacity, it can be considered to be in a "half-load" state; when it is less than 50%, it can be considered to be in a state below half-load.
[0055] Furthermore, the difference between the first and second frequencies is negatively correlated with the second hiccup threshold. For example, a larger difference indicates a higher degree of frequency reduction, thus a smaller second hiccup threshold; conversely, a smaller difference indicates a lower degree of frequency reduction, thus a larger second hiccup threshold. Further, a smaller second hiccup threshold results in a smaller average inductor current when entering hiccup mode, leading to a longer arc detection time; conversely, a larger second hiccup threshold results in a larger average inductor current when entering hiccup mode, leading to a shorter arc detection time. Therefore, the second frequency can be designed according to the arc detection duration requirements, thereby improving design flexibility and meeting the application needs of various scenarios.
[0056] Furthermore, the first frequency corresponds to the first cycle, and the second frequency corresponds to the second cycle. Within the first cycle, the switching transistor Q1 in the first boost circuit 11 has a first conduction time, and within the second cycle, the switching transistor Q1 in the first boost circuit 11 has a second conduction time. The difference between the first and second conduction times is within a preset range, with the lower limit of the preset range being -5% of the first cycle and the upper limit being 5% of the first cycle. In other words, the first and second conduction times are essentially the same, thus ensuring that the conduction time within one cycle before and after the frequency reduction process remains essentially unchanged. This allows for more accurate control of the second hiccup threshold, which is beneficial for extending the arc detection duration. It also meets the load requirements, such as preventing the load from being insufficient when the conduction time is shorter, and preventing an increase in load burden when the conduction time is longer.
[0057] For example, the controller 20 is specifically configured to: when the average value of the inductor current in the first boost circuit 11 is less than the frequency reduction threshold, control the switching frequency of the switching transistor Q1 in the first boost circuit 11 to decrease from a first frequency to a second frequency based on the difference between the average value of the inductor current in the first boost circuit 11 and the frequency reduction threshold. A mapping table between the difference between the average value of the inductor current in the first boost circuit 11 and the frequency reduction threshold and the switching frequency can be determined based on practical experience. In the mapping table, different differences correspond to different switching frequencies, or different difference ranges correspond to different switching frequencies. This mapping table can be pre-configured in the controller 20. When the controller 20 determines the current difference between the average value of the inductor current and the frequency reduction threshold, it can find the corresponding switching frequency from the mapping table and use the frequency found in the table as the second frequency. This allows the second frequency to be determined according to the current actual needs, reducing the probability of hiccups after frequency reduction processing, thereby helping to extend the arc detection time.
[0058] To achieve frequency reduction, when the first frequency corresponds to the first cycle and the second frequency corresponds to the second cycle, the controller 20 is specifically used to: control the switching transistor Q1 to conduct in part of the first cycles within N first cycles, and the total on-time of the switching transistor Q1 within the N first cycles remains unchanged, that is, the total duty cycle of the switching transistor Q1 remains unchanged before and after frequency reduction, where N is the ratio of the first frequency to the second frequency, and the second cycle is N first cycles, where N is an integer greater than 1. In other words, although the conduction status of the switching transistor Q1 within N first cycles is adjusted, the total on-time of the switching transistor Q1 within N first cycles does not change. If the first cycle of the switching transistor Q1 before frequency reduction is represented by T1, and the second cycle of the switching transistor Q1 during frequency reduction is represented by T2, then T2 is N times T1. This indicates that the cycle is expanded by N times during frequency reduction, and the switching frequency is correspondingly reduced by N times. Therefore, it is equivalent to reducing the switching frequency during frequency reduction, which can both reduce the hiccup threshold and ensure the normal operation of the first boost circuit 11.
[0059] When the average value of the inductor current in the first boost circuit 11 is less than the frequency reduction threshold is taken as the trigger condition, the specific implementation methods of frequency reduction processing can include the following:
[0060] (1) The controller 20 is specifically used to: when the triggering condition is met, control the switch Q1 to be turned off in the first k first cycles out of N first cycles, and control the switch Q1 to be turned on in the Nk first cycles after the first k first cycles out of N first cycles; the value of k is a positive integer less than N. In this way, by shuffling the original switching frequency of the switch Q1, the equivalent reduction of the switching frequency is achieved.
[0061] For example, referring to the pulse signal corresponding to frequency reduction method 2 shown in Figure 4, a high level indicates that switch Q1 is on, and a low level indicates that switch Q1 is off. The first cycle is denoted by T1, and the second cycle by T2. Taking N as 2, k as 1, and the conduction time within each first cycle T1 as denoted by a, when the trigger condition is met, time t5 is reached. The period from t5 to t6 is the first first cycle T1, during which switch Q1 is always off. The period from t6 to t8 is the second first cycle T1, during which switch Q1 is on, and the conduction time is 2a. Therefore, the period from t5 to t8 is the frequency reduction processing stage, and the period from t5 to t8 is the second cycle T2, which is twice the first cycle T1. Of course, the frequency reduction method is not limited to frequency reduction method 2 shown in Figure 4; this is just an example for explanation.
[0062] (2) The controller 20 is specifically used to: when the triggering condition is met, control the switch Q1 to be turned on for the first k first cycles out of N first cycles, and control the switch Q1 to be turned off for the Nk first cycles after the first k first cycles out of N first cycles; the value of k is a positive integer less than N. In this way, by shuffling the original switching frequency of the switch Q1, the equivalent reduction of the switching frequency is achieved.
[0063] For example, referring to the pulse signal corresponding to frequency reduction method 1 shown in Figure 4, a high level indicates that switch Q1 is on, and a low level indicates that switch Q1 is off. The first cycle is denoted by T1, and the second cycle by T2. Taking N as 2, k as 1, and the conduction time within each first cycle T1 as denoted by a, when the trigger condition is met, time t5 is reached. From time t5 to t6 is the first first cycle T1, during which switch Q1 is on, and the conduction time is 2a. From time t6 to t8 is the second first cycle T1, during which switch Q1 is always off. Therefore, from time t5 to t8 is the frequency reduction processing stage, and from time t5 to t8 is the second cycle T2, which is twice the first cycle T1. Of course, the frequency reduction method is not limited to frequency reduction method 1 shown in Figure 4; this is just an example for explanation.
[0064] (3) The controller 20 is specifically used to: when the triggering condition is met, control the switch Q1 to be turned off in the first k1 first cycles and the last k2 first cycles in N first cycles, and control the switch Q1 to be turned on in the N-k1-k2 first cycles after the first k1 first cycles and before the last k2 first cycles in N first cycles; the values of k1 and k2 are positive integers less than N.
[0065] In summary, during implementation, any of the above-described implementation methods can be chosen based on actual needs when performing frequency reduction processing; no specific limitations are imposed here. For example, the first and second implementation methods have relatively simpler control logic, making them easier to implement. Therefore, these two methods are suitable for scenarios where the logic control function of the controller 20 is not very strong. The third implementation method has relatively more complex control logic, making it suitable for scenarios where the logic control function of the controller 20 is stronger. Furthermore, when performing frequency reduction processing, with a fixed value for N, the second hiccup threshold remains the same regardless of which implementation method is used. In other words, the implementation method of frequency reduction processing does not affect the size of the hiccup threshold.
[0066] For example, if the average value of the inductor current in the first boost circuit 11 being greater than or equal to the frequency reduction threshold is defined as the exit condition, then the controller 20 is further configured to: when the exit condition is met and the end time of at least one second cycle is reached, control the switching frequency of the switching transistor Q1 to return to the first frequency. For instance, when the end time of one second cycle is reached and the exit condition is met, the frequency reduction process is exited, and the switching frequency returns to the first frequency; or, when the end time of multiple second cycles is reached and the exit condition is met, the frequency reduction process is exited, and the switching frequency returns to the first frequency. If the exit is not checked before exiting, a hiccuping phenomenon may occur. In this case, when exiting the frequency reduction process, the switching frequency will first return to the first frequency, and then the trigger condition will be checked again. If the result is yes, the frequency reduction process will continue. In this case, exiting the frequency reduction process may require executing three more steps. If the exit condition is checked and the frequency reduction process is not exited when the exit condition is not met, the frequency reduction process can continue directly. This reduces the number of operation steps, reduces the computational load of the controller 20, and reduces power consumption.
[0067] Taking the exiting of frequency reduction processing when the end of a second cycle is reached and the exit condition is met as an example, the timing for determining whether the exit condition is met can be set in any of the following ways:
[0068] Method 1: At the end of the second cycle, determine whether the exit condition is met; at this time, the average value of the inductor current in the first boost circuit 11 can be the average value corresponding to the duration of the second cycle or the average value corresponding to the duration of the first cycle. The specific value can be set according to actual needs, and no specific limitation is made here.
[0069] Method 2: The duration of the second cycle includes the duration of the first cycle. When the duration of the first cycle is reached, it is determined whether the exit condition is met. At this time, the average value of the inductor current in the first boost circuit 11 is the average value corresponding to the duration of the first cycle. If the determination result is yes, then when the end time of at least one second cycle is reached, the switching frequency of the control switch Q1 is restored to the first frequency.
[0070] Method 3: The duration of the second cycle includes the duration of multiple first cycles. At each point the duration of a first cycle is reached, it is determined whether the exit condition is met, and this determination is repeated multiple times. If the exit condition is met for a preset number of consecutive times, the switching frequency of the control transistor Q1 is restored to the first frequency at the end of at least one second cycle. This increases the accuracy of the determination and avoids repeated switching of frequency reduction processing due to an inaccurate determination.
[0071] For example, before the frequency reduction process, the inductor current is collected according to a preset collection period. The structure for collecting the inductor current can be any collection circuit known in the art, and is not specifically limited here. When the inductor current is collected, it is output to the controller 20. Therefore, the controller 20 will periodically obtain the inductor current, calculate the average value of the inductor current and compare it with the frequency reduction threshold. Once the trigger condition is met, the frequency reduction process is started.
[0072] During the frequency reduction process, the inductor current can still be periodically collected and output to the controller 20. When the controller 20 receives the inductor current, it can still calculate the average value of the inductor current and compare it with the frequency reduction threshold, but it will not stop the frequency reduction process. Alternatively, even if the controller 20 receives the inductor current, it does not need to compare the average value of the inductor current with the frequency reduction threshold, because the frequency reduction process will proceed normally without interruption regardless of whether the trigger condition is met. Therefore, comparing the average value of the inductor current with the frequency reduction threshold during the frequency reduction process will not trigger any operation. Not performing the comparison operation reduces the computational load of the controller 20 and lowers its power consumption. Furthermore, during the frequency reduction process, the controller 20 can control the acquisition circuit to stop collecting the inductor current, and then control the acquisition circuit to resume collecting the inductor current at the end of N first cycles, which can further reduce power consumption.
[0073] For example, in addition to the first boost circuit 11, controller 20, arc fault detection circuit 40, and inverter circuit 30, the power conversion device 200 can also include more components as needed, such as, but not limited to: a power tracking circuit connected to the controller 20, and relays located in the first positive bus 61 and the first negative bus 62. The power tracking circuit is used to perform power tracking on the photovoltaic modules and outputs maximum power to the controller 20 so that the controller 20 controls the switching transistor Q1 based on the maximum power, thereby improving the power generation efficiency of the photovoltaic system. The relay can be connected to the controller 20, and the arc fault detection circuit 40 can also be connected to the controller 20. When the arc fault detection circuit 40 detects arcing, it outputs a fault signal to the controller 20. When the controller 20 receives the fault signal, it controls the relay to disconnect, thereby disconnecting the first DC power supply 51 from the first boost circuit 11 and preventing damage to the first boost circuit 11, thereby improving the reliability and safety of the power conversion device 200.
[0074] In another embodiment of the power conversion device 200 provided in this application, the structure of the power conversion device 200 in this embodiment is basically similar to that of the power conversion device 200 in the embodiment described in FIG2 above, except that the method for determining the degree of frequency reduction is different. For example, a second frequency can be pre-configured in the controller 20. When the trigger condition is met, the controller 20 performs frequency reduction processing based on the pre-configured second frequency. This eliminates the need for table lookup operations, reduces the computational load of the controller 20, and thus reduces the power consumption of the power conversion device 200.
[0075] It should be understood that the similarities between the power conversion device 200 structure in this embodiment and the power conversion device 200 structure in the embodiment described in FIG2 above can be found in the relevant descriptions in the aforementioned embodiments, and the repeated parts will not be repeated.
[0076] In another embodiment of the power conversion device 200 provided in this application, the structure of the power conversion device 200 in this embodiment is basically similar to that of the power conversion device 200 in the embodiment described in FIG2 above, except that the frequency reduction method is different. For example, while keeping the on-time constant, the frequency reduction is extended from the first cycle to the second cycle, at which point the total duty cycle of the switching transistor Q1 changes before and after frequency reduction. This extends the switching period of the switching transistor Q1 while keeping the on-time constant, correspondingly reducing the switching frequency. This can lower the hiccup threshold and extend the monitoring time of arc detection.
[0077] For example, referring to the pulse signal corresponding to frequency reduction method 3 shown in Figure 4, a high level indicates that switch Q1 is on, and a low level indicates that switch Q1 is off. The first cycle is represented by T1, and the second cycle by T2. When the trigger condition is met, at time t5, switch Q1 is on and the on-time is 'a'. The second cycle T2 ends at time t8. Therefore, the period from time t5 to time t8 is the second cycle T2. It is clear that the total duty cycle of switch Q1 changes before and after frequency reduction, but the on-time remains unchanged and is always 'a'. It should be understood that any pulse signal in Figure 4 is illustrated using the example of a high level indicating switch Q1 is on and a low level indicating switch Q1 is off. However, in actual practice, it can also be set to a low level indicating switch Q1 is on and a high level indicating switch Q1 is off. The specific setting can be made according to actual needs, and no specific limitation is made here.
[0078] Alternatively, considering the pulse signal corresponding to frequency reduction method 4 shown in Figure 4, the difference between frequency reduction method 4 and frequency reduction method 3 is that the duration of the second period is different; in frequency reduction method 4, the second period T2 is from time t5 to time t7.
[0079] In other words, the second period can be an integer multiple or a non-integer multiple of the first period. As long as the second period is greater than the first period, it falls within the protection scope of the embodiments of this application.
[0080] It should be understood that the similarities between the power conversion device 200 structure in this embodiment and the power conversion device 200 structure in the embodiment described in FIG2 above can be found in the relevant descriptions in the aforementioned embodiments, and the repeated parts will not be repeated.
[0081] In another embodiment of the power conversion device 200 provided in this application, the structure of the power conversion device 200 in this embodiment is basically similar to that of the power conversion device 200 in the embodiment described in FIG2 above, except that the mechanism for exiting the frequency reduction process is different. For example, the controller 20 is further configured to: when the end time of at least one second cycle is reached, control the switching frequency of the switching transistor Q1 to return to the first frequency; that is, taking the exiting of the frequency reduction process at the end time of a second cycle as an example, the controller 20 does not determine whether the exit condition is met, but directly exits the frequency reduction process at the end time of the second cycle; then it continues to monitor the inductor current to determine whether to perform the frequency reduction process again. This can reduce the computational load of the controller 20, reduce the power consumption of the controller 20, and also adjust the conduction time to meet the load requirements when the load changes.
[0082] It should be understood that the similarities between the power conversion device 200 structure in this embodiment and the power conversion device 200 structure in the embodiment described in FIG2 above can be found in the relevant descriptions in the aforementioned embodiments, and the repeated parts will not be repeated.
[0083] Figure 5 exemplarily illustrates a structural schematic diagram of another power conversion device 200 provided in this application. Referring to Figure 5, the structure of the power conversion device 200 in this embodiment is basically similar to that of the power conversion device 200 in the embodiment described in Figure 2 above. The difference is that the power conversion device 200 may further include a second boost circuit 12. Exemplarily, the positive input terminal of the second boost circuit 12 is connected to the positive terminal of the second positive bus 63 and the second DC power supply 52 through the second positive bus 63, and the negative input terminal of the second boost circuit 12 is connected to the negative terminal of the second DC power supply 52 through the second negative bus 64. At this time, the arc fault detection circuit 40 may also be connected to the second positive bus 63 and the second negative bus 64. In this case, the arc fault detection circuit 40 can be used to detect whether an arcing phenomenon has occurred at the input terminals of multiple boost circuits. The positive output terminal of the second boost circuit 12 is connected to the positive input terminal of the inverter circuit 30, and the negative output terminal of the second boost circuit 12 is connected to the negative input terminal of the inverter circuit 30. Therefore, the first boost circuit 11 and the second boost circuit 12 are connected to different DC power supplies, and the inverter circuit 30 is connected to the first boost circuit 11 and the second boost circuit 12 respectively.
[0084] The structure of the second boost circuit 12 can be the same as or different from that of the first boost circuit 11. Figure 5 illustrates the case where the structure of the second boost circuit 12 is the same as that of the first boost circuit 11. The switching transistors Q1 in both the second boost circuit 12 and the first boost circuit 11 are connected to the controller 20, so that the controller 20 can control the switching transistors Q1 in the two boost circuits respectively.
[0085] In the prior art, when the first boost circuit 11 enters the hiccup mode, the arc fault detection circuit 40 stops arc detection. If arcing occurs in the path between the second DC power supply 52 and the second boost circuit 12, the arc fault detection circuit 40 will be unable to detect the arcing phenomenon due to the cessation of arc detection, leading to a dangerous situation. In this embodiment, because the hiccup threshold of the first boost circuit 11 is reduced through frequency reduction processing, the probability of the first boost circuit 11 entering the hiccup mode is reduced, allowing arc detection to continue during the extended period. This solves the problem in the prior art where arc detection of the path between the second DC power supply 52 and the second boost circuit 12 cannot be performed during the extended period, achieving longer-term arc monitoring and thus improving the safety of the power conversion device 200.
[0086] It should be understood that the similarities between the power conversion device 200 structure in this embodiment and the power conversion device 200 structure in the embodiment described in FIG2 above can be found in the relevant descriptions in the aforementioned embodiments, and the repeated parts will not be repeated.
[0087] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.
Claims
1. A power conversion device, characterized in that, include: The system includes an arc fault detection circuit, a first boost circuit, a controller, and an inverter circuit. The first boost circuit is connected between a first DC power supply and the inverter circuit. The arc fault detection circuit is connected to the input terminal of the first boost circuit. The first boost circuit includes a switching transistor and an inductor. The switching transistor is connected to the controller and the inductor, respectively. The controller is configured to: control the switching frequency of the switching transistor in the first boost circuit to decrease from a first frequency to a second frequency when the average value of the inductor current in the first boost circuit is less than a frequency reduction threshold; control the first boost circuit to enter a hiccup mode when the average value of the inductor current in the first boost circuit is less than a hiccup threshold; wherein the hiccup threshold is less than the frequency reduction threshold, and the hiccup mode is a mode in which the switching transistor in the first boost circuit operates discontinuously.
2. The power conversion device as described in claim 1, characterized in that, The difference between the first frequency and the second frequency is negatively correlated with the hiccup threshold.
3. The power conversion device as described in claim 1 or 2, characterized in that, The power conversion device further includes a second boost circuit, which is connected between the second DC power supply and the inverter circuit, and the arc fault detection circuit is connected to the input terminal of the second boost circuit.
4. The power conversion device according to any one of claims 1-3, characterized in that, The first frequency corresponds to the first period, and the second frequency corresponds to the second period. During the first period, the switching transistor in the first boost circuit has a first on-time, and during the second period, the switching transistor in the first boost circuit has a second on-time. The difference between the first on-time and the second on-time is within a preset range. The lower limit of the preset range is -5% of the first period, and the upper limit of the preset range is 5% of the first period.
5. The power conversion device according to any one of claims 1-4, characterized in that, The controller is further configured to: when the end of at least one second cycle is reached, control the switching frequency of the switching transistor in the first boost circuit to return to the first frequency; the second cycle is the reciprocal of the second frequency.
6. The power conversion device as described in claim 5, characterized in that, The controller is further configured to: when the exit condition is met and at least one end time of the second cycle is reached, control the switching frequency of the switching transistor to return to the first frequency; The exit condition includes: the average value of the inductor current in the first boost circuit is greater than or equal to the frequency reduction threshold.
7. The power conversion device as described in claim 6, characterized in that, The controller is specifically configured to: the duration of the second cycle includes the duration of a first cycle corresponding to the first frequency; when the duration of the first cycle is reached, the exit condition is satisfied; and when at least one end time of the second cycle is reached, the switching frequency of the switching transistor is controlled to return to the first frequency.
8. The power conversion device as described in claim 6, characterized in that, The controller is specifically configured to: the duration of the second cycle includes the duration of the first cycle corresponding to multiple first frequencies; satisfy the exit condition at each time the duration of the first cycle is reached; satisfy the exit condition for a preset number of consecutive times; and control the switching frequency of the switching transistor to return to the first frequency when at least one end time of the second cycle is reached.
9. The power conversion device according to any one of claims 1-8, characterized in that, The controller is specifically used to: when the average value of the inductor current in the first boost circuit is less than the frequency reduction threshold, control the switching frequency of the switching transistor in the first boost circuit to decrease from a first frequency to a second frequency based on the difference between the average value of the inductor current in the first boost circuit and the frequency reduction threshold.
10. A control method for a first boost circuit in a power conversion device, characterized in that, include: Receive the inductor current from the first boost circuit; When the average value of the inductor current in the first boost circuit is less than the frequency reduction threshold, the switching frequency of the switching transistor in the first boost circuit is reduced from the first frequency to the second frequency; when the average value of the inductor current in the first boost circuit is less than the hiccup threshold, the first boost circuit is controlled to enter hiccup mode. Wherein, the hiccup threshold is less than the frequency reduction threshold, and the hiccup mode is the mode in which the switching transistor in the first boost circuit operates discontinuously.
11. The control method as described in claim 10, characterized in that, The difference between the first frequency and the second frequency is negatively correlated with the hiccup threshold.
12. The control method as described in claim 10 or 11, characterized in that, The first frequency corresponds to the first period, and the second frequency corresponds to the second period. During the first period, the switching transistor in the first boost circuit has a first on-time, and during the second period, the switching transistor in the first boost circuit has a second on-time. The difference between the first on-time and the second on-time is within a preset range. The lower limit of the preset range is -5% of the first period, and the upper limit of the preset range is 5% of the first period.
13. The control method according to any one of claims 10-12, characterized in that, The control method further includes: when the end of at least one second cycle is reached, controlling the switching frequency of the switching transistor in the first boost circuit to return to the first frequency; the second cycle is the reciprocal of the second frequency.