Display substrate and display panel

Abstract

The present disclosure relates to a display substrate and a display panel. The display substrate of the present disclosure comprises: a pixel defining layer, at least partially covering a first electrode and provided with a plurality of pixel openings and at least one accommodating opening, wherein the pixel openings expose at least part of the first electrode, the accommodating opening is located between two adjacent pixel openings, and the material of the pixel defining layer includes a light-shielding material; an isolation structure, located between a layer where a light-emitting functional layer is located and a driving circuit layer, wherein the orthographic projection of the isolation structure on a base substrate at least partially overlaps the orthographic projection of the accommodating opening on the base substrate, and the isolation structure separates at least part of the light-emitting functional layer; at least one encapsulation layer, located on the side of light-emitting devices distant from the base substrate; and a light-shielding layer, located between the encapsulation layer most distant from the base substrate and the driving circuit layer, wherein the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the accommodating opening on the base substrate, and does not overlap the orthographic projections of the pixel openings on the base substrate.

Description

Display substrate and display panel Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) offer advantages such as simple fabrication processes, low cost, high luminous efficiency, ease of forming flexible structures, low power consumption, high color saturation, and wide viewing angles. Display technology utilizing OLEDs has become an important display technology and is currently widely used in display products across various fields. Summary of the Invention

[0003] This disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate and a display panel.

[0004] To achieve the above objectives, this disclosure provides a display substrate, comprising:

[0005] Substrate;

[0006] A driving circuit layer is located on one side of the substrate, and the driving circuit layer includes a plurality of thin-film transistors;

[0007] Multiple light-emitting devices are located on the side of the thin-film transistor away from the substrate. The light-emitting devices are electrically connected to the thin-film transistor and include a first electrode and multiple light-emitting functional layers stacked sequentially along the direction away from the substrate.

[0008] A pixel defining layer at least partially covers the first electrode and has a plurality of pixel openings and at least one receiving opening, wherein the pixel openings expose at least a portion of the first electrode, at least a portion of the light-emitting functional layer is located within the pixel openings, and the receiving opening is located between two adjacent pixel openings, and the material of the pixel defining layer includes a light-shielding material;

[0009] An isolation structure is located between the light-emitting functional layer and the driving circuit layer. The orthographic projection of the isolation structure on the substrate and the orthographic projection of the receiving opening on the substrate at least partially overlap. The isolation structure isolates at least a portion of the light-emitting functional layer.

[0010] At least one encapsulation layer is located on the side of the light-emitting device away from the substrate.

[0011] A light-shielding layer is located between the encapsulation layer furthest from the substrate and the driving circuit layer. The orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the receiving opening on the substrate and does not overlap with the orthographic projection of the pixel opening on the substrate.

[0012] In some embodiments, the isolation structure includes an isolation layer located between the layer containing the first electrode and the driving circuit layer;

[0013] The light-shielding layer is located between the isolation layer and the driving circuit layer;

[0014] The isolation structure further includes an isolation groove formed on the light-shielding layer. The isolation layer includes a first portion, at least a portion of which is located between the pixel defining layer and the light-shielding layer. The orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate. The first portion has a first opening that communicates with the receiving opening and the isolation groove respectively. The orthographic projection of the isolation groove on the substrate includes a first projection area and at least one second projection area. The orthographic projection of the first portion on the substrate covers the second projection area and does not overlap with the first projection area.

[0015] In some embodiments, the isolation layer further includes a second portion connected to the first portion, the second portion being located between the first electrode and the driving circuit layer.

[0016] In some embodiments, the isolation structure includes an isolation pillar, at least a portion of which is located in a receiving opening, and the isolation pillar includes a first surface away from the substrate and a second surface toward the substrate, wherein the orthographic projection of the first surface on the substrate covers and extends beyond the orthographic projection of the second surface on the substrate.

[0017] The light-shielding layer is located between the layer containing the first electrode and the driving circuit layer, and the isolation pillar is located between the layer containing the first electrode and the layer containing the light-emitting functional layer.

[0018] In some embodiments, the receiving opening exposes at least a portion of the light-shielding layer, and the isolation post is disposed in contact with the light-shielding layer.

[0019] In some embodiments, the display substrate further includes an insulating layer located between the layer containing the first electrode and the driving circuit layer;

[0020] The light-shielding layer is located between the insulating layer and the driving circuit layer;

[0021] The insulating layer includes a third portion, at least a portion of which is located between the pixel defining layer and the light-shielding layer, and the orthographic projection of the third portion on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate.

[0022] The isolation pillar is located on the side of the layer containing the third part away from the substrate.

[0023] In some embodiments, the receiving opening exposes at least a portion of the third portion, and the isolation post is disposed in contact with the third portion.

[0024] In some embodiments, the third portion has a second opening communicating with the receiving opening, the second opening exposing at least a portion of the light-shielding layer, and the isolation post is disposed in contact with the light-shielding layer.

[0025] In some embodiments, the insulating layer further includes a fourth portion connected to the third portion, the fourth portion being located between the first electrode and the driving circuit layer.

[0026] In some embodiments, the driving circuit layer further includes a planarization layer located on the side of the thin-film transistor away from the substrate.

[0027] The isolation structure includes an isolation layer, which is located between the planarization layer and the layer containing the first electrode.

[0028] The isolation structure further includes an isolation groove formed on the planarization layer. The isolation layer includes a first portion, which is located between the pixel defining layer and the light-shielding layer and does not overlap with the orthographic projection of the pixel opening on the substrate. The first portion has a first opening that communicates with the receiving opening and the isolation groove respectively. The orthographic projection of the isolation groove on the substrate includes a first projection area and at least one second projection area. The orthographic projection of the first portion on the substrate covers the second projection area and does not overlap with the first projection area.

[0029] The light-shielding layer is located on the side of the light-emitting device away from the substrate.

[0030] In some embodiments, the encapsulation layer is multi-layered, and the light-shielding layer is located between two adjacent encapsulation layers.

[0031] In some embodiments, the light-shielding layer is located between two adjacent encapsulation layers closest to the substrate.

[0032] In some embodiments, the light-emitting device further includes a second electrode located between the light-emitting functional layer and the encapsulation layer, and the light-shielding layer is located between the layer containing the second electrode and the encapsulation layer.

[0033] In some embodiments, the material of the light-shielding layer includes a conductive material, and the light-shielding layer is electrically connected to the second electrodes of two adjacent light-emitting devices.

[0034] In some embodiments, the orthogonal projection of the light-shielding layer on the substrate covers and extends beyond the orthogonal projection of the receiving opening on the substrate.

[0035] This disclosure also provides a display panel, including a display substrate as described in any of the above-described embodiments. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0037] Figure 1 is a schematic cross-sectional view of the display substrate in some embodiments of this disclosure;

[0038] Figure 2 is a schematic cross-sectional view of the display substrate in some other embodiments of this disclosure;

[0039] Figure 3 is a schematic cross-sectional view of the display substrate in some other embodiments of this disclosure;

[0040] Figure 4 is a schematic cross-sectional view of the display substrate in some other embodiments of this disclosure;

[0041] Figure 5 is a cross-sectional structural diagram of a display substrate in some other embodiments of this disclosure;

[0042] Figure 6 is a cross-sectional structural diagram of a display substrate in some other embodiments of this disclosure. Detailed Implementation

[0043] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0047] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0048] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0049] In related technologies, OLED display panels generally include a substrate, a driving circuit layer located on one side of the substrate, and a light-emitting device layer located on the side of the driving circuit layer away from the substrate. The driving circuit layer includes multiple pixel driving circuits, and the light-emitting device layer includes multiple light-emitting devices. The pixel driving circuits are electrically connected to the light-emitting devices, and the pixel driving circuits can provide driving signals to the light-emitting devices to make them emit light.

[0050] A pixel driving circuit typically includes multiple transistors and at least one storage capacitor. For example, the multiple transistors may include a reset transistor, a driving transistor, a compensation transistor, and a light-emitting control transistor. Some of these transistors may be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), while others may be oxide (OPS) thin-film transistors (OTPs). Further, optionally, the active layer of the LTPS TFTs may be made of low-temperature polycrystalline silicon (LTPS), and the active layer of the OPS TFTs may be made of oxide. LTPS TFTs have advantages such as high mobility and fast charging, while OPS TFTs have advantages such as low leakage current. Integrating LTPS and OPS TFTs onto a single pixel circuit forms a low-temperature polycrystalline oxide (LTPO) display panel. This allows for switching the refresh rate of the display panel to achieve low-frequency driving, which helps reduce power consumption and improve display quality. In some products, all thin-film transistors are OPS TFTs.

[0051] The aforementioned thin-film transistors are highly sensitive to light. For example, when light from the environment or light emitted by the light-emitting device enters the area where the thin-film transistor is located, it will affect the driving performance of the thin-film transistor in the light-emitting area. Therefore, it is necessary to set a light-shielding layer in the area where the thin-film transistor is located to block light from entering the area where the thin-film transistor is located, so as to avoid the thin-film transistor being affected by light interference and thus affecting the display effect of the display panel.

[0052] A light-emitting device generally includes a first electrode, a light-emitting functional layer, and a second electrode sequentially stacked along a direction away from the substrate. The first electrode can be electrically connected to a thin-film transistor. The first electrode can be, for example, an anode, and the second electrode can be, for example, a cathode.

[0053] The light-emitting functional layer includes at least one light-emitting material layer and transport material layers located on opposite sides of the light-emitting material layer in its thickness direction. The transport material layers may be, for example, hole transport layers, electron transport layers, hole blocking layers, electron blocking layers, etc.

[0054] Multiple light-emitting devices can emit light of various colors. However, the turn-on voltage of light-emitting devices of different colors is different. For example, the turn-on voltage of a light-emitting device emitting blue light is greater than that of a light-emitting device emitting green light, and also greater than that of a light-emitting device emitting red light.

[0055] When a light-emitting device with a high turn-on voltage is turned on, charge may flow laterally through the transport material layer to the light-emitting material layer emitting other colors of light, causing other light-emitting devices to light up, resulting in color crosstalk and other problems. For example, when a blue light-emitting device is turned on, charge may flow laterally through the transport material layer to the red light-emitting device, causing the red light-emitting device to light up, resulting in color crosstalk.

[0056] Furthermore, with the development of OLED technology, tandem (tandemly stacked) light-emitting devices have gradually attracted attention and are increasingly used in display panels. A tandem light-emitting device is a high-efficiency light-emitting device formed by multiple light-emitting material layers connected in series through interlayers. However, due to the increased number of film layers in a tandem device and the increased density of stacking between these layers, color crosstalk becomes more severe. In some tandem devices, the light-emitting material layers of adjacent devices are even connected as a single unit or overlapped, meaning that when one device with a higher turn-on voltage is lit, the other device is immediately lit as well.

[0057] In order to solve at least one of the aforementioned technical problems, this disclosure provides a display substrate and a display device.

[0058] Figure 1 is a schematic cross-sectional view of the display substrate in some embodiments of this disclosure.

[0059] As shown in FIG1, in some embodiments, a display substrate disclosed herein includes a substrate 10 and a driving circuit layer 20, a light-emitting device 50 layer, and at least one encapsulation layer 80, which are sequentially stacked on one side of the substrate 10 and away from the substrate 10. That is, the light-emitting device 50 layer is located on the side of the driving circuit layer 20 away from the substrate 10, and the encapsulation layer 80 is located on the side of the light-emitting device 50 layer away from the substrate 10. When the encapsulation layer 80 is multi-layered, the multi-layer encapsulation layer 80 is sequentially stacked in the direction away from the substrate 10.

[0060] The light-emitting device 50 layer includes multiple light-emitting devices 50. Each light-emitting device 50 includes a first electrode 51, multiple light-emitting functional layers 52, and a second electrode 53, sequentially stacked along a direction away from the substrate 10. (The light-emitting functional layers 52 and the second electrode 53 are not shown in FIG1.)

[0061] The display substrate also includes a pixel defining layer 60, an isolation structure a, and a light-shielding layer 30.

[0062] The pixel defining layer 60 is located on the side of the layer where the first electrode 51 is located away from the substrate 10. At least a portion of the pixel defining layer 60 covers the first electrode 51. The pixel defining layer 60 has a plurality of pixel openings and at least one receiving opening. The pixel openings expose at least a portion of the first electrode 51. At least a portion of the light-emitting functional layer 52 is located within the pixel openings. The receiving opening is located between two adjacent pixel openings. The material of the pixel defining layer 60 includes a light-shielding material.

[0063] The isolation structure a is located between the layer containing the light-emitting functional layer 52 and the driving circuit layer 20. The orthographic projection of the isolation structure a onto the substrate 10 at least partially overlaps with the orthographic projection of the receiving opening onto the substrate 10. For example, the orthographic projection of the isolation structure a onto the substrate 10 is located within the orthographic projection range of the receiving opening onto the substrate 10. Specifically, at least a portion of the isolation structure a may be located within the receiving opening, or the receiving opening may expose at least a portion of the isolation structure a. The isolation structure a isolates at least a portion of the light-emitting functional layer 52. It is understood that the light-emitting functional layer 52 is multilayered; therefore, the isolation structure a isolates at least a portion of the multilayer light-emitting functional layer 52. For example, in one example, the isolation structure a may isolate all multilayers of the light-emitting functional layer 52.

[0064] Furthermore, for the same light-emitting functional layer 52, the isolation structure a at least isolates the portion of the light-emitting functional layer 52 located between two adjacent light-emitting devices 50.

[0065] For example, in one example, the isolation structure a may surround the light-emitting device 50. In this case, those skilled in the art will understand that the isolation structure a completely isolates the light-emitting functional layer 52 in the circumferential direction surrounding the light-emitting device 50.

[0066] The isolation structure a in this embodiment can completely isolate the light-emitting functional layer 52 surrounding the light-emitting device 50. Therefore, it can greatly alleviate or directly avoid the problem that the light-emitting device 50 with a larger start-up voltage is lit up, causing the light-emitting device 50 with a smaller start-up voltage to be lit up.

[0067] For example, in one instance, the isolation structure a will only isolate the portion of the light-emitting functional layer 52 located between two adjacent light-emitting devices 50. Specifically, the light-emitting functional layer 52 is isolated at or near the midpoint of the line connecting the centers of the two adjacent light-emitting devices 50.

[0068] Specifically, there can be multiple isolation structures a, and at least one isolation structure a is provided between each pair of adjacent light-emitting devices 50 (or between each pair of adjacent pixel openings).

[0069] For example, in one example, an isolation structure a is provided between every two adjacent light-emitting devices 50, which isolates the portion of the light-emitting functional layer 52 located between two adjacent pixel openings. Alternatively, multiple isolation structures a are provided at intervals and surround the pixel openings, and the multiple isolation structures a partially isolate the light-emitting functional layer 52.

[0070] Obviously, in the example above, a portion of the same light-emitting functional layer 52 can be isolated by the isolation structure a, while a portion is not isolated by the isolation structure a.

[0071] In this embodiment of the disclosure, the isolation structure a separates at least part of the light-emitting functional layer 52 located between two adjacent light-emitting devices 50, which can alleviate to some extent the problem that the light-emitting device 50 with a larger start-up voltage is lit up, causing the light-emitting device 50 with a smaller start-up voltage to be lit up.

[0072] Specifically, when the light-emitting functional layer 52 is isolated only at the midpoint or near the center of the line connecting two adjacent light-emitting devices 50, the length of the unisolated light-emitting functional layer 52 that the charge must pass through when flowing from the lit light-emitting device 50 to the unlit light-emitting device 50 is relatively long and has a large resistance. Therefore, when the resistance is large, after the light-emitting device 50 with a larger start-up voltage is lit, the adjacent light-emitting device 50 with a smaller start-up voltage may not be lit.

[0073] Therefore, the embodiments of this disclosure can also avoid the problem that the lighting of the light-emitting device 50 with a larger start-up voltage causes the lighting of the light-emitting device 50 with a smaller start-up voltage to be lit.

[0074] The light-shielding layer 30 is located between the encapsulation layer 80 and the driving circuit layer 20, which are furthest from the substrate 10. The orthogonal projection of the light-shielding layer 30 on the substrate 10 covers the orthogonal projection of the accommodating opening on the substrate 10. The orthogonal projection of the light-shielding layer 30 on the substrate 10 and the orthogonal projection of the pixel opening on the substrate 10 do not overlap.

[0075] Based on the isolation effect of the aforementioned isolation structure a, this embodiment further adds a light-shielding layer 30 between the substrate 10 furthest from the driving circuit layer 20 to block the accommodating opening, thereby preventing ambient light or light emitted by the light-emitting device 50 from entering the relevant film layers of the thin-film transistor. This prevents the thin-film transistor from being affected by light, thus avoiding interference with the driving of the light-emitting device 50, and ultimately preventing the display effect of the display substrate from being affected. Of course, it is understood that the light-shielding layer 30 of this invention cannot cover the pixel opening, thereby avoiding blocking the light emitted by the light-emitting device 50.

[0076] Optionally, as shown in Figure 1, the maximum thickness H1 of the pixel limiting layer 60 is 1 μm to 3 μm, and can further be 1.5 μm to 2.5 μm.

[0077] Optionally, as shown in Figure 1, the maximum thickness H2 of the light-shielding layer 30 is 1 μm to 3 μm, and can further be 1.5 μm to 2.5 μm, for example, 1.3 μm. To ensure the light-shielding effect of the light-shielding layer 30, the minimum thickness of the light-shielding layer 30 is not less than 0.8 μm, for example, 1 μm.

[0078] Optionally, the materials of both the light-shielding layer 30 and the pixel-defining layer 60 may include organic materials, such as polyimide (PI).

[0079] In some embodiments, as shown in FIG1, the isolation structure a includes an isolation layer 40 located between the layer containing the first electrode 51 and the driving circuit layer 20. A light-shielding layer 30 is located between the isolation layer 40 and the driving circuit layer 20.

[0080] As shown in Figure 1, the isolation structure a also includes an isolation groove formed on the light-shielding layer 30.

[0081] Optionally, the depth of the isolation trench can be 0.8μm to 1.5μm, for example, 1μm. Setting the depth of the isolation trench can ensure the isolation effect of the isolation trench.

[0082] The isolation layer 40 includes a first portion 41, at least a portion of which is located between the pixel defining layer 60 and the light-shielding layer 30. The orthographic projection of the first portion 41 on the substrate 10 does not overlap with the orthographic projection of the pixel opening on the substrate 10. The first portion 41 has a first opening that communicates with both the receiving opening and the isolation groove.

[0083] As shown in Figure 1, the orthographic projection of the isolation trench onto the substrate 10 includes a first projection area b and at least one second projection area c. The orthographic projection of the first portion 41 onto the substrate 10 covers the second projection area c and does not overlap with the first projection area b. It is understood that the minimum distance from the wall of the isolation trench to the adjacent light-emitting device 50 is less than the minimum distance from the sidewall of the first opening to the adjacent light-emitting device 50, that is, the isolation layer 40 and the isolation trench can achieve the function of isolating the light-emitting functional layer 52.

[0084] Furthermore, as shown in Figure 1, the maximum distance d1 between the wall of the isolation groove and the central axis L of the isolation groove is greater than the maximum distance d2 between the side wall of the first opening and the central axis L of the isolation groove, thereby further improving the isolation function of the isolation structure 30.

[0085] Optionally, the width of the first opening in the direction of arrangement of two adjacent light-emitting devices 50 is 2μm to 8μm, and can be further 3μm to 6μm, for example 5μm. As shown in Figure 1, the width of the first opening in the direction of arrangement of two adjacent light-emitting devices 50 is d2*2.

[0086] In this embodiment of the disclosure, the first opening exposes the isolation groove. Therefore, the setting of the first opening is conducive to forming the isolation groove at the isolation layer 40, thereby ensuring the isolation effect of the isolation groove.

[0087] In other embodiments, when it is only necessary to isolate a portion of the light-emitting functional layer 52 of two adjacent light-emitting devices 50, the sidewall of the isolation structure a facing the light-emitting device 50 can be designed.

[0088] Specifically, for example, as shown in Figure 1, in the arrangement direction of two adjacent light-emitting devices 50, the first opening has sidewalls arranged opposite to each other, wherein the isolation groove has two groove walls arranged opposite to each other, and the maximum distance d1 from the groove wall to the central axis L of the isolation groove is greater than the distance d2 from the sidewall to the central axis L of the isolation groove.

[0089] In one specific embodiment, along the direction away from the substrate 10, the distance from the first trench wall to the centroidal axis of the isolation trench first gradually increases and then gradually decreases.

[0090] In this embodiment, the isolation layer 40 and the isolation groove can form an undercut structure. Therefore, this embodiment can separate the light-emitting functional layer 52 between two adjacent light-emitting devices 50 through the isolation layer 40 and the isolation groove. Furthermore, it is understood that the separated redundant functional layer is located within the isolation groove.

[0091] In this embodiment, both the light-shielding layer 30 and the isolation structure a are located on the side of the first electrode 51 closest to the substrate 10, meaning that both the light-shielding layer 30 and the isolation structure a need to be formed before the step of fabricating the first electrode 51. Therefore, the isolation structure a further includes an isolation groove formed on the light-shielding layer 30, meaning the light-shielding layer 30 can be reused as part of the isolation structure a. This is equivalent to placing the light-shielding layer 30 and a portion of the isolation structure a in the same layer. It can be understood that the light-shielding layer 30 can be formed simultaneously with the isolation structure a during the formation of the isolation structure a. Therefore, this embodiment simplifies the fabrication process and reduces the complexity of the process.

[0092] Additionally, it should be noted that in this embodiment, since the isolation structure a is formed before the step of preparing the first electrode 51, the isolation structure a may also have a blocking effect on the first electrode 51.

[0093] If the isolation structure a surrounds the light-emitting device 50, it may also isolate the first electrode 51 in the circumferential direction. In this case, the embodiments of this disclosure may not be able to provide auxiliary conductive lines electrically connected to the first electrode 51 in the layer where the first electrode 51 is located to achieve electrical connection with the thin-film transistor in the lower film layer. Therefore, the embodiments of this disclosure are more suitable for display substrates that do not require auxiliary conductive lines to be laid in the layer where the first electrode 51 is located. For example, the first electrode 51 can be directly electrically connected to the thin-film transistor through a via. Specifically, in one example, there is a planarization layer 21 between the first electrode 51 and the thin-film transistor. The first electrode 51 is directly connected to the thin-film transistor through a via penetrating the planarization layer 21, without the need for other auxiliary conductive lines to achieve electrical connection between the first electrode 51 and the thin-film transistor.

[0094] If the orthogonal projection of the isolation structure a onto the substrate 10 only covers a portion of the area between two adjacent light-emitting devices 50 on the substrate 10, that is, in the embodiment where the isolation structure a isolates a portion of the light-emitting functional layer 52 located between two adjacent light-emitting devices 50 as mentioned above, then the first electrode 51 is only partially isolated by the isolation structure a. Therefore, the area not isolated by the isolation structure a can be provided with auxiliary conductive lines to achieve electrical connection with the thin-film transistor in the lower film layer.

[0095] In some embodiments, as shown in FIG1, the isolation layer 40 further includes a second portion 42 connected to the first portion 41, the second portion 42 being located between the first electrode 51 and the driving circuit layer 20.

[0096] Specifically, for example, the driving circuit layer 20 includes a planarization layer 21 located on the side of the thin-film transistor away from the substrate 10, and a second portion 42 is located between the first electrode 51 and the planarization layer 21. Obviously, the orthographic projections of the second portion 42 on the substrate 10 overlap.

[0097] In this embodiment, since the isolation layer 40 needs to form an undercut structure, the isolation layer 40 has a high hardness. Therefore, the second part 42 of the isolation layer 40 is located between the first electrode 51 and the driving circuit layer 20, which can further isolate the driving circuit layer 20 and the light-emitting device 50, and avoid relative displacement between the planarization layer 21 and the light-emitting device 50 due to impact or other reasons, which would have an adverse effect on the display effect.

[0098] In addition, this disclosure also provides a method for fabricating the display substrate shown in FIG1, the steps of which include:

[0099] Step S1: A planarization layer 21 is formed on one side of the substrate 10. Specifically, for example, a thin-film transistor and a planarization layer 21 located on the side of the thin-film transistor away from the substrate 10 are formed on one side of the substrate 10.

[0100] Step S2: A patterned light-shielding material layer is formed on the planarization layer 21, and the light-shielding material layer is located between the first electrodes 51 of two adjacent light-emitting devices 50.

[0101] Step S3: A patterned isolation material layer, a first electrode 51, and a patterned pixel defining layer 60 are then sequentially prepared. The patterned isolation material layer is the isolation layer 40. Furthermore, in this step, the light-shielding material layer also forms a light-shielding layer 30 with isolation grooves during the patterning process of the inorganic material layer. That is, during the patterning process of the isolation material layer, the isolation layer 40 and the isolation layer 40 form an undercut structure.

[0102] Optionally, the material of the isolation layer, i.e., the material of the isolation layer 40, can be an inorganic material, such as SiNx.

[0103] Furthermore, the minimum thickness of the light-shielding layer 30 must be maintained to ensure its light-shielding effect and prevent light leakage. Specifically, the minimum thickness of the light-shielding layer 30 can be controlled by adjusting the film thickness of the inorganic material layer SiNx, the etching time, and the original thickness of the light-shielding material layer. For example, the minimum thickness of the light-shielding layer 30 should not be less than 50 nm. Further, the thickness of the light-shielding layer 30 can be from 50 nm to 250 μm.

[0104] During the subsequent formation of the pixel defining layer 60 in step S3, after the pixel defining layer 60 is developed and removed, the isolation layer 40 and the undercut structure formed by the isolation layer 40 still exist.

[0105] Figure 2 is a cross-sectional view of the display substrate in some other embodiments of this disclosure. Figure 3 is a cross-sectional view of the display substrate in some other embodiments of this disclosure. Figure 4 is a cross-sectional view of the display substrate in some other embodiments of this disclosure.

[0106] As shown in Figures 2, 3, and 4, in some embodiments, the isolation structure a includes an isolation pillar 70. At least a portion of the isolation pillar 70 is located in the receiving opening, and the isolation pillar 70 includes a first surface remote from the substrate 10 and a second surface facing the substrate 10, the orthographic projection of the first surface on the substrate 10 covering and extending beyond the orthographic projection of the second surface on the substrate 10.

[0107] Optionally, the dimension d3 of the surface of the isolation pillar 70 away from the substrate 10 in the arrangement direction of two adjacent light-emitting devices 50 can be 5μm to 15μm, and more preferably 8μm to 10μm. The dimension d4 of the surface of the isolation pillar 70 close to the substrate 10 in the arrangement direction of two adjacent light-emitting devices 50 can be 3μm to 12μm, and more preferably 4μm to 8μm. This embodiment of the present disclosure achieves the isolation effect of the isolation pillar 70 by setting the dimensions d3 and d4.

[0108] Optionally, the thickness H3 of the isolation column 70 can be 1 μm to 3 μm, for example, 2 μm.

[0109] Furthermore, in the direction away from the substrate 10, the area of ​​the cross-section of the isolation pillar 70 perpendicular to the thickness direction of the display substrate is gradually increased. For example, the overall longitudinal section of the isolation pillar 70 presents an "inverted trapezoidal" shape.

[0110] The embodiments disclosed herein can achieve the function of isolating the light-emitting functional layer 52 through the "inverted trapezoidal" isolation pillar 70.

[0111] In other embodiments, when it is only necessary to isolate a portion of the light-emitting functional layer 52 of two adjacent light-emitting devices 50, the sidewall of the isolation structure a facing the light-emitting device 50 can be designed only. For example, in the direction in which the two adjacent light-emitting devices 50 are arranged, the isolation pillar 70 includes two opposing sidewalls, and in the direction away from the substrate 10, the distance from the sidewall to the central axis of the isolation pillar 70 gradually increases.

[0112] In addition, in this embodiment, the light-shielding layer 30 is located between the layer containing the first electrode 51 and the driving circuit layer 20, while the pixel limiting layer 60 is located on the side of the layer containing the first electrode 51 away from the substrate 10. That is, there are relatively few film layers between the light-shielding layer 30 and the pixel limiting layer 60 in this embodiment, which can also be understood as the light-shielding layer 30 and the pixel limiting layer 60 being relatively close.

[0113] Both the light-shielding layer 30 and the pixel-defining layer 60 have light-shielding functions, thus effectively blocking vertically incident light. Furthermore, the light-shielding layer 30 and the pixel-defining layer 60 are close together, resulting in very little space between them for obliquely incident light. Therefore, this embodiment effectively prevents obliquely incident light from leaking through the film gap between the light-shielding layer 30 and the pixel-defining layer 60. It should be noted that in this embodiment, vertically incident light refers to light whose incident direction is parallel to the thickness direction of the display substrate, while obliquely incident light refers to light whose incident direction intersects the thickness direction of the display substrate.

[0114] The isolation pillar 70 is located between the layer containing the first electrode 51 and the layer containing the light-emitting functional layer 52. Specifically, a pixel defining layer 60 is located between the layer containing the first electrode 51 and the layer containing the light-emitting functional layer 52. Therefore, the isolation pillar 70 can be located between the first electrode layer 51 and the pixel defining layer 60, or the isolation pillar 70 can be located between the pixel defining layer 60 and the light-emitting functional layer 52. That is, the present disclosure does not limit the order in which the pixel defining layer 60 and the isolation pillar 70 are fabricated.

[0115] In this embodiment, the light-shielding layer 30 is disposed between the layer containing the first electrode 51 and the driving circuit layer 20, which can prevent light from passing through the film layer between the light-shielding layer 30 and the pixel limiting layer 60 due to the presence of too many film layers between them, thus avoiding light leakage.

[0116] In some embodiments, as shown in Figures 2 and 3, the display substrate further includes an insulating layer 90 located between the layer containing the first electrode 51 and the driving circuit layer 20. A light-shielding layer 30 is located between the insulating layer 90 and the driving circuit layer 20. The insulating layer 90 includes a third portion 91. At least a portion of the third portion 91 is located between the pixel defining layer 60 and the light-shielding layer 30, and the orthographic projection of the third portion 91 onto the substrate 10 does not overlap with the orthographic projection of the pixel opening onto the substrate 10.

[0117] Optionally, the insulating layer 90 can be made of an inorganic material, such as SiNx.

[0118] Obviously, in this embodiment of the present disclosure, there is only a third part 91 of an insulating layer 90 between the pixel limiting layer 60 and the light-shielding layer 30. Therefore, the area between the pixel limiting layer 60 and the light-shielding layer 30 that allows obliquely incident light to pass through is very small. Thus, this embodiment of the present disclosure can block vertically incident light and obliquely incident light to prevent light leakage.

[0119] Among them, the isolation pillar 70 is located on the side of the third part 91 away from the substrate 10.

[0120] In this embodiment, the isolation pillar 70 needs to function as a barrier. Therefore, the area of ​​the cross-section of the isolation pillar 70 perpendicular to the thickness direction of the display substrate decreases as it approaches the substrate 10. As a result, some light may enter from the side of the isolation pillar 70. However, since the light-shielding layer 30 of this embodiment is located on the side of the third part 91 close to the substrate 10, the third part 91 can block the light near the isolation pillar 70, thereby preventing light leakage and ensuring the protection of the thin-film transistor.

[0121] In some embodiments, as shown in FIG2, the receiving opening exposes at least a portion of the third portion 91, and the isolation structure a is disposed in contact with the third portion 91.

[0122] For example, the receiving opening in the pixel limiting layer 60 exposes a portion of the surface of the third portion 91 away from the substrate 10. Therefore, in the embodiment of this disclosure, when forming the isolation pillar 70, the isolation pillar 70 can be directly formed on the side of the surface of the third portion 91 exposed by the receiving opening, which makes it easy to place a portion of the isolation pillar 70 within the receiving opening, thus making it easier to control the formation position of the isolation pillar 70 and minimize the difficulty of the fabrication process.

[0123] In some embodiments, as shown in FIG3, the third portion 91 has a second opening communicating with the receiving opening, the second opening exposing at least a portion of the light-shielding layer 30, and the isolation post 70 is disposed in contact with the light-shielding layer 30.

[0124] It is understood that, in this embodiment of the present disclosure, compared to the embodiment shown in FIG2, an additional step is performed to pattern the insulating layer 90, and the isolation pillar 70 is formed on the surface above the light-shielding layer 30 exposed by the second opening. In this case, the space near the isolation pillar 70 is relatively larger than that in the embodiment shown in FIG2, and the design flexibility of the shape and structure of the isolation pillar 70 is increased, thereby improving the isolation effect of the isolation pillar 70. Furthermore, the accommodating space for the isolated light-emitting functional layer 52 near the isolation pillar 70 is also larger, which is beneficial to the overall design of the display substrate.

[0125] In this embodiment, the isolation structure a is brought into contact with the surface of the light-shielding layer 30 exposed by the second opening. The position of the isolation structure a can be controlled by the position of the second opening, thereby ensuring that the isolation structure a is set in a preset position.

[0126] In the embodiment shown in Figure 2, the insulating layer 90 can provide good support for the isolation structure a, thereby ensuring the positional stability of the isolation structure a and thus ensuring the isolation effect of the isolation structure a on the light-emitting functional layer 52 between two adjacent light-emitting devices 50.

[0127] Furthermore, the material of the insulating layer 90 can be the same as that of the insulating layer 40. Therefore, referring to the structure shown in Figure 1, in the process of patterning the insulating layer 90, the light-shielding layer 30 in Figure 3 may also form an isolation groove similar to that in Figure 1, further increasing the design flexibility of the isolation structure and thus meeting different product requirements.

[0128] In some embodiments, as shown in Figures 2 and 3, the insulating layer 90 further includes a fourth portion 92 connected to the third portion 91, the fourth portion 92 being located between the first electrode 51 and the driving circuit layer 20. Clearly, the orthographic projection of the fourth portion 92 onto the substrate 10 may overlap with the orthographic projection of the pixel opening onto the substrate 10.

[0129] Similarly, the material of the insulating layer 90 can be a material with high hardness. Therefore, by placing the fourth part 92 of the insulating layer 90 between the first electrode 51 and the driving circuit layer 20, the driving circuit layer 20 and the light-emitting device 50 can be further isolated, and the relative displacement between the planarization layer 21 and the light-emitting device 50 due to impact or other reasons can be avoided, which would have an adverse effect on the display effect.

[0130] In some embodiments, as shown in FIG4, the receiving opening exposes at least a portion of the light-shielding layer 30, and the isolation post 70 is disposed in contact with the light-shielding layer 30.

[0131] Compared to the embodiments shown in Figures 2 and 3, the embodiments of this disclosure do not require an additional insulating layer 90. Therefore, the embodiments of this disclosure can reduce one preparation step, thereby simplifying the overall preparation process and reducing the overall process difficulty.

[0132] Furthermore, in this embodiment, the light-shielding layer 30 and the pixel-defining layer 60 are in direct contact, meaning there is no space between them allowing light to pass through. Therefore, the light-shielding layer 30 and the pixel-defining layer 60 can effectively block light from the area between adjacent light-emitting devices 50. Thus, this embodiment achieves a good light leakage prevention effect.

[0133] Accordingly, this disclosure also provides a method for fabricating the display substrate of the embodiments shown in Figures 2 to 4. The method for fabricating the display substrate in the embodiment shown in Figure 2 includes the following steps:

[0134] Step S10: A planarization layer 21 is formed on one side of the substrate 10.

[0135] Step S20: A patterned light-shielding layer 30 is formed on the side of the planarization layer 21 away from the substrate 10, and the orthogonal projection of the light-shielding layer 30 on the substrate 10 is located between the orthogonal projections of the first electrodes 51 of the two adjacent light-emitting devices 50 on the substrate 10.

[0136] Step S30: Then, prepare the insulating material layer, the first electrode 51, the patterned pixel defining layer 60 and the isolation pillar 70 in sequence, or prepare the insulating material layer, the first electrode 51, the isolation pillar 70 and the patterned pixel defining layer 60 in sequence.

[0137] The method for preparing the display substrate in the embodiment shown in Figure 3 includes, in addition to steps S10 to S30 as described above, the method further includes: patterning the insulating material layer after the inorganic material layer is prepared in step S30 and before the first electrode 51 is formed.

[0138] The method for fabricating the display substrate in the embodiment shown in FIG4 includes steps S10 and S20, and further includes: step S40: then sequentially fabricating the first electrode 51, the patterned pixel defining layer 60 and the isolation structure a, or then sequentially fabricating the first electrode 51, the isolation pillar 70 and the patterned pixel defining layer 60.

[0139] Alternatively, the isolation column 70 in this embodiment may be made of organic material.

[0140] Figure 5 is a cross-sectional view of a display substrate according to some other embodiments of the present disclosure. Figure 6 is a cross-sectional view of a display substrate according to some other embodiments of the present disclosure.

[0141] As shown in Figures 5 and 6, in some other embodiments, the driving circuit layer 20 further includes a planarization layer 21 located on the side of the thin-film transistor away from the substrate 10.

[0142] The isolation structure a includes an isolation layer 40, which is located between the planarization layer 21 and the layer containing the first electrode 51.

[0143] The isolation structure a further includes an isolation trench formed on the planarization layer 21. The isolation layer 40 includes a first portion 41 located between the pixel defining layer 60 and the light-shielding layer 30. The first portion 41 has a first opening that communicates with both the receiving opening and the isolation trench. The orthographic projection of the isolation trench onto the substrate 10 includes a first projection area and at least one second projection area. The orthographic projection of the first portion 41 onto the substrate 10 covers the second projection area but does not overlap with the first projection area. The light-shielding layer 30 is located on the side of the light-emitting device 50 away from the substrate 10.

[0144] Similar to the embodiment shown in FIG1, the isolation trench formed by the isolation layer 40 and the planarization layer 21 can isolate the light-emitting functional layer 52. In addition, compared with the embodiment shown in FIG1, the light-shielding layer 30 is disposed on the side of the light-emitting device 50 away from the substrate 10, increasing the distance between the light-shielding layer 30 and the light-emitting device 50. Therefore, the light-shielding layer 30 of the present disclosure can prevent crosstalk between different colors of light emitted by two adjacent light-emitting devices 50.

[0145] In some embodiments, as shown in FIG5, the encapsulation layer 80 is multi-layered, and the light-shielding layer 30 is located between two adjacent encapsulation layers 80.

[0146] For example, in one embodiment, the multilayer encapsulation layer 80 includes a first inorganic layer 81, an organic layer 82, and a second inorganic layer 83 sequentially stacked along a direction away from the substrate 10. The light-shielding layer 30 may be located between the first inorganic layer 81 and the organic layer 82, or it may be located between the organic layer 82 and the second inorganic layer 83.

[0147] In some embodiments, as shown in FIG5, the light-shielding layer 30 is located between two adjacent encapsulation layers 80 closest to the substrate 10.

[0148] For example, the light-shielding layer 30 is located between the first inorganic layer 81 and the organic layer 82. Considering that the light-shielding layer 30 is located on the side of the light-emitting device 50 away from the substrate 10, that is, there will be other film layers between the light-shielding layer 30 and the light-emitting material layer, in order to prevent the light emitted by the light-emitting device 50 or the light in the environment from being transmitted through the film layer between the light-shielding layer 30 and the light-emitting material layer to the area where the opening is located and then incident on the film surface of the thin-film transistor, the light-shielding layer 30 is made as close as possible to the light-emitting device 50, thereby reducing the distance between the light-shielding layer 30 and the light-emitting material layer and reducing the amount of light that can be transmitted.

[0149] Obviously, in this embodiment of the present disclosure, the light-shielding layer 30 is disposed between two adjacent encapsulation layers 80 closest to the substrate 10, mainly to prevent obliquely incident light from being transmitted through the area between the pixel limiting layer 60 and the light-shielding layer 30, thus preventing light leakage.

[0150] In some embodiments, as shown in FIG6, the light-emitting device 50 further includes a second electrode 53 located on the side of the light-emitting functional layer 52 away from the substrate 10, and a light-shielding layer 30 located on the side of the layer where the second electrode 53 is located away from the substrate 10.

[0151] In this embodiment, the second electrode 53 can be formed after the second electrode 53 is formed, to shield the area between two adjacent light-emitting devices 50. Compared to the embodiment shown in FIG. 5, it is closer to the pixel defining layer 60, which can further prevent obliquely incident light from transmitting through the area between the pixel defining layer 60 and the light-shielding layer 30, thus avoiding light leakage. Furthermore, the embodiments of this disclosure are fabricated between the light-emitting device 50 and the encapsulation layer 80, therefore, it will not affect the original fabrication process of the light-emitting device 50 and the encapsulation layer 80.

[0152] In some embodiments, as shown in FIG6, the material of the light-shielding layer 30 includes a conductive material, and the light-shielding layer 30 is electrically connected to the second electrodes 53 of two adjacent light-emitting devices 50.

[0153] In this embodiment of the present disclosure, after the second electrode 53 is formed, a light-shielding layer 30 is formed directly on the side of the second electrode 53 away from the substrate 10 using a conductive material. Furthermore, the light-shielding layer 30 can be connected to two adjacent second electrodes 53. Therefore, in this embodiment of the present disclosure, the light-shielding layer 30 can be used to electrically connect two adjacent second electrodes 53, thereby reducing the resistance of the second electrode 53.

[0154] It is understood that in the embodiments disclosed herein, the light-shielding layer 30 can not only serve as a light-shielding layer, but also as an auxiliary electrode, specifically by helping to reduce the resistance of the second electrode 53, thereby further reducing the power consumption of the entire display substrate.

[0155] For example, in one instance, if the isolation structure a surrounds the light-emitting device 50, the isolation structure a may also isolate the second electrode 53 in the circumferential direction, resulting in the isolation of the second electrodes 53 of different light-emitting devices 53. In this case, the light-shielding layer 30 in this embodiment can serve as an auxiliary electrode to electrically connect the second electrodes 53 of different light-emitting devices.

[0156] In addition, this disclosure also provides a method for fabricating the display substrate shown in Figures 5 and 6, the steps of which include:

[0157] Step S01: A planarization layer 21 is formed on one side of the substrate 10. Specifically, for example, a thin-film transistor and a planarization layer 21 located on the side of the thin-film transistor away from the substrate 10 are formed on one side of the substrate 10.

[0158] Step S02: A patterned insulating material layer is formed on the side of the planarization layer 21 away from the substrate 10, and the insulating material layer is located between the first electrodes 51 of two adjacent light-emitting devices 50. After patterning the insulating material layer, an isolation layer 40 and a planarization layer 21 with isolation trenches can be obtained, and the isolation trenches and the isolation layer 40 form an isolation structure a.

[0159] Step S03: On the side of the isolation layer 40 away from the substrate 10, a first electrode 51, a patterned pixel limiting layer 60, a light-emitting functional layer 52, a second electrode 53, and a multilayer encapsulation layer 80 are formed in sequence.

[0160] In the case shown in Figure 5, the light-shielding layer 30 is formed between the two encapsulation layers 80 in step S03. In the case shown in Figure 6, the light-shielding layer 30 is formed after the second electrode 53 is formed in step S03.

[0161] In some embodiments, as shown in Figures 1 to 6, the orthographic projection of the light-shielding layer 30 on the substrate 10 covers and extends beyond the orthographic projection of the receiving opening on the substrate 10. That is, the orthographic projection of the light-shielding layer 30 on the substrate 10 overlaps with the orthographic projection of the pixel defining layer 60 on the substrate 10. In this case, since both the light-shielding layer 30 and the pixel defining layer 60 have light-shielding functions, the light-shielding layer 30 and the pixel defining layer 60 in the embodiments of this disclosure can provide better light leakage prevention for the area between the two light-emitting devices 50.

[0162] Furthermore, in the embodiments shown in Figures 1, 2, and 3, there is only one film layer between the pixel limiting layer 60 and the light-shielding layer 30, which has a light-shielding function. Specifically, in the embodiment shown in Figure 1, an isolation layer 40 is provided between the pixel limiting layer 60 and the light-shielding layer 30, and in the embodiments shown in Figures 2 and 3, an insulating layer 90 is provided between the pixel limiting layer 60 and the light-shielding layer 30. Therefore, the area where light can leak between the pixel limiting layer 60 and the light-shielding layer 30 is relatively narrow and small. When the orthographic projection of the light-shielding layer 30 on the substrate 10 overlaps with the orthographic projection of the pixel limiting layer 60 on the substrate 10, the pixel limiting layer 60 and the light-shielding layer 30 can block light and prevent light from transmitting to the film layer where the thin-film transistor is located.

[0163] In the embodiments shown in Figures 4 and 5, although the film layer between the pixel defining layer 60 and the light-shielding layer 30 has at least one more film layer than in the embodiments shown in Figures 1 to 3, since the light-shielding layer 30 is located on the side of the light-emitting device 50 away from the substrate 10, the formation of the light-shielding layer 30 is after the formation of the light-emitting device 50. Therefore, it does not affect the formation of the light-emitting device 50 in terms of the fabrication process. Furthermore, those skilled in the art will understand that the display panel also includes a black matrix layer (BM) located on the side of the encapsulation layer 80 away from the substrate 10. The black matrix layer has light-transmitting openings, and the orthogonal projection of the light-transmitting openings on the substrate 10 can cover the orthogonal projection of the pixel openings on the substrate 10. Therefore, in some products, the black matrix layer can also cover and accommodate the orthogonal projection of the openings on the substrate 10. In this case, the fabrication process for the black matrix layer can be used to fabricate the light-shielding layer 30, thereby minimizing the fabrication difficulty of the display substrate in this embodiment.

[0164] Those skilled in the art can configure the isolation structure a and the light-shielding layer 30 according to actual needs.

[0165] In summary, the design scheme disclosed herein can not only satisfy the function of isolating the light-emitting functional layer 52 between adjacent light-emitting devices 50, but also block light through the light-shielding layer 30 to avoid light affecting the device characteristics of the thin-film transistor.

[0166] This disclosure also provides a display device, including a display substrate as described in any of the embodiments of this disclosure.

[0167] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, characterized in that, include: Substrate; A driving circuit layer is located on one side of the substrate, and the driving circuit layer includes a plurality of thin-film transistors; Multiple light-emitting devices are located on the side of the thin-film transistor away from the substrate. The light-emitting devices are electrically connected to the thin-film transistor and include a first electrode and multiple light-emitting functional layers stacked sequentially along the direction away from the substrate. A pixel defining layer at least partially covers the first electrode and has a plurality of pixel openings and at least one receiving opening, wherein the pixel openings expose at least a portion of the first electrode, at least a portion of the light-emitting functional layer is located within the pixel openings, and the receiving opening is located between two adjacent pixel openings, and the material of the pixel defining layer includes a light-shielding material; An isolation structure is located between the light-emitting functional layer and the driving circuit layer. The orthographic projection of the isolation structure on the substrate and the orthographic projection of the receiving opening on the substrate at least partially overlap. The isolation structure isolates at least a portion of the light-emitting functional layer. At least one encapsulation layer is located on the side of the light-emitting device away from the substrate. A light-shielding layer is located between the encapsulation layer furthest from the substrate and the driving circuit layer. The orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the receiving opening on the substrate and does not overlap with the orthographic projection of the pixel opening on the substrate.

2. The display substrate according to claim 1, characterized in that, The isolation structure includes an isolation layer located between the layer containing the first electrode and the driving circuit layer; The light-shielding layer is located between the isolation layer and the driving circuit layer; The isolation structure further includes an isolation groove formed on the light-shielding layer. The isolation layer includes a first portion, at least a portion of which is located between the pixel defining layer and the light-shielding layer. The orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate. The first portion has a first opening that communicates with the receiving opening and the isolation groove respectively. The orthographic projection of the isolation groove on the substrate includes a first projection area and at least one second projection area. The orthographic projection of the first portion on the substrate covers the second projection area and does not overlap with the first projection area.

3. The display substrate according to claim 2, characterized in that, The isolation layer also includes a second portion connected to the first portion, the second portion being located between the first electrode and the driving circuit layer.

4. The display substrate according to claim 1, characterized in that, The isolation structure includes an isolation pillar, at least a portion of which is located in a receiving opening, and the isolation pillar includes a first surface away from the substrate and a second surface facing the substrate, wherein the orthographic projection of the first surface on the substrate covers and extends beyond the orthographic projection of the second surface on the substrate. The light-shielding layer is located between the layer containing the first electrode and the driving circuit layer, and the isolation pillar is located between the layer containing the first electrode and the layer containing the light-emitting functional layer.

5. The display substrate according to claim 4, characterized in that, The receiving opening exposes at least a portion of the light-shielding layer, and the isolation post is disposed in contact with the light-shielding layer.

6. The display substrate according to claim 4, characterized in that, The display substrate further includes an insulating layer located between the layer containing the first electrode and the driving circuit layer; The light-shielding layer is located between the insulating layer and the driving circuit layer; The insulating layer includes a third portion, at least a portion of which is located between the pixel defining layer and the light-shielding layer, and the orthographic projection of the third portion on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate. The isolation pillar is located on the side of the layer containing the third part away from the substrate.

7. The display substrate according to claim 6, characterized in that, The receiving opening exposes at least a portion of the third part, and the isolation column is disposed in contact with the third part.

8. The display substrate according to claim 6, characterized in that, The third part has a second opening that communicates with the receiving opening, the second opening exposing at least a portion of the light-shielding layer, and the isolation post is disposed in contact with the light-shielding layer.

9. The display substrate according to claim 6, characterized in that, The insulating layer also includes a fourth portion connected to the third portion, the fourth portion being located between the first electrode and the driving circuit layer.

10. The display substrate according to claim 1, characterized in that, The driving circuit layer also includes a planarization layer located on the side of the thin-film transistor away from the substrate. The isolation structure includes an isolation layer, which is located between the planarization layer and the layer containing the first electrode. The isolation structure further includes an isolation groove formed on the planarization layer. The isolation layer includes a first portion, which is located between the pixel defining layer and the light-shielding layer and does not overlap with the orthographic projection of the pixel opening on the substrate. The first portion has a first opening that communicates with the receiving opening and the isolation groove respectively. The orthographic projection of the isolation groove on the substrate includes a first projection area and at least one second projection area. The orthographic projection of the first portion on the substrate covers the second projection area and does not overlap with the first projection area. The light-shielding layer is located on the side of the light-emitting device away from the substrate.

11. The display substrate according to claim 10, characterized in that, The encapsulation layer is multi-layered, and the light-shielding layer is located between two adjacent encapsulation layers.

12. The display substrate according to claim 11, characterized in that, The light-shielding layer is located between the two adjacent encapsulation layers closest to the substrate.

13. The display substrate according to claim 10, characterized in that, The light-emitting device further includes a second electrode located between the light-emitting functional layer and the encapsulation layer, and the light-shielding layer is located between the layer containing the second electrode and the encapsulation layer.

14. The display substrate according to claim 13, characterized in that, The material of the light-shielding layer includes a conductive material, and the light-shielding layer is electrically connected to the second electrodes of two adjacent light-emitting devices.

15. The display substrate according to any one of claims 1 to 14, characterized in that, The light-shielding layer's orthogonal projection on the substrate covers and extends beyond the orthogonal projection of the receiving opening on the substrate.

16. A display panel, characterized by Includes the display substrate as described in any one of claims 1 to 15.

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