Driving circuit, driving module, and display device

Abstract

The present disclosure provides a driving circuit, a driving module, and a display device. The driving circuit comprises an input circuit, N output control circuits, and N driving output circuits, N being a positive integer. The input circuit controls the potential of a first node on the basis of an input signal. Under the control of a control voltage, an n-th output control circuit controls the first node to be connected to or disconnected from an n-th output control node, n being a positive integer less than or equal to N. Under the control of the potential of the n-th output control node, an n-th driving output circuit provides an n-th output clock signal to an n-th driving output terminal. The present disclosure facilitates attaining a narrow bezel.

Description

Drive circuit, drive module and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510378152.3, filed in China on March 27, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a driving circuit, a driving module, and a display device. Background Technology

[0004] The related driving circuit cannot easily control multiple driving output terminals to output corresponding driving signals through a first node, which is not conducive to reducing the number of transistors used and to achieving a narrow bezel. Summary of the Invention

[0005] The main objective of this disclosure is to provide a driving circuit that solves the problem that existing driving circuits are not conducive to reducing the number of transistors used and to achieving a narrow bezel.

[0006] In a first aspect, embodiments of this disclosure provide a driving circuit, including an input circuit, N output control circuits, and N driving output circuits; where N is a positive integer.

[0007] The input circuit is electrically connected to the input terminal and the first node, and is used to control the potential of the first node according to the input signal provided by the input terminal;

[0008] The nth output control circuit is electrically connected to the control voltage terminal, the first node, and the nth output control node, respectively, and is used to control the connection or disconnection between the first node and the nth output control node under the control of the control voltage provided by the control voltage terminal; n is a positive integer less than or equal to N;

[0009] The nth drive output circuit is electrically connected to the nth output control node, the nth drive output terminal, and the nth output clock signal terminal, respectively, and is used to provide the nth output clock signal provided by the nth output clock signal terminal to the nth drive output terminal under the control of the potential of the nth output control node.

[0010] Optionally, both the transistors in the input circuit and the transistors in the nth output control circuit are n-type transistors, and the difference between the threshold voltage of the transistor in the nth output control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; or,

[0011] The transistors included in the input circuit and the transistors included in the nth output control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal.

[0012] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes N energy storage circuits;

[0013] The first terminal of the nth energy storage circuit is electrically connected to the nth output control node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive output terminal.

[0014] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal;

[0015] The second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the first voltage terminal, respectively, and is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node.

[0016] The first node control circuit is electrically connected to the first second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

[0017] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal and a second control voltage terminal;

[0018] The second node control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the first node, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. It is also used to control the potential of the second second node according to the second control voltage terminal, and to control the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node.

[0019] The first node control circuit is electrically connected to the first second node, the second second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

[0020] Optionally, the driving circuit further includes a control circuit; the input circuit includes a first input circuit and a second input circuit; the control circuit is electrically connected to the first node, the power supply voltage terminal, and the control node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node; the first input circuit is electrically connected to the input terminal and the control node respectively, and is used to control the potential of the control node according to the input signal; the second input circuit is electrically connected to the input terminal, the control node, and the first node respectively, and is used to control the connection or disconnection between the control node and the first node under the control of the input signal; or,

[0021] The driving circuit further includes a control circuit. The input circuit includes a first input circuit and a second input circuit. The control circuit includes a first control circuit and a second control circuit. The first control circuit is electrically connected to a first node, a power supply voltage terminal, and a control node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node. The second control circuit is electrically connected to the first node, the power supply voltage terminal, and an intermediate node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the intermediate node under the control of the potential of the first node. The first input circuit is electrically connected to the input terminal and the intermediate node, respectively, and is used to control the potential of the intermediate node according to the input signal. The second input circuit is electrically connected to the input terminal, the intermediate node, and the first node, respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the input signal.

[0022] Optionally, the control voltage terminal includes a first control voltage terminal; the first node control circuit includes a first first node control circuit and a second first node control circuit.

[0023] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0024] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node.

[0025] Optionally, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the first node control circuit includes a first first node control circuit, a second first node control circuit, a third first node control circuit and a fourth first node control circuit;

[0026] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0027] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node;

[0028] The third first node control circuit is electrically connected to the second second node, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the second second node;

[0029] The fourth first node control circuit is electrically connected to the second second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the second second node.

[0030] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit and a second first node reset circuit;

[0031] The first node reset circuit is electrically connected to the reset control terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the reset control signal provided by the reset control terminal.

[0032] The second first node reset circuit is electrically connected to the reset control terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the reset control signal.

[0033] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit and a second frame reset circuit.

[0034] The first frame reset circuit is electrically connected to the frame reset terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the frame reset signal provided by the frame reset terminal.

[0035] The second frame reset circuit is electrically connected to the frame reset terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the frame reset signal.

[0036] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes N output reset circuits;

[0037] The nth output reset circuit is electrically connected to the first second node, the nth drive output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node.

[0038] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes N output reset circuits;

[0039] The nth output reset circuit is electrically connected to the first second node, the second second node, the nth drive output terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the second second node.

[0040] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit and a carry energy storage circuit;

[0041] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0042] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0043] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit, a carry output control circuit, and a carry energy storage circuit;

[0044] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0045] The carry-out control circuit is electrically connected to the first control voltage terminal, the carry-out node, and the first node, respectively, and is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal.

[0046] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0047] Optionally, both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors, and the difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal; or,

[0048] The transistors included in the input circuit and the transistors included in the carry-out control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal.

[0049] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit and a carry energy storage circuit;

[0050] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the second second node.

[0051] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0052] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit, a carry output control circuit, and a carry energy storage circuit;

[0053] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal to the carry output terminal under the control of the potential of the second second node.

[0054] The carry-out control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the carry-out node, and the first node, respectively. It is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the carry-out node and the first node under the control of the second control voltage provided by the second control voltage terminal.

[0055] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0056] Optionally, both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the first control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. Similarly, the difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the second control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal. Alternatively,

[0057] Both the transistors in the input circuit and the transistors in the carry-out control circuit are p-type transistors. The difference between the threshold voltage of the transistor whose gate is electrically connected to the first control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the transistor whose gate is electrically connected to the second control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

[0058] Optionally, the input circuit includes an input transistor; the gate and the first terminal of the input transistor are electrically connected to the input terminal, and the second terminal of the input transistor is electrically connected to the first node;

[0059] The control voltage terminal includes a first control voltage terminal; the nth output control circuit includes an nth first transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; or, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the nth output control circuit includes an nth first transistor and an nth second transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; the gate of the nth second transistor is electrically connected to the second control voltage terminal, the first electrode of the nth second transistor is electrically connected to the nth output control node, and the second electrode of the nth second transistor is electrically connected to the first node.

[0060] Optionally, the control circuit includes a control transistor; the first input circuit includes a first input transistor; the second input circuit includes a second input transistor; the gate of the control transistor is electrically connected to the first node; the first terminal of the control transistor is electrically connected to the power supply voltage terminal; and the second terminal of the control transistor is electrically connected to the control node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal; the second terminal of the first input transistor is electrically connected to the control node; the gate of the second input transistor is electrically connected to the input terminal; the first terminal of the second input transistor is electrically connected to the control node; and the second terminal of the second input transistor is electrically connected to the first node; or...

[0061] The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; the first input circuit includes a first input transistor, and the second input circuit includes a second input transistor; the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first control transistor is electrically connected to the control node; the gate of the second control transistor is electrically connected to the first node, the first terminal of the second control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the second control transistor is electrically connected to the intermediate node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal, and the second terminal of the first input transistor is electrically connected to the intermediate node; the gate of the second input transistor is electrically connected to the input terminal, the first terminal of the second input transistor is electrically connected to the intermediate node, and the second terminal of the second input transistor is electrically connected to the first node.

[0062] Optionally, the second node control circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor;

[0063] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0064] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0065] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0066] Optionally, the second node control circuit includes a third transistor, a fourth transistor, a sixth transistor, and a seventh transistor; the first node control circuit includes a fifth transistor and an eighth transistor.

[0067] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0068] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0069] The gate and first terminal of the sixth transistor are electrically connected to the second control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second second node;

[0070] The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal.

[0071] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0072] The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

[0073] Optionally, the first first node control circuit includes a first fifth transistor, and the second first node control circuit includes a second fifth transistor;

[0074] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0075] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0076] Optionally, the first first node control circuit includes a first fifth transistor, the second first node control circuit includes a second fifth transistor; the third first node control circuit includes a first eighth transistor, and the fourth first node control circuit includes a second eighth transistor.

[0077] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0078] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0079] The gate of the first eighth transistor is electrically connected to the second second node, the first terminal of the first eighth transistor is electrically connected to the first node, and the second terminal of the first eighth transistor is electrically connected to the control node.

[0080] The gate of the second eighth transistor is electrically connected to the second second node, the first terminal of the second eighth transistor is electrically connected to the control node, and the second terminal of the second eighth transistor is electrically connected to the first voltage terminal.

[0081] Optionally, the first first node reset circuit includes a first ninth transistor, and the second first node reset circuit includes a second ninth transistor;

[0082] The gate of the first ninth transistor is electrically connected to the reset control terminal, the first terminal of the first ninth transistor is electrically connected to the first node, and the second terminal of the first ninth transistor is electrically connected to the control node.

[0083] The gate of the second ninth transistor is electrically connected to the reset control terminal, the first terminal of the second ninth transistor is electrically connected to the control node, and the second terminal of the second ninth transistor is electrically connected to the first voltage terminal.

[0084] Optionally, the first frame reset circuit includes a first tenth transistor, and the second frame reset circuit includes a second tenth transistor;

[0085] The gate of the first tenth transistor is electrically connected to the frame reset terminal, the first terminal of the first tenth transistor is electrically connected to the first node, and the second terminal of the first tenth transistor is electrically connected to the control node.

[0086] The gate of the second tenth transistor is electrically connected to the frame reset terminal, the first terminal of the second tenth transistor is electrically connected to the control node, and the second terminal of the second tenth transistor is electrically connected to the first voltage terminal.

[0087] Optionally, the nth output reset circuit includes an nth output reset transistor;

[0088] The gate of the nth output reset transistor is electrically connected to the first second node, the first terminal of the nth output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth output reset transistor is electrically connected to the second voltage terminal.

[0089] Optionally, the nth output reset circuit includes an nth first output reset transistor and an nth second output reset transistor;

[0090] The gate of the nth first output reset transistor is electrically connected to the first second node, the first terminal of the nth first output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth first output reset transistor is electrically connected to the second voltage terminal.

[0091] The gate of the nth second output reset transistor is electrically connected to the second second node, the first terminal of the nth second output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth second output reset transistor is electrically connected to the second voltage terminal.

[0092] Optionally, the carry output circuit includes a carry capacitor, a carry output transistor, and a first carry reset transistor;

[0093] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0094] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0095] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0096] Optionally, the carry output circuit includes a carry output transistor and a first carry reset transistor; the carry output control circuit includes a first carry output control transistor; and the carry energy storage circuit includes a carry capacitor.

[0097] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0098] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0099] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0100] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0101] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry energy storage circuit includes a carry capacitor.

[0102] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0103] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0104] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0105] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0106] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry output control circuit includes a first carry output control transistor and a second carry output control transistor.

[0107] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0108] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0109] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0110] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0111] The gate of the second carry-out control transistor is electrically connected to the second control voltage terminal, the first terminal of the second carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the second carry-out control transistor is electrically connected to the first node.

[0112] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0113] Optionally, the nth drive output circuit includes an nth drive output transistor, and the nth energy storage circuit includes an nth output capacitor;

[0114] The gate of the nth driving output transistor is electrically connected to the nth output control node, the first terminal of the nth driving output transistor is electrically connected to the nth output clock signal terminal, and the second terminal of the nth driving output transistor is electrically connected to the nth driving output terminal.

[0115] The first terminal of the nth output capacitor is electrically connected to the nth output control node, and the second terminal of the nth output capacitor is electrically connected to the nth drive output terminal.

[0116] In a second aspect, embodiments of this disclosure provide a drive module including multiple stages of the drive circuits described above.

[0117] In a third aspect, embodiments of this disclosure provide a display device including the driving module described above.

[0118] The driving circuit, driving module, and display device described in this disclosure can reduce the number of transistors used, which is not conducive to achieving a narrow bezel. Attached Figure Description

[0119] Figure 1A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0120] Figure 1B is a structural diagram of the first part of Figure 1A;

[0121] Figure 1C is a structural diagram of the second part of Figure 1A;

[0122] Figure 2A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0123] Figure 2B is a structural diagram of the first part of Figure 2A;

[0124] Figure 2C is a structural diagram of the second part of Figure 2A;

[0125] Figure 3A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0126] Figure 3B is a structural diagram of the first part of Figure 3A;

[0127] Figure 3C is a structural diagram of the second part of Figure 3A;

[0128] Figure 4A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0129] Figure 4B is a structural diagram of the first part of Figure 4A;

[0130] Figure 4C is a structural diagram of the second part of Figure 4A;

[0131] Figure 5A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0132] Figure 5B is a structural diagram of the first part of Figure 5A;

[0133] Figure 5C is a structural diagram of the second part of Figure 5A;

[0134] Figure 6A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0135] Figure 6B is a structural diagram of the first part of Figure 6A;

[0136] Figure 6C is a structural diagram of the second part of Figure 6A;

[0137] Figure 7A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0138] Figure 7B is a structural diagram of the first part of Figure 7A;

[0139] Figure 7C is a structural diagram of the second part of Figure 7A;

[0140] Figure 8A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0141] Figure 8B is a structural diagram of the first part of Figure 8A;

[0142] Figure 8C is a structural diagram of the second part of Figure 8A;

[0143] Figure 9A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0144] Figure 9B is a structural diagram of the first part of Figure 9A;

[0145] Figure 9C is a structural diagram of the second part of Figure 9A;

[0146] Figure 10A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0147] Figure 10B is a structural diagram of the first part of Figure 10A;

[0148] Figure 10C is a structural diagram of the second part of Figure 10A;

[0149] Figure 11A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0150] Figure 11B is a structural diagram of the first part of Figure 11A;

[0151] Figure 11C is a structural diagram of the second part of Figure 11A;

[0152] Figure 12A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0153] Figure 12B is a structural diagram of the first part of Figure 12A;

[0154] Figure 12C is a structural diagram of the second part of Figure 12A;

[0155] Figure 13A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0156] Figure 13B is a structural diagram of the first part of Figure 13A;

[0157] Figure 13C is a structural diagram of the second part of Figure 13A;

[0158] Figure 14A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0159] Figure 14B is a structural diagram of the first part of Figure 14A;

[0160] Figure 14C is a structural diagram of the second part of Figure 14A;

[0161] Figure 15A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0162] Figure 15B is a structural diagram of the first part of Figure 15A;

[0163] Figure 15C is a structural diagram of the second part of Figure 15A;

[0164] Figure 15D is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0165] Figure 15E is a structural diagram of the second part of Figure 15D;

[0166] Figure 16A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0167] Figure 16B is a structural diagram of the first part of Figure 16A;

[0168] Figure 16C is a structural diagram of the second part of Figure 16A;

[0169] Figure 17A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0170] Figure 17B is a structural diagram of the first part of Figure 17A;

[0171] Figure 17C is a structural diagram of the second part of Figure 17A;

[0172] Figure 18A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0173] Figure 18B is a structural diagram of the first part of Figure 18A;

[0174] Figure 18C is a structural diagram of the second part of Figure 18A;

[0175] Figure 19A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0176] Figure 19B is a structural diagram of the first part of Figure 19A;

[0177] Figure 19C is a structural diagram of the second part of Figure 19A;

[0178] Figure 20A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0179] Figure 20B is a structural diagram of the first part of Figure 20A;

[0180] Figure 20C is a structural diagram of the second part of Figure 20A;

[0181] Figure 21A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0182] Figure 21B is a structural diagram of the first part of Figure 21A;

[0183] Figure 21C is a structural diagram of the second part of Figure 21A;

[0184] Figure 21D is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0185] Figure 21E is a structural diagram of the second part of Figure 21D;

[0186] Figure 22A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0187] Figure 22B is a structural diagram of the first part of Figure 22A;

[0188] Figure 22C is a structural diagram of the second part of Figure 22A;

[0189] Figure 22D is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0190] Figure 22E is a structural diagram of the second part of Figure 22D;

[0191] Figure 23A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0192] Figure 23B is a structural diagram of the first part of Figure 23A;

[0193] Figure 23C is a structural diagram of the second part of Figure 23A;

[0194] Figure 24A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0195] Figure 24B is a structural diagram of the first part of Figure 24A;

[0196] Figure 24C is a structural diagram of the second part of Figure 24A;

[0197] Figure 24D is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0198] Figure 24E is a structural diagram of the second part of Figure 24D;

[0199] Figure 25A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0200] Figure 25B is a structural diagram of the first part of Figure 25A;

[0201] Figure 25C is a structural diagram of the second part of Figure 25A;

[0202] Figure 26A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0203] Figure 26B is a structural diagram of the first part of Figure 26A;

[0204] Figure 26C is a structural diagram of the second part of Figure 26A;

[0205] Figure 26D is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0206] Figure 26E is a structural diagram of the second part of Figure 26D;

[0207] Figure 27A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0208] Figure 27B is a structural diagram of the first part of Figure 27A;

[0209] Figure 27C is a structural diagram of the second part of Figure 27A;

[0210] Figure 28A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0211] Figure 28B is a structural diagram of the first part of Figure 28A;

[0212] Figure 28C is a structural diagram of the second part of Figure 28A;

[0213] Figure 29A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0214] Figure 29B is a structural diagram of the first part of Figure 29A;

[0215] Figure 29C is a structural diagram of the second part of Figure 29A;

[0216] Figure 30A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0217] Figure 30B is a structural diagram of the first part of Figure 30A;

[0218] Figure 30C is a structural diagram of the second part of Figure 30A;

[0219] Figure 31 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0220] Figure 32 is a timing diagram of at least one embodiment of the drive module shown in Figure 31. Detailed Implementation

[0221] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0222] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0223] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0224] The driving circuit described in this embodiment includes an input circuit, N output control circuits, and N driving output circuits; N is a positive integer.

[0225] The input circuit is electrically connected to the input terminal and the first node, and is used to control the potential of the first node according to the input signal provided by the input terminal;

[0226] The nth output control circuit is electrically connected to the control voltage terminal, the first node, and the nth output control node, respectively, and is used to control the connection or disconnection between the first node and the nth output control node under the control of the control voltage provided by the control voltage terminal; n is a positive integer less than or equal to N;

[0227] The nth drive output circuit is electrically connected to the nth output control node, the nth drive output terminal, and the nth output clock signal terminal, respectively, and is used to provide the nth output clock signal provided by the nth output clock signal terminal to the nth drive output terminal under the control of the potential of the nth output control node.

[0228] When the driving circuit described in this embodiment is working, the nth output control circuit controls the connection or disconnection between the first node and the nth output control node under the control of the control voltage; the nth drive output circuit provides the nth output clock signal to the nth drive output terminal under the control of the potential of the nth output control node; the driving circuit described in this embodiment can control N drive output terminals to output corresponding drive signals through one first node, which can reduce the number of transistors used and facilitate the realization of narrow bezels.

[0229] Optionally, both the transistors in the input circuit and the transistors in the nth output control circuit are n-type transistors, and the difference between the threshold voltage of the transistor in the nth output control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; or,

[0230] The transistors included in the input circuit and the transistors included in the nth output control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal.

[0231] When the driving circuit described in this embodiment is working, there will be leakage current from the nth output control node to the first node, which will cause an output abnormality at the nth drive output terminal. Based on this, in at least one embodiment of this disclosure, when both the transistors included in the input circuit and the transistors included in the nth output control circuit are n-type transistors, the difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is set to be greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; when both the transistors included in the input circuit and the transistors included in the nth output control circuit are p-type transistors, the difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is set to be less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; so that when the potential of the nth output control node is bootstrapping, the transistors included in the nth output control circuit can be turned off, to prevent leakage from the nth output control node to the first node from causing the potential of the nth output control node to not be properly pulled up, resulting in an output error.

[0232] In at least one embodiment of this disclosure, the effective voltage value of the control voltage can be equal to the effective voltage value of the input signal. In this case, when both the transistors included in the input circuit and the transistors included in the nth output control circuit are n-type transistors, the threshold voltage of the transistor included in the nth output control circuit is set to be greater than the difference between the threshold voltages of the transistors included in the input circuit and the threshold voltage of the transistors included in the input circuit. When both the transistors included in the input circuit and the transistors included in the nth output control circuit are p-type transistors, the threshold voltage of the transistor included in the nth output control circuit is set to be less than the threshold voltage of the transistors included in the input circuit.

[0233] In at least one embodiment of this disclosure, when both the transistors included in the input circuit and the transistors included in the nth output control circuit are n-type transistors,

[0234] The effective voltage value of the input signal is: the voltage value of the input signal when the input signal is a high voltage signal;

[0235] The effective voltage value of the control voltage is: the voltage value of the control voltage when the control voltage is high;

[0236] When both the transistors in the input circuit and the transistors in the nth output control circuit are p-type transistors,

[0237] The effective voltage value of the input signal is: the voltage value of the input signal when the input signal is a low voltage signal;

[0238] The effective voltage value of the control voltage is: the voltage value of the control voltage when the control voltage is low.

[0239] In at least one embodiment of this disclosure, when both the transistor included in the nth output control circuit and the transistor included in the input circuit are n-type transistors, the channel width-to-length ratio of the transistor included in the nth output control circuit is smaller than the channel width-to-length ratio of the transistor included in the input circuit.

[0240] In practical implementation, given that the channel widths of the transistors are the same, for n-type transistors, the transistors with larger channel lengths have larger threshold voltages. Therefore, the channel width-to-length ratio of the transistors included in the nth output control circuit can be set to be smaller than the channel width-to-length ratio of the transistors included in the input circuit.

[0241] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal.

[0242] The second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the first voltage terminal, respectively, and is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node.

[0243] The first node control circuit is electrically connected to the first second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

[0244] In a specific implementation, the control voltage terminal may include a first control voltage terminal, and the driving circuit may further include a second node control circuit and a first node control circuit; the second node control circuit controls the potential of the first second node according to the first control voltage, and controls the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node; the first node control circuit controls the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

[0245] Optionally, the first voltage terminal can be a first low voltage terminal.

[0246] In at least one embodiment of this disclosure, the driving circuit may further include N energy storage circuits;

[0247] The first terminal of the nth energy storage circuit is electrically connected to the nth output control node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive output terminal. The nth energy storage circuit is used to store electrical energy.

[0248] As shown in Figure 1A, the driving circuit described in at least one embodiment of this disclosure includes an input circuit 10, a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a second node control circuit 31, and a first node control circuit 32; the control voltage terminal includes a first control voltage terminal VDDA;

[0249] The input circuit 10 is electrically connected to the input terminal IS and the first node PU, and is used to control the potential of the first node PU according to the input signal provided by the input terminal IS.

[0250] The first output control circuit 11 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the first output control node PU1, respectively, and is used to control the connection or disconnection between the first node PU and the first output control node PU1 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0251] The second output control circuit 12 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the second output control node PU2, respectively, and is used to control the connection or disconnection between the first node PU and the second output control node PU2 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0252] The third output control circuit 13 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the third output control node PU3, respectively, and is used to control the connection or disconnection between the first node PU and the third output control node PU3 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0253] The fourth output control circuit 14 is electrically connected to the first control voltage terminal VDDA, the first node PU, and the fourth output control node PU4, respectively, and is used to control the connection or disconnection between the first node PU and the fourth output control node PU4 under the control of the first control voltage provided by the first control voltage terminal VDDA.

[0254] The first drive output circuit 21 is electrically connected to the first output control node PU1, the first drive output terminal GT1 and the first output clock signal terminal CK1 respectively, and is used to provide the first output clock signal provided by the first output clock signal terminal CK1 to the first drive output terminal GT1 under the control of the potential of the first output control node PU1.

[0255] The second drive output circuit 22 is electrically connected to the second output control node PU2, the second drive output terminal GT2, and the second output clock signal terminal CK2, respectively, and is used to provide the second output clock signal provided by the second output clock signal terminal CK2 to the second drive output terminal GT2 under the control of the potential of the second output control node PU2.

[0256] The third drive output circuit 23 is electrically connected to the third output control node PU3, the third drive output terminal GT3 and the third output clock signal terminal CK3 respectively, and is used to provide the third output clock signal provided by the third output clock signal terminal CK3 to the third drive output terminal GT3 under the control of the potential of the third output control node PU3.

[0257] The fourth drive output circuit 24 is electrically connected to the fourth output control node PU4, the fourth drive output terminal GT4 and the fourth output clock signal terminal CK4 respectively, and is used to provide the fourth output clock signal provided by the fourth output clock signal terminal CK4 to the fourth drive output terminal GT4 under the control of the potential of the fourth output control node PU4.

[0258] The first terminal of the first energy storage circuit SC1 is electrically connected to the first output control node PU1, and the second terminal of the first energy storage circuit SC1 is electrically connected to the first drive output terminal GT1.

[0259] The first terminal of the second energy storage circuit SC2 is electrically connected to the second output control node PU2, and the second terminal of the second energy storage circuit SC2 is electrically connected to the second drive output terminal GT2.

[0260] The first terminal of the third energy storage circuit SC3 is electrically connected to the third output control node PU3, and the second terminal of the third energy storage circuit SC3 is electrically connected to the third drive output terminal GT3.

[0261] The first terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth output control node PU4, and the second terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth drive output terminal GT4.

[0262] The second node control circuit 31 is electrically connected to the first control voltage terminal VDDA, the first node PU, the first second node PDA and the first voltage terminal V1 respectively. It is used to control the potential of the first second node PDA according to the first control voltage provided by the first control voltage terminal VDDA, and control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the potential of the first node PU.

[0263] The first node control circuit 32 is electrically connected to the first second node PDA, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0264] Figure 1B is a structural diagram of the first part B1 in Figure 1A, and Figure 1C is a structural diagram of the second part B2 in Figure 1A.

[0265] As shown in Figure 1B, the first part B1 includes an input circuit 10, a first node control circuit 32, and a second node control circuit 31.

[0266] As shown in Figure 1C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0267] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal and a second control voltage terminal.

[0268] The second node control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the first node, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. It is also used to control the potential of the second second node according to the second control voltage terminal, and to control the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node.

[0269] The first node control circuit is electrically connected to the first second node, the second second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

[0270] In a specific implementation, the control voltage terminal may include a first control voltage terminal and a second control voltage terminal, and the driving circuit may further include a two-node control circuit and a first-node control circuit; the second-node control circuit controls the potential of the first second node according to the first control voltage, and controls the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node, and controls the potential of the second second node according to the second control voltage, and controls the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node; the first-node control circuit controls the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and controls the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

[0271] As shown in Figure 2A, the driving circuit described in at least one embodiment of this disclosure includes an input circuit 10, a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a second node control circuit 31, and a first node control circuit 32; the control voltage terminals include a first control voltage terminal VDDA and a second control voltage terminal VDDB;

[0272] The input circuit 10 is electrically connected to the input terminal IS and the first node PU, and is used to control the potential of the first node PU according to the input signal provided by the input terminal IS.

[0273] The first output control circuit 11 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the first output control node PU1, respectively. It is used to control the connection or disconnection between the first node PU and the first output control node PU1 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the first output control node PU1 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0274] The second output control circuit 12 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the second output control node PU2, respectively. It is used to control the connection or disconnection between the first node PU and the second output control node PU2 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the second output control node PU2 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0275] The third output control circuit 13 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the third output control node PU3, respectively. It is used to control the connection or disconnection between the first node PU and the third output control node PU3 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the third output control node PU3 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0276] The fourth output control circuit 14 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, and the fourth output control node PU4, respectively. It is used to control the connection or disconnection between the first node PU and the fourth output control node PU4 under the control of the first control voltage provided by the first control voltage terminal VDDA, and to control the connection or disconnection between the first node PU and the fourth output control node PU4 under the control of the second control voltage provided by the second control voltage terminal VDDB.

[0277] The first drive output circuit 21 is electrically connected to the first output control node PU1, the first drive output terminal GT1 and the first output clock signal terminal CK1 respectively, and is used to provide the first output clock signal provided by the first output clock signal terminal CK1 to the first drive output terminal GT1 under the control of the potential of the first output control node PU1.

[0278] The second drive output circuit 22 is electrically connected to the second output control node PU2, the second drive output terminal GT2, and the second output clock signal terminal CK2, respectively, and is used to provide the second output clock signal provided by the second output clock signal terminal CK2 to the second drive output terminal GT2 under the control of the potential of the second output control node PU2.

[0279] The third drive output circuit 23 is electrically connected to the third output control node PU3, the third drive output terminal GT3 and the third output clock signal terminal CK3 respectively, and is used to provide the third output clock signal provided by the third output clock signal terminal CK3 to the third drive output terminal GT3 under the control of the potential of the third output control node PU3.

[0280] The fourth drive output circuit 24 is electrically connected to the fourth output control node PU4, the fourth drive output terminal GT4 and the fourth output clock signal terminal CK4 respectively, and is used to provide the fourth output clock signal provided by the fourth output clock signal terminal CK4 to the fourth drive output terminal GT4 under the control of the potential of the fourth output control node PU4.

[0281] The first terminal of the first energy storage circuit SC1 is electrically connected to the first output control node PU1, and the second terminal of the first energy storage circuit SC1 is electrically connected to the first drive output terminal GT1.

[0282] The first terminal of the second energy storage circuit SC2 is electrically connected to the second output control node PU2, and the second terminal of the second energy storage circuit SC2 is electrically connected to the second drive output terminal GT2.

[0283] The first terminal of the third energy storage circuit SC3 is electrically connected to the third output control node PU3, and the second terminal of the third energy storage circuit SC3 is electrically connected to the third drive output terminal GT3.

[0284] The first terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth output control node PU4, and the second terminal of the fourth energy storage circuit SC4 is electrically connected to the fourth drive output terminal GT4.

[0285] The second node control circuit 31 is electrically connected to the first control voltage terminal VDDA, the second control voltage terminal VDDB, the first node PU, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the potential of the first second node PDA according to the first control voltage provided by the first control voltage terminal VDDA, and control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the potential of the first node PU. It is also used to control the potential of the second second node PDB according to the second control voltage provided by the second control voltage terminal VDDB, and control the connection or disconnection between the second second node PDB and the first voltage terminal V1 under the control of the potential of the first node PU.

[0286] The first node control circuit 32 is electrically connected to the first second node PDA, the second second node PDB, the first node PU, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PDB.

[0287] Figure 2B is a structural diagram of the first part B1 in Figure 2A, and Figure 2C is a circuit diagram of the second part B2 in Figure 2A.

[0288] As shown in Figure 2B, the first part B1 includes an input circuit 10, a first node control circuit 32, and a second node control circuit 31.

[0289] As shown in Figure 2C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0290] In at least one embodiment of this disclosure, the driving circuit further includes a control circuit; the input circuit includes a first input circuit and a second input circuit; the control circuit is electrically connected to the first node, the power supply voltage terminal, and the control node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node; the first input circuit is electrically connected to the input terminal and the control node respectively, and is used to control the potential of the control node according to the input signal; the second input circuit is electrically connected to the input terminal, the control node, and the first node respectively, and is used to control the connection or disconnection between the control node and the first node under the control of the input signal; or,

[0291] The driving circuit further includes a control circuit. The input circuit includes a first input circuit and a second input circuit. The control circuit includes a first control circuit and a second control circuit. The first control circuit is electrically connected to a first node, a power supply voltage terminal, and a control node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node. The second control circuit is electrically connected to the first node, the power supply voltage terminal, and an intermediate node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the intermediate node under the control of the potential of the first node. The first input circuit is electrically connected to the input terminal and the intermediate node, respectively, and is used to control the potential of the intermediate node according to the input signal. The second input circuit is electrically connected to the input terminal, the intermediate node, and the first node, respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the input signal.

[0292] As shown in FIG3A, based on at least one embodiment of the driving circuit shown in FIG1A, the driving circuit further includes a control circuit 30; the input circuit includes a first input circuit 101 and a second input circuit 102.

[0293] The control circuit 30 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0294] The first input circuit 101 is electrically connected to the input terminal IS and the control node P1 respectively, and is used to control the potential of the control node P1 according to the input signal;

[0295] The second input circuit 102 is electrically connected to the input terminal IS, the control node P1, and the first node PU, respectively, and is used to control the connection or disconnection between the control node P1 and the first node PU under the control of the input signal. In at least one embodiment of the driving circuit shown in FIG3A, during operation, the control circuit 30 controls the potential of the control node P1 under the control of the potential of the first node PU; and the input circuit is configured to include a first input circuit 101 and a second input circuit 102, which are electrically connected to each other through the control node P1. By controlling the potential of the control node P1, during the drive output stage, the leakage current of the transistors included in the input circuit is reduced, which helps to maintain the potential of the first node PU.

[0296] Figure 3B is a structural diagram of the first part B1 in Figure 3A, and Figure 3C is a structural diagram of the second part B2 in Figure 3A.

[0297] As shown in Figure 3B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first node control circuit 32, and a second node control circuit 31.

[0298] As shown in Figure 3C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0299] As shown in Figure 4A, based on at least one embodiment of the driving circuit shown in Figure 2A, the driving circuit further includes a control circuit 30; the input circuit includes a first input circuit 101 and a second input circuit 102.

[0300] The control circuit 30 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0301] The first input circuit 101 is electrically connected to the input terminal IS and the control node P1 respectively, and is used to control the potential of the control node P1 according to the input signal;

[0302] The second input circuit 102 is electrically connected to the input terminal IS, the control node P1 and the first node PU respectively, and is used to control the connection or disconnection between the control node P1 and the first node PU under the control of the input signal.

[0303] In at least one embodiment of the driving circuit shown in Figure 4A, during operation, the control circuit 30 controls the potential of the control node P1 under the control of the potential of the first node PU; and the input circuit is configured to include a first input circuit 101 and a second input circuit 102, which are electrically connected to each other through the control node P1. By controlling the potential of the control node P1, the leakage current of the transistors included in the input circuit is reduced during the drive output stage, which helps to maintain the potential of the first node PU.

[0304] Figure 4B is a structural diagram of the first part B1 in Figure 4A, and Figure 4C is a structural diagram of the second part B2 in Figure 4A.

[0305] As shown in Figure 4B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first node control circuit 32, and a second node control circuit 31.

[0306] As shown in Figure 4C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0307] As shown in Figure 5A, based on at least one embodiment of the driving circuit shown in Figure 1A, the driving circuit further includes a control circuit.

[0308] The input circuit includes a first input circuit 101 and a second input circuit 102;

[0309] The control circuit includes a first control circuit 301 and a second control circuit 302;

[0310] The first control circuit 301 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0311] The second control circuit 302 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the intermediate node Z1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1 under the control of the potential of the first node PU.

[0312] The first input circuit 101 is electrically connected to the input terminal IS and the intermediate node Z1 respectively, and is used to control the potential of the intermediate node Z1 according to the input signal;

[0313] The second input circuit 102 is electrically connected to the input terminal IS, the intermediate node Z1 and the first node PU respectively, and is used to control the connection or disconnection between the intermediate node Z1 and the first node PU under the control of the input signal.

[0314] In at least one embodiment of the driving circuit shown in Figure 5A, the control circuit includes a first control circuit 301 and a second control circuit 302. The first control circuit 301 controls the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU. The second control circuit 302 controls the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1 under the control of the potential of the first node PU. By controlling the potential of the intermediate node Z1, the leakage current of the transistors included in the input circuit can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0315] Figure 5B is a structural diagram of the first part B1 in Figure 5A, and Figure 5C is a structural diagram of the second part B2 in Figure 5A.

[0316] As shown in Figure 5B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first node control circuit 32, and a second node control circuit 31.

[0317] As shown in Figure 5C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0318] As shown in Figure 6A, based on at least one embodiment of the driving circuit shown in Figure 2A, the driving circuit further includes a control circuit;

[0319] The input circuit includes a first input circuit 101 and a second input circuit 102;

[0320] The control circuit includes a first control circuit 301 and a second control circuit 302;

[0321] The first control circuit 301 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the control node P1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU.

[0322] The second control circuit 302 is electrically connected to the first node PU, the power supply voltage terminal VDD, and the intermediate node Z1, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1 under the control of the potential of the first node PU.

[0323] The first input circuit 101 is electrically connected to the input terminal IS and the intermediate node Z1 respectively, and is used to control the potential of the intermediate node Z1 according to the input signal;

[0324] The second input circuit 102 is electrically connected to the input terminal IS, the intermediate node Z1 and the first node PU respectively, and is used to control the connection or disconnection between the intermediate node Z1 and the first node PU under the control of the input signal.

[0325] In at least one embodiment of the driving circuit shown in Figure 6A, the control circuit includes a first control circuit 301 and a second control circuit 302. The first control circuit 301 controls the connection or disconnection between the power supply voltage terminal VDD and the control node P1 under the control of the potential of the first node PU. The second control circuit 302 controls the connection or disconnection between the power supply voltage terminal VDD and the intermediate node Z1 under the control of the potential of the first node PU. By controlling the potential of the intermediate node Z1, the leakage current of the transistors included in the input circuit can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0326] Figure 6B is a structural diagram of the first part B1 in Figure 6A, and Figure 6C is a structural diagram of the second part B2 in Figure 6A.

[0327] As shown in Figure 6B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first node control circuit 32, and a second node control circuit 31.

[0328] As shown in Figure 6C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0329] In at least one embodiment of this disclosure, the control voltage terminal includes a first control voltage terminal; the first node control circuit includes a first first node control circuit and a second first node control circuit;

[0330] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0331] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node.

[0332] As shown in Figure 7A, based on at least one embodiment of the driving circuit shown in Figure 3A, the first node control circuit includes a first first node control circuit 321 and a second first node control circuit 322.

[0333] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0334] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0335] In at least one embodiment of the driving circuit shown in Figure 7A, when in operation, the first first node control circuit 321 controls the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA; by controlling the potential of the control node P1, the leakage current of the transistor included in the first first node control circuit 321 can be reduced during the driving output stage, which is beneficial to maintaining the potential of the first node PU.

[0336] Figure 7B is a structural diagram of the first part B1 in Figure 7A, and Figure 7C is a structural diagram of the second part B2 in Figure 7A.

[0337] As shown in Figure 7B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, and a second node control circuit 31.

[0338] As shown in Figure 7C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0339] As shown in Figure 8A, based on at least one embodiment of the driving circuit shown in Figure 5A, the first node control circuit includes a first first node control circuit 321 and a second first node control circuit 322.

[0340] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0341] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0342] In at least one embodiment of the driving circuit shown in Figure 8A, when in operation, the first first node control circuit 321 controls the connection or disconnection between the first node PU and the control node P1 under the control of the potential of the first second node PDA; by controlling the potential of the control node P1, the leakage current of the transistor included in the first first node control circuit 321 can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0343] Figure 8B is a structural diagram of the first part B1 in Figure 8A, and Figure 8C is a structural diagram of the second part B2 in Figure 8A.

[0344] As shown in Figure 8B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first node control circuit 321, a second node control circuit 322, and a second node control circuit 31.

[0345] As shown in Figure 8C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0346] In at least one embodiment of this disclosure, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the first node control circuit includes a first first node control circuit, a second first node control circuit, a third first node control circuit and a fourth first node control circuit;

[0347] The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node.

[0348] The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node;

[0349] The third first node control circuit is electrically connected to the second second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the second second node.

[0350] The fourth first node control circuit is electrically connected to the second second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the second second node.

[0351] In specific implementation, the control voltage terminal may include a first control voltage terminal and a second control voltage terminal; the first node control circuit may include a first first node control circuit, a second first node control circuit, a third first node control circuit, and a fourth first node control circuit; the first first node control circuit, under the potential control of the first second node, controls the connection or disconnection between the first node and the control node; the second first node control circuit, under the potential control of the first second node, controls the connection or disconnection between the control node and the first voltage terminal; the third first node control circuit, under the potential control of the second second node, controls the connection or disconnection between the first node and the control node; the fourth first node control circuit, under the potential control of the second second node, controls the connection or disconnection between the control node and the first voltage terminal. The driving circuit described in at least one embodiment of this disclosure reduces the leakage current of the transistors included in the first first node control circuit and the third first node control circuit by setting the potential of the control node P1, thereby facilitating the maintenance of the first node's potential.

[0352] As shown in Figure 9A, based on at least one embodiment of the driving circuit shown in Figure 4A, the first node control circuit includes a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, and a fourth first node control circuit 324.

[0353] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0354] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0355] The third first node control circuit 323 is electrically connected to the second second node PDB, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the second second node PDB.

[0356] The fourth first node control circuit 324 is electrically connected to the second second node PDB, the control node P1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the second second node PDB.

[0357] In at least one embodiment of the driving circuit shown in Figure 9A, during operation, the first first node control circuit 321, under the potential control of the first second node PDA, controls the connection or disconnection between the first node PU and the control node P1; the third first node control circuit 323, under the potential control of the second second node PDB, controls the connection or disconnection between the first node PU and the control node P1; by controlling the potential of the control node P1, the leakage current of the transistors included in the first first node control circuit 321 and the third first node control circuit 323 can be reduced, which is beneficial to maintaining the potential of the first node PU.

[0358] Figure 9B is a structural diagram of the first part B1 in Figure 9A, and Figure 9C is a structural diagram of the second part B2 in Figure 9A.

[0359] As shown in Figure 9B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, and a second node control circuit 31.

[0360] As shown in Figure 9C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0361] As shown in Figure 10A, based on at least one embodiment of the driving circuit shown in Figure 6A, the first node control circuit includes a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, and a fourth first node control circuit 324.

[0362] The first node control circuit 321 is electrically connected to the first second node PDA, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the first second node PDA.

[0363] The second first node control circuit 322 is electrically connected to the first second node PDA, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the first second node PDA.

[0364] The third first node control circuit 323 is electrically connected to the second second node PDB, the first node PU, and the control node P1, respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the potential control of the second second node PDB.

[0365] The fourth first node control circuit 324 is electrically connected to the second second node PDB, the control node P1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the potential of the second second node PDB.

[0366] In at least one embodiment of the driving circuit shown in Figure 10A, during operation, the first first node control circuit 321, under the potential control of the first second node PDA, controls the connection or disconnection between the first node PU and the control node P1; the third first node control circuit 323, under the potential control of the second second node PDB, controls the connection or disconnection between the first node PU and the control node P1; by controlling the potential of the control node P1, the leakage current of the transistors included in the first first node control circuit 321 and the third first node control circuit 323 can be reduced, which is beneficial to maintaining the potential of the first node PU.

[0367] Figure 10B is a structural diagram of the first part B1 in Figure 10A, and Figure 10C is a structural diagram of the second part B2 in Figure 10A.

[0368] As shown in Figure 10B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, and a second node control circuit 31.

[0369] As shown in Figure 10C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0370] The driving circuit described in at least one embodiment of this disclosure further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit and a second first node reset circuit.

[0371] The first node reset circuit is electrically connected to the reset control terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the reset control signal provided by the reset control terminal.

[0372] The second first node reset circuit is electrically connected to the reset control terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the reset control signal.

[0373] In a specific implementation, the driving circuit may further include a first node reset circuit; the first node reset circuit may include a first first node reset circuit and a second first node reset circuit; the first first node reset circuit, under the control of the reset control signal, controls the connection or disconnection between the first node and the control node; the second first node reset circuit, under the control of the reset control signal, controls the connection or disconnection between the control node and the first voltage terminal. By setting the potential of the control node, the leakage current of the transistor included in the first first node reset circuit can be reduced during the drive output stage, which is beneficial to maintaining the potential of the first node PU.

[0374] The driving circuit described in at least one embodiment of this disclosure further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit and a second frame reset circuit.

[0375] The first frame reset circuit is electrically connected to the frame reset terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the frame reset signal provided by the frame reset terminal.

[0376] The second frame reset circuit is electrically connected to the frame reset terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the frame reset signal.

[0377] In specific implementations, the driving circuit described in at least one embodiment of this disclosure may further include a frame reset circuit; the frame reset circuit may include a first frame reset circuit and a second frame reset circuit; the first frame reset circuit, under the control of the frame reset signal, controls the connection or disconnection between the first node and the control node; the second frame reset circuit, under the control of the frame reset signal, controls the connection or disconnection between the control node and the first voltage terminal. By setting the potential of the control node, the leakage current of the transistor included in the first frame reset circuit can be reduced during the driving output stage, which is beneficial to maintaining the potential of the first node PU.

[0378] As shown in FIG11A, based on at least one embodiment of the driving circuit described in FIG7A, the driving circuit described in at least one embodiment of this disclosure further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0379] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0380] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0381] The driving circuit described in at least one embodiment of this disclosure further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0382] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0383] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0384] Figure 11B is a structural diagram of the first part B1 in Figure 11A, and Figure 11C is a structural diagram of the second part B2 in Figure 11A.

[0385] As shown in Figure 11B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0386] As shown in Figure 11C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0387] As shown in Figure 12A, based on at least one embodiment of the driving circuit described in Figure 8A, the driving circuit of at least one embodiment of this disclosure further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0388] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0389] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0390] The driving circuit described in at least one embodiment of this disclosure further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0391] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0392] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0393] Figure 12B is a structural diagram of the first part B1 in Figure 12A, and Figure 12C is a structural diagram of the second part B2 in Figure 12A.

[0394] As shown in Figure 12B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0395] As shown in Figure 12C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0396] As shown in Figure 13A, based on at least one embodiment of the driving circuit described in Figure 9A, the driving circuit of at least one embodiment of this disclosure further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0397] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0398] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0399] The driving circuit described in at least one embodiment of this disclosure further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0400] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0401] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0402] Figure 13B is a structural diagram of the first part B1 in Figure 13A, and Figure 13C is a structural diagram of the second part B2 in Figure 13A.

[0403] As shown in Figure 13B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0404] As shown in Figure 13C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0405] As shown in FIG14A, based on at least one embodiment of the driving circuit described in FIG10A, the driving circuit described in at least one embodiment of this disclosure further includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit 411 and a second first node reset circuit 412;

[0406] The first node reset circuit 411 is electrically connected to the reset control terminal RST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the reset control signal provided by the reset control terminal RST.

[0407] The second first node reset circuit 412 is electrically connected to the reset control terminal RST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the reset control signal.

[0408] The driving circuit described in at least one embodiment of this disclosure further includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit 511 and a second frame reset circuit 512.

[0409] The first frame reset circuit 511 is electrically connected to the frame reset terminal TRST, the first node PU and the control node P1 respectively, and is used to control the connection or disconnection between the first node PU and the control node P1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0410] The second frame reset circuit 512 is electrically connected to the frame reset terminal TRST, the control node P1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the control node P1 and the first voltage terminal V1 under the control of the frame reset signal.

[0411] Figure 14B is a structural diagram of the first part B1 in Figure 14A, and Figure 14C is a structural diagram of the second part B2 in Figure 14A.

[0412] As shown in Figure 14B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, and a second node control circuit 31.

[0413] As shown in Figure 14C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, and a fourth energy storage circuit SC4.

[0414] The driving circuit described in at least one embodiment of this disclosure further includes N output reset circuits;

[0415] The nth output reset circuit is electrically connected to the first second node, the nth drive output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node.

[0416] In a specific implementation, the driving circuit may further include N output reset circuits. The nth output reset circuit controls the connection or disconnection between the nth driving output terminal and the second voltage terminal under the control of the potential of the first second node.

[0417] The driving circuit described in at least one embodiment of this disclosure further includes N output reset circuits;

[0418] The nth output reset circuit is electrically connected to the first second node, the second second node, the nth drive output terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the second second node.

[0419] In a specific implementation, the driving circuit may further include N output reset circuits; the nth output reset circuit controls the connection or disconnection between the nth driving output terminal and the second voltage terminal under the control of the potential of the first second node, and controls the connection or disconnection between the nth driving output terminal and the second voltage terminal under the control of the potential of the second second node.

[0420] Optionally, the second voltage terminal can be a second low voltage terminal.

[0421] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit and a carry energy storage circuit;

[0422] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0423] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0424] In a specific implementation, the driving circuit may further include a carry output circuit; under the control of the potential of the first node, the carry output circuit provides a carry clock signal to the carry output terminal, and under the control of the potential of the first and second nodes, provides a first voltage signal to the carry output terminal.

[0425] In at least one embodiment of this disclosure, the carry signal provided by the carry output terminal can be used for cascading.

[0426] The driving circuit described in at least one embodiment of this disclosure may further include a carry output circuit, a carry output control circuit, and a carry energy storage circuit.

[0427] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node.

[0428] The carry-out control circuit is electrically connected to the first control voltage terminal, the carry-out node, and the first node, respectively, and is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal.

[0429] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0430] In at least one embodiment of this disclosure, a carry output control circuit may be added, wherein the carry output circuit provides a carry clock signal to the carry output terminal under the potential control of the carry output node;

[0431] When both the transistors in the carry-out control circuit and the transistors in the input circuit are n-type transistors, the difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is set to be greater than the difference between the effective voltage of the first control voltage and the effective voltage of the input signal. When both the transistors in the carry-out control circuit and the transistors in the input circuit are p-type transistors, the difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is set to be less than the difference between the effective voltage of the first control voltage and the effective voltage of the input signal. This ensures that when the potential of the carry-out node is bootstrapping, the transistors in the carry-out control circuit can be turned off to prevent leakage from the carry-out node to the first node from causing the potential of the carry-out node to not be properly pulled up, resulting in an incorrect carry signal output.

[0432] Optionally, the driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit;

[0433] The second node setting circuit is electrically connected to the input terminal, the first second node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first second node and the first voltage terminal under the control of the input signal provided by the input terminal.

[0434] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit and a carry energy storage circuit;

[0435] The carry output circuit is electrically connected to the first node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the first node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the second second node.

[0436] The first end of the carry energy storage circuit is electrically connected to the first node, and the second end of the carry energy storage circuit is electrically connected to the carry output end.

[0437] In a specific implementation, the driving circuit may further include a carry output circuit; the carry output circuit provides a carry clock signal to the carry output terminal under the control of the potential of the first node, provides a first voltage signal to the carry output terminal under the control of the potential of the first second node, and provides a first voltage signal to the carry output terminal under the control of the potential of the second second node.

[0438] The driving circuit described in at least one embodiment of this disclosure may further include a carry output circuit, a carry output control circuit, and a carry energy storage circuit.

[0439] The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal to the carry output terminal under the control of the potential of the second second node.

[0440] The carry-out control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the carry-out node, and the first node, respectively. It is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the carry-out node and the first node under the control of the second control voltage provided by the second control voltage terminal.

[0441] The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

[0442] In at least one embodiment of this disclosure, a carry output control circuit may be added, wherein the carry output circuit provides a carry clock signal to the carry output terminal under the potential control of the carry output node;

[0443] When both the transistors included in the carry-out control circuit and the transistors included in the input circuit are n-type transistors, the difference between the threshold voltage of the first carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the second carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be greater than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

[0444] When both the transistors included in the carry-out control circuit and the transistors included in the input circuit are p-type transistors, the difference between the threshold voltage of the first carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the second carry-out control transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is set to be less than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

[0445] This ensures that when the potential of the carry output node is bootstrapping, the transistors included in the carry output control circuit can be turned off to prevent leakage current from the carry output node to the first node from causing the potential of the carry output node to not be properly pulled up, resulting in an incorrect carry signal output.

[0446] Optionally, the driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit;

[0447] The second node setting circuit is electrically connected to the input terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the connection or disconnection between the first second node and the first voltage terminal under the control of the input signal provided by the input terminal, and to control the connection or disconnection between the second second node and the first voltage terminal.

[0448] As shown in FIG15A, based on at least one embodiment of the driving circuit shown in FIG11A, the driving circuit described in at least one embodiment of the present disclosure further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0449] The first output reset circuit 61 is electrically connected to the first second node PDA, the first drive output terminal GT1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0450] The second output reset circuit 62 is electrically connected to the first second node PDA, the second drive output terminal GT2, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0451] The third output reset circuit 63 is electrically connected to the first second node PDA, the third drive output terminal GT3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0452] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0453] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0454] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT, and under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0455] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0456] The driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit 71;

[0457] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the input signal provided by the input terminal IS.

[0458] Figure 15B is a structural diagram of the first part B1 in Figure 15A, and Figure 15C is a structural diagram of the second part B2 in Figure 15A.

[0459] As shown in Figure 15B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0460] As shown in Figure 15C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0461] The differences between at least one embodiment of the driving circuit shown in Figure 15D and at least one embodiment of the driving circuit shown in Figure 15A are as follows:

[0462] The driving circuit described in at least one embodiment of this disclosure further includes a carry output control circuit 150;

[0463] The carry output circuit 70 is not electrically connected to the first node PU, but is electrically connected to the carry output node PU0. It is used to provide the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT under the control of the potential of the carry output node PU0.

[0464] The first terminal of the carry energy storage circuit 80 is electrically connected to the carry output node PU0.

[0465] The carry-out control circuit 150 is electrically connected to the first control voltage terminal VDDA, the carry-out node PU0, and the first node PU, respectively. It is used to control the connection or disconnection between the carry-out node PU0 and the first node PU under the control of the first control voltage provided by the first control voltage terminal VDDA. The structural diagram of the first part B1 in Figure 15D is shown in Figure 15B, and the structural diagram of the second part B2 in Figure 15D is shown in Figure 15E.

[0466] As shown in FIG16A, based on at least one embodiment of the driving circuit shown in FIG12A, the driving circuit described in at least one embodiment of the present disclosure further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0467] The first output reset circuit 61 is electrically connected to the first second node PDA, the first drive output terminal GT1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0468] The second output reset circuit 62 is electrically connected to the first second node PDA, the second drive output terminal GT2, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0469] The third output reset circuit 63 is electrically connected to the first second node PDA, the third drive output terminal GT3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0470] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0471] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0472] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT, and under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0473] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0474] The driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit 71;

[0475] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the input signal provided by the input terminal IS.

[0476] Figure 16B is a structural diagram of the first part B1 in Figure 16A, and Figure 16C is a structural diagram of the second part B2 in Figure 16A.

[0477] As shown in Figure 16B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0478] As shown in Figure 16C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0479] As shown in FIG17A, based on at least one embodiment of the driving circuit shown in FIG13A, the driving circuit described in at least one embodiment of the present disclosure further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, and a fourth output reset circuit 64.

[0480] The first output reset circuit 61 is electrically connected to the first second node PDA, the second second node PDB, the second second node PDB, the first drive output terminal GT1, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0481] The second output reset circuit 62 is electrically connected to the first second node PDA, the second second node PDB, the second drive output terminal GT2, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0482] The third output reset circuit 63 is electrically connected to the first second node PDA, the second second node PDB, the third drive output terminal GT3, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0483] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the second second node PDB, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0484] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0485] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT; under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT; and under the control of the potential of the second second node PDB, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0486] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0487] The driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit 71;

[0488] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1, and to control the connection or disconnection between the second second node PDB and the first voltage terminal V1, under the control of the input signal provided by the input terminal IS.

[0489] Figure 17B is a structural diagram of the first part B1 in Figure 17A, and Figure 17C is a structural diagram of the second part B2 in Figure 17A.

[0490] As shown in Figure 17B, the first part B1 includes a first input circuit 101, a second input circuit 102, a control circuit 30, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0491] As shown in Figure 17C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0492] As shown in FIG18A, based on at least one embodiment of the driving circuit shown in FIG14A, the driving circuit described in at least one embodiment of the present disclosure further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63 and a fourth output reset circuit 64.

[0493] The first output reset circuit 61 is electrically connected to the first second node PDA, the second second node PDB, the first drive output terminal GT1, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0494] The second output reset circuit 62 is electrically connected to the first second node PDA, the second second node PDB, the second drive output terminal GT2, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0495] The third output reset circuit 63 is electrically connected to the first second node PDA, the second second node PDB, the third drive output terminal GT3, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0496] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the second second node PDB, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0497] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0498] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT; under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT; and under the control of the potential of the second second node PDB, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0499] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0500] The driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit 71;

[0501] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1, and to control the connection or disconnection between the second second node PDB and the first voltage terminal V1, under the control of the input signal provided by the input terminal IS.

[0502] Figure 18B is a structural diagram of the first part B1 in Figure 18A, and Figure 18C is a structural diagram of the second part B2 in Figure 18A.

[0503] As shown in Figure 18B, the first part B1 includes a first input circuit 101, a second input circuit 102, a first control circuit 301, a second control circuit 302, a first first node control circuit 321, a second first node control circuit 322, a third first node control circuit 323, a fourth first node control circuit 324, a first first node reset circuit 411, a second first node reset circuit 412, a first frame reset circuit 511, a second frame reset circuit 512, a second node control circuit 31, and a second node setting circuit 71.

[0504] As shown in Figure 18C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0505] As shown in FIG19A, based on at least one embodiment of the driving circuit shown in FIG1, the driving circuit described in at least one embodiment of this disclosure may further include a first node reset circuit 41 and a frame reset circuit 51.

[0506] The first node reset circuit 41 is electrically connected to the reset control terminal RST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the reset control signal provided by the reset control terminal RST.

[0507] The frame reset circuit 51 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0508] The driving circuit described in at least one embodiment of this disclosure further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, and a fourth output reset circuit 64;

[0509] The first output reset circuit 61 is electrically connected to the first second node PDA, the first drive output terminal GT1, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0510] The second output reset circuit 62 is electrically connected to the first second node PDA, the second drive output terminal GT2, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0511] The third output reset circuit 63 is electrically connected to the first second node PDA, the third drive output terminal GT3, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0512] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA.

[0513] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0514] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT, and under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0515] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0516] The driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit 71;

[0517] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1 under the control of the input signal provided by the input terminal IS.

[0518] Figure 19B is a structural diagram of the first part B1 in Figure 19A, and Figure 19C is a structural diagram of the second part B2 in Figure 19A.

[0519] As shown in Figure 19B, the first part B1 includes an input circuit 10, a first node control circuit 32, a first node reset circuit 41, a frame reset circuit 51, a second node control circuit 31, and a second node set circuit 71.

[0520] As shown in Figure 19C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0521] As shown in FIG20A, based on at least one embodiment of the driving circuit shown in FIG2A, the driving circuit described in at least one embodiment of this disclosure may further include a first node reset circuit 41 and a frame reset circuit 51.

[0522] The first node reset circuit 41 is electrically connected to the reset control terminal RST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the reset control signal provided by the reset control terminal RST.

[0523] The frame reset circuit 51 is electrically connected to the frame reset terminal TRST, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0524] The driving circuit described in at least one embodiment of this disclosure further includes a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, and a fourth output reset circuit 64;

[0525] The first output reset circuit 61 is electrically connected to the first second node PDA, the second second node PDB, the first drive output terminal GT1, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the first drive output terminal GT1 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0526] The second output reset circuit 62 is electrically connected to the first second node PDA, the second second node PDB, the second drive output terminal GT2, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the second drive output terminal GT2 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0527] The third output reset circuit 63 is electrically connected to the first second node PDA, the second second node PDB, the third drive output terminal GT3, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the third drive output terminal GT3 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0528] The fourth output reset circuit 64 is electrically connected to the first second node PDA, the second second node PDB, the fourth drive output terminal GT4, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the first second node PDA, and to control the connection or disconnection between the fourth drive output terminal GT4 and the second voltage terminal V2 under the control of the potential of the second second node PDB.

[0529] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 70 and a carry energy storage circuit 80;

[0530] The carry output circuit 70 is electrically connected to the first node PU, the carry clock signal terminal CK_C, the carry output terminal CT, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. Under the control of the potential of the first node PU, it provides the carry clock signal provided by the carry clock signal terminal CK_C to the carry output terminal CT; under the control of the potential of the first second node PDA, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT; and under the control of the potential of the second second node PDB, it provides the first voltage signal provided by the first voltage terminal V1 to the carry output terminal CT.

[0531] The first end of the carry energy storage circuit 80 is electrically connected to the first node PU, and the second end of the carry energy storage circuit 80 is electrically connected to the carry output terminal CT.

[0532] The driving circuit described in at least one embodiment of this disclosure may further include a second node setting circuit 71;

[0533] The second node setting circuit 71 is electrically connected to the input terminal IS, the first second node PDA, the second second node PDB, and the first voltage terminal V1, respectively. It is used to control the connection or disconnection between the first second node PDA and the first voltage terminal V1, and to control the connection or disconnection between the second second node PDB and the first voltage terminal V1, under the control of the input signal provided by the input terminal IS.

[0534] Figure 20B is a structural diagram of the first part B1 in Figure 20A, and Figure 20C is a structural diagram of the second part B2 in Figure 20A.

[0535] As shown in Figure 20B, the first part B1 includes an input circuit 10, a first node control circuit 32, a first node reset circuit 41, a frame reset circuit 51, a second node control circuit 31, and a second node set circuit 71.

[0536] As shown in Figure 20C, the second part B2 includes a first output control circuit 11, a second output control circuit 12, a third output control circuit 13, a fourth output control circuit 14, a first drive output circuit 21, a second drive output circuit 22, a third drive output circuit 23, a fourth drive output circuit 24, a first energy storage circuit SC1, a second energy storage circuit SC2, a third energy storage circuit SC3, a fourth energy storage circuit SC4, a first output reset circuit 61, a second output reset circuit 62, a third output reset circuit 63, a fourth output reset circuit 64, a carry output circuit 70, and a carry energy storage circuit 80.

[0537] Optionally, the input circuit includes an input transistor; the gate and the first terminal of the input transistor are electrically connected to the input terminal, and the second terminal of the input transistor is electrically connected to the first node;

[0538] The control voltage terminal includes a first control voltage terminal; the nth output control circuit includes an nth first transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; or, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the nth output control circuit includes an nth first transistor and an nth second transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; the gate of the nth second transistor is electrically connected to the second control voltage terminal, the first electrode of the nth second transistor is electrically connected to the nth output control node, and the second electrode of the nth second transistor is electrically connected to the first node.

[0539] Optionally, the control circuit includes a control transistor; the first input circuit includes a first input transistor; the second input circuit includes a second input transistor; the gate of the control transistor is electrically connected to the first node; the first terminal of the control transistor is electrically connected to the power supply voltage terminal; and the second terminal of the control transistor is electrically connected to the control node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal; the second terminal of the first input transistor is electrically connected to the control node; the gate of the second input transistor is electrically connected to the input terminal; the first terminal of the second input transistor is electrically connected to the control node; and the second terminal of the second input transistor is electrically connected to the first node; or...

[0540] The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; the first input circuit includes a first input transistor, and the second input circuit includes a second input transistor; the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first control transistor is electrically connected to the control node; the gate of the second control transistor is electrically connected to the first node, the first terminal of the second control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the second control transistor is electrically connected to the intermediate node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal, and the second terminal of the first input transistor is electrically connected to the intermediate node; the gate of the second input transistor is electrically connected to the input terminal, the first terminal of the second input transistor is electrically connected to the intermediate node, and the second terminal of the second input transistor is electrically connected to the first node.

[0541] Optionally, the second node control circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor;

[0542] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0543] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0544] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0545] Optionally, the second node control circuit includes a third transistor, a fourth transistor, a sixth transistor, and a seventh transistor; the first node control circuit includes a fifth transistor and an eighth transistor.

[0546] The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node;

[0547] The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

[0548] The gate and first terminal of the sixth transistor are electrically connected to the second control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second second node;

[0549] The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal.

[0550] The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

[0551] The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

[0552] Optionally, the first first node control circuit includes a first fifth transistor, and the second first node control circuit includes a second fifth transistor;

[0553] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0554] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0555] Optionally, the first first node control circuit includes a first fifth transistor, the second first node control circuit includes a second fifth transistor; the third first node control circuit includes a first eighth transistor, and the fourth first node control circuit includes a second eighth transistor.

[0556] The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node.

[0557] The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

[0558] The gate of the first eighth transistor is electrically connected to the second second node, the first terminal of the first eighth transistor is electrically connected to the first node, and the second terminal of the first eighth transistor is electrically connected to the control node.

[0559] The gate of the second eighth transistor is electrically connected to the second second node, the first terminal of the second eighth transistor is electrically connected to the control node, and the second terminal of the second eighth transistor is electrically connected to the first voltage terminal.

[0560] Optionally, the first first node reset circuit includes a first ninth transistor, and the second first node reset circuit includes a second ninth transistor;

[0561] The gate of the first ninth transistor is electrically connected to the reset control terminal, the first terminal of the first ninth transistor is electrically connected to the first node, and the second terminal of the first ninth transistor is electrically connected to the control node.

[0562] The gate of the second ninth transistor is electrically connected to the reset control terminal, the first terminal of the second ninth transistor is electrically connected to the control node, and the second terminal of the second ninth transistor is electrically connected to the first voltage terminal.

[0563] Optionally, the first frame reset circuit includes a first tenth transistor, and the second frame reset circuit includes a second tenth transistor;

[0564] The gate of the first tenth transistor is electrically connected to the frame reset terminal, the first terminal of the first tenth transistor is electrically connected to the first node, and the second terminal of the first tenth transistor is electrically connected to the control node.

[0565] The gate of the second tenth transistor is electrically connected to the frame reset terminal, the first terminal of the second tenth transistor is electrically connected to the control node, and the second terminal of the second tenth transistor is electrically connected to the first voltage terminal.

[0566] Optionally, the nth output reset circuit includes an nth output reset transistor;

[0567] The gate of the nth output reset transistor is electrically connected to the first second node, the first terminal of the nth output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth output reset transistor is electrically connected to the second voltage terminal.

[0568] Optionally, the nth output reset circuit includes an nth first output reset transistor and an nth second output reset transistor;

[0569] The gate of the nth first output reset transistor is electrically connected to the first second node, the first terminal of the nth first output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth first output reset transistor is electrically connected to the second voltage terminal.

[0570] The gate of the nth second output reset transistor is electrically connected to the second second node, the first terminal of the nth second output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth second output reset transistor is electrically connected to the second voltage terminal.

[0571] Optionally, the carry output circuit includes a carry output transistor and a first carry reset transistor; the carry energy storage circuit includes a carry capacitor;

[0572] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0573] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0574] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0575] Optionally, the carry output circuit includes a carry output transistor and a first carry reset transistor; the carry output control circuit includes a first carry output control transistor; and the carry energy storage circuit includes a carry capacitor.

[0576] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0577] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0578] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0579] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0580] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry energy storage circuit includes a carry capacitor.

[0581] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0582] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0583] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0584] The first end of the carry capacitor is electrically connected to the first node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0585] Optionally, the carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry output control circuit includes a first carry output control transistor and a second carry output control transistor.

[0586] The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal.

[0587] The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal.

[0588] The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry-output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal.

[0589] The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node.

[0590] The gate of the second carry-out control transistor is electrically connected to the second control voltage terminal, the first terminal of the second carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the second carry-out control transistor is electrically connected to the first node.

[0591] The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

[0592] Optionally, the nth drive output circuit includes an nth drive output transistor and an nth output capacitor;

[0593] The gate of the nth driving output transistor is electrically connected to the nth output control node, the first terminal of the nth driving output transistor is electrically connected to the nth output clock signal terminal, and the second terminal of the nth driving output transistor is electrically connected to the nth driving output terminal.

[0594] The first terminal of the nth output capacitor is electrically connected to the nth output control node, and the second terminal of the nth output capacitor is electrically connected to the nth drive output terminal.

[0595] As shown in Figure 21A, based on at least one embodiment of the driving circuit shown in Figure 19A, the input circuit includes an input transistor MI;

[0596] The gate and source of the input transistor MI are electrically connected to the input terminal IS, and the drain of the input transistor MI is electrically connected to the first node PU.

[0597] The control voltage terminal includes a first control voltage terminal VDDA;

[0598] The first output control circuit includes a first transistor M11;

[0599] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0600] The second output control circuit includes a second first transistor M21;

[0601] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0602] The third output control circuit includes a third first transistor M31;

[0603] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0604] The fourth output control circuit includes a fourth first transistor M41;

[0605] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0606] The second node control circuit includes a third transistor M3 and a fourth transistor M4, and the first node control circuit includes a fifth transistor M;

[0607] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0608] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0609] The gate of M5 is electrically connected to the first second node PDA, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0610] The first node reset circuit includes a ninth transistor M9;

[0611] The gate of M9 is electrically connected to the reset control terminal RST, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0612] The frame reset circuit includes a tenth transistor M10;

[0613] The gate of M10 is electrically connected to the frame reset terminal TRST, the source of M10 is electrically connected to the first node PU, and the drain of M10 is electrically connected to the first low voltage terminal.

[0614] The second node setting circuit includes an eleventh transistor M011;

[0615] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0616] The carry output circuit includes a carry output transistor MC and a first carry reset transistor MF1; the carry energy storage circuit includes a carry capacitor C0.

[0617] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0618] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0619] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0620] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0621] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0622] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0623] The first output reset circuit includes a first output reset transistor MR1;

[0624] The gate of MR1 is electrically connected to the first second node PDA, the source of MR1 is electrically connected to the first drive output terminal GT1, and the drain of MR1 is electrically connected to the second low voltage terminal VGL.

[0625] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0626] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0627] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0628] The second output reset circuit includes a second output reset transistor MR2;

[0629] The gate of MR2 is electrically connected to the first second node PDA, the source of MR2 is electrically connected to the second drive output terminal GT2, and the drain of MR2 is electrically connected to the second low voltage terminal VGL.

[0630] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0631] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0632] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0633] The first output reset circuit includes a third output reset transistor MR3;

[0634] The gate of MR3 is electrically connected to the first second node PDA, the source of MR3 is electrically connected to the third drive output terminal GT3, and the drain of MR3 is electrically connected to the second low voltage terminal VGL.

[0635] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0636] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0637] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0638] The fourth output reset circuit includes a fourth output reset transistor MR4;

[0639] The gate of MR4 is electrically connected to the first second node PDA, the source of MR4 is electrically connected to the fourth drive output terminal GT4, and the drain of MR4 is electrically connected to the second low voltage terminal VGL.

[0640] In at least one embodiment shown in Figure 21A, all transistors are n-type transistors.

[0641] In at least one embodiment shown in Figure 21A, the threshold voltage of M11 is greater than the threshold voltage of MI to prevent leakage from the first output control node PU1 to the first node PU.

[0642] The threshold voltage of M21 is greater than the threshold voltage of MI to prevent leakage from the second output control node PU2 to the first node PU.

[0643] The threshold voltage of M31 is greater than the threshold voltage of MI to prevent leakage from the third output control node PU3 to the first node PU.

[0644] The threshold voltage of M41 is greater than the threshold voltage of MI to prevent leakage from the fourth output control node PU4 to the first node PU.

[0645] In at least one embodiment shown in Figure 21A, when the input signal provided by IS is a high-voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage when the first control voltage provided by VDDA is a high voltage. The threshold voltages of M11, M21, M31, and M41 are set to be greater than the threshold voltage of MI, respectively, so that when the potentials of PU1, PU2, PU3, and PU4 rise automatically, M11, M21, M31, and M41 are turned off to prevent leakage from PU1 to PU4. The leakage current from PU2 to PU, from PU3 to PU, and from PU4 to PU prevents the maintenance of high potentials for PU1, PU2, PU3, and PU4, leading to output errors. The potentials of PU are V0-Vthi. Vdda-V0+Vthi is set to be less than Vth11, Vdda-V0+Vthi to be less than Vth21, Vdda-V0+Vthi to be less than Vth31, and Vdda-V0+Vthi to be less than Vth41. When the potentials of PU1, PU2, PU3, and PU4 rise automatically, M11, M21, M31, and M41 are turned off. Here, Vthi is the threshold voltage of MI, Vth11 is the threshold voltage of M11, Vth21 is the threshold voltage of M21, Vth31 is the threshold voltage of M31, and Vth41 is the threshold voltage of M41.

[0646] At least one embodiment of the driving circuit shown in Figure 21A of this disclosure controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0647] In at least one embodiment of the driving circuit shown in FIG21A of this disclosure, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA, which is beneficial to reducing the number of transistors used and to achieving a narrow bezel.

[0648] Figure 21B is a structural diagram of the first part B1 in Figure 21A, and Figure 21C is a structural diagram of the second part B2 in Figure 21A.

[0649] As shown in Figure 21B, the first part B1 includes MI, M3, M4, M5, M9, M10 and M011;

[0650] As shown in Figure 21C, the second part B2 includes MC, C0, MF1, MT1, C1, M11, MR1, MT2, C2, M21, MR2, MT3, C3, M31, MR3, MT4, C4, M41, and MR4.

[0651] In at least one embodiment of the driving circuit shown in FIG21A of this disclosure, VDDA can be used to provide a high voltage signal.

[0652] In at least one embodiment of the driving circuit shown in FIG21A of this disclosure, the channel width-to-length ratio of M3 may be smaller than that of M4, so that when M3 and M4 are turned on at the same time, the potential of PU is low voltage.

[0653] In at least one embodiment of the driving circuit shown in FIG21A of this disclosure, VDDA provides a high voltage signal during operation; a frame display time may include an input phase, an output phase, and a reset phase set sequentially.

[0654] During the input phase, IS provides a high voltage signal, RST and TRST provide low voltage signals, MI is turned on, PU and IS are connected, and the potential of PU is high voltage; M4 is turned on, pulling the potential of PDA low; M11, M21, M31 and M41 are all turned on, PU1 is connected to PU, PU2 is connected to PU, PU3 is connected to PU, PU4 is connected to PU, and the potentials of PU1, PU2, PU3 and PU4 are all high voltage; CK_C, CK1, CK2, CK3 and CK4 all provide low voltage signals; CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0655] During the output phase, IS provides a low voltage signal, RST and TRST provide low voltage signals, MI is turned off, and the potentials of PU, PU1, PU2, PU3 and PU4 are all high voltage signals.

[0656] During the output phase, when CK_C provides a high voltage signal, CT provides a high voltage signal;

[0657] During the output phase, when CK1 provides a high voltage signal, GT1 provides a high voltage signal; when CK2 provides a high voltage signal, GT2 provides a high voltage signal; when CK3 provides a high voltage signal, GT3 provides a high voltage signal; and when CK4 provides a high voltage signal, GT4 provides a high voltage signal.

[0658] During the reset phase, IS provides a low voltage signal, RST provides a high voltage signal, TRST provides a low voltage signal, M9 is on, MI is off, PU's potential is low voltage, M3 is on, M4 is off, PDA's potential is high voltage, M5 is on; MF1 is on, CT provides a low voltage signal, MR1, MR2, MR3 and MR4 are on, and GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0659] In at least one embodiment of the driving circuit shown in Figure 21A of this disclosure, during the blank time period between two display frames, TRST can provide a high voltage signal, M10 is turned on, PU has a low voltage potential, M3 is turned on, M4 is turned off, PDA has a high voltage potential, and CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0660] The differences between at least one embodiment of the driving circuit shown in Figure 21D of this disclosure and at least one embodiment of the driving circuit shown in Figure 21A of this disclosure are as follows:

[0661] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01;

[0662] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[0663] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[0664] In at least one embodiment shown in Figure 21D, all transistors are n-type transistors.

[0665] The structural diagram of the first part B1 in Figure 21D is shown in Figure 21B, and the structural diagram of the second part B2 in Figure 21D is shown in Figure 21E.

[0666] In at least one embodiment shown in FIG21D of this disclosure, M01 is added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 being turned on when the potential of PU0 is bootstrapping.

[0667] In practical implementation, when both M01 and MI are replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI to prevent output errors caused by M01 turning on when the potential of PU0 is bootstrapping.

[0668] As shown in Figure 22A, based on at least one embodiment of the driving circuit shown in Figure 20A, the input circuit includes an input transistor MI;

[0669] The gate and source of the input transistor MI are electrically connected to the input terminal IS, and the drain of the input transistor MI is electrically connected to the first node PU.

[0670] The control voltage terminals include a first control voltage terminal VDDA and a second control voltage terminal VDDB.

[0671] The first output control circuit includes a first transistor M11 and a first transistor M12;

[0672] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0673] The gate of M12 is electrically connected to the second control voltage terminal VDDB, the source of M12 is electrically connected to the first output control node PU1, and the drain of M12 is electrically connected to the first node PU; the threshold voltage of M12 is greater than the threshold voltage of MI.

[0674] The second output control circuit includes a second first transistor M21 and a second second transistor M22;

[0675] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0676] The gate of M22 is electrically connected to the second control voltage terminal VDDB, the source of M22 is electrically connected to the second output control node PU2, and the drain of M22 is electrically connected to the first node PU; the threshold voltage of M22 is greater than the threshold voltage of MI.

[0677] The third output control circuit includes a third first transistor M31 and a third second transistor M32;

[0678] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0679] The gate of M32 is electrically connected to the second control voltage terminal VDDB, the source of M32 is electrically connected to the third output control node PU3, and the drain of M32 is electrically connected to the first node PU; the threshold voltage of M32 is greater than the threshold voltage of MI.

[0680] The fourth output control circuit includes a fourth first transistor M41 and a fourth second transistor M42;

[0681] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0682] The gate of M42 is electrically connected to the second control voltage terminal VDDB, the source of M42 is electrically connected to the fourth output control node PU4, and the drain of M42 is electrically connected to the first node PU; the threshold voltage of M42 is greater than the threshold voltage of MI.

[0683] The second node control circuit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7; the first node control circuit includes a fifth transistor M5 and an eighth transistor M8.

[0684] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0685] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0686] The gate and source of M6 are electrically connected to the second control voltage terminal VDDB, and the drain of M6 is electrically connected to the second node PDB.

[0687] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the second node PDB, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0688] The gate of M5 is electrically connected to the first second node PDA, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0689] The gate of M8 is electrically connected to the second node PDB, the source of M8 is electrically connected to the first node PU, and the drain of M8 is electrically connected to the first low voltage terminal LVGL.

[0690] The first node reset circuit includes a ninth transistor M9;

[0691] The gate of M9 is electrically connected to the reset control terminal RST, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0692] The frame reset circuit includes a tenth transistor M10;

[0693] The gate of M10 is electrically connected to the frame reset terminal TRST, the source of M10 is electrically connected to the first node PU, and the drain of M10 is electrically connected to the first low voltage terminal.

[0694] The second node setting circuit includes an eleventh transistor M011 and a twelfth transistor M012;

[0695] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0696] The gate of M012 is electrically connected to the input terminal IS, the source of M012 is electrically connected to the second second node PDB, and the drain of M12 is electrically connected to the first low voltage terminal LVGL.

[0697] The carry output circuit includes a carry output transistor MC, a first carry reset transistor MF1, and a second carry reset transistor MF2; the carry energy storage circuit includes a carry capacitor C0.

[0698] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0699] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0700] The gate of MF2 is electrically connected to the second node PDB, the source of MF2 is electrically connected to the carry output terminal CT, and the drain of MF2 is electrically connected to the first low voltage terminal LVGL.

[0701] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0702] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0703] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0704] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0705] The first output reset circuit includes a first first output reset transistor MR11 and a first second output reset transistor MR12;

[0706] The gate of MR11 is electrically connected to the first second node PDA, the source of MR11 is electrically connected to the first drive output terminal GT1, and the drain of MR11 is electrically connected to the second low voltage terminal VGL.

[0707] The gate of MR12 is electrically connected to the second second node PDB, the source of MR12 is electrically connected to the first drive output terminal GT1, and the drain of the first second output reset transistor MR12 is electrically connected to the second low voltage terminal VGL.

[0708] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0709] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0710] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0711] The second output reset circuit includes a second first output reset transistor MR21 and a second second output reset transistor MR22;

[0712] The gate of MR21 is electrically connected to the first second node PDA, the source of MR21 is electrically connected to the second drive output terminal GT2, and the drain of MR21 is electrically connected to the second low voltage terminal VGL.

[0713] The gate of MR22 is electrically connected to the second node PDB, the source of MR22 is electrically connected to the second drive output terminal GT2, and the drain of MR22 is electrically connected to the second low voltage terminal VGL.

[0714] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0715] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0716] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0717] The third output reset circuit includes a third first output reset transistor MR31 and a third second output reset transistor MR32;

[0718] The gate of MR31 is electrically connected to the first second node PDA, the source of MR31 is electrically connected to the third drive output terminal GT3, and the drain of MR31 is electrically connected to the second low voltage terminal VGL.

[0719] The gate of MR32 is electrically connected to the second node PDB, the source of MR32 is electrically connected to the third drive output terminal GT3, and the drain of MR12 is electrically connected to the second low voltage terminal VGL.

[0720] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0721] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0722] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0723] The fourth output reset circuit includes a fourth first output reset transistor MR41 and a fourth second output reset transistor MR42;

[0724] The gate of MR41 is electrically connected to the first second node PDA, the source of MR41 is electrically connected to the fourth drive output terminal GT4, and the drain of MR41 is electrically connected to the second low voltage terminal VGL.

[0725] The gate of MR42 is electrically connected to the second node PDB, the source of MR42 is electrically connected to the fourth drive output terminal GT4, and the drain of MR42 is electrically connected to the second low voltage terminal VGL.

[0726] In at least one embodiment shown in Figure 22A, all transistors are n-type transistors.

[0727] In at least one embodiment shown in Figure 22A, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal.

[0728] When the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vddb of the second control voltage provided by VDDB when VDDB provides a high voltage signal.

[0729] In at least one embodiment shown in Figure 22A, the threshold voltage of M11 is greater than the threshold voltage of MI, and the threshold voltage of M12 is greater than the threshold voltage of MI, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0730] The threshold voltage of M21 is greater than the threshold voltage of MI, and the threshold voltage of M22 is greater than the threshold voltage of MI, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0731] The threshold voltage of M31 is greater than the threshold voltage of MI, and the threshold voltage of M32 is greater than the threshold voltage of MI, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0732] The threshold voltage of M41 is greater than the threshold voltage of MI, and the threshold voltage of M42 is greater than the threshold voltage of MI, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0733] At least one embodiment of the driving circuit shown in Figure 22A of this disclosure controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0734] In at least one embodiment of the driving circuit shown in FIG22A of this disclosure, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA and PDB, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0735] In at least one embodiment of the driving circuit shown in FIG22A of this disclosure, when VDDA provides a high voltage signal, VDDB can provide a low voltage signal; when VDDB provides a low voltage signal, VDDA can provide a high voltage signal, and PDA and PDB work alternately.

[0736] In at least one embodiment of the driving circuit shown in FIG22A of this disclosure, the channel width-to-length ratio of M4 can be greater than that of M3, and the channel width-to-length ratio of M7 can be greater than that of M6.

[0737] Figure 22B is a structural diagram of the first part B1 in Figure 22A, and Figure 22C is a structural diagram of the second part B2 in Figure 22A.

[0738] As shown in Figure 22B, the first part B1 includes MI, M3, M4, M5, M6, M7, M8, M9, M10, M011 and M012;

[0739] As shown in Figure 22C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31, MR32, MT4, C4, M41, M42, MR41, and MR42.

[0740] In at least one embodiment of the driving circuit shown in FIG22A of this disclosure, when VDDA provides a high voltage signal and VDDB provides a low voltage signal, a frame display time may include an input stage, an output stage and a reset stage set sequentially.

[0741] During the input phase, IS provides a high voltage signal, RST and TRST both provide low voltage signals, MI is on, PU is connected to IS, and the potential of PU is high voltage; M3 and M4 are on, and the potential of PDA is low voltage; M11, M21, M31 and M41 are all on, PU1 is connected to PU, PU2 is connected to PU, PU3 is connected to PU, PU4 is connected to PU, and the potentials of PU1, PU2, PU3 and PU4 are all high voltage; CK_C, CK1, CK2, CK3 and CK4 all provide low voltage signals; CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0742] During the output phase, IS provides a low voltage signal, RST and TRST provide low voltage signals, MI is turned off, and the potentials of PU, PU1, PU2, PU3 and PU4 are all high voltage signals.

[0743] During the output phase, when CK_C provides a high voltage signal, CT provides a high voltage signal;

[0744] During the output phase, when CK1 provides a high voltage signal, GT1 provides a high voltage signal; when CK2 provides a high voltage signal, GT2 provides a high voltage signal; when CK3 provides a high voltage signal, GT3 provides a high voltage signal; and when CK4 provides a high voltage signal, GT4 provides a high voltage signal.

[0745] During the reset phase, IS provides a low voltage signal, RST provides a high voltage signal, TRST provides a low voltage signal, M9 is on, MI is off, PU's potential is low voltage, M3 is on, M4 is off, PDA's potential is high voltage, M5 is on; MF1 is on, CT provides a low voltage signal, MR11, MR21, MR31 and MR41 are on, and GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0746] In at least one embodiment of the driving circuit shown in Figure 22A of this disclosure, when VDDA provides a high voltage signal and VDDB provides a low voltage signal, during the blank time period between two display frames, TRST can provide a high voltage signal, M10 is turned on, the potential of PU is low voltage, M3 is turned on, M4 is turned off, the potential of PDA is high voltage, and CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0747] In at least one embodiment of the driving circuit shown in FIG22A of this disclosure, when VDDA provides a low voltage signal and VDDB provides a high voltage signal, a frame display time may include an input stage, an output stage and a reset stage set sequentially.

[0748] During the input phase, IS provides a high voltage signal, RST and TRST both provide low voltage signals, MI is on, PU is connected to IS, and the potential of PU is high voltage; M3 and M4 are on, and the potential of PDB is low voltage; M12, M22, M32 and M42 are all on, PU1 is connected to PU, PU2 is connected to PU, PU3 is connected to PU, PU4 is connected to PU, and the potentials of PU1, PU2, PU3 and PU4 are all high voltage; CK_C, CK1, CK2, CK3 and CK4 all provide low voltage signals; CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0749] During the output phase, IS provides a low voltage signal, RST and TRST provide low voltage signals, MI is turned off, and the potentials of PU, PU1, PU2, PU3 and PU4 are all high voltage signals.

[0750] During the output phase, when CK_C provides a high voltage signal, CT provides a high voltage signal;

[0751] During the output phase, when CK1 provides a high voltage signal, GT1 provides a high voltage signal; when CK2 provides a high voltage signal, GT2 provides a high voltage signal; when CK3 provides a high voltage signal, GT3 provides a high voltage signal; and when CK4 provides a high voltage signal, GT4 provides a high voltage signal.

[0752] During the reset phase, IS provides a low voltage signal, RST provides a high voltage signal, TRST provides a low voltage signal, M9 is on, MI is off, PU's potential is low voltage, M3 is on, M4 is off, PDA's potential is high voltage, M5 is on; MF2 is on, CT provides a low voltage signal, MR12, MR22, MR32 and MR42 are on, and GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0753] In at least one embodiment of the driving circuit shown in Figure 22A of this disclosure, when VDDA provides a high voltage signal and VDDB provides a low voltage signal, during the blank time period between two display frames, TRST can provide a high voltage signal, M10 is turned on, the potential of PU is low voltage, M6 is turned on, M7 is turned off, the potential of PDB is high voltage, and CT, GT1, GT2, GT3 and GT4 all provide low voltage signals.

[0754] The differences between at least one embodiment of the driving circuit shown in Figure 22D of this disclosure and at least one embodiment of the driving circuit shown in Figure 22A of this disclosure are as follows:

[0755] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01 and a second carry-out control transistor M02.

[0756] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[0757] The gate of M02 is electrically connected to VDDB, the source of M02 is electrically connected to the carry output node PU0, and the drain of M02 is electrically connected to PU.

[0758] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[0759] In at least one embodiment shown in Figure 22D, all transistors are n-type transistors.

[0760] The structural diagram of the first part B1 in Figure 22D is shown in Figure 22B, and the structural diagram of the second part B2 in Figure 22D is shown in Figure 22E.

[0761] In at least one embodiment shown in FIG22D of this disclosure, M01 and M02 are added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, and the threshold voltage of M02 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0762] In practical implementation, when M01, M02 and MI are all replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI, and the threshold voltage of M02 can be set to be less than the threshold voltage of MI. This prevents output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0763] As shown in Figure 23A, based on at least one embodiment of the drive circuit shown in Figure 15A,

[0764] The control circuit includes a control transistor M0, the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB.

[0765] The gate of M0 is electrically connected to the first node PU, the first terminal of M0 is electrically connected to the power supply voltage terminal VDD, and the drain of M0 is electrically connected to the control node P1.

[0766] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the control node P1.

[0767] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the control node P1, and the drain of the MIB is electrically connected to the first node PU.

[0768] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0769] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0770] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0771] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0772] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0773] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0774] The first first node control circuit includes a first fifth transistor M15, and the second first node control circuit includes a second fifth transistor M25;

[0775] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0776] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0777] The second node control circuit includes a third transistor M3 and a fourth transistor M4;

[0778] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0779] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0780] The second node setting circuit includes an eleventh transistor M011;

[0781] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0782] The first output control circuit includes a first transistor M11;

[0783] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0784] The second output control circuit includes a second first transistor M21;

[0785] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0786] The third output control circuit includes a third first transistor M31;

[0787] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0788] The fourth output control circuit includes a fourth first transistor M41;

[0789] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0790] The carry output circuit includes a carry output transistor MC and a first carry reset transistor MF1; the carry energy storage circuit includes a carry capacitor C0.

[0791] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0792] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0793] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0794] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0795] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0796] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0797] The first output reset circuit includes a first output reset transistor MR1;

[0798] The gate of MR1 is electrically connected to the first second node PDA, the source of MR1 is electrically connected to the first drive output terminal GT1, and the drain of MR1 is electrically connected to the second low voltage terminal VGL.

[0799] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0800] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0801] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0802] The second output reset circuit includes a second output reset transistor MR2;

[0803] The gate of MR2 is electrically connected to the first second node PDA, the source of MR2 is electrically connected to the second drive output terminal GT2, and the drain of MR2 is electrically connected to the second low voltage terminal VGL.

[0804] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0805] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0806] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0807] The first output reset circuit includes a third output reset transistor MR3;

[0808] The gate of MR3 is electrically connected to the first second node PDA, the source of MR3 is electrically connected to the third drive output terminal GT3, and the drain of MR3 is electrically connected to the second low voltage terminal VGL.

[0809] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0810] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0811] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0812] The fourth output reset circuit includes a fourth output reset transistor MR4;

[0813] The gate of MR4 is electrically connected to the first second node PDA, the source of MR4 is electrically connected to the fourth drive output terminal GT4, and the drain of MR4 is electrically connected to the second low voltage terminal VGL.

[0814] In at least one embodiment shown in Figure 23A, all transistors are n-type transistors.

[0815] Figure 23B is a structural diagram of the first part B1 in Figure 23A, and Figure 23C is a structural diagram of the second part B2 in Figure 23A.

[0816] As shown in Figure 23B, the first part B1 includes MIA, MIB, M0, M3, M4, M15, M25, M19, M29, M110, M210 and M011;

[0817] As shown in Figure 23C, the second part B2 includes MC, C0, MF1, MT1, C1, M11, MR1, MT2, C2, M21, MR2, MT3, C3, M31, MR3, MT4, C4, M41, and MR4.

[0818] In at least one embodiment shown in Figure 23A, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal.

[0819] In at least one embodiment shown in Figure 23A, the threshold voltage of M11 is greater than the threshold voltage of MIA, and the threshold voltage of M11 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0820] The threshold voltage of M21 is greater than the threshold voltage of MIA, and the threshold voltage of M21 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0821] The threshold voltage of M31 is greater than the threshold voltage of MIA, and the threshold voltage of M31 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0822] The threshold voltage of M41 is greater than the threshold voltage of MIA, and the threshold voltage of M41 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0823] At least one embodiment of the driving circuit shown in Figure 23A of this disclosure controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0824] In at least one embodiment of the driving circuit shown in FIG23A of this disclosure, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0825] In at least one embodiment of the driving circuit shown in FIG23A of this disclosure, VDDA can be used to provide a high voltage signal.

[0826] In at least one embodiment of the drive circuit shown in Figure 23A of this disclosure, when the potential of PU is high, M0 is turned on, the potential of P1 is high, the intermediate nodes of MIA and MIB are electrically connected to P1, the intermediate nodes of M19 and M29 are electrically connected to P1, the intermediate nodes of M110 and M210 are electrically connected to P1, and the intermediate nodes of M15 and M25 are electrically connected to P1, so as to reduce the leakage current of MIB, reduce the leakage current of M19, reduce the leakage current of M110, reduce the leakage current of M15, and facilitate the maintenance of the potential of PU.

[0827] As shown in Figure 24A, based on at least one embodiment of the driving circuit shown in Figure 17A,

[0828] The control circuit includes a control transistor M0, the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB.

[0829] The gate of M0 is electrically connected to the first node PU, the first terminal of M0 is electrically connected to the power supply voltage terminal VDD, and the drain of M0 is electrically connected to the control node P1.

[0830] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the control node P1.

[0831] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the control node P1, and the drain of the MIB is electrically connected to the first node PU.

[0832] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0833] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0834] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0835] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0836] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0837] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0838] The first first node control circuit includes a first fifth transistor M15, the second first node control circuit includes a second fifth transistor M25; the third first node control circuit includes a first eighth transistor M18, and the fourth first node control circuit includes a second eighth transistor M28.

[0839] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0840] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0841] The gate of M18 is electrically connected to the second node PDB, the source of M18 is electrically connected to the first node PU, and the drain of M18 is electrically connected to the control node P1.

[0842] The gate of M28 is electrically connected to the second node PDB, the source of M28 is electrically connected to the control node P1, and the drain of M28 is electrically connected to the first low voltage terminal LVGL.

[0843] The second node control circuit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7;

[0844] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0845] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0846] The gate and source of M6 are electrically connected to the second control voltage terminal VDDB, and the drain of M6 is electrically connected to the second node PDB.

[0847] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the second node PDB, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0848] The second node setting circuit includes an eleventh transistor M011 and a twelfth transistor M012;

[0849] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0850] The gate of M012 is electrically connected to the input terminal IS, the source of M012 is electrically connected to the second second node PDB, and the drain of M012 is electrically connected to the first low voltage terminal LVGL.

[0851] The carry output circuit includes a carry output transistor MC, a first carry reset transistor MF1, and a second carry reset transistor MF2; the carry energy storage circuit includes a carry capacitor.

[0852] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0853] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0854] The gate of MF2 is electrically connected to the second node PDB, the source of MF2 is electrically connected to the carry output terminal CT, and the drain of MF2 is electrically connected to the first low voltage terminal LVGL.

[0855] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0856] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0857] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0858] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0859] The first output reset circuit includes a first first output reset transistor MR11 and a first second output reset transistor MR12;

[0860] The gate of MR11 is electrically connected to the first second node PDA, the source of MR11 is electrically connected to the first drive output terminal GT1, and the drain of MR11 is electrically connected to the second low voltage terminal VGL.

[0861] The gate of MR12 is electrically connected to the second second node PDB, the source of MR12 is electrically connected to the first drive output terminal GT1, and the drain of the first second output reset transistor MR12 is electrically connected to the second low voltage terminal VGL.

[0862] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0863] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0864] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0865] The second output reset circuit includes a second first output reset transistor MR21 and a second second output reset transistor MR22;

[0866] The gate of MR21 is electrically connected to the first second node PDA, the source of MR21 is electrically connected to the second drive output terminal GT2, and the drain of MR21 is electrically connected to the second low voltage terminal VGL.

[0867] The gate of MR22 is electrically connected to the second node PDB, the source of MR22 is electrically connected to the second drive output terminal GT2, and the drain of MR22 is electrically connected to the second low voltage terminal VGL.

[0868] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0869] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0870] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0871] The third output reset circuit includes a third first output reset transistor MR31 and a third second output reset transistor MR32;

[0872] The gate of MR31 is electrically connected to the first second node PDA, the source of MR31 is electrically connected to the third drive output terminal GT3, and the drain of MR31 is electrically connected to the second low voltage terminal VGL.

[0873] The gate of MR32 is electrically connected to the second node PDB, the source of MR32 is electrically connected to the third drive output terminal GT3, and the drain of MR12 is electrically connected to the second low voltage terminal VGL.

[0874] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0875] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0876] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0877] The fourth output reset circuit includes a fourth first output reset transistor MR41 and a fourth second output reset transistor MR42;

[0878] The gate of MR41 is electrically connected to the first second node PDA, the source of MR41 is electrically connected to the fourth drive output terminal GT4, and the drain of MR41 is electrically connected to the second low voltage terminal VGL.

[0879] The gate of MR42 is electrically connected to the second node PDB, the source of MR42 is electrically connected to the fourth drive output terminal GT4, and the drain of MR42 is electrically connected to the second low voltage terminal VGL.

[0880] In at least one embodiment shown in Figure 24A, all transistors are n-type transistors.

[0881] Figure 24B is a structural diagram of the first part B1 in Figure 24A, and Figure 24C is a structural diagram of the second part B2 in Figure 24A.

[0882] As shown in Figure 24B, the first part B1 includes MIA, MIB, M0, M3, M4, M15, M25, M6, M7, M18, M28, M19, M29, M110, M210, M011 and M012.

[0883] As shown in Figure 24C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31, MR32, MT4, C4, M41, M42, MR41, and MR42.

[0884] In at least one embodiment shown in Figure 24A, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal.

[0885] When the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vddb of the second control voltage provided by VDDB when VDDB provides a high voltage signal.

[0886] In at least one embodiment shown in Figure 24A, the threshold voltage of M11 is greater than the threshold voltage of MIA, the threshold voltage of M11 is greater than the threshold voltage of MIB, the threshold voltage of M12 is greater than the threshold voltage of MIA, and the threshold voltage of M12 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0887] The threshold voltage of M21 is greater than the threshold voltage of MIA, the threshold voltage of M21 is greater than the threshold voltage of MIB, the threshold voltage of M22 is greater than the threshold voltage of MIA, and the threshold voltage of M22 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0888] The threshold voltage of M31 is greater than the threshold voltage of MIA, the threshold voltage of M31 is greater than the threshold voltage of MIB, the threshold voltage of M32 is greater than the threshold voltage of MIA, and the threshold voltage of M32 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0889] The threshold voltage of M41 is greater than the threshold voltage of MIA, the threshold voltage of M41 is greater than the threshold voltage of MIB, the threshold voltage of M42 is greater than the threshold voltage of MIA, and the threshold voltage of M42 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0890] At least one embodiment of the driving circuit shown in Figure 24A of this disclosure controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0891] In at least one embodiment of the driving circuit shown in FIG24A of this disclosure, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share the PDA and PDB, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0892] At least one embodiment of the drive circuit shown in Figure 24A of this disclosure, when in operation,

[0893] When the potential of PU is high, M0 is turned on, and the potential of P1 is high.

[0894] The intermediate nodes of MIA and MIB are electrically connected to P1, the intermediate nodes of M19 and M29 are electrically connected to P1, the intermediate nodes of M110 and M210 are electrically connected to P1, the intermediate nodes of M15 and M25 are electrically connected to P1, and the intermediate nodes of M18 and M28 are electrically connected to P1 to reduce leakage current in MIB, M19, M110, M15, and M18, thereby helping to maintain the potential of PU.

[0895] The differences between at least one embodiment of the driving circuit shown in Figure 24D of this disclosure and at least one embodiment of the driving circuit shown in Figure 24A of this disclosure are as follows:

[0896] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01 and a second carry-out control transistor M02.

[0897] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[0898] The gate of M02 is electrically connected to VDDB, the source of M02 is electrically connected to the carry output node PU0, and the drain of M02 is electrically connected to PU.

[0899] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[0900] In at least one embodiment shown in Figure 24D, all transistors are n-type transistors.

[0901] The structural diagram of the first part B1 in Figure 24D is shown in Figure 24B, and the structural diagram of the second part B2 in Figure 24D is shown in Figure 24E.

[0902] In at least one embodiment shown in Figure 24D of this disclosure, M01 and M02 are added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, and the threshold voltage of M02 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0903] In practical implementation, when M01, M02 and MI are all replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI, and the threshold voltage of M02 can be set to be less than the threshold voltage of MI. This prevents output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[0904] As shown in Figure 25A, based on at least one embodiment of the driving circuit shown in Figure 16A,

[0905] The first control circuit includes a first control transistor MOA, and the second control circuit includes a second control transistor MOB; the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB.

[0906] The gate of MOA is electrically connected to the first node PU, the source of MOA is electrically connected to the power supply voltage terminal VDD, and the drain of MOA is electrically connected to the control node P1.

[0907] The gate of MOSFET is electrically connected to the first node PU, the source of MOSFET is electrically connected to the power supply voltage terminal VDD, and the drain of MOSFET is electrically connected to the intermediate node Z1.

[0908] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the intermediate node Z1.

[0909] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the intermediate node Z1, and the drain of the MIB is electrically connected to the first node PU.

[0910] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0911] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0912] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0913] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0914] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0915] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0916] The first first node control circuit includes a first fifth transistor M15, and the second first node control circuit includes a second fifth transistor M25;

[0917] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0918] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0919] The second node control circuit includes a third transistor M3 and a fourth transistor M4;

[0920] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0921] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0922] The second node setting circuit includes an eleventh transistor M011;

[0923] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0924] The first output control circuit includes a first transistor M11;

[0925] The gate of M11 is electrically connected to the first control voltage terminal VDDA, the source of M11 is electrically connected to the first output control node PU1, and the drain of M11 is electrically connected to the first node PU; the threshold voltage of M11 is greater than the threshold voltage of MI.

[0926] The second output control circuit includes a second first transistor M21;

[0927] The gate of M21 is electrically connected to the first control voltage terminal VDDA, the source of M21 is electrically connected to the second output control node PU2, and the drain of M21 is electrically connected to the first node PU; the threshold voltage of M21 is greater than the threshold voltage of MI.

[0928] The third output control circuit includes a third first transistor M31;

[0929] The gate of M31 is electrically connected to the first control voltage terminal VDDA, the source of M31 is electrically connected to the third output control node PU3, and the drain of M31 is electrically connected to the first node PU; the threshold voltage of M31 is greater than the threshold voltage of MI.

[0930] The fourth output control circuit includes a fourth first transistor M41;

[0931] The gate of M41 is electrically connected to the first control voltage terminal VDDA, the source of M41 is electrically connected to the fourth output control node PU4, and the drain of M41 is electrically connected to the first node PU; the threshold voltage of M41 is greater than the threshold voltage of MI.

[0932] The carry output circuit includes a carry output transistor MC and a first carry reset transistor MF1; the carry energy storage circuit includes a carry capacitor C0.

[0933] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0934] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0935] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0936] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0937] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0938] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0939] The first output reset circuit includes a first output reset transistor MR1;

[0940] The gate of MR1 is electrically connected to the first second node PDA, the source of MR1 is electrically connected to the first drive output terminal GT1, and the drain of MR1 is electrically connected to the second low voltage terminal VGL.

[0941] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[0942] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[0943] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[0944] The second output reset circuit includes a second output reset transistor MR2;

[0945] The gate of MR2 is electrically connected to the first second node PDA, the source of MR2 is electrically connected to the second drive output terminal GT2, and the drain of MR2 is electrically connected to the second low voltage terminal VGL.

[0946] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[0947] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[0948] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[0949] The first output reset circuit includes a third output reset transistor MR3;

[0950] The gate of MR3 is electrically connected to the first second node PDA, the source of MR3 is electrically connected to the third drive output terminal GT3, and the drain of MR3 is electrically connected to the second low voltage terminal VGL.

[0951] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[0952] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[0953] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[0954] The fourth output reset circuit includes a fourth output reset transistor MR4;

[0955] The gate of MR4 is electrically connected to the first second node PDA, the source of MR4 is electrically connected to the fourth drive output terminal GT4, and the drain of MR4 is electrically connected to the second low voltage terminal VGL.

[0956] Figure 25B is a structural diagram of the first part B1 in Figure 25A, and Figure 25C is a structural diagram of the second part B2 in Figure 25A.

[0957] As shown in Figure 25B, the first part B1 includes MIA, MIB, M0A, M0B, M3, M4, M15, M25, M19, M29, M110, M210 and M011;

[0958] As shown in Figure 25C, the second part B2 includes MC, C0, MF1, MT1, C1, M11, MR1, MT2, C2, M21, MR2, MT3, C3, M31, MR3, MT4, C4, M41, and MR4.

[0959] In at least one embodiment shown in Figure 25A, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage when the first control voltage provided by VDDA is a high voltage.

[0960] In at least one embodiment shown in Figure 25A, the threshold voltage of M11 is greater than the threshold voltage of MIA, and the threshold voltage of M11 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[0961] The threshold voltage of M21 is greater than the threshold voltage of MIA, and the threshold voltage of M21 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[0962] The threshold voltage of M31 is greater than the threshold voltage of MIA, and the threshold voltage of M31 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[0963] The threshold voltage of M41 is greater than the threshold voltage of MIA, and the threshold voltage of M41 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[0964] At least one embodiment of the driving circuit shown in Figure 25A of this disclosure controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[0965] In at least one embodiment of the driving circuit shown in FIG25A of this disclosure, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share a PDA, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[0966] In at least one embodiment of the drive circuit shown in Figure 25A of this disclosure, when the potential of PU is high, both M0A and M0B are turned on, VDD is connected to Z1, and P1 is connected to VDD. The potentials of Z1 and P1 are both high, so as to reduce the leakage current of M1B, reduce the leakage current of M19, reduce the leakage current of M110, reduce the leakage current of M15, and facilitate the maintenance of the potential of PU.

[0967] As shown in Figure 26A, based on at least one embodiment of the driving circuit shown in Figure 18A,

[0968] The first control circuit includes a first control transistor MOA, and the second control circuit includes a second control transistor MOB; the first input circuit includes a first input transistor MIA, and the second input circuit includes a second input transistor MIB.

[0969] The gate of MOA is electrically connected to the first node PU, the source of MOA is electrically connected to the power supply voltage terminal VDD, and the drain of MOA is electrically connected to the control node P1.

[0970] The gate of MOSFET is electrically connected to the first node PU, the source of MOSFET is electrically connected to the power supply voltage terminal VDD, and the drain of MOSFET is electrically connected to the intermediate node Z1.

[0971] The gate of MIA and the source of MIA are both electrically connected to the input terminal IS, and the drain of MIA is electrically connected to the intermediate node Z1.

[0972] The gate of the MIB is electrically connected to the input terminal IS, the source of the MIB is electrically connected to the intermediate node Z1, and the drain of the MIB is electrically connected to the first node PU.

[0973] The first first node reset circuit includes a first ninth transistor M19, and the second first node reset circuit includes a second ninth transistor M29.

[0974] The gate of M19 is electrically connected to the reset control terminal RST, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the control node P1.

[0975] The gate of M29 is electrically connected to the reset control terminal RST, the source of M29 is electrically connected to the control node P1, and the drain of M29 is electrically connected to the first low voltage terminal LVGL.

[0976] The first frame reset circuit includes a first tenth transistor M110, and the second frame reset circuit includes a second tenth transistor M210.

[0977] The gate of M110 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the first node PU, and the drain of M110 is electrically connected to the control node P1.

[0978] The gate of M210 is electrically connected to the frame reset terminal TRST, the source of M110 is electrically connected to the control node P1, and the drain of M210 is electrically connected to the first low voltage terminal LVGL.

[0979] The first first node control circuit includes a first fifth transistor M15, the second first node control circuit includes a second fifth transistor M25; the third first node control circuit includes a first eighth transistor M18, and the fourth first node control circuit includes a second eighth transistor M28.

[0980] The gate of M15 is electrically connected to the first second node PDA, the source of M15 is electrically connected to the first node PU, and the drain of M15 is electrically connected to the control node P1.

[0981] The gate of M25 is electrically connected to the first second node PDA, the source of M25 is electrically connected to the control node P1, and the drain of M25 is electrically connected to the first low voltage terminal LVGL.

[0982] The gate of M18 is electrically connected to the second node PDB, the source of M18 is electrically connected to the first node PU, and the drain of M18 is electrically connected to the control node P1; the gate of M28 is electrically connected to the second node PDB, the source of M28 is electrically connected to the control node P1, and the drain of M28 is electrically connected to the first low voltage terminal LVGL.

[0983] The second node control circuit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7;

[0984] The gate and source of M3 are electrically connected to the first control voltage terminal VDDA, and the drain of M3 is electrically connected to the first second node PDA.

[0985] The gate of M4 is electrically connected to the first node PU, the source of M4 is electrically connected to the first second node PDA, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0986] The gate and source of M6 are electrically connected to the second control voltage terminal VDDB, and the drain of M6 is electrically connected to the second node PDB.

[0987] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the second node PDB, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0988] The second node setting circuit includes an eleventh transistor M011 and a twelfth transistor M012;

[0989] The gate of M011 is electrically connected to the input terminal IS, the source of M011 is electrically connected to the first second node PDA, and the drain of M011 is electrically connected to the first low voltage terminal LVGL.

[0990] The gate of M012 is electrically connected to the input terminal IS, the source of M012 is electrically connected to the second second node PDB, and the drain of M012 is electrically connected to the first low voltage terminal LVGL.

[0991] The carry output circuit includes a carry output transistor MC, a first carry reset transistor MF1, and a second carry reset transistor MF2; the carry energy storage circuit includes a carry capacitor C0.

[0992] The gate of MC is electrically connected to the first node PU, the source of MC is electrically connected to the carry clock signal terminal CK_C, and the drain of MC is electrically connected to the carry output terminal CT.

[0993] The gate of MF1 is electrically connected to the first second node PDA, the source of MF1 is electrically connected to the carry output terminal CT, and the drain of MF1 is electrically connected to the first low voltage terminal LVGL.

[0994] The gate of MF2 is electrically connected to the second node PDB, the source of MF2 is electrically connected to the carry output terminal CT, and the drain of MF2 is electrically connected to the first low voltage terminal LVGL.

[0995] The first end of the carry capacitor C0 is electrically connected to the first node PU, and the second end of the carry capacitor C0 is electrically connected to the carry output terminal CT.

[0996] The first drive output circuit includes a first drive output transistor MT1, and the first energy storage circuit includes a first output capacitor C1.

[0997] The gate of MT1 is electrically connected to the first output control node PU1, the source of MT1 is electrically connected to the first output clock signal terminal CK1, and the drain of MT1 is electrically connected to the first drive output terminal GT1.

[0998] The first end of C1 is electrically connected to the first output control node PU1, and the second end of C1 is electrically connected to the first drive output terminal GT1.

[0999] The first output reset circuit includes a first first output reset transistor MR11 and a first second output reset transistor MR12;

[1000] The gate of MR11 is electrically connected to the first second node PDA, the source of MR11 is electrically connected to the first drive output terminal GT1, and the drain of MR11 is electrically connected to the second low voltage terminal VGL.

[1001] The gate of MR12 is electrically connected to the second second node PDB, the source of MR12 is electrically connected to the first drive output terminal GT1, and the drain of the first second output reset transistor MR12 is electrically connected to the second low voltage terminal VGL.

[1002] The second drive output circuit includes a second drive output transistor MT2, and the second energy storage circuit includes a second output capacitor C2;

[1003] The gate of MT2 is electrically connected to the second output control node PU2, the source of MT2 is electrically connected to the second output clock signal terminal CK2, and the drain of MT2 is electrically connected to the second drive output terminal GT2.

[1004] The first end of C2 is electrically connected to the second output control node PU2, and the second end of C2 is electrically connected to the second drive output terminal GT2.

[1005] The second output reset circuit includes a second first output reset transistor MR21 and a second second output reset transistor MR22;

[1006] The gate of MR21 is electrically connected to the first second node PDA, the source of MR21 is electrically connected to the second drive output terminal GT2, and the drain of MR21 is electrically connected to the second low voltage terminal VGL.

[1007] The gate of MR22 is electrically connected to the second node PDB, the source of MR22 is electrically connected to the second drive output terminal GT2, and the drain of MR22 is electrically connected to the second low voltage terminal VGL.

[1008] The third drive output circuit includes a third drive output transistor MT3, and the third energy storage circuit includes a third output capacitor C3.

[1009] The gate of MT3 is electrically connected to the third output control node PU3, the source of MT3 is electrically connected to the third output clock signal terminal CK3, and the drain of MT3 is electrically connected to the third drive output terminal GT3.

[1010] The first end of C3 is electrically connected to the third output control node PU3, and the second end of C3 is electrically connected to the third drive output terminal GT3.

[1011] The third output reset circuit includes a third first output reset transistor MR31 and a third second output reset transistor MR32;

[1012] The gate of MR31 is electrically connected to the first second node PDA, the source of MR31 is electrically connected to the third drive output terminal GT3, and the drain of MR31 is electrically connected to the second low voltage terminal VGL.

[1013] The gate of MR32 is electrically connected to the second node PDB, the source of MR32 is electrically connected to the third drive output terminal GT3, and the drain of MR12 is electrically connected to the second low voltage terminal VGL.

[1014] The fourth drive output circuit includes a fourth drive output transistor MT4, and the fourth energy storage circuit includes a fourth output capacitor C4.

[1015] The gate of MT4 is electrically connected to the fourth output control node PU4, the source of MT4 is electrically connected to the fourth output clock signal terminal CK4, and the drain of MT4 is electrically connected to the fourth drive output terminal GT4.

[1016] The first end of C4 is electrically connected to the fourth output control node PU4, and the second end of C4 is electrically connected to the fourth drive output terminal GT4.

[1017] The fourth output reset circuit includes a fourth first output reset transistor MR41 and a fourth second output reset transistor MR42;

[1018] The gate of MR41 is electrically connected to the first second node PDA, the source of MR41 is electrically connected to the fourth drive output terminal GT4, and the drain of MR41 is electrically connected to the second low voltage terminal VGL.

[1019] The gate of MR42 is electrically connected to the second node PDB, the source of MR42 is electrically connected to the fourth drive output terminal GT4, and the drain of MR42 is electrically connected to the second low voltage terminal VGL.

[1020] Figure 26B is a structural diagram of the first part B1 in Figure 26A, and Figure 26C is a structural diagram of the second part B2 in Figure 26A.

[1021] As shown in Figure 26B, the first part B1 includes MIA, MIB, M0A, M0B, M3, M4, M6, M7, M15, M25, M18, M28, M19, M29, M110, M210, M011 and M012.

[1022] As shown in Figure 26C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31, MR32, MT4, C4, M41, M42, MR41, and MR42.

[1023] In at least one embodiment shown in Figure 26A, all transistors are n-type transistors.

[1024] In at least one embodiment shown in Figure 26A, when the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vdda of the first control voltage provided by VDDA when VDDA provides a high voltage signal.

[1025] When the input signal provided by IS is a high voltage signal, the voltage value V0 of the input signal is equal to the voltage value Vddb of the second control voltage provided by VDDB when VDDB provides a high voltage signal.

[1026] In at least one embodiment shown in Figure 26A, the threshold voltage of M11 is greater than the threshold voltage of MIA, the threshold voltage of M11 is greater than the threshold voltage of MIB, the threshold voltage of M12 is greater than the threshold voltage of MIA, and the threshold voltage of M12 is greater than the threshold voltage of MIB, in order to prevent leakage from the first output control node PU1 to the first node PU.

[1027] The threshold voltage of M21 is greater than the threshold voltage of MIA, the threshold voltage of M21 is greater than the threshold voltage of MIB, the threshold voltage of M22 is greater than the threshold voltage of MIA, and the threshold voltage of M22 is greater than the threshold voltage of MIB, in order to prevent leakage from the second output control node PU2 to the first node PU.

[1028] The threshold voltage of M31 is greater than the threshold voltage of MIA, the threshold voltage of M31 is greater than the threshold voltage of MIB, the threshold voltage of M32 is greater than the threshold voltage of MIA, and the threshold voltage of M32 is greater than the threshold voltage of MIB, in order to prevent leakage from the third output control node PU3 to the first node PU.

[1029] The threshold voltage of M41 is greater than the threshold voltage of MIA, the threshold voltage of M41 is greater than the threshold voltage of MIB, the threshold voltage of M42 is greater than the threshold voltage of MIA, and the threshold voltage of M42 is greater than the threshold voltage of MIB, in order to prevent leakage from the fourth output control node PU4 to the first node PU.

[1030] At least one embodiment of the driving circuit shown in Figure 26A of this disclosure controls GT1, GT2, GT3 and GT4 to output a first driving signal, a second driving signal, a third driving signal and a fourth driving signal respectively through a first node PU, which can reduce the number of transistors used and facilitate the realization of a narrow bezel.

[1031] In at least one embodiment of the driving circuit shown in FIG26A of this disclosure, the first output reset circuit, the second output reset circuit, the third output reset circuit, and the fourth output reset circuit share PDA and PDB, which helps to reduce the number of transistors used and facilitates the realization of a narrow bezel.

[1032] In at least one embodiment of the drive circuit shown in Figure 26A of this disclosure, when the potential of PU is high, both M0A and M0B are turned on, VDD is connected to Z1, P1 is connected to VDD, the potentials of Z1 and P1 are both high, the intermediate nodes of M19 and M29 are electrically connected to P1, the intermediate nodes of M110 and M210 are electrically connected to P1, the intermediate nodes of M15 and M25 are electrically connected to P1, and the intermediate nodes of M18 and M28 are electrically connected to P1, so as to reduce the leakage current of M1B, reduce the leakage current of M19, reduce the leakage current of M110, reduce the leakage current of M15, reduce the leakage current of M18, and facilitate the maintenance of the potential of PU.

[1033] The differences between at least one embodiment of the driving circuit shown in Figure 26D of this disclosure and at least one embodiment of the driving circuit shown in Figure 26A of this disclosure are as follows:

[1034] It also includes a carry-out control circuit, which includes a first carry-out control transistor M01 and a second carry-out control transistor M02.

[1035] The gate of M01 is electrically connected to VDDA, the source of M01 is electrically connected to the carry output node PU0, and the drain of M01 is electrically connected to PU.

[1036] The gate of M02 is electrically connected to VDDB, the source of M02 is electrically connected to the carry output node PU0, and the drain of M02 is electrically connected to PU.

[1037] The gate of MC is electrically connected to PU0; the first terminal of C0 is electrically connected to PU0.

[1038] In at least one embodiment shown in Figure 26D, all transistors are n-type transistors.

[1039] The structural diagram of the first part B1 in Figure 26D is shown in Figure 26B, and the structural diagram of the second part B2 in Figure 26D is shown in Figure 26E.

[1040] In at least one embodiment shown in Figure 26D of this disclosure, M01 and M02 are added, and the threshold voltage of M01 is set to be greater than the threshold voltage of MI, and the threshold voltage of M02 is set to be greater than the threshold voltage of MI, so as to prevent output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[1041] In practical implementation, when M01, M02 and MI are all replaced with p-type transistors, the threshold voltage of M01 can be set to be less than the threshold voltage of MI, and the threshold voltage of M02 can be set to be less than the threshold voltage of MI. This prevents output errors caused by M01 and M02 being turned on when the potential of PU0 is bootstrapping.

[1042] The difference between at least one embodiment of the driving circuit shown in Figure 27A of this disclosure and at least one embodiment of the driving circuit shown in Figure 24A of this disclosure is that:

[1043] Excluding PU4, MT4, C4, GT4, M41, M42, MR41 and MR42.

[1044] At least one embodiment of the drive circuit shown in Figure 27A of this disclosure outputs three levels of drive signals.

[1045] Figure 27B is a structural diagram of the first part B1 in Figure 27A, and Figure 27C is a structural diagram of the second part B2 in Figure 27A.

[1046] As shown in Figure 27B, the first part B1 includes MIA, MIB, M0, M3, M4, M6, M7, M15, M25, M18, M28, M19, M29, M110, M210, M011 and M012.

[1047] As shown in Figure 27C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31 and MR32.

[1048] The difference between at least one embodiment of the driving circuit shown in Figure 28A of this disclosure and at least one embodiment of the driving circuit shown in Figure 27A of this disclosure is that:

[1049] Excluding PU3, MT3, C3, GT3, M31, M32, MR31 and MR32.

[1050] At least one embodiment of the drive circuit shown in Figure 28A of this disclosure outputs two levels of drive signals.

[1051] Figure 28B is a structural diagram of the first part B1 in Figure 28A, and Figure 28C is a structural diagram of the second part B2 in Figure 28A.

[1052] As shown in Figure 28B, the first part B1 includes MIA, MIB, M0, M3, M4, M6, M7, M15, M25, M18, M28, M19, M29, M110, M210, M011 and M012.

[1053] As shown in Figure 28C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21 and MR22.

[1054] The difference between at least one embodiment of the driving circuit shown in Figure 29A of this disclosure and at least one embodiment of the driving circuit shown in Figure 22A of this disclosure is that:

[1055] Excluding PU4, MT4, C4, GT4, M41, M42, MR41 and MR42.

[1056] At least one embodiment of the drive circuit shown in Figure 29A of this disclosure outputs three levels of drive signals.

[1057] Figure 29B is a structural diagram of the first part B1 in Figure 29A, and Figure 29C is a structural diagram of the second part B2 in Figure 29A.

[1058] As shown in Figure 29B, the first part B1 includes MI, M3, M4, M6, M7, M5, M8, M9, M10, M011 and M012;

[1059] As shown in Figure 29C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21, MR22, MT3, C3, M31, M32, MR31 and MR32.

[1060] The difference between at least one embodiment of the driving circuit shown in Figure 30A of this disclosure and at least one embodiment of the driving circuit shown in Figure 29A of this disclosure is that:

[1061] Excluding PU3, MT3, C3, GT3, M31, M32, MR31 and MR32.

[1062] At least one embodiment of the drive circuit shown in Figure 30A of this disclosure outputs two levels of drive signals.

[1063] The driving module described in this embodiment includes multiple stages of the aforementioned driving circuits.

[1064] Figure 30B is a structural diagram of the first part B1 in Figure 30A, and Figure 30C is a structural diagram of the second part B2 in Figure 30A.

[1065] As shown in Figure 30B, the first part B1 includes MI, M3, M4, M6, M7, M5, M8, M9, M10, M011 and M012;

[1066] As shown in Figure 30C, the second part B2 includes MC, C0, MF1, MF2, MT1, C1, M11, M12, MR11, MR12, MT2, C2, M21, M22, MR21 and MR22.

[1067] As shown in Figure 31, the first driving module can be set on the left side of the display area, and the second driving module can be set on the right side of the display area.

[1068] The first driving module may include a first-stage first driving circuit S11, a second-stage first driving circuit S21, a third-stage first driving circuit S31, and a fourth-stage first driving circuit S41.

[1069] The second drive module may include a first-stage second drive circuit S12, a second-stage second drive circuit S22, a third-stage second drive circuit S32, and a fourth-stage second drive circuit S42.

[1070] S11 is electrically connected to the first clock signal line CLK1, the third clock signal line CLK3, the fifth clock signal line CLK5, and the seventh clock signal line CLK7, respectively.

[1071] S21 is electrically connected to the ninth clock signal line CLK9, the eleventh clock signal line CLK11, the thirteenth clock signal line CLK13, and the fifteenth clock signal line CLK15, respectively.

[1072] S31 is electrically connected to the seventeenth clock signal line CLK17, the nineteenth clock signal line CLK19, the twenty-first clock signal line CLK21, and the twenty-third clock signal line CLK23, respectively.

[1073] S41 is electrically connected to the first clock signal line CLK1, the third clock signal line CLK3, the fifth clock signal line CLK5, and the seventh clock signal line CLK7, respectively.

[1074] The first drive output terminal of S11 is electrically connected to the first row of gate line G1, the second drive output terminal of S11 is electrically connected to the third row of gate line G3, the third drive output terminal of S11 is electrically connected to the fifth row of gate line G5, and the fourth drive output terminal of S11 is electrically connected to the seventh row of gate line G7.

[1075] The first drive output terminal of S21 is electrically connected to the ninth row of gate line G9, the second drive output terminal of S21 is electrically connected to the eleventh row of gate line G11, the third drive output terminal of S21 is electrically connected to the thirteenth row of gate line G13, and the fourth drive output terminal of S21 is electrically connected to the fifteenth row of gate line G15.

[1076] The first drive output terminal of S31 is electrically connected to the seventeenth row gate line G17, the second drive output terminal of S31 is electrically connected to the nineteenth row gate line G19, the third drive output terminal of S31 is electrically connected to the twenty-first row gate line G21, and the fourth drive output terminal of S31 is electrically connected to the twenty-third row gate line G23.

[1077] The first drive output terminal of S41 is electrically connected to the 25th row gate line G25, the second drive output terminal of S41 is electrically connected to the 27th row gate line G27, the third drive output terminal of S41 is electrically connected to the 29th row gate line G29, and the fourth drive output terminal of S41 is electrically connected to the 31st row gate line G31.

[1078] The input terminal of S11 is electrically connected to the first starting voltage line STV1; the reset terminal of S11 is electrically connected to the carry output terminal of S31.

[1079] The input terminal of S21 is electrically connected to the carry output terminal of S11, and the reset terminal of S21 is electrically connected to the carry output terminal of S41.

[1080] The input terminal of S31 is electrically connected to the carry output terminal of S21;

[1081] The input terminal of S41 is electrically connected to the carry output terminal of S31;

[1082] S12 is electrically connected to the second clock signal line CLK2, the fourth clock signal line CLK4, the sixth clock signal line CLK6, and the eighth clock signal line CLK8, respectively.

[1083] S22 is electrically connected to the tenth clock signal line CLK10, the twelfth clock signal line CLK12, the fourteenth clock signal line CLK14, and the sixteenth clock signal line CLK16, respectively.

[1084] S32 is electrically connected to the eighteenth clock signal line CLK18, the twentieth clock signal line CLK20, the twenty-second clock signal line CLK22, and the twenty-fourth clock signal line CLK24, respectively.

[1085] S42 is electrically connected to the second clock signal line CLK2, the fourth clock signal line CLK4, the sixth clock signal line CLK6, and the eighth clock signal line CLK8, respectively.

[1086] The first drive output terminal of S12 is electrically connected to the second row of gate line G2, the second drive output terminal of S12 is electrically...

Claims

1. A driving circuit, comprising an input circuit, N output control circuits, and N driving output circuits; N is a positive integer; The input circuit is electrically connected to the input terminal and the first node, and is used to control the potential of the first node according to the input signal provided by the input terminal; The nth output control circuit is electrically connected to the control voltage terminal, the first node, and the nth output control node, respectively, and is used to control the connection or disconnection between the first node and the nth output control node under the control of the control voltage provided by the control voltage terminal; n is a positive integer less than or equal to N; The nth drive output circuit is electrically connected to the nth output control node, the nth drive output terminal, and the nth output clock signal terminal, respectively, and is used to provide the nth output clock signal provided by the nth output clock signal terminal to the nth drive output terminal under the control of the potential of the nth output control node.

2. The driving circuit as described in claim 1, wherein, Both the transistors in the input circuit and the transistors in the nth output control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the nth output control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal; or, The transistors included in the input circuit and the transistors included in the nth output control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the nth output control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the control voltage and the effective voltage value of the input signal.

3. The driving circuit as described in claim 1, wherein, It also includes N energy storage circuits; The first terminal of the nth energy storage circuit is electrically connected to the nth output control node, and the second terminal of the nth energy storage circuit is electrically connected to the nth drive output terminal.

4. The driving circuit as described in claim 1, wherein, It also includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal; The second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the first voltage terminal, respectively, and is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. The first node control circuit is electrically connected to the first second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node.

5. The driving circuit as described in claim 1, wherein, It also includes a second node control circuit and a first node control circuit; the control voltage terminal includes a first control voltage terminal and a second control voltage terminal. The second node control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the first node, the first second node, the second second node, and the first voltage terminal, respectively. It is used to control the potential of the first second node according to the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the first voltage terminal under the control of the potential of the first node. It is also used to control the potential of the second second node according to the second control voltage terminal, and to control the connection or disconnection between the second second node and the first voltage terminal under the control of the potential of the first node. The first node control circuit is electrically connected to the first second node, the second second node, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the second second node.

6. The driving circuit as described in claim 4 or 5, wherein, The driving circuit further includes a control circuit; the input circuit includes a first input circuit and a second input circuit; the control circuit is electrically connected to the first node, the power supply voltage terminal, and the control node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node; the first input circuit is electrically connected to the input terminal and the control node respectively, and is used to control the potential of the control node according to the input signal; The second input circuit is electrically connected to the input terminal, the control node, and the first node, respectively, and is used to control the connection or disconnection between the control node and the first node under the control of the input signal; or, The driving circuit further includes a control circuit. The input circuit includes a first input circuit and a second input circuit. The control circuit includes a first control circuit and a second control circuit. The first control circuit is electrically connected to a first node, a power supply voltage terminal, and a control node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the control node under the control of the potential of the first node. The second control circuit is electrically connected to the first node, the power supply voltage terminal, and an intermediate node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the intermediate node under the control of the potential of the first node. The first input circuit is electrically connected to the input terminal and the intermediate node, respectively, and is used to control the potential of the intermediate node according to the input signal. The second input circuit is electrically connected to the input terminal, the intermediate node, and the first node, respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the input signal.

7. The driving circuit as described in claim 6, wherein, The control voltage terminal includes a first control voltage terminal; the first node control circuit includes a first first node control circuit and a second first node control circuit. The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node. The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node.

8. The driving circuit as described in claim 6, wherein, The control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the first node control circuit includes a first first node control circuit, a second first node control circuit, a third first node control circuit and a fourth first node control circuit; The first node control circuit is electrically connected to the first second node, the first node, and the control node, respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the first second node. The second first node control circuit is electrically connected to the first second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the first second node; The third first node control circuit is electrically connected to the second second node, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the potential control of the second second node; The fourth first node control circuit is electrically connected to the second second node, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the potential of the second second node.

9. The driving circuit as described in claim 6, wherein, It also includes a first node reset circuit; the first node reset circuit includes a first first node reset circuit and a second first node reset circuit; The first node reset circuit is electrically connected to the reset control terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the reset control signal provided by the reset control terminal. The second first node reset circuit is electrically connected to the reset control terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the reset control signal.

10. The driving circuit as described in claim 6, wherein, It also includes a frame reset circuit; the frame reset circuit includes a first frame reset circuit and a second frame reset circuit. The first frame reset circuit is electrically connected to the frame reset terminal, the first node and the control node respectively, and is used to control the connection or disconnection between the first node and the control node under the control of the frame reset signal provided by the frame reset terminal. The second frame reset circuit is electrically connected to the frame reset terminal, the control node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the first voltage terminal under the control of the frame reset signal.

11. The driving circuit as described in claim 4, wherein, It also includes N output reset circuits; The nth output reset circuit is electrically connected to the first second node, the nth drive output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node.

12. The driving circuit as described in claim 5, wherein, It also includes N output reset circuits; The nth output reset circuit is electrically connected to the first second node, the second second node, the nth drive output terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the nth drive output terminal and the second voltage terminal under the control of the potential of the second second node.

13. The driving circuit as described in claim 4, wherein, It also includes a carry-out output circuit, a carry-out control circuit, and a carry-out energy storage circuit; The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, and to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node. The carry-out control circuit is electrically connected to the first control voltage terminal, the carry-out node, and the first node, respectively, and is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal. The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

14. The driving circuit as described in claim 13, wherein, Both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal; or, The transistors included in the input circuit and the transistors included in the carry-out control circuit are both p-type transistors. The difference between the threshold voltage of the transistor included in the carry-out control circuit and the threshold voltage of the transistor included in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal.

15. The driving circuit as described in claim 5, wherein, It also includes a carry-out output circuit, a carry-out control circuit, and a carry-out energy storage circuit; The carry output circuit is electrically connected to the carry output node, the carry clock signal terminal, the carry output terminal, the first second node, the second second node, and the first voltage terminal, respectively. It is used to provide the carry clock signal provided by the carry clock signal terminal to the carry output terminal under the control of the potential of the carry output node, to provide the first voltage signal provided by the first voltage terminal to the carry output terminal under the control of the potential of the first second node, and to provide the first voltage signal to the carry output terminal under the control of the potential of the second second node. The carry-out control circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the carry-out node, and the first node, respectively. It is used to control the connection or disconnection between the carry-out node and the first node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the carry-out node and the first node under the control of the second control voltage provided by the second control voltage terminal. The first end of the carry energy storage circuit is electrically connected to the carry output node, and the second end of the carry energy storage circuit is electrically connected to the carry output terminal.

16. The driving circuit as described in claim 15, wherein, Both the transistors in the input circuit and the transistors in the carry-out control circuit are n-type transistors. The difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the first control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the transistor in the carry-out control circuit whose gate is electrically connected to the second control voltage terminal and the threshold voltage of the transistor in the input circuit is greater than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal; or... Both the transistors in the input circuit and the transistors in the carry-out control circuit are p-type transistors. The difference between the threshold voltage of the transistor whose gate is electrically connected to the first control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the first control voltage and the effective voltage value of the input signal. The difference between the threshold voltage of the transistor whose gate is electrically connected to the second control voltage terminal in the carry-out control circuit and the threshold voltage of the transistor in the input circuit is less than the difference between the effective voltage value of the second control voltage and the effective voltage value of the input signal.

17. The driving circuit as claimed in claim 1, wherein, The input circuit includes an input transistor; the gate and the first terminal of the input transistor are electrically connected to the input terminal, and the second terminal of the input transistor is electrically connected to the first node; The control voltage terminal includes a first control voltage terminal; the nth output control circuit includes an nth first transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; or, the control voltage terminal includes a first control voltage terminal and a second control voltage terminal; the nth output control circuit includes an nth first transistor and an nth second transistor; the gate of the nth first transistor is electrically connected to the first control voltage terminal, the first electrode of the nth first transistor is electrically connected to the nth output control node, and the second electrode of the nth first transistor is electrically connected to the first node; The gate of the nth second transistor is electrically connected to the second control voltage terminal, the first terminal of the nth second transistor is electrically connected to the nth output control node, and the second terminal of the nth second transistor is electrically connected to the first node.

18. The driving circuit as claimed in claim 6, wherein, The control circuit includes a control transistor; the first input circuit includes a first input transistor; the second input circuit includes a second input transistor; the gate of the control transistor is electrically connected to the first node; the first terminal of the control transistor is electrically connected to the power supply voltage terminal; and the second terminal of the control transistor is electrically connected to the control node; the gate and the first terminal of the first input transistor are both electrically connected to the input terminal; the second terminal of the first input transistor is electrically connected to the control node; the gate of the second input transistor is electrically connected to the input terminal; the first terminal of the second input transistor is electrically connected to the control node; and the second terminal of the second input transistor is electrically connected to the first node; or... The first control circuit includes a first control transistor, and the second control circuit includes a second control transistor; the first input circuit includes a first input transistor, and the second input circuit includes a second input transistor; the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first control transistor is electrically connected to the control node; the gate of the second control transistor is electrically connected to the first node, the first terminal of the second control transistor is electrically connected to the power supply voltage terminal, and the second terminal of the second control transistor is electrically connected to the intermediate node; the gate of the first input transistor and the first terminal of the first input transistor are both electrically connected to the input terminal, and the second terminal of the first input transistor is electrically connected to the intermediate node; the gate of the second input transistor is electrically connected to the input terminal, the first terminal of the second input transistor is electrically connected to the intermediate node, and the second terminal of the second input transistor is electrically connected to the first node.

19. The driving circuit as claimed in claim 4, wherein, The second node control circuit includes a third transistor and a fourth transistor, and the first node control circuit includes a fifth transistor; The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node; The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal. The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal.

20. The driving circuit as described in claim 5, wherein, The second node control circuit includes a third transistor, a fourth transistor, a sixth transistor, and a seventh transistor; the first node control circuit includes a fifth transistor and an eighth transistor. The gate and the first terminal of the third transistor are electrically connected to the first control voltage terminal, and the second terminal of the third transistor is electrically connected to the first second node; The gate of the fourth transistor is electrically connected to the first node, the first terminal of the fourth transistor is electrically connected to the first second node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal. The gate and first terminal of the sixth transistor are electrically connected to the second control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second second node; The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal. The gate of the fifth transistor is electrically connected to the first second node, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the first voltage terminal. The gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

21. The driving circuit as claimed in claim 7, wherein, The first first node control circuit includes a first fifth transistor, and the second first node control circuit includes a second fifth transistor; The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node. The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal.

22. The driving circuit as described in claim 8, wherein, The first first node control circuit includes a first fifth transistor, the second first node control circuit includes a second fifth transistor; the third first node control circuit includes a first eighth transistor, and the fourth first node control circuit includes a second eighth transistor. The gate of the first fifth transistor is electrically connected to the first second node, the first terminal of the first fifth transistor is electrically connected to the first node, and the second terminal of the first fifth transistor is electrically connected to the control node. The gate of the second fifth transistor is electrically connected to the first second node, the first terminal of the second fifth transistor is electrically connected to the control node, and the second terminal of the second fifth transistor is electrically connected to the first voltage terminal. The gate of the first eighth transistor is electrically connected to the second second node, the first terminal of the first eighth transistor is electrically connected to the first node, and the second terminal of the first eighth transistor is electrically connected to the control node. The gate of the second eighth transistor is electrically connected to the second second node, the first terminal of the second eighth transistor is electrically connected to the control node, and the second terminal of the second eighth transistor is electrically connected to the first voltage terminal.

23. The driving circuit as described in claim 9, wherein, The first first node reset circuit includes a first ninth transistor, and the second first node reset circuit includes a second ninth transistor; The gate of the first ninth transistor is electrically connected to the reset control terminal, the first terminal of the first ninth transistor is electrically connected to the first node, and the second terminal of the first ninth transistor is electrically connected to the control node. The gate of the second ninth transistor is electrically connected to the reset control terminal, the first terminal of the second ninth transistor is electrically connected to the control node, and the second terminal of the second ninth transistor is electrically connected to the first voltage terminal.

24. The driving circuit as claimed in claim 10, wherein, The first frame reset circuit includes a first tenth transistor, and the second frame reset circuit includes a second tenth transistor; The gate of the first tenth transistor is electrically connected to the frame reset terminal, the first terminal of the first tenth transistor is electrically connected to the first node, and the second terminal of the first tenth transistor is electrically connected to the control node. The gate of the second tenth transistor is electrically connected to the frame reset terminal, the first terminal of the second tenth transistor is electrically connected to the control node, and the second terminal of the second tenth transistor is electrically connected to the first voltage terminal.

25. The driving circuit as claimed in claim 11, wherein, The nth output reset circuit includes an nth output reset transistor; The gate of the nth output reset transistor is electrically connected to the first second node, the first terminal of the nth output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth output reset transistor is electrically connected to the second voltage terminal.

26. The driving circuit as described in claim 12, wherein, The nth output reset circuit includes an nth first output reset transistor and an nth second output reset transistor; The gate of the nth first output reset transistor is electrically connected to the first second node, the first terminal of the nth first output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth first output reset transistor is electrically connected to the second voltage terminal. The gate of the nth second output reset transistor is electrically connected to the second second node, the first terminal of the nth second output reset transistor is electrically connected to the nth drive output terminal, and the second terminal of the nth second output reset transistor is electrically connected to the second voltage terminal.

27. The driving circuit as claimed in claim 13, wherein, The carry output circuit includes a carry output transistor and a first carry reset transistor; the carry output control circuit includes a first carry output control transistor; the carry energy storage circuit includes a carry capacitor; The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal. The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal. The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node. The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

28. The driving circuit as described in claim 15, wherein, The carry output circuit includes a carry output transistor, a first carry reset transistor, and a second carry reset transistor; the carry output control circuit includes a first carry output control transistor and a second carry output control transistor; the carry energy storage circuit includes a carry capacitor. The gate of the carry output transistor is electrically connected to the carry output node, the first terminal of the carry output transistor is electrically connected to the carry clock signal terminal, and the second terminal of the carry output transistor is electrically connected to the carry output terminal. The gate of the first carry-reset transistor is electrically connected to the first second node, the first terminal of the first carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the first carry-reset transistor is electrically connected to the first voltage terminal. The gate of the second carry-reset transistor is electrically connected to the second second node, the first terminal of the second carry-reset transistor is electrically connected to the carry output terminal, and the second terminal of the second carry-reset transistor is electrically connected to the first voltage terminal. The gate of the first carry-out control transistor is electrically connected to the first control voltage terminal, the first terminal of the first carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the first carry-out control transistor is electrically connected to the first node. The gate of the second carry-out control transistor is electrically connected to the second control voltage terminal, the first terminal of the second carry-out control transistor is electrically connected to the carry-out node, and the second terminal of the second carry-out control transistor is electrically connected to the first node. The first end of the carry capacitor is electrically connected to the carry output node, and the second end of the carry capacitor is electrically connected to the carry output terminal.

29. The driving circuit as described in claim 3, wherein, The nth drive output circuit includes an nth drive output transistor, and the nth energy storage circuit includes an nth output capacitor; The gate of the nth driving output transistor is electrically connected to the nth output control node, the first terminal of the nth driving output transistor is electrically connected to the nth output clock signal terminal, and the second terminal of the nth driving output transistor is electrically connected to the nth driving output terminal. The first terminal of the nth output capacitor is electrically connected to the nth output control node, and the second terminal of the nth output capacitor is electrically connected to the nth drive output terminal.

30. A drive module comprising multiple stages of drive circuits as described in any one of claims 1 to 29.

31. A display device comprising the driving module as described in claim 30.

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