Display panel and display device

Abstract

The present disclosure provides a display panel and a display device. Each driving circuit column in the display panel corresponds to two data lines, odd-numbered sub-pixel driving circuits in the driving circuit column are coupled to a first data line, and even-numbered sub-pixel driving circuits in the driving circuit column are coupled to a second data line; at least some data lines are divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups are alternately arranged, and each data line group comprises two adjacent data lines; the distance between two data lines in each first data line group is less than the distance between two data lines in each second data line group; and the two data lines in the same first data line group are both first data lines or second data lines.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510364878.1, filed in China on March 26, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0004] Currently, with reduced market demand for lower costs, there is a trend towards smaller and less functional driver ICs (Source ICs) in display devices. This has led to the introduction of Dual Data Line (DDL) designs in display device design to address the issue of insufficient data writing caused by the smaller Source ICs. However, due to limited layout space, designing too many data lines can cause crosstalk between closely spaced data lines, resulting in crosstalk-related display defects. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display panel and a display device.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] A first aspect of this disclosure provides a display panel, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a sub-pixel driving circuit, each sub-pixel driving circuit including a driving transistor, the plurality of sub-pixel driving circuits being divided into multiple columns of driving circuits; the display panel further comprising:

[0008] Multiple data lines, each column of driving circuits corresponds to two of the data lines, the odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to the first data line of the two data lines, and the even-numbered sub-pixel driving circuit in the driving circuit column is coupled to the second data line of the two data lines.

[0009] At least a portion of the data lines are divided into multiple first data line groups and multiple second data line groups, which are arranged alternately. Each data line group includes two adjacent data lines. Between the orthographic projection of the first data line group on the substrate and the orthographic projection of the adjacent second data line group on the substrate, there is an orthographic projection of the gate of the driving transistor in a column of driving circuits on the substrate. The distance between two data lines in the first data line group is smaller than the distance between two data lines in the second data line group.

[0010] In the same group of the first data lines, both data lines are either the first data line or both are the second data line.

[0011] Optionally, the multiple columns of driving circuits are divided into multiple groups of driving circuits, and each group of driving circuits includes two adjacent columns of driving circuits.

[0012] The gates of the two rows of driving transistors in the driving circuit group are alternately projected onto the substrate and the first data line group is alternately projected onto the substrate. The projection of the second data line group onto the substrate is located between the projections of the gates of the two rows of driving transistors in the corresponding driving circuit group onto the substrate.

[0013] In two adjacent sets of drive circuit groups, in the data lines coupled to one set of drive circuit groups, the first data line is located on the first side of the corresponding drive circuit column, and the second data line is located on the second side of the corresponding drive circuit column; in the data lines coupled to the other set of drive circuit groups, the first data line is located on the second side of the corresponding drive circuit column, and the second data line is located on the first side of the corresponding drive circuit column; the first side and the second side are opposite to each other along a first direction.

[0014] Optionally, the display panel further includes multiple gating units, each including a first gating subunit, a second gating subunit, a third gating subunit, and a fourth gating subunit; the display panel also includes a first gating control line, a second gating control line, a third gating control line, and a fourth gating control line.

[0015] The first gating subunit is coupled to the first gating control line, the corresponding data signal input terminal, and the first data line corresponding to the first column of the driving circuit in the corresponding driving circuit group, respectively, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line under the control of the first gating control line.

[0016] The second gating subunit is coupled to the second gating control line, the corresponding data signal input terminal, and the first data line corresponding to the second column of the driving circuit in the corresponding driving circuit group, respectively, and is used to control the electrical connection between the data signal input terminal and the first data line to be turned on or off under the control of the second gating control line.

[0017] The third gating subunit is coupled to the third gating control line, the corresponding data signal input terminal, and the second data line corresponding to the first column of the driving circuit in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line under the control of the third gating control line.

[0018] The fourth gating subunit is coupled to the fourth gating control line, the corresponding data signal input terminal, and the second data line corresponding to the second column of the driving circuit in the corresponding driving circuit group, and is used to control the electrical connection between the data signal input terminal and the second data line to be turned on or off under the control of the fourth gating control line.

[0019] Optionally, the sub-pixel driving circuit further includes a data writing transistor, a first reset transistor, a first conductive connection portion, and a second conductive connection portion;

[0020] The first terminal of the data writing transistor is coupled to the corresponding data line through the first conductive connection portion, and the second terminal of the data writing transistor is coupled to the first terminal of the driving transistor; the second terminal of the first reset transistor is coupled to the gate of the driving transistor through the second conductive connection portion.

[0021] In at least a portion of the sub-pixels, the orthographic projection of the second conductive connection portion on the substrate is located between the orthographic projection of the active layer of the data writing transistor on the substrate and the orthographic projection of the data line coupled to the data writing transistor on the substrate; in the at least a portion of the sub-pixels, the first conductive connection portion includes a first connection portion and a second connection portion coupled together, the extension direction of the first connection portion intersects the extension direction of the second connection portion, the first connection portion is coupled to the corresponding data line, and the second connection portion is coupled to the first pole of the data writing transistor.

[0022] Optionally, the display panel further includes a power line, wherein the orthographic projection of the first conductive connection portion on the substrate overlaps at least partially with the orthographic projection of the power line on the substrate.

[0023] Optionally, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels;

[0024] In the driving circuit group, the first column of driving circuits includes sub-pixel driving circuits for alternating red sub-pixels and sub-pixel driving circuits for alternating blue sub-pixels, and the second column of driving circuits includes sub-pixel driving circuits for a plurality of green sub-pixels arranged in sequence.

[0025] Optionally, in two adjacent sets of driving circuits, the first column of driving circuits in one set includes alternating sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels, and the first column of driving circuits in the other set includes alternating sub-pixel driving circuits for blue sub-pixels and sub-pixel driving circuits for red sub-pixels.

[0026] Optionally, the two data lines in the same group of second data lines include one first data line and one second data line.

[0027] Optionally, the display panel further includes multiple first signal lines, with one of the first signal lines located between two data lines in the second data line group.

[0028] Optionally, the display panel further includes multiple power lines, wherein the orthographic projection of the power line corresponding to the driving circuit column on the substrate is located between the orthographic projections of the two data lines corresponding to the driving circuit column on the substrate.

[0029] Optionally, the plurality of sub-pixels are divided into multiple rows of driving circuits, and in the same row of driving circuits, the sub-pixel driving circuits of two adjacent sub-pixels are mirror-symmetrical.

[0030] Optionally, the display panel includes a hole area, an isolation area, and a pixel area, wherein the isolation area is located between the hole area and the pixel area; the multiple data lines include multiple data lines that cross the hole area, and the multiple data lines that cross the hole area include multiple first-type data lines and multiple second-type data lines;

[0031] The first type of data line includes a first data portion, a first type of cross-region data portion, and a second data portion that are coupled in sequence. The first data portion and the second data portion are located on opposite sides of the aperture area. The first data portion, the first type of cross-region data portion, and the second data portion are all located in the pixel area.

[0032] The second type of data line includes a third data portion, a second type of cross-region data portion, and a fourth data portion that are coupled in sequence. The third data portion and the fourth data portion are located on opposite sides of the aperture area. Both the third data portion and the fourth data portion are located in the pixel area. The second type of cross-region data portion is located in the isolation area.

[0033] Optionally, the plurality of second-type data lines are divided into a first part of second-type data lines and a second part of second-type data lines, with the plurality of first-type data lines located between the first part of second-type data lines and the second part of second-type data lines.

[0034] Optionally, the first data portion of the first type of data line and the third data portion of the second type of data line are arranged alternately; the second data portion of the first type of data line and the fourth data portion of the second type of data line are arranged alternately.

[0035] Optionally, the first type of data line is coupled to the corresponding green sub-pixel, and the second type of data line is coupled to the corresponding red sub-pixel and / or blue sub-pixel.

[0036] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel. Attached Figure Description

[0037] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0038] Figure 1 is a circuit schematic diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0039] Figure 2 is a schematic diagram of the layout of the active layer in the sub-pixels of the array distribution provided in an embodiment of this disclosure;

[0040] Figure 3 is a schematic diagram of the layout of the active layer and the first gate metal layer in the sub-pixels of the array distribution provided in an embodiment of the present disclosure;

[0041] Figure 4 is a schematic diagram of the layout of the second gate metal layer in the sub-pixels of the array distribution provided in the embodiment of this disclosure;

[0042] Figure 5 is a schematic diagram of the layout with a second gate metal layer added based on Figure 3;

[0043] Figure 6 is a schematic diagram of the layout of interlayer insulating layer vias in sub-pixels distributed in an array according to an embodiment of this disclosure;

[0044] Figure 7 is a schematic diagram of the layout with added interlayer insulating layer vias based on Figure 5;

[0045] Figure 8 is a schematic diagram of the layout of the first source / drain metal layer in the sub-pixels of the array distribution provided in an embodiment of this disclosure;

[0046] Figure 9 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 7;

[0047] Figure 10 is a schematic diagram of the layout with added passivation layer vias based on Figure 9;

[0048] Figure 11 is a schematic diagram of the layout of planar layer vias in sub-pixels distributed in an array according to an embodiment of the present disclosure;

[0049] Figure 12 is a schematic diagram of the layout with added planarization layer vias based on Figure 10;

[0050] Figure 13 is a schematic diagram of the layout of the second source / drain metal layer in the sub-pixels of the array distribution provided in an embodiment of this disclosure;

[0051] Figure 14 is a schematic diagram of the layout with a second source / drain metal layer added based on Figure 12;

[0052] Figure 15 is a schematic diagram of the connection between the data line and the gating unit in the display panel provided in an embodiment of this disclosure;

[0053] Figure 16 is a timing diagram of the gating control line provided in an embodiment of this disclosure;

[0054] Figure 17 is a schematic diagram of the layout of the gating unit provided in an embodiment of this disclosure;

[0055] Figure 18 is a schematic diagram of the first layout near the hole area provided in an embodiment of this disclosure;

[0056] Figure 19 is a schematic diagram of the second layout near the hole area provided in an embodiment of this disclosure;

[0057] Figure 20 is a wiring diagram corresponding to Figure 18;

[0058] Figure 21 is a schematic diagram of the mirror layout of the sub-pixel driving circuit provided in an embodiment of this disclosure. Detailed Implementation

[0059] To further illustrate the display panel and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0060] Please refer to Figures 1 to 14. This disclosure provides a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a sub-pixel driving circuit, which includes a driving transistor. The plurality of sub-pixel driving circuits are divided into multiple columns of driving circuits. The display panel further includes:

[0061] Multiple data lines, each column of driving circuits corresponds to two data lines, the odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to the first data line DA1 of the two data lines, and the even-numbered sub-pixel driving circuit in the driving circuit column is coupled to the second data line DA2 of the two data lines.

[0062] At least a portion of the data lines are divided into multiple first data line groups Z11 and multiple second data line groups Z12, which are arranged alternately. Each data line group includes two adjacent data lines. Between the orthographic projection of the first data line group Z11 on the substrate and the orthographic projection of the adjacent second data line group Z12 on the substrate, there is an orthographic projection of the gate of the driving transistor included in a column of driving circuits on the substrate. The distance between two data lines in the first data line group Z11 is smaller than the distance between two data lines in the second data line group Z12.

[0063] In the same group of the first data lines Z11, both data lines are either the first data line DA1 or both are the second data line DA2.

[0064] For example, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of driving circuits and multiple columns of driving circuits. The multiple rows of driving circuits are arranged along a second direction, and each row of driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of driving circuits are arranged along the first direction, and each column of driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction intersects with the second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0065] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light.

[0066] For example, the specific structure of the sub-pixel driving circuit is varied, such as: 7T1C (including 7 transistors and 1 capacitor) circuit structure, 8T1C (including 8 transistors and 1 capacitor) circuit structure, etc., but not limited to these.

[0067] The following section uses the 7T1C circuit structure of the sub-pixel driving circuit as an example to explain in detail the connection relationship of the sub-pixel driving circuit in the nth row of driving circuits.

[0068] The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emission control transistor T6, and a storage capacitor Cst.

[0069] The gate of the first reset transistor T1 is coupled to the corresponding first scan line GA1, the first terminal of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second terminal of the first reset transistor T1 is coupled to the gate T3-g (i.e., the first node N1) of the driving transistor T3.

[0070] The gate of the compensation transistor T2 is coupled to the corresponding second scan line GA2, the first terminal of the compensation transistor T2 is coupled to the second terminal (i.e. the third node N3) of the driving transistor T3, and the second terminal of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0071] The gate of the data writing transistor T4 is coupled to the corresponding second scan line GA2, the first terminal of the data writing transistor T4 is coupled to the corresponding data line DA, and the second terminal of the data writing transistor T4 is coupled to the first terminal (i.e., the second node N2) of the driving transistor T3.

[0072] The gate of the power control transistor T5 is coupled to the corresponding light-emitting control signal line EM, the first terminal of the power control transistor T5 is coupled to the corresponding power supply line VDD, and the second terminal of the power control transistor T5 is coupled to the first terminal of the driving transistor T3.

[0073] The gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM. The first terminal of the light-emitting control transistor T6 is coupled to the second terminal of the driving transistor T3. The second terminal of the light-emitting control transistor T6 is coupled to the anode of the corresponding light-emitting element (i.e., the fourth node N4). The cathode of the light-emitting element receives the negative power supply signal VSS.

[0074] The gate of the second reset transistor T7 is coupled to the first scan line GA1' corresponding to the next row of the driving circuit. The first terminal of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2. The second terminal of the second reset transistor T7 is coupled to the anode of the corresponding light-emitting element.

[0075] The first plate Cst1 of the storage capacitor Cst is reused as the gate of the driving transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD.

[0076] For example, the display panel further includes a plurality of data lines arranged along the first direction, each data line including at least a portion extending along the second direction. Each column of driving circuits corresponds to two of the data lines, and the orthographic projection of the gate of the driving transistor included in the driving circuit column on the substrate is located between the orthographic projections of the corresponding two data lines on the substrate.

[0077] For example, the plurality of data lines includes a start data line, an end data line, and a plurality of intermediate data lines located between the start data line and the end data line; the plurality of intermediate data lines are divided into a plurality of first data line groups Z11 and a plurality of second data line groups Z12, the first data line groups Z11 and the second data line groups Z12 being arranged alternately along the first direction. Each of the first data line groups Z11 and the second data line groups Z12 includes two adjacent data lines.

[0078] For example, the minimum distance between two data lines in the first data line group Z11 is less than the minimum distance between two data lines in the second data line group Z12. The minimum distance between adjacent first data line groups Z11 and second data line groups Z12 is greater than the minimum distance between two data lines in the second data line group Z12.

[0079] For example, both data lines in the same group of first data lines Z11 are the first data line DA1, that is, both data lines in the same group of first data lines Z11 are coupled to the odd-numbered sub-pixel; or, both data lines in the same group of first data lines Z11 are the second data line DA2, that is, both data lines in the same group of first data lines Z11 are coupled to the even-numbered sub-pixel.

[0080] As can be seen from the specific structure of the display panel described above, in the display panel provided in this embodiment, each column of driving circuits is configured with two data lines. The odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to the first data line DA1 of the two data lines, and the even-numbered sub-pixel driving circuit in the driving circuit column is coupled to the second data line DA2 of the two data lines. This configuration allows the odd-numbered and even-numbered sub-pixel driving circuits in a column of driving circuits to be provided with data signals by different data lines, which prolongs the time for the data lines to write data signals to the corresponding sub-pixel driving circuits, ensuring that each sub-pixel driving circuit can be fully written with data signals, and avoiding display defects caused by insufficient data signal writing.

[0081] In the display panel provided in this embodiment, the distance between two data lines in the first data line group Z11 is set to be less than the distance between two data lines in the second data line group Z12. Both data lines in the same first data line group Z11 are either the first data line DA1 or both are the second data line DA2. This allows two data lines that are closer together in the first data line group Z11 to write data signals to the sub-pixel driving circuit located in the same odd-numbered row, or to write data signals to the sub-pixels located in the same even-numbered row, when scanning an odd-numbered row or an even-numbered row of sub-pixels in the display panel. In this way, the two data lines that are close to each other in the first data line group Z11 can be controlled by the gating sub-unit, and the time for writing data signals is close. That is, the two data lines can write data signals to the sub-pixel driving circuit at the same time, thereby shortening the time difference for writing data signals between the two data lines that are close to each other in the first data line group Z11. This reduces the risk that one data line has completed the data writing work and is in a floating state, while being interfered with by the other data line. Therefore, the display panel provided by the embodiments of this disclosure effectively reduces the crosstalk problem between closely spaced data lines and improves the crosstalk-related display problems caused by crosstalk between data lines.

[0082] As shown in Figures 2 to 14, in some embodiments, the multiple columns of driving circuits are divided into multiple groups of driving circuits Z2, and each group of driving circuits Z2 includes two adjacent columns of driving circuits.

[0083] The gates of the two columns of driving transistors in the driving circuit group Z2 are alternately projected onto the substrate and the first data line group Z11 is alternately projected onto the substrate. The projection of the second data line group Z12 onto the substrate is located between the projections of the gates of the two columns of driving transistors in the corresponding driving circuit group Z2 onto the substrate.

[0084] In two adjacent sets of drive circuit groups Z2, in the data lines coupled to one set of drive circuit groups Z2, the first data line DA1 is located on the first side of the corresponding drive circuit column, and the second data line DA2 is located on the second side of the corresponding drive circuit column; in the data lines coupled to the other set of drive circuit groups Z2, the first data line DA1 is located on the second side of the corresponding drive circuit column, and the second data line DA2 is located on the first side of the corresponding drive circuit column; the first side and the second side are opposite to each other along a first direction.

[0085] For example, the multiple drive circuit columns are divided into multiple drive circuit groups Z2, which are arranged along the first direction. Two drive circuit columns within each drive circuit group Z2 include two columns of drive transistors.

[0086] The above configuration method can ensure that both data lines in the same group of the first data lines are either the first data line DA1 or the second data line DA2.

[0087] As shown in Figures 13 to 17, in some embodiments, the display panel further includes multiple gating units, each gating unit including a first gating subunit (including a first gating transistor T8), a second gating subunit (including a second gating transistor T9), a third gating subunit (including a third gating transistor T10), and a fourth gating subunit (including a fourth gating transistor T11); the display panel also includes a first gating control line MUX1, a second gating control line MUX2, a third gating control line MUX3, and a fourth gating control line MUX4;

[0088] The first gating subunit is coupled to the first gating control line MUX1, the corresponding data signal input terminal (e.g., A1, A2, A3, A4), and the first data line DA1 corresponding to the first column of the driving circuit in the corresponding driving circuit group Z2, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal A1 and the first data line DA1 under the control of the first gating control line MUX1.

[0089] The second gating subunit is coupled to the second gating control line MUX2, the corresponding data signal input terminal, and the first data line DA1 corresponding to the second column of the driving circuit in the corresponding driving circuit group Z2, respectively, and is used to control the electrical connection between the data signal input terminal and the first data line DA1 to be turned on or off under the control of the second gating control line MUX2.

[0090] The third gating subunit is coupled to the third gating control line MUX3, the corresponding data signal input terminal, and the second data line DA2 corresponding to the first column of the driving circuit in the corresponding driving circuit group Z2, respectively, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line DA2 under the control of the third gating control line MUX3.

[0091] The fourth gating subunit is coupled to the fourth gating control line MUX4, the corresponding data signal input terminal, and the second data line DA2 corresponding to the second column of the driving circuit in the corresponding driving circuit group Z2, and is used to control the electrical connection between the data signal input terminal and the second data line DA2 to be turned on or off under the control of the fourth gating control line MUX4.

[0092] For example, the first gating subunit includes a first gating transistor T8, the gate of the first gating transistor T8 is coupled to the first gating control line MUX1, the first terminal of the first gating transistor T8 is coupled to the corresponding data signal input terminal, and the second terminal of the first gating transistor T8 is coupled to the first data line DA1 corresponding to the first column of the driving circuit in the corresponding driving circuit group Z2.

[0093] For example, the second gating subunit includes a second gating transistor T9, the gate of the second gating transistor T9 is coupled to the second gating control line MUX2, the first terminal of the second gating transistor T9 is coupled to the corresponding data signal input terminal, and the second terminal of the second gating transistor T9 is coupled to the first data line DA1 corresponding to the second column of the driving circuit in the corresponding driving circuit group Z2.

[0094] For example, the third gating subunit includes a third gating transistor T10, the gate of the third gating transistor T10 is coupled to the third gating control line MUX3, the first terminal of the third gating transistor T10 is coupled to the corresponding data signal input terminal, and the second terminal of the third gating transistor T10 is coupled to the second data line DA2 corresponding to the first column of the driving circuit in the corresponding driving circuit group Z2.

[0095] For example, the fourth gating sub-unit includes a fourth gating transistor T11, the gate of the fourth gating transistor T11 is coupled to the fourth gating control line MUX4, the first terminal of the fourth gating transistor T11 is coupled to the corresponding data signal input terminal, and the second terminal of the fourth gating transistor T11 is coupled to the second data line DA2 corresponding to the second column of the driving circuit in the corresponding driving circuit group Z2.

[0096] For example, the first gating transistor T8, the second gating transistor T9, the third gating transistor T10, and the fourth gating transistor T11 are all P-type transistors, but are not limited to this.

[0097] More specifically, the above embodiment is based on MUX1:4 (i.e., one data signal input terminal corresponds to four data lines), specifically column MUX1:2 (i.e., one column of driving circuit corresponds to two data lines) + row MUX1:2 (i.e., odd-numbered rows of driving circuit correspond to the first data line, and even-numbered rows of driving circuit correspond to the second data line), combined with odd and even row driving of shift register units. This can improve the sub-pixel threshold voltage compensation time and enhance display uniformity. However, since MUX1:4 doubles the number of data lines that need to be set, the spatial arrangement will inevitably result in a decrease in the distance between adjacent data lines, meaning that the parasitic capacitance between adjacent data lines will increase. At the same time, crosstalk between data lines will increase, easily leading to crosstalk-related display defects.

[0098] Figure 15 illustrates the MUX1:4 timing diagram corresponding to the DDL scheme. The first gating signal transmitted by the first gating control line MUX1, the second gating signal transmitted by the second gating control line MUX2, the third gating signal transmitted by the third gating control line MUX3, and the fourth gating signal transmitted by the fourth gating control line MUX4 are sequentially at an active level (e.g., low level). When the gating signal is at an active level, the corresponding gating transistor is turned on, and the data signal provided by the data signal input terminal is written to the corresponding data line.

[0099] The time period outlined by the dashed box in Figure 15 corresponds to the low potential of the scan signal GateP[2n-1]. At this time, the data writing transistor T4 in the 2n-1 row sub-pixels is turned on. The data lines controlled by the first gating control line MUX1 and the second gating control line MUX2 write data signals to the gate of the driving transistor T3 through the data writing transistor T4 and the compensation transistor T2 (the data signals on this data line are either pre-stored or written during the current time period). That is, the data lines controlled by the first gating control line MUX1 and the second gating control line MUX2 write data signals to the N1 node. During this time period, the data lines corresponding to the 2n row sub-pixels are controlled by the third gating control line MUX3 and the fourth gating control line MUX4 to write data signals to the data lines and store them in the data lines. When the scan signal GateP[2n] is at a low level, the corresponding sub-pixel driving circuit is written. If the parasitic capacitance between the data lines controlled by the third gate control line MUX3 and the fourth gate control line MUX4 and the data lines controlled by the first gate control line MUX1 and the second gate control line MUX2 is large, the data lines controlled by the third gate control line MUX3 and the fourth gate control line MUX4 will directly pull the data voltage of the data lines controlled by the first gate control line MUX1 and the second gate control line MUX2 when the data voltage jumps. Since the scan signal GateP[2n-1] is at a low potential at this time, the pulled data voltage will be directly written into the corresponding sub-pixel driving circuit, causing the sub-pixel driving circuit to have abnormal signal writing, which is manifested as poor crosstalk.

[0100] In the display panel provided in the above embodiment, a DDL combined with MUX1:4 driving design is adopted. Two data lines with large parasitic capacitance in the same first data line group are adjusted to data lines corresponding to the same row of sub-pixels through MUX transformation. This ensures that the two data lines that are close to each other in the entire display panel will only be the second data line DA2 controlled by MUX3 and MUX4, or the first data line DA1 controlled by MUX1 and MUX2. This greatly reduces the crosstalk problem between data lines in the same first data line group.

[0101] As shown in Figures 2 to 14, in some embodiments, the sub-pixel driving circuit further includes a data writing transistor T4, a first reset transistor T1, a first conductive connection portion 31, and a second conductive connection portion 32.

[0102] In at least some sub-pixels, the first terminal of the data writing transistor T4 is coupled to the corresponding data line through the first conductive connection portion 31, and the second terminal of the data writing transistor T4 is coupled to the first terminal of the driving transistor T3; the second terminal of the first reset transistor T1 is coupled to the gate of the driving transistor through the second conductive connection portion 32.

[0103] In at least a portion of the sub-pixels, the orthographic projection of the second conductive connection portion 32 on the substrate is located between the orthographic projection of the active layer of the data writing transistor T4 on the substrate and the orthographic projection of the data line coupled to the data writing transistor T4 on the substrate; in the at least a portion of the sub-pixels, the first conductive connection portion 31 includes a first connection portion 311 and a second connection portion 312 coupled together, the extension direction of the first connection portion 311 intersects the extension direction of the second connection portion 312, the first connection portion 311 is coupled to the corresponding data line, and the second connection portion 312 is coupled to the first pole of the data writing transistor T4.

[0104] For example, the first conductive connection portion 31 and the second conductive connection portion 32 are disposed in the same layer and made of the same material, but are not limited thereto.

[0105] For example, in at least some sub-pixels, the data writing transistor T4 included in the sub-pixel is located on one side of the sub-pixel driving circuit included in the sub-pixel, and the data line coupled to the data writing transistor T4 included in the sub-pixel is located on the other side of the sub-pixel driving circuit, that is, the data writing transistor T4 included in the sub-pixel and the data line coupled to the data writing transistor T4 are located on opposite sides of the sub-pixel driving circuit.

[0106] For example, the first conductive connection portion 31 includes a first connection portion 311 and a second connection portion 312 coupled together, and the first connection portion 311 and the second connection portion 312 are formed as an integral structure.

[0107] The above configuration allows for the connection between the data writing transistors T4, which are far apart, and the data lines coupled to them, in at least some of the sub-pixels, through the first conductive connection portion 31.

[0108] As shown in Figures 8, 13 and 14, in some embodiments, the display panel further includes a power line VDD, and the orthographic projection of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the power line VDD on the substrate.

[0109] The above configuration enables the power line VDD to shield the signal transmitted by the first conductive connection 31 from interference from surrounding signals, thus ensuring the stability of the signal transmitted by the first conductive connection 31.

[0110] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; in the driving circuit group Z2, the first column of driving circuits includes sub-pixel driving circuits for alternating red sub-pixels and sub-pixel driving circuits for alternating blue sub-pixels, and the second column of driving circuits includes sub-pixel driving circuits for a plurality of green sub-pixels arranged in sequence.

[0111] For example, the first column of driving circuits includes sub-pixel driving circuits for red sub-pixels and blue sub-pixels arranged alternately along the second direction, and the second column of driving circuits includes sub-pixel driving circuits for a plurality of green sub-pixels arranged sequentially along the second direction.

[0112] For example, in two adjacent sets of driving circuit groups Z2, the first column of driving circuits in one set of driving circuit groups Z2 includes alternating sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels, and the first column of driving circuits in the other set of driving circuit groups Z2 includes alternating sub-pixel driving circuits for blue sub-pixels and sub-pixel driving circuits for red sub-pixels.

[0113] By arranging subpixels in the above manner, each data line can be coupled to a subpixel of only one color. This means that the range of data signal transitions on each data line is small. Thus, even if one data line in the first data line group Z11 experiences a data signal transition, the crosstalk to the other data line is also small. Similarly, if one data line in the second data line group Z12 experiences a data signal transition, the crosstalk to the other data line is also small.

[0114] As shown in Figure 13, in some embodiments, the display panel further includes multiple power lines VDD, and the orthographic projection of the power line VDD corresponding to the driving circuit column on the substrate is located between the orthographic projections of the two data lines corresponding to the driving circuit column on the substrate.

[0115] For example, the power line VDD is used to transmit a power signal with a stable potential.

[0116] For example, the orthographic projection of the power line VDD corresponding to the drive circuit column on the substrate is located between the orthographic projection of the first data line DA1 and the second data line DA2 corresponding to the drive circuit column on the substrate.

[0117] For example, the power line VDD corresponding to the driving circuit column is located between the red data line used to transmit the data signal corresponding to the red sub-pixel and the blue data line used to transmit the data signal corresponding to the blue sub-pixel; or, the power line VDD corresponding to the driving circuit column is located between the green data line used to transmit the data signal corresponding to the green sub-pixel and the green data line used to transmit the data signal corresponding to the green sub-pixel.

[0118] The above configuration allows the power line VDD to effectively shield the crosstalk between the two data lines corresponding to the drive circuit column.

[0119] In some embodiments, the display panel further includes a shielding line, the orthographic projection of which is located between the orthographic projections of the two data lines in the first data line group onto the substrate.

[0120] For example, the shielded wire is used to transmit an initialization signal, that is, the shielded wire is multiplexed as an initialization signal line; or, the shielded wire is used to transmit a power signal, that is, the shielded wire is multiplexed as a power line VDD.

[0121] It should be noted that the shielding line can be set when the product PPI is relatively small, that is, the pixel size is relatively large and there is sufficient layout space.

[0122] The above configuration enables the shielding cable to effectively shield crosstalk between the two data lines in the first data line group.

[0123] As shown in Figure 13, in some embodiments, the two data lines in the same group of second data lines Z12 include a first data line DA1 and a second data line DA2.

[0124] For example, the display panel also includes a plurality of first signal lines 40, with one of the first signal lines 40 between two data lines in the second data line group Z12.

[0125] For example, the first signal line 40 includes FIP leads, but is not limited to this. It should be noted that, in order to meet the requirement of narrowing the bottom bezel of the display panel, the display panel can be configured to adopt an FIP design, that is, the data lines of the left and right bezels of the display panel are connected to the FIP leads, and the leads extend to the middle area of ​​the display panel, and then extend from the middle area to the bottom bezel area, thereby narrowing the width of the bottom bezel of the display panel.

[0126] For example, the first signal line 40 may include a power line VDD or an initialization signal line, but is not limited to this.

[0127] The above configuration includes a first signal line 40 between the two data lines in the second data line group Z12, so that the first signal line 40 can effectively shield the crosstalk between the two data lines in the second data line group Z12.

[0128] As shown in Figure 21, in some embodiments, the plurality of sub-pixels are divided into multiple rows of driving circuits, and in the same row of driving circuits, the sub-pixel driving circuits of two adjacent sub-pixels are mirror-symmetrical.

[0129] It should be noted that the F shown in Figure 21 represents a sub-pixel driving circuit, and does not mean that the sub-pixel driving circuits are laid out in an F shape. It can be seen that in the same row of driving circuits, the sub-pixel driving circuits of two adjacent sub-pixels are mirror symmetrical. In the same column of driving circuits, the layout of each sub-pixel driving circuit is the same and no mirroring is performed.

[0130] For example, in the same row of driving circuits, the adjacent odd-numbered sub-pixel driving circuits and even-numbered sub-pixel driving circuits are mirror-symmetrical.

[0131] For example, the sub-pixel driving circuits of two adjacent sub-pixels are mirror-symmetric, and the axis of symmetry of the mirror symmetry is located between the sub-pixel driving circuits of the two adjacent sub-pixels and extends along the second direction.

[0132] The above configuration helps the display panel achieve a higher PPI, while the FIP horizontal and vertical routing layout is better, the symmetry is better, and the anode layer in the display panel has better flatness.

[0133] As shown in Figures 18 to 20, in some embodiments, the display panel is configured to include a hole area 50, an isolation area 51, and a pixel area 52, wherein the isolation area 51 is located between the hole area 50 and the pixel area 52; the multiple data lines include multiple data lines that cross the hole area, and the multiple data lines that cross the hole area include multiple first-type data lines and multiple second-type data lines;

[0134] The first type of data line includes a first data portion 61, a first type of cross-area data portion 62, and a second data portion 63 coupled in sequence. The first data portion 61 and the second data portion 63 are located on opposite sides of the aperture area 50. The first data portion 61, the first type of cross-area data portion 62, and the second data portion 63 are all located in the pixel area 52.

[0135] The second type of data line includes a third data portion 71, a second type of cross-area data portion 72 and a fourth data portion 73 coupled in sequence. The third data portion 71 and the fourth data portion 73 are located on opposite sides of the aperture area 50. The third data portion 71 and the fourth data portion 73 are both located in the pixel area 52. The second type of cross-area data portion 72 is located in the isolation area 51.

[0136] For example, the display panel includes an aperture area 50, an isolation area 51, and a pixel area 52. The isolation area 51 is located between the aperture area 50 and the pixel area 52, the isolation area 51 surrounds the aperture area 50, and the pixel area 52 surrounds the isolation area 51.

[0137] For example, the multiple data lines include multiple data lines that cross the hole area. The data lines that cross the hole area mean that if the data line is extended along the second direction, the data line will pass through the hole area 50. However, in the actual layout, the data line will bypass the hole area 50, that is, it will not pass through the hole area 50.

[0138] For example, the first type of data line includes a first data portion 61, a first type cross-area data portion 62 and a second data portion 63 coupled in sequence, the first data portion 61 and the second data portion 63 being located on opposite sides of the aperture area 50 along a second direction.

[0139] For example, both the first data portion 61 and the second data portion 63 extend along a second direction, and the first type of cross-region data portion 62 includes a portion extending along a first direction and a portion extending along a second direction. When the first type of data line adopts the above structure, it is formed as a HIP winding method.

[0140] For example, the second type of data line includes a third data portion 71, a second type cross-area data portion 72 and a fourth data portion 73 coupled in sequence, wherein the third data portion 71 and the fourth data portion 73 are located on opposite sides of the aperture area 50 along the second direction.

[0141] For example, both the third data portion 71 and the fourth data portion 73 extend along the second direction, and the second type of cross-area data portion 72 extends along the edge of the hole area 50. When the first type of data line adopts the above structure, it is formed as a Fanout winding method.

[0142] For example, as shown in Figures 18 and 20, the plurality of second-type data lines are divided into a first part of second-type data lines and a second part of second-type data lines, and the plurality of first-type data lines (located in region B1) are located between the first part of second-type data lines (located in region B2) and the second part of second-type data lines (located in region B3).

[0143] For example, as shown in Figure 19, the first data portion 61 (located in region C1) of the first type of data line and the third data portion 71 (located in region C2) of the second type of data line are arranged alternately; the second data portion 63 (located in region C3) of the first type of data line and the fourth data portion 73 (located in region C4) of the second type of data line are arranged alternately. For example, the first type of data line is coupled to the corresponding green sub-pixel, and the second type of data line is coupled to the corresponding red sub-pixel and / or blue sub-pixel.

[0144] It is worth noting that by adopting a design where each column of driving circuits corresponds to two data lines (i.e., DDL design), the number of data lines in the display panel will be doubled. This will also double the number of data lines that need to be wound in the hole area 50. If only the Fanout winding method is used, the doubling of the number of windings in the hole area 50 will increase the wiring space in the isolation area 51, which will directly lead to an increase in the bezel of the hole area 50.

[0145] The above-described configuration combines HIP (Hardware Injection) and Fanout (Fanout) wiring methods, which can significantly narrow the bezel width of the hole area 50 under the DDL (Device Detailing) design. More specifically, the display panel provided in this embodiment can reduce 152 Fanout wirings, thereby reducing the bezel width of the hole area 50 by approximately 190 micrometers.

[0146] It should be noted that, as shown in Figure 2, the driving transistor T3 includes a third active layer 23, the first reset transistor T1 includes a first active layer 21, the second reset transistor T7 includes a seventh active layer 27, the compensation transistor T2 includes a second active layer 22, the data writing transistor T4 includes a fourth active layer 24, the power control transistor T5 includes a fifth active layer 25, and the light-emitting control transistor T6 includes a sixth active layer 26.

[0147] As shown in Figures 3 to 14, the first conductive connection part 31 is coupled to the first pole of the data writing transistor T4 through the sixth via Via6, and the first conductive connection part 31 is coupled to the corresponding data line through the twelfth via Via12 and the seventeenth via Via17.

[0148] The second conductive connection portion 32 is coupled to the second terminal of the compensation transistor T2 and the second terminal of the first reset transistor T1 through the fifth via Via5, and the second conductive connection portion 32 is coupled to the gate T3-g of the driving transistor T3 through the seventh via Via7.

[0149] The third conductive connection part 33 is coupled to the first initialization signal line Vinit1 through the first via Via1, and the third conductive connection part 33 is coupled to the first pole of the first reset transistor T1 through the second via Via2.

[0150] The fourth conductive connection part 34 is coupled to the first terminal of the data writing transistor T4 through via Via0, and the fourth conductive connection part 34 is coupled to the corresponding data line through the thirteenth via Via13 and the twentieth via Via20.

[0151] The fifth conductive connection portion 35 is coupled to the first pole of the second reset transistor T7 through the third via Via3, and is coupled to the second initialization signal line Vinit2 through the fourth via Via4.

[0152] The sixth conductive connection portion 36 is coupled to the second electrode of the light-emitting control transistor T6 and the second electrode of the second reset transistor T7 through the ninth via Via9, and is coupled to the ninth conductive connection portion 39 through the fifteenth via Via15 and the nineteenth via Via19. The ninth conductive connection portion 39 is coupled to the corresponding anode layer.

[0153] The power compensation line 38 is coupled to the second plate Cst2 of the storage capacitor Cst through the eighth via Via8 and the eleventh via Via11, coupled to the first terminal of the power control transistor T5 through the tenth via Via10, and coupled to the power line VDD through the fourteenth via Via14 and the eighteenth via Via18.

[0154] FIP lateral lead 37 is coupled to the corresponding longitudinal FIP lead through the sixteenth via Via 16.

[0155] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0156] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0157] In the display panel provided in the above embodiment, each column of driving circuits is configured with two data lines. The odd-numbered sub-pixel driving circuit in the column of driving circuits is coupled to the first data line DA1 of the two data lines, and the even-numbered sub-pixel driving circuit in the column of driving circuits is coupled to the second data line DA2 of the two data lines. This configuration allows the odd-numbered and even-numbered sub-pixel driving circuits in a column of driving circuits to have their data signals provided by different data lines. This extends the time for the data lines to write data signals to the corresponding sub-pixel driving circuits, ensuring that each sub-pixel driving circuit can be fully written with data signals, and avoiding display defects caused by insufficient data signal writing.

[0158] In the display panel provided in the above embodiment, the distance between two data lines in the first data line group Z11 is set to be less than the distance between two data lines in the second data line group Z12. Both data lines in the same first data line group Z11 are either the first data line DA1 or the second data line DA2. This allows two data lines that are closer together in the first data line group Z11 to write data signals to the sub-pixel driving circuit located in the same odd-numbered row or to the sub-pixel located in the same even-numbered row when scanning a row of odd-numbered sub-pixels in the display panel. In this way, the two data lines that are close to each other in the first data line group Z11 can be controlled by the gating sub-unit, and the time for writing data signals is close. That is, the two data lines can write data signals to the sub-pixel driving circuit at the same time, thereby shortening the time difference for writing data signals between the two data lines that are close to each other in the first data line group Z11. This reduces the risk that one data line has completed the data writing work and is in a floating state, while being interfered with by the other data line. Therefore, the display panel provided by the above embodiment effectively reduces the crosstalk problem between closely spaced data lines and improves the crosstalk-related display problems caused by crosstalk between data lines.

[0159] The display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0160] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment or strip shape. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0161] It should be noted that the layout area of ​​a column unit is the layout area occupied by all sub-pixel driving circuits in that column unit. The layout area occupied by each sub-pixel driving circuit can be a region capable of accommodating that sub-pixel driving circuit. For example, this region can be a rectangular region, but it is not limited to this.

[0162] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0163] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0164] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0165] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupling,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “above,” “below,” “left,” and “right” are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described object changes. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be located “directly” above or below the other element, or there may be intermediate elements present. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a sub-pixel driving circuit, each sub-pixel driving circuit including a driving transistor, the plurality of sub-pixels including the plurality of sub-pixel driving circuits being divided into multiple columns of driving circuits; The display panel also includes: Multiple data lines, each column of driving circuits corresponds to two of the data lines, the odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to the first data line of the two data lines, and the even-numbered sub-pixel driving circuit in the driving circuit column is coupled to the second data line of the two data lines. At least a portion of the data lines are divided into multiple first data line groups and multiple second data line groups, which are arranged alternately. Each data line group includes two adjacent data lines. Between the orthographic projection of the first data line group on the substrate and the orthographic projection of the adjacent second data line group on the substrate, there is an orthographic projection of the gate of the driving transistor in a column of driving circuits on the substrate. The distance between two data lines in the first data line group is smaller than the distance between two data lines in the second data line group. In the same group of the first data lines, both data lines are either the first data line or both are the second data line.

2. The display panel according to claim 1, wherein, The multi-column drive circuit column is divided into multiple groups of drive circuit groups, and each group of drive circuit groups includes two adjacent drive circuit columns. The gates of the two rows of driving transistors in the driving circuit group are alternately projected onto the substrate and the first data line group is alternately projected onto the substrate. The projection of the second data line group onto the substrate is located between the projections of the gates of the two rows of driving transistors in the corresponding driving circuit group onto the substrate. In two adjacent sets of drive circuit groups, in the data lines coupled to one set of drive circuit groups, the first data line is located on the first side of the corresponding drive circuit column, and the second data line is located on the second side of the corresponding drive circuit column; in the data lines coupled to the other set of drive circuit groups, the first data line is located on the second side of the corresponding drive circuit column, and the second data line is located on the first side of the corresponding drive circuit column; the first side and the second side are opposite to each other along a first direction.

3. The display panel according to claim 2, wherein, The display panel further includes multiple gating units, each including a first gating subunit, a second gating subunit, a third gating subunit, and a fourth gating subunit; the display panel also includes a first gating control line, a second gating control line, a third gating control line, and a fourth gating control line. The first gating subunit is coupled to the first gating control line, the corresponding data signal input terminal, and the first data line corresponding to the first column of the driving circuit in the corresponding driving circuit group, respectively, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line under the control of the first gating control line. The second gating subunit is coupled to the second gating control line, the corresponding data signal input terminal, and the first data line corresponding to the second column of the driving circuit in the corresponding driving circuit group, respectively, and is used to control the electrical connection between the data signal input terminal and the first data line to be turned on or off under the control of the second gating control line. The third gating subunit is coupled to the third gating control line, the corresponding data signal input terminal, and the second data line corresponding to the first column of the driving circuit in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line under the control of the third gating control line. The fourth gating subunit is coupled to the fourth gating control line, the corresponding data signal input terminal, and the second data line corresponding to the second column of the driving circuit in the corresponding driving circuit group, and is used to control the electrical connection between the data signal input terminal and the second data line to be turned on or off under the control of the fourth gating control line.

4. The display panel according to claim 2, wherein, The sub-pixel driving circuit further includes a data writing transistor, a first reset transistor, a first conductive connection portion, and a second conductive connection portion; In at least some sub-pixels, the first terminal of the data writing transistor is coupled to the corresponding data line through a first conductive connection, and the second terminal of the data writing transistor is coupled to the first terminal of the driving transistor; the second terminal of the first reset transistor is coupled to the gate of the driving transistor through the second conductive connection. In at least some sub-pixels, the orthographic projection of the second conductive connection portion on the substrate is located between the orthographic projection of the active layer of the data writing transistor on the substrate and the orthographic projection of the data line coupled to the data writing transistor on the substrate. In at least a portion of the sub-pixels, the first conductive connection includes a first connection portion and a second connection portion coupled together, the extension direction of the first connection portion intersects the extension direction of the second connection portion, the first connection portion is coupled to the corresponding data line, and the second connection portion is coupled to the first pole of the data writing transistor.

5. The display panel according to claim 4, wherein, The display panel also includes a power line, and the orthographic projection of the first conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate.

6. The display panel according to claim 2, wherein, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; In the driving circuit group, the first column of driving circuits includes sub-pixel driving circuits for alternating red sub-pixels and sub-pixel driving circuits for alternating blue sub-pixels, and the second column of driving circuits includes sub-pixel driving circuits for a plurality of green sub-pixels arranged in sequence.

7. The display panel according to claim 6, wherein, In two adjacent sets of driving circuits, the first column of driving circuits in one set includes alternating sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels, while the first column of driving circuits in the other set includes alternating sub-pixel driving circuits for blue sub-pixels and sub-pixel driving circuits for red sub-pixels.

8. The display panel according to claim 1, wherein, The two data lines in the same group of second data lines include one first data line and one second data line.

9. The display panel according to claim 8, wherein, The display panel also includes multiple first signal lines, with one of the first signal lines located between two data lines in the second data line group.

10. The display panel according to claim 1, wherein, The display panel also includes multiple power lines, and the orthographic projection of the power line corresponding to the drive circuit column on the substrate is located between the orthographic projections of the two data lines corresponding to the drive circuit column on the substrate.

11. The display panel according to any one of claims 1 to 10, wherein, The multiple sub-pixels are divided into multiple rows of driving circuits. In the same row of driving circuits, the driving circuits of two adjacent sub-pixels are mirror-symmetrical.

12. The display panel according to any one of claims 1 to 10, wherein, The display panel includes a hole area, an isolation area, and a pixel area, with the isolation area located between the hole area and the pixel area; the multiple data lines include multiple data lines that cross the hole area, and the multiple data lines that cross the hole area include multiple first-type data lines and multiple second-type data lines; The first type of data line includes a first data portion, a first type of cross-region data portion, and a second data portion that are coupled in sequence. The first data portion and the second data portion are located on opposite sides of the aperture area. The first data portion, the first type of cross-region data portion, and the second data portion are all located in the pixel area. The second type of data line includes a third data portion, a second type of cross-region data portion, and a fourth data portion that are coupled in sequence. The third data portion and the fourth data portion are located on opposite sides of the aperture area. Both the third data portion and the fourth data portion are located in the pixel area. The second type of cross-region data portion is located in the isolation area.

13. The display panel according to claim 12, wherein, The plurality of second-type data lines are divided into a first part of second-type data lines and a second part of second-type data lines, and the plurality of first-type data lines are located between the first part of second-type data lines and the second part of second-type data lines.

14. The display panel according to claim 12, wherein, The first type of data line includes a first data portion and the second type of data line includes a third data portion, which are arranged alternately; the first type of data line includes a second data portion and the second type of data line includes a fourth data portion, which are arranged alternately.

15. The display panel according to claim 14, wherein, The first type of data line is coupled to the corresponding green sub-pixel, and the second type of data line is coupled to the corresponding red sub-pixel and / or blue sub-pixel.

16. A display device comprising a display panel as claimed in any one of claims 1 to 15.

Images