Pixel circuit, driving method, and display apparatus
Patent Information
- Application Number
- PCT/CN2026/078949
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-28
- Filing Date
- 2026-02-12
- Publication Date
- 2026-10-01
Smart Images
Figure CN2026078949_01102026_PF_FP_ABST
Abstract
Description
Pixel circuits, driving methods, and display devices
[0001] Cross-references to related applications
[0002] This application claims priority to Chinese Patent Application No. 202510387343.6, filed in China on March 28, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology
[0004] With the rapid development of AMOLED (Active-matrix organic light-emitting diode), medium and large-sized tablet computers and laptops have become important future development directions. Customers have increasingly strong demands for high-frequency displays. Existing pixel circuits perform threshold voltage compensation and data voltage writing simultaneously. High-frequency technology leads to line time compression, which cannot effectively compensate for the threshold voltage of the driving transistor in the driving circuit, and thus cannot achieve high-frequency driving. Summary of the Invention
[0005] The main objective of this disclosure is to provide a pixel circuit, driving method, and display device to solve the problems that existing pixel circuits cannot guarantee data voltage writing time and cannot guarantee display effect while ensuring display uniformity during high-frequency display.
[0006] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a first control circuit, a first setting circuit, a first energy storage circuit, a second energy storage circuit, and a data writing circuit.
[0007] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.
[0008] The first control circuit is electrically connected to the first reset control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first reset control signal provided by the first reset control terminal;
[0009] The first set circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset control signal;
[0010] The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end;
[0011] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node.
[0012] The first end of the second energy storage circuit is electrically connected to the second node, and the second end of the second energy storage circuit is electrically connected to the third node.
[0013] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit;
[0014] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.
[0015] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal;
[0016] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.
[0017] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second setting circuit and a third setting circuit;
[0018] The second setting circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first initial control signal provided by the first initial control terminal;
[0019] The third setting circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.
[0020] Optionally, the first initial control terminal and the second initial control terminal are the same control terminal.
[0021] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a fourth setting circuit;
[0022] The fourth set circuit is electrically connected to the second reset control terminal, the reference voltage terminal, and the fourth node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the fourth node under the control of the second reset control signal provided by the second reset control terminal.
[0023] Optionally, the driving circuit includes a driving transistor, the first control circuit includes a first transistor, the first set circuit includes a second transistor, the data writing circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.
[0024] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.
[0025] The gate of the first transistor is electrically connected to the first reset control terminal, the first terminal of the first transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first transistor is electrically connected to the second node.
[0026] The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the reference voltage terminal, and the second terminal of the second transistor is electrically connected to the first node.
[0027] The gate of the third transistor is electrically connected to the scan terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the first node.
[0028] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node.
[0029] The first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the third node.
[0030] Optionally, the first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor;
[0031] The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.
[0032] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.
[0033] Optionally, the second set circuit includes a sixth transistor, and the third set circuit includes a seventh transistor;
[0034] The gate of the sixth transistor is electrically connected to the first initial control terminal, the first terminal of the sixth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the sixth transistor is electrically connected to the third node.
[0035] The gate of the seventh transistor is electrically connected to the second initial control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.
[0036] Optionally, the fourth set circuit includes an eighth transistor;
[0037] The gate of the eighth transistor is electrically connected to the second reset control terminal, the first terminal of the eighth transistor is electrically connected to the reference voltage terminal, and the second terminal of the eighth transistor is electrically connected to the fourth node.
[0038] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, wherein the refresh frame includes a compensation phase and a data writing phase set sequentially; the driving method includes:
[0039] During the compensation phase, the first control circuit, under the control of the first reset control signal, controls the connection between the power supply voltage terminal and the second node, and the first set circuit, under the control of the first reset control signal, writes the reference voltage provided by the reference voltage terminal into the first node.
[0040] At the start of the compensation phase, the drive circuit, under the control of the potential of the first node, controls the connection between the second and third nodes to charge the first and second energy storage circuits, and changes the potential of the third node until the drive circuit, under the control of the potential of the first node, controls the disconnection between the second and third nodes.
[0041] During the data writing phase, the data writing circuit, under the control of the scanning signal, writes the data voltage provided by the data line into the first node.
[0042] Optionally, the pixel circuit further includes a second set circuit and a third set circuit; the refresh frame further includes a reset phase set before the compensation phase; the driving method further includes:
[0043] During the reset phase, the second set circuit, under the control of the first initial control signal, writes the first initial voltage into the third node; the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element.
[0044] During the compensation phase, the second set circuit, under the control of the first initial control signal, controls the disconnection between the first initial voltage terminal and the third node.
[0045] Optionally, the pixel circuit further includes a fourth setting circuit; the driving method further includes:
[0046] During the reset, compensation, and data writing phases, the fourth set circuit, under the control of the second reset control signal, writes the reference voltage to the fourth node.
[0047] Optionally, the driving method described in at least one embodiment of this disclosure further includes:
[0048] During the compensation and data writing phases, the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element.
[0049] Optionally, the pixel circuit further includes a third setting circuit, a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit; the holding frame includes a setting phase and a holding light-emitting phase set sequentially; the driving method includes:
[0050] During the setting phase, the third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the power supply voltage terminal to disconnect from the second node; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the third node to disconnect from the first electrode of the light-emitting element.
[0051] During the light-emitting phase, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node. The second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element. The driving circuit drives the light-emitting element to emit light.
[0052] Optionally, the pixel circuit further includes a second setting circuit, and the driving method further includes:
[0053] During the setting phase, the second setting circuit, under the control of the first initial control signal, writes the first initial voltage into the third node.
[0054] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.
[0055] The pixel circuit described in this embodiment separates the data voltage writing and threshold voltage compensation during operation, requiring less scanning time per line. This ensures sufficient data voltage writing time during high-frequency display, allowing the pixel circuit to be fully charged by the data voltage while maintaining display uniformity, thus guaranteeing display performance. Attached Figure Description
[0056] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;
[0057] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;
[0058] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;
[0059] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;
[0060] Figure 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;
[0061] Figure 6 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;
[0062] Figure 7A is a schematic diagram of the first operating state of the pixel circuit described in at least one embodiment of the present disclosure, as shown in Figure 5.
[0063] Figure 7B is a schematic diagram of the first operating state of the pixel circuit described in at least one embodiment of the present disclosure, as shown in Figure 5.
[0064] Figure 7C is a schematic diagram of the first operating state of the pixel circuit described in at least one embodiment of the present disclosure, as shown in Figure 5.
[0065] Figure 7D is a schematic diagram of the first operating state of the pixel circuit described in at least one embodiment of the present disclosure, as shown in Figure 5.
[0066] Figure 8 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;
[0067] Figure 9 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;
[0068] Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;
[0069] Figure 11 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 10. Detailed Implementation
[0070] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.
[0071] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.
[0072] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.
[0073] As shown in Figure 1, the pixel circuit described in at least one embodiment of this disclosure includes a driving circuit 10, a first control circuit 11, a first setting circuit 12, a first energy storage circuit 13, a second energy storage circuit 14, and a data writing circuit 15.
[0074] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1.
[0075] The first control circuit 11 is electrically connected to the first reset control terminal GR1, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the first reset control signal provided by the first reset control terminal GR1.
[0076] The first set circuit 12 is electrically connected to the first reset control terminal GR1, the reference voltage terminal REF and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first node N1 under the control of the first reset control signal;
[0077] The data writing circuit 15 is electrically connected to the scanning terminal GW, the data line Dj and the first node N1 respectively, and is used to write the data voltage provided by the data line Dj into the first node N1 under the control of the scanning signal provided by the scanning terminal GW.
[0078] The first terminal of the first energy storage circuit 13 is electrically connected to the first node N1, and the second terminal of the first energy storage circuit 13 is electrically connected to the fourth node N4.
[0079] The first end of the second energy storage circuit 14 is electrically connected to the second node N2, and the second end of the second energy storage circuit 14 is electrically connected to the third node N3.
[0080] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, when in operation, the refresh frame may include a compensation stage and a data writing stage set sequentially.
[0081] During the compensation phase, the first control circuit 11, under the control of the first reset control signal, controls the connection between the power supply voltage terminal ELVDD and the second node N2, and the first set circuit 12, under the control of the first reset control signal, writes the reference voltage Vref provided by the reference voltage terminal REF into the first node N1.
[0082] At the start of the compensation phase, the drive circuit 10, under the control of the potential of the first node N1, controls the connection between the second node N2 and the third node N3 to charge the first energy storage circuit 13 and the second energy storage circuit 14, and changes the potential of the third node N3 until the drive circuit 10, under the control of the potential of the first node N1, controls the connection between the second node N2 and the third node N3 to perform threshold voltage compensation.
[0083] During the data writing phase, the data writing circuit 15, under the control of the scanning signal, writes the data voltage provided by the data line Dj into the first node N1.
[0084] In at least one embodiment of the pixel circuit described in this disclosure, the data voltage writing and threshold voltage compensation are designed separately during operation, requiring less scanning time per line. This ensures that the data voltage writing time is guaranteed during high-frequency display, and that the pixel circuit can be fully charged by the data voltage while ensuring display uniformity, thus guaranteeing the display effect.
[0085] In the pixel circuit described in at least one embodiment of this disclosure, the first control circuit 11 and the first set circuit 12 share the first reset control terminal, which can reduce the number of GOA (Gate On Array) modules used in the display device and facilitate the realization of narrow bezels.
[0086] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1, a first light-emitting control circuit 21, and a second light-emitting control circuit 22.
[0087] The first light-emitting control circuit 21 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.
[0088] The second light-emitting control circuit 22 is electrically connected to the light-emitting control terminal EM, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.
[0089] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.
[0090] Optionally, the first voltage terminal can be a low voltage terminal.
[0091] Optionally, the light-emitting element can be an OLED (Organic Light-Emitting Diode), the first electrode of the light-emitting element can be an anode, and the second electrode of the light-emitting element can be a cathode, but this is not a limitation. In specific implementations, the light-emitting element can be other types of light-emitting diodes.
[0092] The pixel circuit described in at least one embodiment of this disclosure further includes a second setting circuit and a third setting circuit;
[0093] The second setting circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first initial control signal provided by the first initial control terminal;
[0094] The third setting circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.
[0095] In a specific implementation, the pixel circuit may further include a second setting circuit and a third setting circuit (T8); the second setting circuit, under the control of the first initial control signal, writes the first initial voltage into the third node to initialize the potential of the third node; the third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.
[0096] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a second set circuit 32 and a third set circuit 33;
[0097] The second setting circuit 32 is electrically connected to the first initial control terminal GI1, the first initial voltage terminal I1 and the third node N3 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the first initial control signal provided by the first initial control terminal GI1.
[0098] The third setting circuit 33 is electrically connected to the second initial control terminal GI2, the second initial voltage terminal I2 and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the second initial control signal provided by the second initial control terminal GI2.
[0099] In at least one embodiment of this disclosure, the first initial control terminal and the second initial control terminal are the same control terminal, so as to reduce the number of control terminals used, thereby reducing the number of GOA (Gate On Array) modules used in the display device, which is beneficial to achieving a narrow bezel.
[0100] The pixel circuit described in at least one embodiment of this disclosure further includes a fourth setting circuit;
[0101] The fourth set circuit is electrically connected to the second reset control terminal, the reference voltage terminal, and the fourth node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the fourth node under the control of the second reset control signal provided by the second reset control terminal.
[0102] In a specific implementation, the pixel circuit may further include a fourth setting circuit, which, under the control of the second reset control signal, writes a reference voltage into the fourth node to set the potential of the fourth node.
[0103] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a fourth setting circuit 34;
[0104] The fourth set circuit 34 is electrically connected to the second reset control terminal GR2, the reference voltage terminal REF, and the fourth node N4, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the fourth node N4 under the control of the second reset control signal provided by the second reset control terminal GR2.
[0105] In at least one embodiment of the pixel circuit shown in FIG4 of this disclosure, when in operation, the refresh frame further includes a reset phase set before the compensation phase;
[0106] During the reset phase, the second set circuit 32, under the control of the first initial control signal, writes the first initial voltage Vinit1 into the third node N3; the third set circuit 33, under the control of the second initial control signal, writes the second initial voltage Vinit2 into the first electrode of the light-emitting element E1.
[0107] During the compensation phase, the second set circuit 32, under the control of the first initial control signal, controls the first initial voltage terminal I1 to disconnect from the third node N3.
[0108] In a specific implementation, the transistors in the first control circuit 11 are turned on only after the transistors in the second set circuit 32 are turned off, so that setting the third node N3 will not affect the threshold voltage compensation of the driving transistors in the driving circuit.
[0109] In at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure, during operation, in the reset phase, compensation phase, and data writing phase, the fourth set circuit 34, under the control of the second reset control signal, writes the reference voltage Vref into the fourth node N4 to set the potential of the fourth node N4, thereby stabilizing the potential of the fourth node N4, so that the potential of the fourth node N4 does not affect the potential of the third node N3 during the compensation phase and the data writing phase.
[0110] In at least one embodiment of the pixel circuit shown in FIG4 of this disclosure, during operation, in the reset phase, compensation phase and data writing phase, the third set circuit 33, under the control of the second initial control signal, writes the second initial voltage Vinit2 into the first pole of the light-emitting element E1 to clear the residual charge in the first pole of the light-emitting element E1 and to fully initialize the first pole of the light-emitting element E1.
[0111] During the reset phase, the second set circuit 32, under the control of the first initial control signal, writes the first initial voltage Vinit1 into the third node N3 to reset the potential of the third node N3.
[0112] In at least one embodiment of the pixel circuit shown in FIG4 of this disclosure, when in operation, the holding frame includes a setting phase and a holding light-emitting phase that are set sequentially;
[0113] During the setting phase, the third setting circuit 33, under the control of the second initial control signal, writes the second initial voltage Vinit2 into the first electrode of the light-emitting element E1; the second setting circuit 32, under the control of the first initial control signal, writes the first initial voltage Vinit1 into the third node N3; the first light-emitting control circuit 21, under the control of the light-emitting control signal, controls the power supply voltage terminal ELVDD to disconnect from the second node N2; the second light-emitting control circuit 22, under the control of the light-emitting control signal, controls the third node N3 to disconnect from the first electrode of the light-emitting element E1.
[0114] During the light-emitting phase, the first light-emitting control circuit 21 controls the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal. The second light-emitting control circuit 22 controls the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal. The driving circuit 10 drives the light-emitting element E1 to emit light.
[0115] In specific implementation, within the holding frame, the light-emitting stage is set before the holding light-emitting stage; in the set stage, the light-emitting element does not emit light, and the third set circuit 33, under the control of the second initial control signal, writes the second initial voltage Vinit2 into the first electrode of the light-emitting element E1 to clear the residual charge in the first electrode of the light-emitting element E1; the second set circuit 32, under the control of the first initial control signal, writes the first initial voltage Vinit1 into the third node N3 to improve the hysteresis phenomenon of the driving transistor included in the driving circuit.
[0116] Optionally, the driving circuit includes a driving transistor, the first control circuit includes a first transistor, the first set circuit includes a second transistor, the data writing circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.
[0117] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.
[0118] The gate of the first transistor is electrically connected to the first reset control terminal, the first terminal of the first transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first transistor is electrically connected to the second node.
[0119] The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the reference voltage terminal, and the second terminal of the second transistor is electrically connected to the first node.
[0120] The gate of the third transistor is electrically connected to the scan terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the first node.
[0121] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node.
[0122] The first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the third node.
[0123] Optionally, the first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor;
[0124] The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.
[0125] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.
[0126] Optionally, the second set circuit includes a sixth transistor, and the third set circuit includes a seventh transistor;
[0127] The gate of the sixth transistor is electrically connected to the first initial control terminal, the first terminal of the sixth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the sixth transistor is electrically connected to the third node.
[0128] The gate of the seventh transistor is electrically connected to the second initial control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.
[0129] Optionally, the fourth set circuit includes an eighth transistor;
[0130] The gate of the eighth transistor is electrically connected to the second reset control terminal, the first terminal of the eighth transistor is electrically connected to the reference voltage terminal, and the second terminal of the eighth transistor is electrically connected to the fourth node.
[0131] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 4, the driving circuit includes a driving transistor DT, the first control circuit includes a first transistor T1, the first set circuit includes a second transistor T2, the data writing circuit includes a third transistor T3, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.
[0132] The first gate of the driving transistor DT is electrically connected to the first node N1, the second gate of the driving transistor DT is electrically connected to the drain of the driving transistor DT, the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3.
[0133] The gate of the first transistor T1 is electrically connected to the first reset control terminal GR1, the source of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first transistor T1 is electrically connected to the second node N2.
[0134] The gate of the second transistor T2 is electrically connected to the first reset control terminal GR1, the source of the second transistor T2 is electrically connected to the reference voltage terminal REF, and the drain of the second transistor T2 is electrically connected to the first node N1; the reference voltage terminal REF is used to provide the reference voltage Vref;
[0135] The gate of the third transistor T3 is electrically connected to the scan terminal GW, the source of the third transistor T3 is electrically connected to the data line Dj, and the drain of the third transistor T3 is electrically connected to the first node N1.
[0136] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the fourth node N4.
[0137] The first terminal of the second capacitor C2 is electrically connected to the second node N2, and the second terminal of the second capacitor C2 is electrically connected to the third node N3;
[0138] The first light-emitting control circuit includes a fourth transistor T4, and the second light-emitting control circuit includes a fifth transistor T5; the light-emitting element is an organic light-emitting diode O1.
[0139] The gate of the fourth transistor T4 is electrically connected to the light-emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the second node N2.
[0140] The gate of the fifth transistor T5 is electrically connected to the light-emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the third node N3, the drain of the fifth transistor T5 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low-voltage terminal ELVSS.
[0141] The second set circuit includes a sixth transistor T6, and the third set circuit includes a seventh transistor T7;
[0142] The gate of the sixth transistor T6 is electrically connected to the first initial control terminal GI1, the source of the sixth transistor T6 is electrically connected to the first initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the third node N3; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.
[0143] The gate of the seventh transistor T7 is electrically connected to the first initial control terminal GI1, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.
[0144] The fourth set circuit includes an eighth transistor T8;
[0145] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal GR2, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal REF, and the drain of the eighth transistor T8 is electrically connected to the fourth node N4.
[0146] In at least one embodiment of the pixel circuit shown in Figure 5, the first initial control terminal and the second initial control terminal are the same control terminal, so as to reduce the number of control terminals used, reduce the number of GOA modules included in the display device, and facilitate the realization of narrow bezels.
[0147] I1 and I2 can share the same initial voltage terminal, but this is not a limitation.
[0148] In at least one embodiment of the pixel circuit shown in Figure 5, DT is a dual-gate transistor.
[0149] In at least one embodiment of the pixel circuit shown in Figure 5, T1-T8 are n-type transistors and DT is an n-type transistor, but not limited thereto.
[0150] As shown in FIG6, when at least one embodiment of the pixel circuit shown in FIG5 of this disclosure is in operation, the refresh frame FS may include a reset stage S11, a compensation stage S12, a data writing stage S13 and a refresh light emission stage S14 set sequentially.
[0151] During the reset phase S11, EM provides a low voltage signal, GR1 provides a low voltage signal, GR2 provides a high voltage signal, GI1 provides a high voltage signal, and GW provides a high voltage signal, as shown in Figure 7A. T8 is turned on, and the reference voltage Vref is written to N4 to reset the potential of N4. T6 and T7 are turned on, and the first initial voltage Vinit1 is written to N3, and the second initial voltage Vinit2 is written to the anode of O1. T3, T2, T4, T5, and T1 are in the off state.
[0152] During the compensation phase S12, EM provides a low voltage signal, GR1 provides a high voltage signal, GR2 provides a high voltage signal, GI1 provides a low voltage signal, and GW provides a low voltage signal, as shown in Figure 7B. T8 remains on, T6 and T7 are off, and T2 and T1 are on, thus completing the initialization of the potential of N1.
[0153] At the start of the compensation phase S12, DT is turned on, and the current flows through T1 and DT to charge C1 and C2, changing the potential of N3 until DT is turned off. At this time, the potential of N3 gradually changes from Vinit1 to Vref-Vth, where Vth is the threshold voltage of DT, thus completing the threshold voltage compensation.
[0154] At the start of the compensation phase S12, the gate-drain voltage Vgd of DT must be less than Vth, that is, Vref-Vdd is less than Vth, where Vdd is the voltage value of the power supply voltage provided by ELVDD.
[0155] During the data writing phase S13, EM provides a low voltage signal, GR1 provides a low voltage signal, GR2 provides a high voltage signal, GI1 provides a low voltage signal, and G2 provides a high voltage signal, as shown in Figure 7C. T8 remains on, T3 is on, and the data line Dj provides the data voltage Vdata to N1; T2, DT, T4, T5, T1, T7, and T6 are off; the potential of N4 is stabilized by T8, so the potential of N3 will not be disturbed and will remain at Vref-Vth.
[0156] During the refresh emission stage S14, EM provides a high-voltage signal, GR1 and GR2 provide low-voltage signals, GI1 provides a low-voltage signal, and GW provides a low-voltage signal, as shown in Figure 7D. DT, T4, and T5 are turned on, and current flows through T4, DT, and T5 to charge the anode of O1 until O1 stably emits light. The anode voltage of O1 becomes the emission voltage Vo1 of O1. The potential of N3 can be approximately equal to the anode voltage of O1. Through coupling and bootstrapping of C1 and C2, the change in potential of N1 is equal to the change in potential of N3. The potential difference between N1 and N3 is maintained at Vdata - Vref + Vth. The driving current Id generated by DT to drive O1 to emit light can be K(Vref - Vdata). 2 Where K is the current coefficient of DT; Id is not affected by the threshold voltage of DT, and the brightness of the image output from the display panel can be maintained uniformly, regardless of the characteristics of DT.
[0157] In at least one embodiment of the pixel circuit shown in FIG5 of this disclosure, T1 is turned on only after T6 is turned off, so that setting the potential of N3 does not affect the threshold voltage compensation of the driving transistor.
[0158] As shown in Figures 8 and 9, when at least one embodiment of the pixel circuit shown in Figure 5 of this disclosure is in operation, the holding frame FB may include a setting phase S21 and a holding light emission phase S22 that are set sequentially.
[0159] During the set phase S21, EM provides a low voltage signal, GR1 and GR2 provide low voltage signals, GI1 provides a high voltage signal, GW provides a low voltage signal, T6 and T7 are both turned on, I1 provides a first initial voltage Vinit1 to N3, and I2 provides a second initial voltage Vinit2 to the anode of O1.
[0160] During the light-emitting phase S22, EM provides a high voltage signal, while GR1, GR2, GI1, and GW all provide low voltage signals. T4 and T5 are turned on, and DT drives O1 to emit light.
[0161] As shown in Figure 8, the duration of the set phase S21 is less than that shown in Figure 9.
[0162] As shown in Figure 9, the duration of S21 is extended to fully initialize the anode of O1.
[0163] The differences between at least one embodiment of the pixel circuit shown in Figure 10 of this disclosure and at least one embodiment of the pixel circuit shown in Figure 5 of this disclosure are as follows:
[0164] The gate of T7 is electrically connected to the second initial control terminal GI2.
[0165] As shown in Figure 11, in at least one embodiment of the pixel circuit shown in Figure 10 of this disclosure, T6 and T7 are controlled by GI1 and GI2 respectively during operation. During the refresh frame FS, T7 can be turned on for a longer period of time to fully initialize the anode of O1, while T6 is turned on for a shorter period of time.
[0166] As shown in Figure 11, during the reset phase S11, compensation phase S12, and data writing phase S13, GI2 provides a high voltage signal, T7 is turned on, and the anode of O1 is initialized.
[0167] As shown in FIG11, when at least one embodiment of the pixel circuit shown in FIG10 of this disclosure is in operation, the holding frame FB may include a setting phase S21 and a holding light emission phase S22 that are set sequentially.
[0168] During the setting phase S21, GI2 provides a high voltage signal, T7 turns on, and the anode potential of O1 is reset.
[0169] Optionally, during the set phase S21, GI1 can also provide a high voltage signal, T6 is turned on, and Vinit1 is written to N3 to improve the hysteresis of the driving transistor DT.
[0170] The driving method described in this embodiment is applied to the aforementioned pixel circuit, and the refresh frame includes a compensation stage and a data writing stage set sequentially; the driving method includes:
[0171] During the compensation phase, the first control circuit, under the control of the first reset control signal, controls the connection between the power supply voltage terminal and the second node, and the first set circuit, under the control of the first reset control signal, writes the reference voltage provided by the reference voltage terminal into the first node.
[0172] At the start of the compensation phase, the drive circuit, under the control of the potential of the first node, controls the connection between the second and third nodes to charge the first and second energy storage circuits, and changes the potential of the third node until the drive circuit, under the control of the potential of the first node, controls the disconnection between the second and third nodes.
[0173] During the data writing phase, the data writing circuit, under the control of the scanning signal, writes the data voltage provided by the data line into the first node.
[0174] In the driving method described in this embodiment, the data voltage writing and threshold voltage compensation are designed separately, requiring less scanning time per line. This ensures that the data voltage writing time is guaranteed during high-frequency display, and that the pixel circuit is fully charged by the data voltage while ensuring display uniformity, thus guaranteeing the display effect.
[0175] In at least one embodiment of this disclosure, the pixel circuit further includes a second set circuit and a third set circuit; the refresh frame further includes a reset phase set before the compensation phase; the driving method further includes:
[0176] During the reset phase, the second set circuit, under the control of the first initial control signal, writes the first initial voltage into the third node to initialize the potential of the third node; the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.
[0177] During the compensation phase, the second set circuit, under the control of the first initial control signal, controls the disconnection between the first initial voltage terminal and the third node.
[0178] In at least one embodiment of this disclosure, the pixel circuit further includes a fourth setting circuit; the driving method further includes:
[0179] During the reset phase, compensation phase, and data writing phase, the fourth set circuit, under the control of the second reset control signal, writes the reference voltage into the fourth node to set the potential of the fourth node.
[0180] The driving method described in at least one embodiment of this disclosure further includes:
[0181] During the compensation and data writing phases, the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.
[0182] In at least one embodiment of this disclosure, the pixel circuit further includes a third setting circuit, a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit; the holding frame includes a setting phase and a holding light-emitting phase that are set sequentially; the driving method includes:
[0183] During the setting phase, the third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the power supply voltage terminal to disconnect from the second node; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the third node to disconnect from the first electrode of the light-emitting element.
[0184] During the light-emitting phase, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node. The second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element. The driving circuit drives the light-emitting element to emit light.
[0185] In at least one embodiment of this disclosure, the pixel circuit further includes a second setting circuit, and the driving method further includes:
[0186] During the setting phase, the second setting circuit, under the control of the first initial control signal, writes the first initial voltage into the third node to improve the hysteresis phenomenon of the driving transistors included in the driving circuit.
[0187] The display device described in this disclosure includes the pixel circuit described above.
[0188] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A pixel circuit, comprising a driving circuit, a first control circuit, a first setting circuit, a first energy storage circuit, a second energy storage circuit, and a data writing circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node. The first control circuit is electrically connected to the first reset control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first reset control signal provided by the first reset control terminal; The first set circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset control signal; The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end; The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node. The first end of the second energy storage circuit is electrically connected to the second node, and the second end of the second energy storage circuit is electrically connected to the third node.
2. The pixel circuit as described in claim 1, wherein, It also includes a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal. The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; The second electrode of the light-emitting element is electrically connected to the first voltage terminal.
3. The pixel circuit as described in claim 2, wherein, It also includes a second set circuit and a third set circuit; The second setting circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first initial control signal provided by the first initial control terminal; The third setting circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.
4. The pixel circuit as described in claim 3, wherein, The first initial control terminal and the second initial control terminal are the same control terminal.
5. The pixel circuit according to any one of claims 1 to 4, wherein, It also includes a fourth set circuit; The fourth set circuit is electrically connected to the second reset control terminal, the reference voltage terminal, and the fourth node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the fourth node under the control of the second reset control signal provided by the second reset control terminal.
6. The pixel circuit as described in claim 1, wherein, The driving circuit includes a driving transistor, the first control circuit includes a first transistor, the first set circuit includes a second transistor, the data writing circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node. The gate of the first transistor is electrically connected to the first reset control terminal, the first terminal of the first transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first transistor is electrically connected to the second node. The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the reference voltage terminal, and the second terminal of the second transistor is electrically connected to the first node. The gate of the third transistor is electrically connected to the scan terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node. The first terminal of the second capacitor is electrically connected to the second node, and the second terminal of the second capacitor is electrically connected to the third node.
7. The pixel circuit as described in claim 2, wherein, The first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.
8. The pixel circuit as described in claim 3, wherein, The second set circuit includes a sixth transistor, and the third set circuit includes a seventh transistor; The gate of the sixth transistor is electrically connected to the first initial control terminal, the first terminal of the sixth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the sixth transistor is electrically connected to the third node. The gate of the seventh transistor is electrically connected to the second initial control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.
9. The pixel circuit as described in claim 5, wherein, The fourth set circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the second reset control terminal, the first terminal of the eighth transistor is electrically connected to the reference voltage terminal, and the second terminal of the eighth transistor is electrically connected to the fourth node.
10. A driving method applied to a pixel circuit as described in any one of claims 1 to 9, wherein a refresh frame includes a compensation phase and a data writing phase set sequentially; the driving method includes: During the compensation phase, the first control circuit, under the control of the first reset control signal, controls the connection between the power supply voltage terminal and the second node, and the first set circuit, under the control of the first reset control signal, writes the reference voltage provided by the reference voltage terminal into the first node. At the start of the compensation phase, the drive circuit, under the control of the potential of the first node, controls the connection between the second and third nodes to charge the first and second energy storage circuits, and changes the potential of the third node until the drive circuit, under the control of the potential of the first node, controls the disconnection between the second and third nodes. During the data writing phase, the data writing circuit, under the control of the scanning signal, writes the data voltage provided by the data line into the first node.
11. The driving method as described in claim 10, wherein, The pixel circuit further includes a second setting circuit and a third setting circuit; The refresh frame also includes a reset phase set before the compensation phase; the driving method further includes: During the reset phase, the second set circuit, under the control of the first initial control signal, writes the first initial voltage into the third node; The third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element; During the compensation phase, the second set circuit, under the control of the first initial control signal, controls the disconnection between the first initial voltage terminal and the third node.
12. The driving method as described in claim 10, wherein, The pixel circuit further includes a fourth setting circuit; the driving method further includes: During the reset, compensation, and data writing phases, the fourth set circuit, under the control of the second reset control signal, writes the reference voltage to the fourth node.
13. The driving method as described in claim 11, wherein, Also includes: During the compensation and data writing phases, the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element.
14. The driving method as described in claim 10, wherein, The pixel circuit further includes a third setting circuit, a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit; the holding frame includes a setting phase and a holding light-emitting phase set sequentially; the driving method includes: During the setting phase, the third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the power supply voltage terminal to disconnect from the second node; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the third node to disconnect from the first electrode of the light-emitting element. During the light-emitting phase, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node. The second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element. The driving circuit drives the light-emitting element to emit light.
15. The driving method as described in claim 14, wherein, The pixel circuit further includes a second setting circuit, and the driving method further includes: During the setting phase, the second setting circuit, under the control of the first initial control signal, writes the first initial voltage into the third node.
16. A display device comprising a pixel circuit as claimed in any one of claims 1 to 9.