Matching test method and apparatus for chiplets

Abstract

A matching test method and apparatus for chiplets, relating to the technical field of electronics, and for use in implementing matching tests of different chiplets during chip development. The method comprises: acquiring first model information and second model information, the first model information being used for indicating first interface test information of a first chiplet, the second model information being used for indicating second interface test information of a second chiplet, and the first chiplet and the second chiplet being chiplets to be packaged in a same chip (S201); and performing a matching test on the first chiplet and the second chiplet on the basis of the first interface test information and the second interface test information, the matching test including matching tests for interface interconnection, interface repair, and BIST information (S202).

Description

A method and apparatus for testing the matching of core particles.

[0001] This application claims priority to Chinese Patent Application No. 202510352705.8, filed on March 24, 2025, entitled "A method and apparatus for matching core particles", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a method and apparatus for testing chip matching. Background Technology

[0003] A chiplet is a small, combinable chip with a specific function; it can also be called a die, wafer, or piece. Chiplet technology integrates multiple chiplets together using advanced packaging techniques to form a system-on-a-chip (SoC). Using chiplet technology can improve the performance of SoCs while achieving low cost and high yield.

[0004] Chips based on chip technology typically contain tens of thousands of interconnecting interfaces used for high-speed data transmission. If manufacturing defects are introduced into these interfaces, the chip's functionality will be compromised, impacting the overall yield of the packaged chip. Furthermore, if these defects go undetected during chip testing, defective chips may end up in the final product line, resulting in even greater losses. Therefore, interface testing is crucial from the perspectives of testing, yield, and cost.

[0005] Multiple chips within the same system-on-a-chip (SoC) typically originate from different suppliers or development teams. Testing the interfaces of these chips requires the interfaces of the interconnected chips and the design of the test circuit to be compatible. Therefore, achieving compatible testing of different chips during chip development has become a pressing technical challenge. Summary of the Invention

[0006] This application provides a chip matching test method and apparatus, which can be used to perform matching tests on different chips during chip development.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, a matching test method for a chip is provided. The method includes: acquiring first model information and second model information, wherein the first model information and second model information can be a general model information generated based on test-related structures and information in the chip, the first model information is used to indicate first interface test information of the first chip, and the second model information is used to indicate second interface test information of the second chip, wherein the first chip and the second chip are chips for packaging in the same chip, one of the first chip and the second chip can be a chip that has been generated or manufactured, and the other chip can be a chip in the development stage; and performing a matching test on the first chip and the second chip based on the first interface test information and the second interface test information, wherein the matching test includes matching tests of interface interconnection, interface repair, and BIST information.

[0009] In the above technical solution, for the first and second chips used for packaging in the same chip, matching tests can be performed on the first and second chips based on the first interface test information of the first chip indicated by the first model information and the second interface test information of the second chip indicated by the second model information. The first and second model information can be a general model information generated based on the test-related structures and information in the chip. In this way, during the chip development process, the matching test of the first and second chips can be directly performed based on the first and second model information, thereby eliminating the need for matching at multiple stages of chip development, simplifying the matching process, and improving matching efficiency. Optionally, this method can also be used to perform matching tests on two manufactured chips, or on two chips that are integrated in the same chip and interconnected.

[0010] In one possible implementation of the first aspect, either the first interface test information or the second interface test information is used to indicate the interface mapping information of the corresponding chip. This interface mapping information indicates at least one of the following: an identifier of the interface cluster, an interface index, and an index of the BIST circuit. Optionally, the index of the BIST circuit includes the index of the controller and the index of the excitation circuit. In the above possible implementations, the interface mapping information can be used to determine multiple interfaces of the same interface cluster and the correspondence between the interface cluster and the BIST circuit.

[0011] In one possible implementation of the first aspect, either the first interface test information or the second interface test information is further used to indicate the BIST information of the corresponding chip, wherein the BIST information indicates at least one of the following: interaction mode, preamble, data type, and type of BIST circuit. In the above possible implementations, matching tests of the BIST information of the first chip and the second chip can be performed based on the BIST information in the first interface test information and the second interface test information.

[0012] In one possible implementation of the first aspect, the interaction mode includes: synchronous or asynchronous; and / or, the data type includes at least one of the following: fixed type, checkerboard type, row bar type, column bar type, or pseudo-random code; and / or, the type of the BIST circuit includes one of the following: transmitting type, receiving type, and transmitting-receiving type. In the above possible implementations, the matching test of the BIST information of the first chip and the second chip can be performed based on the BIST information in the first interface test information and the second interface test information.

[0013] In one possible implementation of the first aspect, either the first interface test information or the second interface test information is further used to indicate the interface information of the corresponding chip, which indicates at least one of the following: interface identifier, direction, and signal type. Optionally, the direction includes one of the following: input, output, input-output, or floating; and / or, the signal type includes one of the following: data signal, clock signal, floating signal, asynchronous handshake signal, or redundant interface. In the above possible implementations, matching tests of any two interconnected interfaces in the first chip and the second chip can be achieved based on the interface information in the first interface test information and the second interface test information.

[0014] In one possible implementation of the first aspect, either the first interface test information or the second interface test information is further used to indicate the interface cluster information of the corresponding core, wherein the interface cluster information indicates at least one of the following: interface cluster identifier, interfaces with different functions, and interface repair information. Optionally, the interfaces with different functions include at least one of the following: data interface, clock interface, redundant interface, floating interface, and asynchronous handshake interface; and / or, the interface repair information includes one of the following: interfaces of at least one interface group, and repair type of the interface group. In the above possible implementations, the interconnection relationship and interface repair matching test of any interface cluster information in the first core and the second core can be realized based on the interface cluster information in the first interface test information and the second interface test information.

[0015] In one possible implementation of the first aspect, either the first interface test information or the second interface test information is further used to indicate the core information of the corresponding core, which indicates at least one of the following: core identifier and version information. In the above possible implementations, the core to which the model information obtained by the matching test belongs can be determined through the core information.

[0016] In one possible implementation of the first aspect, a matching test is performed on the first chip and the second chip based on the first interface test information and the second interface test information. This includes: performing a matching test on the first chip and the second chip based on the interconnection information of the first chip and the second chip, as well as the first interface test information and the second interface test information. In the above possible implementation, the matching test of the two chips can be directly performed during chip development based on the interconnection information and the interface test information indicated by the model information of the two interconnected chips. This eliminates the need for separate matching at multiple stages of chip development, thereby simplifying the matching process and improving matching efficiency.

[0017] In one possible implementation of the first aspect, the interconnection information is used to indicate the interconnection relationship between multiple interfaces in the first core and multiple interfaces in the second core. In the above possible implementation, the interconnection information can indicate the interconnection relationship between multiple interfaces in two interconnected cores, thereby facilitating matching tests on the interconnected interfaces in the first and second cores.

[0018] In one possible implementation of the first aspect, the interface interconnection matching test between the first core and the second core includes: matching the interface information of any two interconnected interfaces in the first core and the second core, and matching the interconnection relationship of interface clusters in the first core or the second core. The above possible implementation achieves the interface interconnection matching test between the first core and the second core.

[0019] In one possible implementation of the first aspect, the interface repair matching test between the first core and the second core includes: performing a matching test on the interconnection relationship of interface groups in any interface cluster of the first core or the second core, and performing a matching test on the repair type of the interface groups. The above possible implementation achieves the interface repair matching test between the first core and the second core.

[0020] In one possible implementation of the first aspect, performing a BIST information matching test on the first core and the second core includes: performing a matching test on the BIST information corresponding to multiple interconnected interface clusters in the first core or the second core. In the above possible implementation, the BIST information matching test between the first core and the second core is implemented.

[0021] Secondly, a matching test apparatus for a chip is provided. The apparatus includes: a receiving unit for acquiring first model information and second model information, wherein the first model information is used to indicate first interface test information of a first chip, and the second model information is used to indicate second interface test information of a second chip, wherein the first chip and the second chip are chips for packaging in the same chip; and a processing unit for performing a matching test on the first chip and the second chip based on the first interface test information and the second interface test information, wherein the matching test includes matching tests for interface interconnection, interface repair, and built-in self-test BIST information.

[0022] In one possible implementation of the second aspect, either the first interface test information or the second interface test information is used to indicate the interface mapping information of the corresponding chip, which is used to indicate at least one of the following: the identifier of the interface cluster, the interface index, and the index of the BIST circuit.

[0023] In one possible implementation of the second aspect, the index of the BIST circuit includes the index of the controller and the index of the excitation circuit.

[0024] In one possible implementation of the second aspect, either the first interface test information or the second interface test information is further used to indicate the BIST information of the corresponding chip, which indicates at least one of the following: interaction mode, preamble, data type, and type of BIST circuit.

[0025] In one possible implementation of the second aspect, the interaction mode includes: synchronous or asynchronous; and / or, the data type includes at least one of the following: fixed type, checkerboard type, row bar type, column bar type, or pseudo-random code; and / or, the type of the BIST circuit includes one of the following: transmitting type, receiving type, and transmitting-receiving type.

[0026] In one possible implementation of the second aspect, either the first interface test information or the second interface test information is further used to indicate the interface information of the corresponding chip, which indicates at least one of the following: interface identifier, direction, and signal type.

[0027] In one possible implementation of the second aspect, the direction includes one of the following: input, output, input-output, or floating; and / or, the signal type includes one of the following: data signal, clock signal, floating signal, asynchronous handshake signal, or redundant interface.

[0028] In one possible implementation of the second aspect, either the first interface test information or the second interface test information is further used to indicate the interface cluster information of the corresponding core, which is used to indicate at least one of the following: interface cluster identifier, interfaces with different functions, and interface repair information.

[0029] In one possible implementation of the second aspect, the interface with different functions includes at least one of the following: a data interface, a clock interface, a redundant interface, a floating interface, and an asynchronous handshake interface; and / or, the interface repair information includes one of the following: an interface of at least one interface group, and a repair type of the interface group.

[0030] In one possible implementation of the second aspect, either the first interface test information or the second interface test information is further used to indicate the corresponding core information, which is used to indicate at least one of the following: core identifier and version information.

[0031] In one possible implementation of the second aspect, the processing unit is further configured to: perform a matching test on the first core and the second core based on the interconnection information of the first core and the second core, as well as the first interface test information and the second interface test information.

[0032] In one possible implementation of the second aspect, the interconnection information is used to indicate the interconnection relationship between multiple interfaces in the first core and multiple interfaces in the second core.

[0033] In one possible implementation of the second aspect, the processing unit is further configured to: perform a matching test on the interface information of any two interconnected interfaces in the first core and the second core, and perform a matching test on the interconnection relationship of the interface clusters in the first core or the second core.

[0034] In one possible implementation of the second aspect, the processing unit is further configured to: perform a matching test on the interconnection relationship of interface groups in any interface cluster of the first core or the second core, and perform a matching test on the repair type of the interface groups.

[0035] In one possible implementation of the second aspect, the processing unit is further configured to: perform a matching test on the BIST information corresponding to multiple interconnected interface clusters in the first or second core.

[0036] In another aspect of this application, an electronic device is provided, comprising: a processor and a memory, wherein the memory stores instructions, and the processor executes the instructions in the memory to cause the electronic device to perform the methods provided by the first aspect or any possible implementation thereof.

[0037] In another aspect of this application, a computer-readable storage medium is provided, which stores a computer program or instructions that, when the computer program or instructions are executed by a device, cause the device to implement the method provided by the first aspect or any possible implementation thereof.

[0038] In another aspect of this application, a computer program product is provided, comprising: a computer program (also referred to as code or instructions) that, when executed by a device, causes the device to perform the method provided by the first aspect or any possible implementation thereof.

[0039] Understandably, the beneficial effects achieved by any of the computer-readable storage media and computer program products provided above can be referred to in accordance with the beneficial effects of the methods provided above, and will not be repeated here. Attached Figure Description

[0040] Figure 1 is a schematic diagram of a chip based on chip technology provided in an embodiment of this application;

[0041] Figure 2 is a schematic diagram of the distribution of interface clusters in a chip according to an embodiment of this application;

[0042] Figure 3 is a schematic diagram of a chip interconnect structure provided in an embodiment of this application;

[0043] Figure 4 is a schematic diagram of an interface interconnection provided in an embodiment of this application;

[0044] Figure 5 is a schematic diagram of interface repair in a core provided by an embodiment of this application;

[0045] Figure 6 is a schematic diagram of a chip development process provided in an embodiment of this application;

[0046] Figure 7 is a flowchart illustrating a chip matching test method provided in an embodiment of this application;

[0047] Figure 8 is a schematic diagram of interface repair in two interconnected cores provided in an embodiment of this application;

[0048] Figure 9 is a schematic diagram of a BIST circuit and interface cluster in a chip provided in an embodiment of this application;

[0049] Figure 10 is a schematic diagram of the structure of a core matching test device provided in an embodiment of this application;

[0050] Figure 11 is a schematic diagram of another matching test device for core particles provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0052] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0053] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0054] Before introducing the embodiments of this application, the application scenarios involved in this application will be described first.

[0055] A chiplet is a small, combinable chip with a specific function. It can also be called a die, wafer, or tile. Chiplet technology integrates multiple small chips together using advanced packaging techniques to form a larger chip, which can be a system-on-a-chip (SoC). 2.5D or 3D stacking techniques can be used to interconnect and package multiple chips into a large chip. These multiple small chips can use different processes, have different functions, and may even be supplied by different vendors. Integrating multiple chips into a large chip using chiplet technology can reduce chip design time and cost, while improving chip performance and ensuring high yield. For example, as shown in Figure 1, the chip includes multiple small chips located within the same package. These multiple small chips can include the same and / or different types of small chips. Different types of small chips can include computing chips, cache chips, base chips, storage chips, interface chips, and connectivity chips, etc. In Figure 1, different types of small chips are represented by different shapes or different filling methods.

[0056] Chips based on chip technology typically contain tens of thousands of interconnected interfaces used for high-speed data transmission. If manufacturing defects are introduced into these interfaces, the chip's functionality will be compromised, impacting the overall yield of the packaged chip. Furthermore, if these defects go undetected during chip testing, defective chips may end up in the final product line, resulting in even greater losses. Therefore, interface testing is crucial from the perspectives of testing, yield, and cost. This interface testing can also be called input / output (IO) interface testing, IO testing, or interconnect IO testing. In this application, "interface" and "IO" can be considered equivalent, and "interface" can be replaced with "IO" in the following text.

[0057] During interface testing, the multiple interfaces of each core can be divided into different types of interface clusters (IO clusters). That is, the multiple interfaces of each core include one or more interface clusters, and each interface cluster can include multiple interfaces. The physical arrangement of different interface clusters can be the same or different, and the same type of interface cluster can appear multiple times in different locations within the core. For example, Figure 2 shows a schematic diagram of the distribution of interface clusters corresponding to multiple interfaces of a core. Interfaces located in the same location area and using the same filling method belong to the same interface cluster, while interfaces located in different location areas and using different filling methods belong to different interface clusters. Multiple interface clusters of the same type use the same filling method. These interface clusters can also be called IO MACRO (abbreviated as MACRO or macro), interface sets (which can be represented as IOs), or interface areas. Optionally, each interface cluster can include one or more interface groups (IO groups); when an interface cluster includes an interface group, that interface cluster can also be called an interface group.

[0058] In one possible embodiment, interface testing is performed using a built-in self-test (BIST) method. The sending end transmits stimulus data (or test data or transmitted values), and the receiving end receives and compares the stimulus data with the compared data (or expected values) to complete the test. For example, as shown in Figure 3, core A and core B are interconnected. Both core A and core B include at least one BIST circuit and multiple interface clusters (IO clusters). Each BIST circuit may include a controller and multiple stimulus circuits. The controller can be used to control the multiple stimulus circuits; each stimulus circuit can be coupled to one or more interface clusters for testing the one or more interface clusters. Optionally, the stimulus circuit can be used to generate and compare stimulus data; therefore, the stimulus circuit can also be called a stimulus generation and comparison circuit. In practical applications, the stimulus circuit can be a wrapper.

[0059] During the aforementioned interface testing, it is required that the interface interconnection between the two core particles cannot cross interface clusters. That is, an interface in the same interface cluster of one core particle can only interconnect with an interface in one interface cluster of another core particle, and cannot interconnect with multiple interface clusters of another core particle. If the interface interconnection between the two core particles is incorrect, the BIST test cannot be performed. For example, Figure 4(a) shows a schematic diagram of a correct interface interconnection, and Figure 4(b) shows a schematic diagram of an incorrect interface interconnection.

[0060] Furthermore, during interconnect interface repair, the interfaces of both core particles must be replaced simultaneously to complete the repair; that is, the interface repair methods and specifications of the two core particles must be consistent. Optionally, interface repair can be achieved through shifting, which can include left shifting and right shifting. For example, as shown in Figure 5(a), a core particle includes 32 interfaces for normal communication (represented as 1 to 32) and two redundant interfaces (represented as P and Q). When one of the 32 interfaces fails, interface repair can be performed by shifting left using the redundant interface P, or by shifting right using the redundant interface Q. If the interface repair methods of the two core particles are inconsistent, interface repair cannot be achieved. For example, as shown in Figure 5(b), the redundant interfaces in the two interconnected core particles are in different positions. One core particle performs interface repair by shifting two interfaces to the right, while the other performs interface repair by shifting one interface to the right. In this case, interface repair cannot be achieved when an interface failure occurs in these two core particles.

[0061] Furthermore, multiple chips within the same system-on-a-chip (SoC) typically originate from different suppliers or development teams. Testing the interfaces of these chips requires the interfaces of the two interconnected chips to be compatible with the design of the test circuits. For example, as shown in Figure 6(a), the chip development process usually includes multiple stages such as requirements analysis, architecture design, logic design, physical design, manufacturing, and testing. At different stages within these stages, data verification is required for the two interconnected chips (represented as chip A and chip B). For instance, in the requirements analysis stage, it is necessary to clarify which interfaces the two chips have, their specific specifications, and uses; in the architecture design stage, it is necessary to clarify the interface interaction methods (e.g., asynchronous or synchronous), whether interface repair is supported, the structure of interface repair, and whether they match; in the design stage, it is necessary to clarify whether the interface clusters of the two chips match and whether the BIST design specifications meet the requirements; in the testing stage, the sending and receiving of the BIST circuits in the two chips need to match. Performing data verification at multiple stages of chip development presents problems such as cumbersome processes, large amounts of data to be compared, and long processing times. Therefore, how to achieve matching tests between different chips during chip development has become a technical problem that urgently needs to be solved.

[0062] Based on this, embodiments of this application provide a chip matching test method, which can be used to implement matching tests of two chips during chip development. For example, one of the two chips may be a chip that has already been generated or manufactured, and the other chip may be under development and intended to be packaged in the same chip as the manufactured chip. For two chips to be packaged in the same chip, this method can perform matching tests on the two chips based on the interface test information indicated by the model information of the two chips. The model information of one chip may be a general model information generated based on the test-related structures and information in the chip. For example, as shown in Figure 6(b), during chip development, model information of two chips (represented as chip A and chip B) can be obtained through electronic design automation (EDA) tools, and matching tests can be performed based on the model information of the two chips, thereby simplifying the matching process and improving matching efficiency. Optionally, this method can also be used to implement matching tests of two manufactured chips, or matching tests of two chips that are integrated in the same chip and interconnected.

[0063] Figure 7 is a flowchart illustrating a chip matching test method provided in an embodiment of this application. This method can be executed by an electronic device, such as an EDA tool installed on the electronic device. The method includes the following steps.

[0064] S201: Obtain first model information and second model information. The first model information is used to indicate the first interface test information of the first chip, and the second model information is used to indicate the second interface test information of the second chip. The first chip and the second chip are chips used to be packaged in the same chip.

[0065] The first and second cores can be two cores of the same type or two cores of different types. For example, both the first and second cores can be computation cores; or, one of the first and second cores can be a computation core and the other a storage core. Each of the first and second cores can include multiple interfaces and at least one BIST circuit. The multiple interfaces can be divided into at least one interface cluster, and each BIST circuit can be used to test one or more interface clusters, that is, one BIST circuit corresponds to one or more interface clusters.

[0066] Furthermore, the first model information refers to the model information of the first core, and the second model information refers to the model information of the second core. The model information of each core can be used to indicate the interface test information of that core. This model information can be generated based on the test-related structures and information in that core. For example, during the development of each core, the model information of that core can be generated based on the relevant structures and information of the interface and BIST circuit in that core.

[0067] Furthermore, the model information of each core element can have one or more domain segments (or fields). The interface test information indicated by this model information can be located in the same domain segment of the model information or in different domain segments of the model information. The interface test information indicated by the model information of each core element is described below.

[0068] In one possible embodiment, the interface test information for each chip can be used to indicate at least one of the following information for the corresponding chip: chip information, interface information, interface mapping information, interface cluster information, and BIST information. The interface information can be at the interface level, indicating basic information about any interface. The interface mapping information can be at the interface level, indicating the correspondence between any interface and an interface cluster, and / or between any interface and a BIST circuit. The interface cluster information can be at the interface cluster level, indicating the composition information of any interface cluster. The BIST information can be at the BIST circuit level, indicating information related to BIST testing. The various types of information in the interface test information are described and illustrated below.

[0069] Optionally, the core information may indicate or include at least one of the following: core identifier and version information. The core information in the model information can distinguish the cores belonging to different model information. For example, the model information may include a die info field to indicate core information, the format of which may be: “dieinfo”{“IDCODE”:“ID100”,“Version”:“V1”}, indicating that the core identifier is ID100 and the version information is V1.

[0070] Optionally, the interface information may indicate or include at least one of the following: interface identifier, direction, and signal type. For the interface information of any interface in the core, the interface identifier identifies the interface, the direction indicates the transmission direction of the interface, and the signal type indicates the type of signal transmitted by the interface. The directions of different interfaces within the same core may include, but are not limited to: input (in), output (out), input-output (inout), and floating (also referred to as a link). Table 1 shows multiple different directions, along with the meaning and verification points for each direction. The signal types of different interfaces within the same core may include, but are not limited to: data signal, clock signal (CLK), floating signal, asynchronous handshake signal (e.g., ready), and redundant interface (redundancy, redun). The floating signal may be represented as a link, and the asynchronous handshake signal may include valid and ready signals, etc. Table 2 shows multiple different signal types, along with the meaning and verification points for each signal type.

[0071] Table 1

[0072] Table 2

[0073] For example, the model information includes a port info field for indicating interface information. The format of the port info field can be as follows, indicating that the interface with the interface identifier 3D_TX_DATA0 has the direction of inout and the signal type of data, and the interface with the interface identifier 3D_TX_CLK has the direction of in and the signal type of CLK.

[0074] Optionally, the interface mapping information indicates or includes at least one of the following: the identifier of the interface cluster, the interface index, and the index of the BIST circuit. The interface mapping information in the model information distinguishes the interface cluster to which any interface belongs and the corresponding BIST circuit. For the interface mapping information of any interface in the core, the identifier of the interface cluster refers to the identifier of the interface cluster to which the interface belongs, or the type of the interface cluster; the interface index refers to the index of the interface within the interface cluster; and the index of the BIST circuit refers to the index of the BIST circuit corresponding to the interface, or the index of the BIST circuit used to test the interface. Optionally, when the BIST circuit includes a controller and one or more excitation circuits, the index of the BIST circuit corresponding to a certain interface may include the index of the controller corresponding to the interface and the index of the excitation circuit corresponding to the interface. In practical applications, the activation circuit can be a wrapper.

[0075] For example, the model information includes a port mapping field for indicating interface information. The format of the port mapping field can be as follows, where the interface cluster to which the interface with the interface identifier 3D_TX_DATA0 belongs is identified as 3D_IO_MACRO_1, the interface index is 10, the wrapper index is 0, and the controller index is 1. The interface cluster to which the interface with the interface identifier 3D_TX_CLK belongs is identified as 3D_IO_MACRO_1, the interface index is 11, the wrapper index is 0, and the controller index is 1.

[0076] Optionally, the interface cluster information may indicate at least one of the following: interface cluster identifier, interfaces with different functions, and interface repair information. Further, an interface cluster may also include multiple interface groups, and the interface cluster information may also be at the granularity of a single interface group to indicate interfaces with different functions within each interface group; optionally, the interface repair information may also be at the granularity of an interface group to indicate repair information for each interface group, and this interface group may also be referred to as a repair group.

[0077] The aforementioned interface cluster identifier is used to identify interface clusters; different interface clusters within the same core correspond to different interface cluster identifiers. Optionally, the interfaces with different functions may include at least one of the following: data interface, clock interface, redundant interface, floating interface, asynchronous handshake interface, etc. This interface repair information, also known as repair specification, is used to describe the repair structure of the interface cluster. Optionally, this interface repair information may include one of the following: at least one interface group's interfaces, and the repair type (or repair method) of the interface group; the repair type may include at least one of the following: left shift (shiftleft), right shift (shiftright). Based on this interface cluster information, the function and repair specification of interfaces at different indices within any interface cluster can be determined.

[0078] For example, the model information includes a macro_info field for indicating interface cluster information. The format of the macro_info field can be as follows, and it indicates that: the interface cluster identified as IO_MACRO1 includes data interfaces with indices 0 to 31, clock interfaces with indices 32 to 33, and redundant interfaces with indices 35 to 36; the interface group repair_group1 includes data interfaces with indices 0 to 15, a redundant interface with index 35, and a repair type of left shift; and the interface group repair_group2 includes data interfaces with indices 16 to 31, a redundant interface with index 36, and a repair type of right shift.

[0079] Optionally, the BIST information indicates at least one of the following: interaction mode (sync_mode), prefix_lead_code, data type (pattern type), and BIST circuit type (type). The interaction mode indicates the data interaction mode of the interconnect interface, which can be synchronous (sync) or asynchronous (asynchronous). The prefix can be a codeword used for synchronization, and the data following the prefix is ​​the test data. The data type, also known as the pattern type, indicates the type of test data and can include at least one of the following: solid, checkboard, row strip, column strip, or pseudo-random code (prb). The BIST circuit type includes one of the following: transmit (TX), receive (RX), or transmit receive (TRX). Optionally, the BIST circuit type can specifically be the type of controller in the BIST circuit. Table 3 below shows various information in the BIST information, along with descriptions and verification points for each.

[0080] Table 3

[0081] For example, the aforementioned fixed type can refer to multiple interfaces in the same interface cluster having all 0 or all 1 test data; the checkerboard type can refer to any two adjacent interfaces in the same interface cluster having opposite test data, such as one interface having 0 test data and the other having 1 test data; the row bar type can refer to any two adjacent rows of interfaces in the same interface cluster having opposite test data, such as one row of interfaces having all 0 test data and the other row having all 1 test data; the column bar type can refer to any two adjacent columns of interfaces in the same interface cluster having opposite test data, such as one column of interfaces having all 0 test data and the other column having all 1 test data.

[0082] For example, the model information includes an IOBIST_info field for indicating BIST information. The format of the IOBIST_info field can be as follows, and it indicates that the interaction mode is synchronous, the preamble is 01010101, the data type is solid, and the type of BIST circuit is TRX.

[0083] It is understood that the multiple domain segments in the model information shown above, as well as the format and indication information of each domain segment, are merely exemplary. In practical applications, the model information may also include domain segments different from the above multiple domain segments, or carry multiple pieces of information from different domain segments in the same domain segment, or carry information from the same domain segment in different domain segments, etc. This application embodiment does not specify this.

[0084] S202: Based on the first interface test information and the second interface test information, perform a matching test on the first core and the second core. The matching test includes interface interconnection, interface repair and BIST information matching test.

[0085] Optionally, the interface interconnection matching test for the first core and the second core may include: matching the interface information of any two interconnected interfaces, and matching the interconnection relationship of any interface cluster. If the interface information of all interconnected interfaces in the first core and the second core match, and the interconnection relationship of all interface clusters matches, then the interface interconnection matching test for the first core and the second core is successful.

[0086] When performing a matching test on the interface information of two interconnected interfaces, if the interface information of the two interconnected interfaces does not meet the corresponding checkpoints, such as mismatched directions or inconsistent signal types, then the two interfaces are not matched. If the interface information of the two interconnected interfaces meets the corresponding checkpoints, such as matched directions or consistent signal types, then the two interfaces are matched. For example, interface P1 in the first core is interconnected with interface P2 in the second core. Assuming that the direction of interface P1 is "in" and the signal type is "data", and the direction of interface P2 is "out" and the signal type is "data", then the direction "in" of interface P1 matches the direction "out" of interface P2, and the signal type "data" of interface P1 matches the signal type "data" of interface P2. Therefore, interface P1 and interface P2 are matched.

[0087] When performing a matching test on the interconnection relationships of interface clusters in a core particle, if one or more interface clusters in a certain core particle contain multiple interfaces in another core particle that are interconnected by multiple interfaces in another core particle that do not belong to the same interface cluster, then the interconnection relationship matching of the interface clusters fails. For any core particle in the first core particle and the second core particle, if the multiple interfaces in each interface cluster of that core particle are interconnected by multiple interfaces in another core particle that all belong to the same interface cluster, then the interconnection relationship matching of the interface clusters succeeds. For example, taking the first interface cluster in the first core particle as an example, assuming that the first interface cluster includes multiple first interfaces P11 to P1n, and the second interface cluster in the second core particle includes multiple second interfaces P21 to P2n, when the multiple first interfaces P11 to P1n are interconnected with the multiple second interfaces P21 to P2n respectively, the interconnection relationship between the first interface cluster and the second interface cluster is successfully matched.

[0088] Furthermore, when an interface cluster includes multiple interface groups, the matching of the interconnection relationship of the interface cluster can be performed at the interface group level. That is, it can be determined whether multiple interfaces of another core that are interconnected by multiple interfaces of the same interface group in any interface cluster of a core particle belong to the same interface group.

[0089] In one possible embodiment, performing an interface interconnection matching test on the first core and the second core based on the first interface test information and the second interface test information may include: performing a matching test on the interface information of any two interconnected interfaces in the first core and the second core, as well as the interconnection relationship of the interface cluster of any core, based on the interface information, interface mapping information, and interface cluster information in the first interface test information and the second interface test information.

[0090] Optionally, the interface repair matching test for the first and second core particles can be performed at the interface cluster level. This interface repair matching test may include: matching the interconnection relationships of interface groups within any interface cluster, and matching the repair types of the interface groups. If the interface repair matching tests for all interconnected interface clusters in the first and second core particles are successful, then the interface repair matching test for the first and second core particles is successful.

[0091] Taking an interface cluster comprising multiple interface groups as an example, if multiple interfaces in one interface group of an interface cluster are interconnected with multiple interfaces in another core that do not belong to the same interface group in the same interface cluster, then the interconnection relationship of the interface groups fails to match. For any core in the first and second cores, if multiple interfaces in each interface group of that core are interconnected with multiple interfaces in another core that all belong to the same interface group in the same interface cluster, then the interconnection relationship of the interface groups matches successfully. If the repair type of one interface group is different from the repair type of another interconnected interface group, for example, the repair types of the two interface groups are right shift and left shift respectively, then the repair types of the two interface groups do not match. If the repair type of one interface group is the same as the repair type of another interconnected interface group, for example, the repair type of both interface groups is right shift by 1 interface, then the repair types of the two interface groups match.

[0092] For example, as shown in Figure 8, the first interface cluster of the first core particle includes two interface groups, with multiple odd-numbered interfaces forming one interface group and multiple even-numbered interfaces forming another interface group. The second interface cluster of the second core particle interconnected with the first interface cluster also includes two interface groups, with the first part of the interfaces forming one interface group and the second part of the interfaces forming another interface group. The last interface in each interface group of the first and second interface clusters is a redundant interface, and the corresponding repair method is right shift. Therefore, the interconnection relationship of the interface groups in the first and second core particles does not match, but the repair types of the interface groups match. As a result, the interface repair matching test of the first and second core particles fails.

[0093] In one possible embodiment, performing interface interconnection matching tests on the first core and the second core based on the first interface test information and the second interface test information may include: performing matching tests on the interconnection relationship of interface groups of any interface cluster in the first core and the second core and the repair type of the interface groups based on the interface mapping information and interface cluster information in the first interface test information and the second interface test information.

[0094] Optionally, the BIST information matching test for the first and second cores may include, but is not limited to, matching the BIST information corresponding to the two interconnected interface clusters. That is, matching at least one of the following in the BIST information corresponding to the two interconnected interface clusters: interaction mode, preamble, data type, and BIST circuit type. If the matching test of the BIST information corresponding to all two interconnected interface clusters in the first and second cores is successful, then the matching test of the BIST information for the first and second cores is successful. For example, for any two interconnected interface clusters in the first and second cores, if the interaction mode, preamble, data type, and BIST circuit type in the BIST information corresponding to the interface clusters are consistent, then the matching test of the BIST information for the two interconnected interface clusters is successful; if the interaction mode, preamble, data type, or BIST circuit type in the BIST information corresponding to the interface clusters are inconsistent, then the matching test of the BIST information for the two interconnected interface clusters fails.

[0095] Specifically, for the BIST circuits in the first and second cores, when multiple interface clusters corresponding to a certain BIST circuit in one core are interconnected with multiple interface clusters corresponding to at least two BIST circuits in the other core, the BIST information of that certain BIST circuit can be matched with the BIST information of the at least two BIST circuits respectively. For example, as shown in Figure 9, both the first and second cores include two BIST circuits. The first three interface clusters in the first core correspond to BIST circuit 11, and the last two interface clusters correspond to BIST circuit 12. The first two interface clusters in the second core correspond to BIST circuit 21, and the last three interface clusters correspond to BIST circuit 22. Therefore, during the BIST information matching test, the BIST information of BIST circuit 11 can be matched with the BIST information of BIST circuit 21, and the BIST information of BIST circuit 11 can be matched with the BIST information of BIST circuit 22. Figure 9 illustrates this using an example where each BIST circuit includes a controller and a packager.

[0096] In one possible embodiment, performing a BIST information matching test on the first core and the second core may include: performing a matching test on the BIST information corresponding to multiple interconnected interface clusters in the first core and the second core based on the interface mapping information, interface cluster information, and BIST information in the first interface test information and the second interface test information.

[0097] Furthermore, the method further includes: acquiring interconnection information, which can be used to indicate the interconnection relationship between two interconnected cores and multiple interfaces in the two cores, that is, to indicate the interconnection relationship between multiple interfaces of the first core and multiple interfaces of the second core. Optionally, the interconnection information includes an identifier of the first core, an identifier of the second core, and an interface of another core interconnected by each of the multiple interfaces of either the first core or the second core. For example, the format of the interconnection information can be as follows, indicating that the two interconnected cores are dieA and dieB, that interface 3DIO_DATA0 in dieA is interconnected with interface 3DIO_DATA0 in dieB, that interface 3DIO_DATA1 in dieA is interconnected with interface 3DIO_DATA1 in dieB, and that interface 3DIO_DATA2 in dieA is interconnected with interface 3DIO_DATA2 in dieB, etc.

[0098] To facilitate understanding, the method flow of this application embodiment is illustrated below. As a possible example, the method flow may include: acquiring interconnection information between a first core and a second core, wherein the interconnection information indicates the interconnection relationship between multiple interfaces of the first core and multiple interfaces of the second core, thereby determining which interfaces require information verification based on the interconnection relationship; acquiring first model information and second model information, wherein the first model information indicates first interface test information and the second model information indicates second interface test information, thereby obtaining interface information (e.g., direction and signal type), the interface cluster to which the interface belongs, and the BIST information corresponding to the interface cluster, etc., based on the first interface test information and the second interface test information; and matching the opposite direction and type of any two interconnected interfaces. The process involves: matching the interconnection relationships of any interface cluster within a core particle to determine if the same interface cluster interconnects with multiple other interface clusters; matching the interconnection relationships of any interface group within the core particle's interface cluster to determine if an interface group interconnects with multiple other interface groups; performing interface repair matching tests on the first and second core particles, such as determining whether the interconnection relationships of the interface groups of the two interconnected interface clusters match and whether the repair types match; and performing BIST information matching tests on the first and second core particles, such as determining the corresponding BIST information based on the interconnection relationships of the interface clusters, and determining whether the interaction modes, controller types, data types, and preambles in the corresponding BIST information are consistent.

[0099] In this embodiment, for a first chip and a second chip used for packaging in the same chip, a matching test can be performed on the first chip and the second chip according to the first interface test information of the first chip indicated by the first model information and the second interface test information of the second chip indicated by the second model information. The first model information and the second model information can be a general model information generated based on the test-related structures and information in the chip. In this way, during the chip development process, the matching test of the first chip and the second chip can be directly performed according to the first model information and the second model information, so that matching does not need to be performed separately in multiple stages of chip development, thereby simplifying the matching process and improving the matching efficiency.

[0100] The foregoing mainly describes the solutions provided by the embodiments of this application from the perspective of the method flow executed by the electronic device. It is understood that, in order to achieve the above functions, the electronic device includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0101] This application embodiment can divide an electronic device into functional modules based on the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The following description uses the division of functional modules according to each function as an example.

[0102] Figure 10 shows a schematic diagram of a chip matching test device according to the above embodiments, in the case of using integrated units. This device can be an electronic device or a chip applied to an electronic device, and includes a receiving unit 301 and a processing unit 302. In one possible embodiment, the receiving unit 301 can be used to support the device in performing S201 of the above method embodiments and / or obtaining the interconnection information of the first and second chips; the processing unit 302 can be used to support the device in performing S202 of the above method embodiments and / or other technical processes described herein. All relevant content of each step involved in the above method embodiments can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0103] Based on hardware implementation, the processing unit 302 in this application embodiment can be the processor of the device, and the receiving unit 301 can be the receiver of the device. The receiver can usually be integrated with the transmitter as a transceiver. The specific transceiver can also be called a communication interface or interface circuit.

[0104] Figure 11 shows a schematic diagram of another chip matching test device according to the above embodiments provided in this application. The device can be an electronic device or a chip applied to an electronic device. The device includes a processor 312, a memory 311, a communication interface 313 and a bus 314. The processor 312, the memory 311 and the communication interface 313 are connected through the bus 314.

[0105] The processor 312 is used to control and manage the operation of the device. In one possible embodiment, the processor 312 can be used to support the device in performing S202 of the above method embodiments, and / or other steps described herein. The communication interface 313 is used to support the device in communication, such as supporting the device to communicate with other external devices.

[0106] In this embodiment, the processor 312 may be a central processing unit (CPU), graphics processing unit (GPU), image signal processor (ISP), neural-network processing unit (NPU), digital signal processor (DSP), microprocessor, microcontroller, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor 312 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc. The bus 314 may include an address bus, a data bus, a control bus, etc.

[0107] Optionally, the electronic devices in the embodiments of this application may include, but are not limited to: mobile phones, tablet computers, laptop computers, handheld computers, mobile internet devices (MID), in-vehicle devices (e.g., devices on vehicles such as cars, electric vehicles, airplanes, ships, trains, and high-speed trains), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying devices (e.g., intelligent robots, drones, airplanes), etc.

[0108] In another embodiment of this application, a chip is provided, including a processor, for calling and executing instructions stored in a memory, causing a computing device on which the chip is installed to perform the method provided in the above-described method embodiments.

[0109] In another embodiment of this application, another chip is provided, including: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is used to execute code in the memory. When the code is executed, the processor is used to execute the method provided in the above method embodiments.

[0110] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of the processing device, the embodiments of the positioning system, and the embodiments of the chip, and will not be repeated here.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0112] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0113] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0114] In another embodiment of this application, a computer-readable storage medium is also provided, which stores a computer program or instructions that, when executed on a device (which may be a microcontroller, chip, etc.), cause the device to perform the steps of the above-described method embodiments.

[0115] In another embodiment of this application, a computer program product is also provided, which includes computer instructions that, when executed by a device, cause the device to perform the steps of the above-described method embodiments.

[0116] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A matching test method of a core pellet, characterized by, The method includes: Obtain first model information and second model information. The first model information is used to indicate the first interface test information of the first chip, and the second model information is used to indicate the second interface test information of the second chip. The first chip and the second chip are chips used to be packaged in the same chip. Based on the first interface test information and the second interface test information, a matching test is performed on the first core and the second core. The matching test includes matching tests of interface interconnection, interface repair, and built-in self-test BIST information.

2. The method of claim 1, wherein, The interface test information, either the first interface test information or the second interface test information, is used to indicate the interface mapping information of the corresponding chip, and the interface mapping information is used to indicate at least one of the following: the identifier of the interface cluster, the interface index, and the index of the BIST circuit.

3. The method of claim 2, wherein, The index of the BIST circuit includes the index of the controller and the index of the excitation circuit.

4. The method according to any one of claims 1 to 3, characterized in that, The first interface test information or the second interface test information is further used to indicate the BIST information of the corresponding chip, wherein the BIST information is used to indicate at least one of the following: interaction mode, preamble, data type, and type of BIST circuit.

5. The method according to claim 4, characterized in that, The interaction modes include: synchronous or asynchronous; and / or, The data type includes at least one of the following: fixed type, checkerboard type, row bar type, column bar type, or pseudo-random code; and / or, The BIST circuit can be one of the following types: transmitting, receiving, or transmitting-receiving.

6. The method according to any one of claims 1 to 5, characterized in that, The interface test information, either the first interface test information or the second interface test information, is further used to indicate the interface information of the corresponding chip, wherein the interface information is used to indicate at least one of the following: interface identifier, direction, and signal type.

7. The method according to claim 6, characterized in that, The direction includes one of the following: input, output, input-output, or floating; and / or, The signal type includes one of the following: data signal, clock signal, floating signal, asynchronous handshake signal, and redundant interface.

8. The method according to any one of claims 1-7, characterized in that, The interface test information, either the first interface test information or the second interface test information, is further used to indicate the interface cluster information of the corresponding core, and the interface cluster information is used to indicate at least one of the following: interface cluster identifier, interfaces with different functions, and interface repair information.

9. The method according to claim 8, characterized in that, The interfaces with different functions include at least one of the following: data interface, clock interface, redundant interface, floating interface, asynchronous handshake interface; and / or, The interface repair information includes one of the following: at least one interface of an interface group, and the repair type of the interface group.

10. The method according to any one of claims 1-9, characterized in that, The interface test information, either the first interface test information or the second interface test information, is further used to indicate the corresponding chip information, which is used to indicate at least one of the following: chip identifier and version information.

11. The method according to any one of claims 1-10, characterized in that, Based on the first interface test information and the second interface test information, a matching test is performed on the first core and the second core, including: Based on the interconnection information of the first core and the second core, as well as the first interface test information and the second interface test information, a matching test is performed on the first core and the second core.

12. The method according to claim 11, characterized in that, The interconnection information is used to indicate the interconnection relationship between multiple interfaces in the first core and multiple interfaces in the second core.

13. The method according to claim 11 or 12, characterized in that, Perform interface interconnection matching tests on the first core and the second core, including: A matching test is performed on the interface information of any two interconnected interfaces in the first core and the second core, and a matching test is performed on the interconnection relationship of the interface clusters in the first core or the second core.

14. The method according to any one of claims 11-13, characterized in that, The interface repair matching test between the first core and the second core includes: A matching test is performed on the interconnection relationship of interface groups in any interface cluster of the first core or the second core, and a matching test is performed on the repair type of the interface group.

15. The method according to any one of claims 11-14, characterized in that, Perform a BIST information matching test on the first core and the second core, including: A matching test is performed on the BIST information corresponding to multiple interconnected interface clusters in the first or second core.

16. A matching test device for core particles, characterized in that, The device includes: A receiving unit is used to acquire first model information and second model information. The first model information is used to indicate the first interface test information of the first chip, and the second model information is used to indicate the second interface test information of the second chip. The first chip and the second chip are chips used to be packaged in the same chip. The processing unit is configured to perform a matching test on the first chip and the second chip based on the first interface test information and the second interface test information. The matching test includes matching tests of interface interconnection, interface repair, and built-in self-test BIST information.

17. The apparatus according to claim 16, characterized in that, The interface test information, either the first interface test information or the second interface test information, is used to indicate the interface mapping information of the corresponding chip, and the interface mapping information is used to indicate at least one of the following: the identifier of the interface cluster, the interface index, and the index of the BIST circuit.

18. The apparatus according to claim 17, characterized in that, The index of the BIST circuit includes the index of the controller and the index of the excitation circuit.

19. The apparatus according to any one of claims 16-18, characterized in that, The first interface test information or the second interface test information is further used to indicate the BIST information of the corresponding chip, wherein the BIST information is used to indicate at least one of the following: interaction mode, preamble, data type, and type of BIST circuit.

20. The apparatus according to claim 19, characterized in that, The interaction modes include: synchronous or asynchronous; and / or, The data type includes at least one of the following: fixed type, checkerboard type, row bar type, column bar type, or pseudo-random code; and / or, The BIST circuit can be one of the following types: transmitting, receiving, or transmitting-receiving.

21. The apparatus according to any one of claims 16-20, characterized in that, The interface test information, either the first interface test information or the second interface test information, is further used to indicate the interface information of the corresponding chip, wherein the interface information is used to indicate at least one of the following: interface identifier, direction, and signal type.

22. The apparatus according to claim 21, characterized in that, The direction includes one of the following: input, output, input-output, or floating; and / or, The signal type includes one of the following: data signal, clock signal, floating signal, asynchronous handshake signal, and redundant interface.

23. The apparatus according to any one of claims 16-22, characterized in that, The interface test information, either the first interface test information or the second interface test information, is further used to indicate the interface cluster information of the corresponding core, and the interface cluster information is used to indicate at least one of the following: interface cluster identifier, interfaces with different functions, and interface repair information.

24. The apparatus according to claim 23, characterized in that, The interfaces with different functions include at least one of the following: data interface, clock interface, redundant interface, floating interface, asynchronous handshake interface; and / or, The interface repair information includes one of the following: at least one interface of an interface group, and the repair type of the interface group.

25. The apparatus according to any one of claims 16-24, characterized in that, The interface test information, either the first interface test information or the second interface test information, is further used to indicate the corresponding chip information, which is used to indicate at least one of the following: chip identifier and version information.

26. The apparatus according to any one of claims 16-25, characterized in that, The processing unit is also used for: Based on the interconnection information of the first core and the second core, as well as the first interface test information and the second interface test information, a matching test is performed on the first core and the second core.

27. The apparatus according to claim 26, characterized in that, The interconnection information is used to indicate the interconnection relationship between multiple interfaces in the first core and multiple interfaces in the second core.

28. The apparatus according to claim 26 or 27, characterized in that, The processing unit is also used for: A matching test is performed on the interface information of any two interconnected interfaces in the first core and the second core, and a matching test is performed on the interconnection relationship of the interface clusters in the first core or the second core.

29. The apparatus according to any one of claims 26-28, characterized in that, The processing unit is also used for: A matching test is performed on the interconnection relationship of interface groups in any interface cluster of the first core or the second core, and a matching test is performed on the repair type of the interface group.

30. The apparatus according to any one of claims 26-29, characterized in that, The processing unit is also used for: A matching test is performed on the BIST information corresponding to multiple interconnected interface clusters in the first or second core.

31. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing instructions, the processor executing the instructions in the memory to cause the electronic device to perform the method according to any one of claims 1-15.

32. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on the device, cause the device to perform the method as described in any one of claims 1-15.

33. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a device, causes the device to perform the method as described in any one of claims 1-15.

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