Display device and display panel

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a through hole, a through-hole encapsulation area surrounding the through hole, and a display area surrounding the through-hole encapsulation area. The display panel comprises a base substrate, a display layer, a thin-film encapsulation layer, and a touch function layer that are sequentially stacked. The display panel comprises at least one light-blocking structure arranged in the through-hole encapsulation area and surrounding the through hole. The light-blocking structure comprises a bottom metal structure located in the display structure and a top metal structure located in the touch function layer, and the bottom metal structure and the top metal structure are arranged to overlap each other. The display panel can reduce the light crosstalk interference of the display area on the through hole.

Description

Display devices and display panels

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202510353769.X, filed on March 24, 2025, entitled “Display Device and Display Panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display device and a display panel. Background Technology

[0004] A punch-hole display involves creating a hole in the display area of ​​the screen and placing a camera or other light-sensing element behind it, which can effectively increase the screen-to-body ratio of the display device. However, pixel emission may cause optical crosstalk to the hole, adversely affecting the performance of the light-sensing element and reducing the user experience.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display device and display panel that reduce crosstalk interference from the display area to the through hole.

[0007] According to one aspect of this disclosure, a display panel is provided, including a through-hole, a through-hole encapsulation region surrounding the through-hole, and a display region surrounding the through-hole encapsulation region; the display panel includes a substrate, a display layer, a thin film encapsulation layer, and a touch function layer sequentially stacked;

[0008] The display panel has at least one light-blocking structure surrounding the through-hole in the through-hole encapsulation area; the light-blocking structure includes a bottom metal structure in the display layer and a top metal structure in the touch function layer, and the bottom metal structure and the top metal structure are overlapped.

[0009] According to one embodiment of the present disclosure, the display layer includes at least one gate metal layer, at least one source / drain metal layer, and a pixel electrode layer sequentially stacked on one side of the substrate; the touch function layer includes a first touch metal layer and a second touch metal layer sequentially stacked on one side of the display layer.

[0010] The light-blocking structure includes at least one auxiliary trace;

[0011] The bottom metal structure of the auxiliary wiring includes at least two of the gate metal sub-wirings located in the gate metal layer, the source / drain metal sub-wirings located in the source / drain metal layer, and the electrode metal sub-wirings located in the pixel electrode layer.

[0012] The top metal structure of the auxiliary trace includes at least one of a first touch metal sub-trace located in the first touch metal layer and a second touch metal sub-trace located in the second touch metal layer.

[0013] According to one embodiment of the present disclosure, the display layer includes multiple source / drain metal layers stacked sequentially; the auxiliary traces have corresponding source / drain metal sub-traces in any source / drain metal layer, and at least a portion of the surfaces of two adjacent source / drain metal sub-traces are interconnected; the electrode metal sub-traces are at least partially interconnected with the surface of the source / drain metal sub-traces furthest from the substrate.

[0014] The display layer further includes a pixel definition layer or a support pillar layer located on the side of the pixel electrode layer away from the substrate. The pixel definition layer or the support pillar layer is provided with a first insulating structure corresponding to each of the auxiliary traces. The first insulating structure covers each source / drain metal sub-trace and electrode metal sub-trace of the corresponding auxiliary trace.

[0015] According to one embodiment of the present disclosure, the display layer includes a multilayer wiring unit layer stacked sequentially, the wiring unit layer including a source / drain metal layer and a planarization layer located on the side of the source / drain metal layer away from the substrate.

[0016] The display panel has at least one auxiliary wiring group, and any one of the auxiliary wiring groups includes a plurality of auxiliary wirings that are adjacent to each other and sequentially surround the through hole;

[0017] In the same auxiliary routing group, any auxiliary routing has a corresponding source / drain metal sub-routes in any source / drain metal layer, and there is a gap between two adjacent source / drain metal sub-routes in the same source / drain metal layer.

[0018] Each planarization layer has a second insulation structure that corresponds one-to-one with the auxiliary routing group. The second insulation structure covers the gaps between the source and drain metal sub-routes and the source and drain metal sub-routes in the same wiring unit layer.

[0019] According to one embodiment of the present disclosure, in the same auxiliary routing group, the electrode metal sub-routes of any one of the auxiliary routings do not overlap with the electrode metal sub-routes of the other auxiliary routings; or, in the same auxiliary routing group, the electrode metal sub-routes of each of the auxiliary routings are interconnected to form a whole.

[0020] According to one embodiment of the present disclosure, the display panel has at least one auxiliary wiring group, and any one of the auxiliary wiring groups includes a plurality of auxiliary wirings that are adjacent to each other and sequentially surround the through hole.

[0021] In the same auxiliary routing group, the top metal structure of any one of the auxiliary routings is not connected to the top metal structures of the other auxiliary routings; or, in the same auxiliary routing group, the top metal structures of each of the auxiliary routings are connected to each other to form a whole.

[0022] According to one embodiment of the present disclosure, the display panel has a winding area in the through-hole encapsulation area; the auxiliary traces include inner auxiliary traces located between the winding area and the through-hole, and / or include outer auxiliary traces located between the winding area and the display area.

[0023] According to one embodiment of the present disclosure, the display layer includes at least one gate metal layer, at least one source / drain metal layer, and a pixel electrode layer sequentially stacked on one side of the substrate; the touch function layer includes a first touch metal layer and a second touch metal layer sequentially stacked on one side of the display layer.

[0024] The light-blocking structure includes at least one encapsulated barrier.

[0025] The bottom metal structure of the encapsulation dam includes at least two of the following: a gate metal sub-dam located in the gate metal layer, a source / drain metal sub-dam located in the source / drain metal layer, and an electrode metal sub-dam located in the pixel electrode layer.

[0026] The top metal structure of the encapsulation barrier includes at least one of a first touch metal sub-barrier located in the first touch metal layer and a second touch metal sub-barrier located in the second touch metal layer.

[0027] According to one embodiment of the present disclosure, the display layer includes multiple source / drain metal layers stacked sequentially, and the bottom metal structure of the encapsulation dam has a corresponding source / drain metal sub-barrier in any source / drain metal layer, and at least a portion of the surfaces of two adjacent source / drain metal sub-barriers are connected to each other.

[0028] According to one embodiment of the present disclosure, the bottom metal structure of the encapsulation dam further includes an electrode metal sub-barrier, the electrode metal sub-barrier being at least partially interconnected with the surface of the source / drain metal sub-barrier furthest from the substrate.

[0029] According to one embodiment of the present disclosure, the display layer further includes a pixel definition layer or a support pillar layer located on the side of the pixel electrode layer away from the substrate. The pixel definition layer or the support pillar layer is provided with a fourth insulating structure corresponding to the encapsulation dam. The fourth insulating structure covers the bottom metal structure of the corresponding encapsulation dam.

[0030] According to one embodiment of the present disclosure, the display panel has a transition region surrounding the through-hole in the through-hole encapsulation region; near the edge of the transition region near the display region, the step difference between the surface of the thin film encapsulation layer away from the substrate and the substrate is a first step difference; near the edge of the transition region near the through-hole, the step difference between the surface of the thin film encapsulation layer away from the substrate and the substrate is a second step difference; the first step difference is greater than the second step difference.

[0031] The metal layer of the touch function layer covers the transition area.

[0032] According to one embodiment of the present disclosure, the display panel further includes a color filter layer located on the side of the touch function layer away from the substrate, the color filter layer having a black matrix layer;

[0033] The black matrix layer covers at least a portion of the through-hole packaging area.

[0034] According to another aspect of this disclosure, a display device is provided, including the display panel described above.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] Figure 1 is a schematic diagram of the planar structure of the display panel in one embodiment of this disclosure.

[0038] Figure 2 is a partial cross-sectional view of the display panel in one embodiment of this disclosure.

[0039] Figure 3 is a schematic diagram of the planar structure of the display panel in one embodiment of this disclosure.

[0040] Figure 4 is a schematic diagram of the planar structure of the display panel in the through-hole encapsulation area in one embodiment of this disclosure.

[0041] Figure 5 is a cross-sectional view of the display panel in the through-hole encapsulation area according to one embodiment of the present disclosure.

[0042] Figure 6 is a schematic diagram of possible cross-beam optical paths in a display device.

[0043] Figure 7 is a schematic diagram of the structure of the display panel in the through-hole encapsulation area in one embodiment of this disclosure.

[0044] Figure 8 is a cross-sectional view of the display panel in the through-hole encapsulation area in the first example of this disclosure.

[0045] Figure 9 is a cross-sectional view of the display panel in the through-hole encapsulation area in the second example of this disclosure.

[0046] Figure 10 is a cross-sectional view of the display panel in the through-hole encapsulation area in the third example of this disclosure.

[0047] Figure 11 is a cross-sectional view of the display panel in the through-hole encapsulation area in the fourth example of this disclosure.

[0048] Figure 12 is a cross-sectional view of the display panel in the through-hole encapsulation area in the fifth example of this disclosure.

[0049] Figure 13 is a cross-sectional view of the display panel in the through-hole encapsulation area in the sixth example of this disclosure.

[0050] Figure 14 is a cross-sectional view of the display panel in the through-hole encapsulation area in the seventh example of this disclosure.

[0051] Figure 15 is a cross-sectional view of the display panel in the through-hole encapsulation area in the eighth example of this disclosure.

[0052] Figure 16 is a cross-sectional view of the display panel in the through-hole encapsulation area in the ninth example of this disclosure.

[0053] Figure 17 is a cross-sectional view of the display panel in the through-hole encapsulation area in the tenth example of this disclosure. Detailed Implementation

[0054] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0055] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0056] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0057] In this embodiment, the material of the metal layer can be selected from elemental metals, alloys formed from multiple elemental metals, or conductive metal oxides (e.g., conductive ITO, IGZO, etc.). The metal layer can include a single film layer or a stack of multiple sub-metal layers.

[0058] In this disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are located in different film layers, but the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate at least partially overlap.

[0059] In this disclosure, when describing structure C as covering structure D, it means that structure C is located on the side of structure D away from the substrate, and the orthographic projection of structure D on the substrate is located within the orthographic projection of structure C on the substrate.

[0060] In this disclosure, when describing directions such as inner side and outer side, the radial direction from the through hole to the display area is taken as the outward direction, and the radial direction from the display area to the through hole is taken as the inward direction. Accordingly, when describing the inner side of a structure E / region F, it refers to the area of ​​the structure E / region F that is close to the through hole; when describing one side of a structure E / region F, it refers to the side of the structure E / region F that is close to the display area.

[0061] In this disclosure, structural layer X is located on the side of structural layer Y facing away from the substrate. This can be understood as structural layer X being formed on the side of structural layer Y facing away from the substrate. When structural layer Y is a patterned structure, a portion of structural layer X may also be located at the same physical height as structural layer Y or below the physical height of structural layer Y, wherein the substrate serves as the height reference.

[0062] This disclosure provides a display panel and a display device using the display panel. Figure 1 is a schematic planar structure diagram of the display panel PNL in one embodiment of this disclosure (through holes are not shown). Referring to Figure 1, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with an array of display units DU, each display unit DU including a sub-pixel PX and a pixel driving circuit PDC driving the sub-pixel PX. The display panel PNL does not provide display units DU in the peripheral area BB, or the provided display units DU are not used for displaying images. In the example of Figure 1, the display panel PNL is provided with a plurality of scan lines GL extending along the row direction DH in the display area AA, each scan line GL corresponding to a row of display units. The pixel driving circuit PDC of each display unit DU in the row of display units is electrically connected to the corresponding scan line GL. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, each data line DL corresponding to a column of display units. Each display unit DU in the display unit column has its pixel driving circuit PDC electrically connected to its corresponding data line DL. Thus, each display unit DU's pixel driving circuit PDC is connected to a scan line GL and a data line DL. When a scan signal is applied to the scan line GL, the driving voltage applied to the data line DL can be written into the pixel driving circuit PDC, allowing the pixel driving circuit PDC to control the brightness of the sub-pixel PX based on the written driving voltage. It is understood that in other embodiments of this disclosure, the arrangement of the display units DU and the connection methods with the data lines DL and scan lines GL may differ from the example in Figure 1.

[0063] Figure 2 is a partial cross-sectional view of a display panel PNL according to one embodiment of this disclosure. In the example of Figure 2, the display panel PNL may include a substrate SBT, a display layer DPL, a thin film encapsulation layer TFE, and a touch function layer TSL stacked sequentially. The display layer DPL contains sub-pixels PX and a pixel driving circuit PDC for driving the sub-pixels PX. The thin film encapsulation layer TFE is used to encapsulate and protect the sub-pixels PX, and the touch function layer TSL is used to implement touch functionality.

[0064] In one example, referring to Figure 2, the display layer DPL may include a driving layer DRL and a pixel layer PXL stacked sequentially on one side of the substrate SBT; the pixel layer PXL contains sub-pixels PX, and the driving layer DRL contains a pixel driving circuit PDC for driving the sub-pixels PX. Each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image.

[0065] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can be polyimide.

[0066] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a transistor (e.g., a thin-film transistor) and a storage capacitor. Further, the transistor may be selected from top-gate thin-film transistors, bottom-gate thin-film transistors, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type thin-film transistor or a P-type thin-film transistor.

[0067] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. Exemplarily, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a LPS transistor. In other embodiments of this disclosure, some thin-film transistors are LPS transistors, and some thin-film transistors are MODS transistors.

[0068] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate metal layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN, stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer SCL, gate insulating layer GI, gate metal layer GT, interlayer dielectric layer ILD, and source / drain metal layer SD. The positional relationship of each layer can be determined based on the thin-film transistor's layer structure. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form partial traces or conductive structures if necessary. The gate layer can be used to form one or more gate layer traces such as scan traces, reset control traces, and light emission control traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data traces, drive power supply voltage traces, or other source / drain metal layer traces, or it can be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any one of the aforementioned semiconductor layer SCL, gate metal layer GT, source / drain metal layer SD may be multilayered. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate metal layers GT. Correspondingly, the insulating film layers in the driving layer DRL (e.g., gate insulating layer GI, interlayer dielectric layer ILD, planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed. Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer SD away from the substrate SBT to protect the source / drain metal layer SD.

[0069] In one embodiment of this disclosure, the film layer between the substrate SBT and the first source / drain metal layer SD1 can be referred to as a whole as a transistor layer TFTL. The transistor layer TFTL has a semiconductor layer SCL, a gate insulating layer GI, and a gate metal layer GT required for forming a thin film transistor. For example, in the example of FIG4, the transistor layer TFTL includes an inorganic buffer layer BUF, a polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate metal layer GT1, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a second gate metal layer GT2, and an interlayer dielectric layer ILD, which are sequentially stacked on one side of the substrate SBT. In the example shown in Figure 4, the driving layer DRL includes two semiconductor layers SCL (polysilicon semiconductor layer PSCL and metal oxide semiconductor layer OSCL), three gate insulating layers GI (first gate insulating layer GI1, second gate insulating layer GI2, and third gate insulating layer GI3), two gate metal layers GT (first gate metal layer GT1 and second gate metal layer GT2), two source drain metal layers SD (first source drain metal layer SD1 and second source drain metal layer SD2), and two planarization layers PLN (first planarization layer PLN1 and second planarization layer PLN2). The polysilicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate metal layer GT1 can form low-temperature polysilicon thin-film transistors (LTPO transistors), while the first gate metal layer GT1, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the second gate metal layer GT2 can form metal oxide thin-film transistors (MOTs). Thus, this display panel PNL is a display panel employing LTPO technology.

[0070] In one embodiment of this disclosure, the structure between the transistor layer TFTL and the pixel layer PXL can be referred to as the wiring layer MRL. One important function of the wiring layer MRL is to realize electrical connections between different devices, such as thin-film transistors, storage capacitors, and sub-pixels PX. Optionally, the wiring layer MRL may include one or more wiring unit layers MF, each wiring unit layer MF may include a source / drain metal layer SD and a planarization layer PLN located on the side of the source / drain metal layer SD away from the substrate SBT. It is understood that in some examples, the wiring unit layer MF may also include a passivation layer, which may be disposed between the source / drain metal layer SD and the planarization layer PLN to protect the source / drain metal layer SD.

[0071] For example, in the example of Figure 4, the wiring layer MRL includes a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, and a second planarization layer PLN2, which are sequentially stacked on the side of the transistor layer TFTL away from the substrate SBT. Thus, the wiring layer MRL includes two wiring unit layers MF1 (including the first source / drain metal layer SD1 and the first planarization layer PLN1) and a second wiring unit layer MF2 (including the second source / drain metal layer SD2 and the second planarization layer PLN2). When the display panel PNL requires more source / drain metal layers SD, the number of wiring unit layers MF can be adaptively increased (i.e., the source / drain metal layers SD and the planarization layer PLN are increased simultaneously). For example, when the display panel PNL is provided with three source / drain metal layers SD, the wiring layer MRL includes a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer, and a third planarization layer (the third source / drain metal layer and the third planarization layer serve as the third wiring unit layer) stacked in sequence.

[0072] In one embodiment of this disclosure, referring to FIG2, the sub-pixel PX in the pixel layer PXL is a thin-film light-emitting element, which may include two electrodes stacked together and a light-emitting functional unit sandwiched between the two electrodes. In the example of FIG2, the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area of ​​the display panel. The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes, with each pixel hole exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EFL), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PX. The light-emitting functional layer EFL at least covers the pixel electrodes exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrode and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EFL, causing the EFL to emit light. The portion of the EFL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrode, the common electrode layer COML, and the light-emitting functional unit form a sub-pixel PX. One of the pixel electrode and the common electrode layer COML serves as the anode of the sub-pixel PX, and the other serves as the cathode of the sub-pixel PX.

[0073] In one embodiment of this disclosure, the display panel further includes a support pillar layer (not shown in FIG. 2) located on the side of the pixel definition layer (PDL) away from the substrate. This support pillar layer is used to form a plurality of support pillars to support a precision metal mask during the evaporation process. In one example, the support pillar layer and the pixel definition layer (PDL) can be made of the same material and fabricated in the same process; for example, a grayscale masking process can be used on the same organic material layer to simultaneously form the pixel definition layer and the support pillar layer. In another example, after forming the pixel definition layer, a new organic material layer can be coated and patterned to form the support pillars of the support pillar layer.

[0074] In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer COML serves as the cathode of the sub-pixel PX.

[0075] In the example of Figure 2, the sub-pixel PX is an organic light-emitting diode (OLED). It is understood that in other embodiments of this disclosure, the sub-pixel may also be other types of light-emitting elements, such as current-driven light-emitting elements such as QLED, PLED, Micro LED, Mini LED, etc.

[0076] The display panel PNL illustrated in Figure 2 uses LTPO technology to drive the OLED as sub-pixels PX in its display layer DPL. It is understood that the display panel PNL of this embodiment is not limited to this; other driving technologies can be used in the driving layer DRL, and other light-emitting elements can be used in the pixel layer PXL.

[0077] In the example of Figure 2, the thin-film encapsulation layer TFE can be disposed on the surface of the pixel layer PXL away from the substrate SBT, and it can include alternately stacked inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the thin-film encapsulation layer TFE can also adopt other structures, such as multiple stacked inorganic encapsulation layers.

[0078] In the example of Figure 2, the touch functional layer TSL can be disposed on the side of the thin-film encapsulation layer TFE away from the pixel layer PXL, so that the display panel PNL has touch functionality. In the example of Figure 2, the touch functional layer TSL includes a first touch metal layer TMA, a touch insulating layer TLD, and a second touch metal layer TMB sequentially stacked on the surface of the thin-film encapsulation layer TFE. It is understood that in other examples, the touch functional layer TSL may also include an insulating layer or an organic layer covering the second touch metal layer TMB.

[0079] In the example of Figure 2, the touch functional layer (TSL) comprises two metal layers. It will be understood that in other embodiments of this disclosure, the touch functional layer (TSL) may also comprise more metal layers or employ fewer metal layers.

[0080] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may further include a color filter layer CFL located on the side of the touch functional layer TSL away from the substrate SBT. The color filter layer CFL has color filter units CFU corresponding to sub-pixels PX. For example, a red color filter unit is disposed above a red sub-pixel, a green color filter unit is disposed above a green sub-pixel, and a blue color filter unit is disposed above a blue sub-pixel. This improves the purity of the emitted color of the display panel PNL, thereby increasing its color gamut, and also reduces interference from ambient light on normal display. In one example, referring to FIG2, the color filter layer CFL also has a black matrix layer BM, which can be located between sub-pixels PX to reduce emitted crosstalk and further reduce reflection of ambient light.

[0081] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may further include a protective layer OC, which may be disposed on the surface of the display panel PNL away from the substrate SBT to protect the display panel PNL. In the example of FIG2, the protective layer OC is disposed on the surface of the color filter layer CFL away from the substrate SBT.

[0082] Figure 3 is a schematic planar structure diagram of a display panel PNL according to one embodiment of this disclosure. The display panel PNL provided in this embodiment includes a through-hole HH, a through-hole encapsulation area HA surrounding the through-hole HH, and a display area AA surrounding the through-hole encapsulation area HA.

[0083] In a display device using this display panel PNL, a photosensitive element CA (see Figure 4) can be disposed on the back of the display panel PNL. The photosensitive element CA can be configured one-to-one with a through-hole HH, and the photosensitive element CA can face the corresponding through-hole HH to receive light transmitted from the through-hole HH. The photosensitive element CA can be one or more light sensors, such as a camera, an optical fingerprint recognition chip, or a light intensity sensor. In one example, the photosensitive component can be a camera, such as a CCD (charge-coupled device) camera.

[0084] Figure 4 is a planar structural diagram of the display panel PNL at the through-hole packaging area HA in one example; Figure 5 is a cross-sectional structural diagram of the display panel PNL at the through-hole packaging area HA in one example.

[0085] In the examples of Figures 4 and 5, along the direction from the display area AA towards the via HH, the via package area HA sequentially includes a winding area HA2, a first barrier area HA3, a second barrier area HA4, and a third barrier area HA5. Within the winding area HA2, the display panel PNL is provided with a transition winding CL to ensure that the signal lines around the via HH are not interrupted by the via HH. For example, the transition winding CL may include a first transition winding for ensuring electrical continuity of the scan line GL, and a second transition winding for ensuring electrical continuity of the data line DL. Depending on the needs, one or more transition windings may be provided within the winding area HA2, bypassing the via HH, for example, encircling the via HH half a turn. Depending on the needs, the transition winding CL may be disposed on one or more metal layers of the display layer DPL, for example, the transition winding CL may be disposed on one or more metal layers such as the gate metal layer GT, the source / drain metal layer SD, etc.

[0086] Referring to Figures 4 and 5, to ensure the stable performance of the adapter winding CL, an auxiliary line area HA1 can be provided on at least one side of the winding area HA2, and the auxiliary line area HA1 is provided with auxiliary traces ML. Thus, when the adapter winding CL is fabricated using processes such as photolithography, the auxiliary traces ML can ensure that each adapter winding CL is in a generally uniform process environment, improving the fabrication yield of the adapter winding CL. In the examples of Figures 4 and 5, the auxiliary line area HA1 can include an inner auxiliary line area HA11 located inside the winding area HA2 (on the side closer to the via HH) and an outer auxiliary line area HA12 located outside the winding area HA2 (on the side closer to the display area AA). Thus, the auxiliary traces ML can include an inner auxiliary trace MLA located in the inner auxiliary line area HA11 (between the winding area HA2 and the via HH), and an outer auxiliary trace MLB located in the outer auxiliary line area HA12 (between the winding area HA2 and the display area AA).

[0087] In other examples of this disclosure, the auxiliary line area HA1 may also be set only on one side of the winding area HA2, for example, only the inner auxiliary line area HA11 or only the outer auxiliary line area HA12; correspondingly, the auxiliary routing ML may include only the inner auxiliary routing MLA or only the outer auxiliary routing MLB.

[0088] In one example, the display panel PNL can have only an inner auxiliary line area HA11 without an outer auxiliary line area HA12; that is, the display panel PNL only has an inner auxiliary trace MLA without an outer auxiliary trace MLB. On one hand, the distance between the winding area HA2 and the display area AA is relatively short, and the trace density within the display area AA is very high. Therefore, even if the display panel PNL does not have an auxiliary trace ML between the winding area HA2 and the display area AA, it will not cause a significant decrease in the yield of the transition winding CL. At the same time, by omitting the outer auxiliary line area HA12, the size of the through-hole package area HA can be reduced, thereby increasing the display area of ​​the display panel PNL. Inside the winding area HA2, the density of metal traces is relatively low. Therefore, setting an inner auxiliary line area HA11 and setting an inner auxiliary trace MLA within the inner auxiliary line area HA11 is beneficial for improving the yield of the innermost one or more transition winding CLs.

[0089] Understandably, depending on the needs of electrical connection, the auxiliary trace ML can be disconnected if necessary to ensure the electrical connection between the adapter winding CL and the display area AA. This allows the auxiliary trace ML to have one or more breaks rather than forming a complete continuous loop. Of course, the auxiliary trace ML can also form a complete continuous loop.

[0090] In one example, referring to Figures 4 and 5, one or more first dams RA are provided within the first barrier region HA3, and the first dams RA can be arranged around the through hole HH. The lower surface of the thin-film encapsulation layer TFE (the surface close to the substrate SBT, such as the lower surface of the first inorganic encapsulation layer CVD1) can cooperate with the first dams RA, thereby extending the invasion path of water and oxygen from the through hole HH to the display area AA, and improving the encapsulation effect of the through hole encapsulation region HA.

[0091] Optionally, the display panel PNL can be configured with 2 to 8 sequentially surrounding first retaining walls RA in the first retaining wall area HA3, for example, 2, 3, 4, 5, 6, 7 or 8 first retaining walls RA.

[0092] In one example, a gate metal layer GT or a source / drain metal layer SD can be used to form the first dam RA, for example, a single source / drain metal layer SD or multiple stacked source / drain metal layers SD can be used to form the first dam RA.

[0093] For example, the first dam RA is formed using a source / drain metal layer SD, which comprises multiple stacked metal sublayers (e.g., a titanium / aluminum / titanium sandwich structure, or a molybdenum-copper-molybdenum sandwich structure). Due to the different etching rates of the different metal sublayers, the sides of the first dam RA can be concave, for example, making the cross-section of the first dam RA H-shaped or T-shaped. Thus, when forming the thin-film encapsulation layer TFE, the first dam RA can not only increase the water and oxygen intrusion path, but also block the continuity of the organic encapsulation layer IJP, further improving the encapsulation effect.

[0094] In one embodiment of this disclosure, referring to Figures 4 and 5, the display panel PNL has at least one encapsulation dam RD surrounding the through-hole HH within the second barrier region HA4. During the fabrication of the thin-film encapsulation layer TFE, this encapsulation dam RD can block the organic encapsulation layer IJP, preventing it from overflowing into the inner side of the encapsulation dam RD, thereby ensuring that the organic encapsulation layer IJP is covered by the inorganic encapsulation layer. Thus, within the second barrier region HA4, the organic encapsulation layer IJP is no longer required within the thin-film encapsulation layer TFE, leaving only the inorganic encapsulation layer. This inorganic encapsulation layer can cooperate with the encapsulation dam RD to achieve effective encapsulation and prevent water and oxygen intrusion. The encapsulation dam RD is convex, which lengthens the water and oxygen intrusion path, thereby improving the encapsulation effect.

[0095] In the example disclosed herein, only one encapsulation dam RD is provided within the second retaining wall area HA4. This reduces the size of the through-hole encapsulation area HA, thereby improving the display effect and user experience. It is understood that in other embodiments of this disclosure, the number of encapsulation dam RDs can be multiple, for example, 2 to 4 encapsulation dam RDs can be provided sequentially around the through-hole HH.

[0096] In one embodiment of this disclosure, referring to Figures 4 and 5, the display panel PNL has at least one second dam RB surrounding the through hole HH within the third retaining wall area HA5, for example, 2 to 9 second dam RBs are provided sequentially surrounding the through hole HH. When the display panel PNL is cut to form the through hole HH, the second dam RB can suppress and block cracks generated at the edge of the through hole HH, avoiding cracks from causing defects in the display panel PNL.

[0097] In one example, during the preparation of the thin-film encapsulation layer TFE, the first inorganic encapsulation layer CVD1 can be combined with the second dam RB to further increase the water and oxygen intrusion pathway.

[0098] In one example, the second dam RB can be fabricated using at least one of the source / drain metal layer SD or the gate metal layer GT.

[0099] In one embodiment of this disclosure, referring to FIG5, the display device may further be provided with a transparent cover plate CG, which may be disposed on the light-emitting side of the display panel PNL. For example, the transparent cover plate CG is disposed on the side of the pixel layer PXL away from the substrate SBT.

[0100] In one embodiment of this disclosure, referring to FIG. 5, the display device may further be provided with a back film BF, which may be disposed on the backlight side of the display panel PNL, for example, on the side of the substrate SBT away from the pixel layer PXL. The back film BF can protect and support the display panel PNL. In one example, referring to FIG. 5, the back film BF may be provided with through holes for avoiding the photosensitive element CA.

[0101] Referring to Figure 6, a display device using this display panel PNL can have a photosensitive element CA installed at the through-hole HH, for example, a camera. If light emitted from the display area AA shines onto the through-hole HH, it will affect the final effect of the photosensitive element CA. Taking smartphones as an example, the camera performance is a key concern for both manufacturers and users. Although in most cases, the camera performance depends primarily on the camera configuration and its performance, it has been found that light emitted from the display area AA shining onto the through-hole HH has a significant and direct impact on the image quality. In this disclosure, the phenomenon of light from the display area AA shining onto the through-hole HH and affecting the photosensitive element CA within the through-hole HH is referred to as light crosstalk interference from the display area AA to the through-hole HH. As the size of the through-hole package area HA becomes smaller, the light crosstalk interference from the display area AA to the through-hole HH becomes increasingly prominent. This light crosstalk interference from the display area AA to the through-hole HH affects color difference in images, resulting in a poorer user experience.

[0102] Figure 6 is a schematic diagram of possible crosstalk optical paths in a display device. In the examples in Figure 6, optical path A indicates that the light emitted from sub-pixel PX is reflected by the metal layer of the touch function layer TSL and then illuminates the via HH. Optical path B indicates that the light emitted from sub-pixel PX is reflected by the transparent cover plate CG and then illuminates the via HH. Optical path C indicates that the light emitted from sub-pixel PX is reflected by metal structures such as the source / drain metal layer SD and the gate metal layer GT, and then reflected by multiple film layers before illuminating the via HH. Optical path D indicates that the light emitted from sub-pixel PX directly illuminates the via HH. As can be seen from Figure 6, if the structure within the via package region HA is not improved, the light emitted from sub-pixel PX can illuminate the via HH through multiple paths, resulting in a strong level of crosstalk interference from the display area AA to the via HH. In particular, as the width of the via package region HA decreases, some crosstalk paths will be further enhanced, leading to a more prominent crosstalk interference from the display area AA to the via HH.

[0103] Based on this, this disclosure improves at least one structure of the display panel PNL within the through-hole encapsulation region HA to reduce or eliminate crosstalk interference from the display region AA to the through-hole HH, thereby improving the performance of the photosensitive element CA using the display panel PNL. Referring to Figure 7, the display panel PNL of this disclosure has at least one light-blocking structure M0 surrounding the through-hole HH in the through-hole encapsulation region HA; the light-blocking structure M0 includes a bottom metal structure MA located in the display layer DPL and a top metal structure MB located in the touch functional layer TSL, and the bottom metal structure MA and the top metal structure MB are overlapped. In this embodiment, the light-blocking structure M0 includes the overlapping bottom metal structure MA and the top metal structure MB, both of which are made of metallic material and are opaque. Their overlap forms a light-shielding barrier, thereby blocking at least part of the light from the display region AA. Furthermore, since the bottom metal structure MA and the top metal structure MB are stacked together, only light that can enter between the bottom metal structure MA and the top metal structure MB can be reflected by the upper surface of the bottom metal structure MA or the lower surface of the top metal structure MB towards the through hole HH. Therefore, the bottom metal structure MA and the top metal structure MB block each other, effectively reducing light leakage in the direction of the display area AA.

[0104] In one embodiment of this disclosure, referring to Figures 8 to 14, the light-blocking structure M0 includes at least one auxiliary trace ML; the bottom metal structure MA of the auxiliary trace ML includes at least two of the gate metal sub-trace LG located on the gate metal layer GT, the source / drain metal sub-trace LSD located on the source / drain metal layer SD, and the electrode metal sub-trace LPE located on the pixel electrode layer PEL; the top metal structure MB of the auxiliary trace ML includes at least one of the first touch metal sub-trace LTA located on the first touch metal layer TMA and the second touch metal sub-trace LTB located on the second touch metal layer TMB.

[0105] In conventional techniques, the auxiliary trace ML only includes a sub-trace located on the gate metal layer GT or a sub-trace located on the source / drain metal layers SD. In this embodiment, more metal layers can be used to fabricate the auxiliary trace ML, which blocks light from the display area AA without adding any new structures. Optionally, adjacent sub-traces of the bottom metal structure MA of the auxiliary trace ML are overlapped. This ensures that the bottom metal structure MA has a smaller gap and better light-blocking effect.

[0106] In this embodiment of the disclosure, adjacent sub-traces of the bottom metal structure MA of the auxiliary trace ML can be interconnected or separated by an insulating layer. For example, the bottom metal structure MA of the auxiliary trace ML can employ a light-blocking strategy of continuous metal stacking or a light-blocking strategy of non-continuous metal stacking at the wiring layer MRL.

[0107] For example, in the examples of Figures 8, 10, 11, and 13, the bottom metal structure MA of the auxiliary trace ML employs a light-blocking strategy of continuous metal stacking in the wiring layer MRL. In these examples, the display layer DPL includes multiple source / drain metal layers SD stacked sequentially. The bottom metal structure MA of the auxiliary trace ML has a corresponding source / drain metal sub-trace LSD in any source / drain metal layer SD, and at least a portion of the surfaces of two adjacent source / drain metal sub-traces LSD are interconnected. The electrode metal sub-trace LPE is at least partially interconnected with the surface of the source / drain metal sub-trace LSD furthest from the substrate SBT. The display layer DPL also includes a pixel definition layer PDL and / or a support pillar layer located on the side of the pixel electrode layer PEL furthest from the substrate SBT. One or both of the pixel definition layer PDL and the support pillar layer are provided with a first insulating structure LC corresponding one-to-one with the auxiliary trace ML. The first insulating structure LC covers each source / drain metal sub-trace LSD and electrode metal sub-trace LPE of the corresponding auxiliary trace ML.

[0108] In these examples, adjacent source / drain metal sub-traces (LSD) and electrode metal sub-traces (LPE) of the same bottom metal structure (MA) are stacked sequentially to form a tall metal barrier, which can effectively block light. The auxiliary trace (ML) is equipped with a first insulating structure (LC), which covers the metal barrier formed by each source / drain metal sub-traces (LSD) and electrode metal sub-traces (LPE), thereby effectively stabilizing the structure of these metal barriers, such as reducing the risk of metal barrier collapse.

[0109] For another example, in the examples of Figures 9 and 12, the bottom metal structure MA of the auxiliary trace ML uses a light-blocking strategy of discontinuous metal stacking on the wiring layer MRL. In these examples, the display layer DPL includes a multilayer wiring unit layer MF stacked sequentially. The wiring unit layer MF includes a source / drain metal layer SD and a planarization layer PLN located on the side of the source / drain metal layer SD away from the substrate SBT. The display panel PNL has at least one auxiliary trace group MLS. Each auxiliary trace group MLS includes a plurality of auxiliary traces ML adjacent to each other and sequentially surrounding the via HH. In the same auxiliary trace group MLS, the bottom metal structure MA of any auxiliary trace ML has a corresponding source / drain metal sub-trace LSD in any source / drain metal layer SD, and there is a gap between two adjacent source / drain metal sub-traces LSD in the same source / drain metal layer SD. Each planarization layer PLN has a second insulating structure LSC corresponding one-to-one with the auxiliary trace group MLS. The second insulating structure LSC covers the gap between each source / drain metal sub-trace LSD in the same wiring unit layer MF and each source / drain metal sub-trace LSD.

[0110] In these examples, there is a risk of residual metal particles between two adjacent source / drain metal sub-traces (LSDs) located in the same source / drain metal layer (SD). Without treatment, these residual metal particles can lead to a decrease in panel yield. In this example, after each source / drain metal sub-traces (LSDs) of a wiring unit layer (MF) is formed, a planarization layer (PLN) of that wiring unit layer (MF) needs to be fabricated. This PLN forms a second insulating structure (LSC) that covers adjacent source / drain metal sub-traces (LSDs) and the gaps between them. Thus, even if metal particles remain in the gaps between the source / drain metal sub-traces (LSDs), these particles are covered and fixed by the second insulating structure (LSC) and will not transfer to other areas (e.g., to the display area AA) in subsequent fabrication processes. This effectively improves the fabrication yield of the display panel PNL.

[0111] In these examples, adjacent source / drain metal sub-traces LSD of the same auxiliary trace ML can be separated by a planarization layer PLN; however, considering the sequential interception of light by the auxiliary trace ML in the auxiliary trace group MLS, and the fact that the source / drain metal sub-traces LSD themselves have a certain width, the auxiliary trace ML can still play a good light-blocking role.

[0112] In this embodiment of the disclosure, the electrode metal sub-traces LPE of two adjacent auxiliary traces ML of the auxiliary trace group MLS can be connected to each other as a whole, or they can be independent of each other.

[0113] For example, in the examples of Figures 8 and 11, within the same auxiliary trace group MLS, the electrode metal sub-trace LPE of any one auxiliary trace ML does not overlap with the electrode metal sub-trace LPEs of the other auxiliary traces ML, and there is a gap between adjacent electrode metal sub-trace LPEs. Furthermore, within the same auxiliary trace group MLS, the first insulating structure LC of any one auxiliary trace ML is not connected to the first insulating structure LC of the other auxiliary traces ML, and there is a gap between adjacent first insulating structures LC. Thus, the electrode metal sub-trace LPE and the first insulating structure LC form an independent unit. This allows the first inorganic encapsulation layer CVD1 of the thin-film encapsulation layer TFE to have a more tortuous surface, thereby extending the water and oxygen intrusion path.

[0114] For another example, in the examples of Figures 9 and 12, within the same auxiliary trace group MLS, the electrode metal sub-traces LPE of each auxiliary trace ML are interconnected to form a whole. In other words, the structure of the auxiliary trace group MLS located in the pixel electrode layer PEL covers the gaps between the auxiliary traces ML. Furthermore, the first insulating structure LC of each auxiliary trace ML in the same auxiliary trace group MLS is interconnected to form a whole.

[0115] In this embodiment of the disclosure, the top metal structures MB of two adjacent auxiliary traces ML of the auxiliary trace group MLS can be connected to each other as a whole, or they can be independent of each other.

[0116] For example, in the examples of Figures 8 and 11, in the same auxiliary trace group MLS, the top metal structure MB of any one of the auxiliary traces ML is not connected to the top metal structures MB of the other auxiliary traces ML, and there is a gap between two adjacent top metal structures MB.

[0117] For another example, in the examples of Figures 9 and 12, within the same auxiliary trace group MLS, the top metal structures MB of each auxiliary trace ML are interconnected to form a whole. In other words, the metal structure of the auxiliary trace group MLS covers the gaps between the auxiliary traces ML in the touch function layer TSL.

[0118] In this embodiment of the disclosure, the auxiliary trace ML in the touch function layer TSL may include only the first touch metal sub-trace LTA, or only the second touch metal sub-trace LTB, or a stack of the first touch metal sub-trace LTA and the second touch metal sub-trace LTB.

[0119] For example, in the examples of Figures 8-14, the top metal structure MB of the auxiliary trace ML includes a first touch metal sub-trace LTA and a second touch metal sub-trace LTB stacked together. In the examples of Figures 8-14, the orthographic projection of the second touch metal sub-trace LTB onto the substrate SBT lies within the orthographic projection of the first touch metal sub-trace LTA onto the substrate SBT. It is understood that in other examples of this disclosure, the second touch metal sub-trace LTB may also cover the first touch metal sub-trace LTA, for example, the orthographic projection of the first touch metal sub-trace LTA onto the substrate SBT lies within the orthographic projection of the second touch metal sub-trace LTB onto the substrate SBT.

[0120] In one embodiment of this disclosure, the auxiliary trace ML in the touch functional layer TSL may consist only of a metal structure, such as only a first touch metal sub-trace LTA or a second touch metal sub-trace LTB, or both a first touch metal sub-trace LTA and a second touch metal sub-trace LTB stacked together. In another embodiment of this disclosure, referring to FIG14, the auxiliary trace ML in the touch functional layer TSL may further include a third insulating structure LTC located in the touch insulating layer TLD, the third insulating structure LTC being sandwiched between the first touch metal sub-trace LTA and the second touch metal sub-trace LTB, or the third insulating structure LTC covering the second touch metal sub-trace LTB. In one example, the auxiliary trace ML in the touch functional layer TSL includes a first touch metal sub-trace LTA, a third insulating structure LTC, and a second touch metal sub-trace LTB stacked sequentially. In this configuration, the third insulating structure LTC is disposed on the surface of the first touch metal sub-trace LTA away from the substrate SBT, and the orthographic projection of the third insulating structure LTC onto the substrate SBT lies within the orthographic projection of the first touch metal sub-trace LTA onto the substrate SBT. The second touch metal sub-trace LTB covers the third insulating structure LTC, meaning the orthographic projection of the second touch metal sub-trace LTB onto the substrate SBT covers the orthographic projection of the third insulating structure LTC onto the substrate SBT. Furthermore, the second touch metal sub-trace LTB covers both the third insulating structure LTC and the first touch metal sub-trace LTA. Thus, the third insulating structure LTC can raise the top surface of the second touch metal sub-trace LTB, thereby increasing the total height of the top metal structure MB and improving the light-blocking effect of the auxiliary trace ML.

[0121] In this embodiment of the disclosure, the display panel PNL can have auxiliary traces ML provided in one or both of the inner auxiliary line area HA11 and the outer auxiliary line area HA12. For example, the display panel PNL can have an inner auxiliary trace MLA provided in the inner auxiliary line area HA11, or an outer auxiliary trace MLB provided in the outer auxiliary line area HA12, or an inner auxiliary trace MLA provided in the inner auxiliary line area HA11 and an outer auxiliary trace MLB provided in the outer auxiliary line area HA12. Since the outer auxiliary trace MLB is closer to the sub-pixel PX, the outer auxiliary trace MLB has a better light-blocking effect.

[0122] The auxiliary routing ML in the embodiments of this disclosure is illustrated below with reference to several examples.

[0123] Figure 8 is a schematic diagram of the structure of the display panel PNL in the first example of this disclosure. In the example of Figure 8, the display panel PNL has two inner auxiliary traces MLA in the inner auxiliary line area HA11, and the two inner auxiliary traces MLA are arranged around the via HH in sequence. The bottom metal structure MA of the inner auxiliary trace MLA includes a first gate metal sub-trace LG1 located in the first gate metal layer GT1, a second gate metal sub-trace LG2 located in the second gate metal layer GT2, a first source drain metal sub-trace LSD1 located in the first source drain metal layer SD1, a second source drain metal sub-trace LSD2 located in the second source drain metal layer SD2, and an electrode metal sub-trace LPE located in the pixel electrode layer PEL. The first source drain metal sub-trace LSD1, the second source drain metal sub-trace LSD2, and the electrode metal sub-trace LPE are stacked and connected in sequence, and the first insulating structure LC covers the stacked structure formed by the first source drain metal sub-trace LSD1, the second source drain metal sub-trace LSD2, and the electrode metal sub-trace LPE. The top metal structure MB of the inner auxiliary trace MLA includes a first touch metal sub-trace LTA located in the first touch metal layer TMA and a second touch metal sub-trace LTB located in the second touch metal layer TMB. The first touch metal sub-trace LTA and the second touch metal sub-trace LTB are stacked and connected sequentially. In the example of Figure 8, the two inner auxiliary traces MLA are independent, and the metal structures of the two inner auxiliary traces MLA in the same layer are not connected to each other. Referring to Figure 8, due to the obstruction of the metal structure in the inner auxiliary trace MLA, only the light between light rays E1 and E2 can pass through the inner auxiliary trace MLA. Therefore, the inner auxiliary trace MLA can effectively reduce the crosstalk interference of the display area AA to the via HH.

[0124] Figure 9 is a schematic diagram of the structure of the display panel PNL in the second example of this disclosure. In the example of Figure 9, the display panel PNL has two inner auxiliary lines MLA in the inner auxiliary line area HA11, and the two inner auxiliary lines MLA are arranged to surround the via HH in sequence. The two inner auxiliary lines MLA form an auxiliary line group MLS. For any one inner auxiliary line MLA, the bottom metal structure MA of the inner auxiliary line MLA includes a first gate metal sub-line LG1 located in the first gate metal layer GT1, a second gate metal sub-line LG2 located in the second gate metal layer GT2, a first source drain metal sub-line LSD1 located in the first source drain metal layer SD1, a second source drain metal sub-line LSD2 located in the second source drain metal layer SD2, and an electrode metal sub-line LPE located in the pixel electrode layer PEL. In the first wiring unit layer MF1, the first source-drain metal layer SD1 forms two first source-drain metal sub-traces LSD1. The first planarization layer PLN1 forms a second insulating structure LSC1 that covers both first source-drain metal sub-traces LSD1 and the gap between them. Thus, the metal particles between the two first source-drain metal sub-traces LSD1 can be fully encapsulated by the second insulating structure LSC1. In the second wiring unit layer MF2, the second source-drain metal layer SD2 forms two second source-drain metal sub-traces LSD2. The second planarization layer PLN2 forms a second insulating structure LSC2 that covers both second source-drain metal sub-traces LSD2 and the gap between them. Thus, the metal particles between the two second source-drain metal sub-traces LSD2 can be fully encapsulated by the second insulating structure LSC2. Thus, a second insulating structure LSC1 is sandwiched between the first source / drain metal sub-trace LSD1 and the second source / drain metal sub-trace LSD2, and a second insulating structure LSC2 is sandwiched between the electrode metal sub-trace LPE and the second source / drain metal sub-trace LSD2. In the example of Figure 9, the electrode metal sub-trace LPE overlaps with both second source / drain metal sub-traces LSD2, meaning that the electrode metal sub-traces LPE of the two inner auxiliary traces MLA are interconnected as a whole. The first insulating structure LC covers the electrode metal sub-trace LPE. The top metal structure MB of the inner auxiliary trace MLA includes a first touch metal sub-trace LTA located in the first touch metal layer TMA and a second touch metal sub-trace LTB located in the second touch metal layer TMB, with the first touch metal sub-trace LTA and the second touch metal sub-trace LTB stacked and connected sequentially. In the example of Figure 9, the first touch metal sub-trace LTA of the two inner auxiliary traces MLA are connected to each other as a whole, and the second touch metal sub-trace LTB of the two inner auxiliary traces MLA are connected to each other as a whole.In this example, although the presence of the second insulating structures LSC1 and LSC2 creates light-transmitting gaps between the first source / drain metal sub-trace LSD1, the second source / drain metal sub-trace LSD2, and the electrode metal sub-trace LPE, the setting of the auxiliary trace MLA within two turns further blocks the transmitted light, effectively reducing the light transmission in these gaps.

[0125] Figure 10 is a schematic diagram of the structure of the display panel PNL in the third example of this disclosure. In the example of Figure 10, the display panel PNL has an external auxiliary trace MLB in the external auxiliary line area HA12. The bottom metal structure MA of the external auxiliary trace MLB includes a first gate metal sub-trace LG1 located in the first gate metal layer GT1, a second gate metal sub-trace LG2 located in the second gate metal layer GT2, a first source drain metal sub-trace LSD1 located in the first source drain metal layer SD1, a second source drain metal sub-trace LSD2 located in the second source drain metal layer SD2, and an electrode metal sub-trace LPE located in the pixel electrode layer PEL. The first source drain metal sub-trace LSD1, the second source drain metal sub-trace LSD2, and the electrode metal sub-trace LPE are stacked and connected in sequence, and the first insulating structure LC covers the stacked structure formed by the first source drain metal sub-trace LSD1, the second source drain metal sub-trace LSD2, and the electrode metal sub-trace LPE. The top metal structure MB of the external auxiliary trace MLB includes a first touch metal sub-trace LTA located in the first touch metal layer TMA and a second touch metal sub-trace LTB located in the second touch metal layer TMB. The first touch metal sub-trace LTA and the second touch metal sub-trace LTB are stacked and connected sequentially. In the example of Figure 10, the external auxiliary trace MLB is closer to the sub-pixel PX, which allows the external auxiliary trace MLB to achieve a better light-shielding effect.

[0126] Figure 11 is a schematic diagram of the structure of the display panel PNL in the fourth example of this disclosure. In the example of Figure 11, the display panel PNL has two external auxiliary traces MLB that sequentially surround the through hole HH in the external auxiliary line area HA12. The structure of each external auxiliary trace MLB is basically similar to the structure of the external auxiliary trace MLB illustrated in Figure 10.

[0127] Figure 12 is a schematic diagram of the structure of the display panel PNL in the fifth example of this disclosure. In the example of Figure 12, the display panel PNL has two external auxiliary traces MLB in the outer auxiliary line area HA12. The two external auxiliary traces MLB are arranged sequentially around the through hole HH and form an auxiliary trace group MLS. The structure of the auxiliary trace group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary trace group MLS in the inner auxiliary line area HA11 shown in the example of Figure 9.

[0128] Figure 13 is a schematic diagram of the display panel PNL in the sixth example of this disclosure. In this example of Figure 13, the display panel PNL has two inner auxiliary traces MLA that sequentially surround the through hole HH in the inner auxiliary line area HA11, and one outer auxiliary trace MLB in the outer auxiliary line area HA12. In this example, the structure of the two inner auxiliary traces MLA in the inner auxiliary line area HA11 is basically similar to the structure of the two inner auxiliary traces MLA in the example of Figure 8, and the structure of the outer auxiliary trace MLB in the outer auxiliary line area HA12 is basically similar to the structure of the outer auxiliary trace MLB in the example of Figure 10.

[0129] Figure 14 is a schematic diagram of the structure of the display panel PNL in the seventh example of this disclosure. In the example of Figure 14, the display panel PNL has two inner auxiliary traces MLA that surround the through hole HH in the inner auxiliary line area HA11. The inner auxiliary traces MLA in this example are basically similar to the inner auxiliary traces MLA shown in Figure 8. The main difference is that the inner auxiliary traces MLA shown in Figure 14 contain a third insulating structure LTC located in the touch insulating layer TLD. The third insulating structure LTC is sandwiched between the first touch metal sub-trace LTA and the second touch metal sub-trace LTB.

[0130] It is understandable that in the examples shown in Figures 8 to 14, the display panel PNL has two source / drain metal layers SD (i.e., the first source / drain metal layer SD1 and the second source / drain metal layer SD2). Therefore, the auxiliary trace ML can have a first source / drain metal sub-trace LSD1 and a second source / drain metal sub-trace LSD2. It is also understandable that when the display panel PNL has more source / drain metal layers SD, the auxiliary trace ML can have more source / drain metal sub-trace LSD.

[0131] In the examples of Figures 8 to 14, the first insulating structure LC is formed by the pixel definition layer (PDL). It is understood that in other embodiments of this disclosure, the first insulating structure LC may also be formed by the support pillar layer, or it may be formed together with the support pillar layer and the pixel definition layer (PDL).

[0132] In some embodiments of this disclosure, the encapsulation dam RD can also be used as the light-blocking structure MO. Referring to FIG15, the bottom metal structure MA of the encapsulation dam RD includes at least two of the gate metal sub-dam located on the gate metal layer GT, the source / drain metal sub-dam DSD located on the source / drain metal layer SD, and the electrode metal sub-dam DPE located on the pixel electrode layer PEL; the top metal structure MB of the encapsulation dam RD includes at least one of the first touch metal sub-dam DTA located on the first touch metal layer TMA and the second touch metal sub-dam DTB located on the second touch metal layer TMB. In related technologies, the encapsulation dam RD is basically formed of organic materials, and its main function is to prevent the organic encapsulation layer IJP from overflowing. However, in this embodiment, by setting a metal structure in the encapsulation dam RD, the encapsulation dam RD can have a light-blocking effect.

[0133] In one embodiment of this disclosure, the display layer DPL includes multiple source / drain metal layers SD stacked sequentially. The bottom metal structure MA of the encapsulation dam RD has a corresponding source / drain metal sub-dam DSD in any one of the source / drain metal layers SD, and at least a portion of the surfaces of two adjacent source / drain metal sub-dam DSDs are connected to each other. Thus, a higher light-blocking height can be achieved by stacking the source / drain metal sub-dam DSDs.

[0134] In one embodiment of this disclosure, the bottom metal structure MA of the encapsulation dam RD further includes an electrode metal sub-dam, the electrode metal sub-dam DPE, which is at least partially interconnected with the surface of the source / drain metal sub-dam DSD furthest from the substrate SBT. Thus, the electrode metal sub-dam DPE can further increase the metal stacking height of the bottom metal structure MA, further improving the light-blocking effect.

[0135] For example, in the example of Figure 15, the encapsulation dam RD includes a first source / drain metal sub-dam DSD1 located on the first source / drain metal layer SD1, a second source / drain metal sub-dam DSD2 located on the second source / drain metal layer SD2, and an electrode metal sub-dam DPE located on the pixel electrode layer PEL. The first source / drain metal sub-dam DSD1, the second source / drain metal sub-dam DSD2, and the electrode metal sub-dam DPE are stacked sequentially and connected to form a continuous metal stack structure. In this example, the display panel PNL has two source / drain metal layers SD, therefore two source / drain metal sub-dams DSD are provided. It is understood that when the display panel PNL has more source / drain metal layers SD, the encapsulation dam RD can also have more source / drain metal sub-dams DSD.

[0136] In one embodiment of this disclosure, the display layer DPL further includes a pixel definition layer PDL and / or a support pillar layer located on the side of the pixel electrode layer PEL away from the substrate SBT. One or both of the pixel definition layer PDL and the support pillar layer are provided with a fourth insulating structure DC corresponding one-to-one with the package barrier RD. The fourth insulating structure DC covers the bottom metal structure MA of the corresponding package barrier RD. For example, in the example of FIG15, the fourth insulating structure DC covers the metal stack formed by the first source / drain metal sub-barrier DSD1, the second source / drain metal sub-barrier DSD2, and the electrode metal sub-barrier DPE. It is understood that in other embodiments of this disclosure, the fourth insulating structure DC may also be formed by the support pillar layer, or the pixel definition layer and the support pillar layer may be formed together.

[0137] In the example of Figure 15, the first source / drain metal sub-barrier DSD1, the second source / drain metal sub-barrier DSD2, and the electrode metal sub-barrier DPE are stacked and connected sequentially. It is understood that in other embodiments of this disclosure, a lifting unit formed by an insulating layer may also be provided between adjacent metal layers of the first source / drain metal sub-barrier DSD1, the second source / drain metal sub-barrier DSD2, and the electrode metal sub-barrier DPE; furthermore, the upper metal layer may cover the lower lifting unit, so that the lower lifting unit can substantially raise the light-blocking height of the upper metal layer. For example, a first lifting unit located on the first planarization layer PLN1 may be provided between the first source / drain metal sub-barrier DSD1 and the second source / drain metal sub-barrier DSD2, and the second source / drain metal sub-barrier DSD2 may cover the first lifting unit, so that the second source / drain metal sub-barrier DSD2 can also form effective light blocking on the side of the first lifting unit. For another example, a second lifting unit located in the second planarization layer PLN2 can be provided between the second source drain metal sub-barrier DSD2 and the electrode metal sub-barrier DPE. The electrode metal sub-barrier DPE covers the second lifting unit, which allows the electrode metal sub-barrier DPE to also form effective light blocking on the side of the second lifting unit.

[0138] In the example of Figure 15, the top metal structure MB of the encapsulation dam RD includes a first touch metal sub-dam DTA located in the first touch metal layer TMA and a second touch metal sub-dam DTB located in the second touch metal layer TMB. The first touch metal sub-dam DTA and the second touch metal sub-dam DTB are stacked and connected, without a touch insulating layer TLD between them. It is understood that in some other embodiments of this disclosure, the encapsulation dam RD may further include a third lifting unit located in the touch insulating layer TLD, which may be located between the first touch metal sub-dam DTA and the second touch metal sub-dam DTB. Further, the second touch metal sub-dam DTB covers the third lifting unit. It is also understood that in some other embodiments of this disclosure, the top metal structure MB of the encapsulation dam RD may include only the first touch metal sub-dam DTA or only the second touch metal sub-dam DTB; or, the encapsulation dam RD may not provide the first touch metal sub-dam DTA, but instead provide a third raising unit and a second touch metal sub-dam DTB covering the third raising unit.

[0139] Referring to FIG16, in some embodiments of this disclosure, the display panel PNL has a transition region HA6 surrounding the via HH in the via encapsulation region HA; near the edge of the transition region HA6 close to the display region AA, the step difference between the surface of the thin film encapsulation layer TFE away from the substrate SBT and the substrate SBT is a first step difference H1; near the edge of the transition region HA6 close to the via HH, the step difference between the surface of the thin film encapsulation layer TFE away from the substrate SBT and the substrate SBT is a second step difference H2; the first step difference H1 is greater than the second step difference H2; the metal layer of the touch function layer TSL covers the transition region HA6.

[0140] Referring to Figure 16, due to the obstruction of the encapsulation dam RD, the organic encapsulation layer IJP will not cross the area where the encapsulation dam RD is located. However, the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 will cross the area where the encapsulation dam RD is located and continue to extend towards the via HH to ensure that the organic encapsulation layer IJP is sealed with an inorganic layer. Therefore, along the direction from the display area AA to the via HH, the thin film encapsulation layer TFE exhibits the characteristic of the organic encapsulation layer IJP gradually disappearing and the thickness of the thin film encapsulation layer TFE decreasing in this transition region HA6. The part of the thin film encapsulation layer TFE covering the encapsulation dam RD no longer has the organic encapsulation layer IJP, and after crossing the organic encapsulation layer IJP, it will gradually descend as the encapsulation dam RD approaches the downward slope of the via HH. Thus, at the end of the transition region HA6 near the via HH, the height of the upper surface of the thin film encapsulation layer TFE (e.g., the surface of the second inorganic encapsulation layer CVD2 away from the substrate SBT) is relatively low. In related technologies, the metal layer of the touch functional layer TSL does not cover the transition region HA6; however, in this embodiment, the metal layer of the touch functional layer TSL can cover the transition region HA6. By utilizing the step difference of the upper surface of the thin film encapsulation layer TFE on the inner side (the side near the via HH) and the outer side (the side near the display area AA) of the transition region HA6, a continuous metal structure with a large step difference is formed. This allows the metal structure of the touch functional layer TSL to have a large step difference within the transition region HA6, thereby playing the role of a metal light-blocking wall.

[0141] It is understandable that within the transition region HA6, the upper surface of the thin-film encapsulation layer TFE may not decrease sequentially from the outside to the inside (from the display area AA towards the via HH); the upper surface of the thin-film encapsulation layer TFE may have fluctuations within the transition region HA6. For example, in the example of Figure 16, the transition region HA6 spans the encapsulation barrier RD; the thin-film encapsulation layer TFE has an organic encapsulation layer IJP on the outer portion of the transition region HA6; the thin-film encapsulation layer TFE spans the encapsulation barrier RD within the transition region HA6 and extends to the side of the encapsulation barrier RD near the via HH. Thus, on the outer portion of the transition region HA6, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT is the first step difference H1; on the inner portion of the transition region HA6, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT is the second step difference H2; above the encapsulation barrier RD, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT is the third step difference H3. In the example of Figure 16, the first step difference H1, the third step difference H3, and the second step difference H2 decrease sequentially. However, between the outer portion of the transition region HA6 and above the encapsulation dam RD, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT may not be greater than the third step difference H3. Of course, in other embodiments of this disclosure, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT between the outer portion of the transition region HA6 and above the encapsulation dam RD may also not be less than the third step difference H3.

[0142] In the example of Figure 16, both the first touch metal layer TMA and the second touch metal layer TMB cover the transition region HA6. It is understood that in some other embodiments of this disclosure, either only the first touch metal layer TMA or only the second touch metal layer TMB may cover the transition region HA6.

[0143] In one embodiment of this disclosure, referring to FIG16, the first touch metal layer TMA and the second touch metal layer TMB may also cover at least a portion of the area between the transition area HA6 and the display area AA, for example, covering the winding area HA2 or the first barrier area HA3, or covering the third barrier area HA5.

[0144] In one embodiment of this disclosure, referring to FIG17, the display panel PNL further includes a color filter layer CFL located on the side of the touch functional layer TSL away from the substrate SBT, the color filter layer CFL having a black matrix layer BM; the black matrix layer BM covers at least a portion of the through-hole encapsulation area HA. ​​Thus, when light emitted from a sub-pixel PX directly illuminates the black matrix layer BM, or when light emitted from a sub-pixel PX is reflected by structures such as metal, film, or cover plate and then illuminates the black matrix layer BM, the light can be absorbed by the black matrix layer BM instead of continuing to be reflected. This effectively terminates continuous light reflection and thus effectively reduces the amount of light entering the through-hole HH.

[0145] It is understood that the examples in Figures 8 to 14 merely illustrate a scheme for improving the auxiliary traces ML of the display panel PNL to reduce crosstalk; the example in Figure 15 merely illustrates a scheme for improving the package dam RD to reduce crosstalk; the example in Figure 16 merely illustrates a scheme for improving the coverage of the touch function layer TSL to reduce crosstalk; and the example in Figure 17 merely illustrates a scheme for improving the coverage of the black matrix layer BM to reduce crosstalk. In other embodiments of this disclosure, multiple of the above-mentioned improvement schemes may be used simultaneously.

[0146] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a through-hole, a through-hole encapsulation region surrounding the through-hole, and a display region surrounding the through-hole encapsulation region; the display panel comprising a substrate, a display layer, a thin film encapsulation layer, and a touch function layer sequentially stacked; The display panel has at least one light-blocking structure surrounding the through-hole in the through-hole encapsulation area; the light-blocking structure includes a bottom metal structure in the display layer and a top metal structure in the touch function layer, and the bottom metal structure and the top metal structure are overlapped.

2. The display panel according to claim 1, wherein, The display layer includes at least one gate metal layer, at least one source / drain metal layer, and a pixel electrode layer, which are sequentially stacked on one side of the substrate; the touch function layer includes a first touch metal layer and a second touch metal layer, which are sequentially stacked on one side of the display layer. The light-blocking structure includes at least one auxiliary trace; The bottom metal structure of the auxiliary wiring includes at least two of the gate metal sub-wirings located in the gate metal layer, the source / drain metal sub-wirings located in the source / drain metal layer, and the electrode metal sub-wirings located in the pixel electrode layer. The top metal structure of the auxiliary trace includes at least one of a first touch metal sub-trace located in the first touch metal layer and a second touch metal sub-trace located in the second touch metal layer.

3. The display panel according to claim 2, wherein, The display layer includes multiple source and drain metal layers stacked sequentially; the auxiliary traces have corresponding source and drain metal sub-traces in any source and drain metal layer, and at least a portion of the surfaces of two adjacent source and drain metal sub-traces are interconnected; the electrode metal sub-traces are at least partially interconnected with the surface of the source and drain metal sub-traces furthest from the substrate. The display layer further includes a pixel definition layer or a support pillar layer located on the side of the pixel electrode layer away from the substrate. The pixel definition layer or the support pillar layer is provided with a first insulating structure corresponding to each of the auxiliary traces. The first insulating structure covers each source / drain metal sub-trace and electrode metal sub-trace of the corresponding auxiliary trace.

4. The display panel according to claim 2, wherein, The display layer includes a multilayer wiring unit layer stacked sequentially, and the wiring unit layer includes a source / drain metal layer and a planarization layer located on the side of the source / drain metal layer away from the substrate. The display panel has at least one auxiliary wiring group, and any one of the auxiliary wiring groups includes a plurality of auxiliary wirings that are adjacent to each other and sequentially surround the through hole; In the same auxiliary routing group, any auxiliary routing has a corresponding source / drain metal sub-routes in any source / drain metal layer, and there is a gap between two adjacent source / drain metal sub-routes in the same source / drain metal layer. Each planarization layer has a second insulation structure that corresponds one-to-one with the auxiliary routing group. The second insulation structure covers the gaps between the source and drain metal sub-routes and the source and drain metal sub-routes in the same wiring unit layer.

5. The display panel according to claim 4, wherein, In the same auxiliary routing group, the electrode metal sub-routes of any one of the auxiliary routings do not overlap with the electrode metal sub-routes of the other auxiliary routings; or, in the same auxiliary routing group, the electrode metal sub-routes of each of the auxiliary routings are interconnected to form a whole.

6. The display panel according to claim 2, wherein, The display panel has at least one auxiliary wiring group, and any one of the auxiliary wiring groups includes a plurality of auxiliary wirings that are adjacent to each other and sequentially surround the through hole; In the same auxiliary routing group, the top metal structure of any one of the auxiliary routings is not connected to the top metal structures of the other auxiliary routings; or, in the same auxiliary routing group, the top metal structures of each of the auxiliary routings are connected to each other to form a whole.

7. The display panel according to claim 2, wherein, The display panel has a winding area in the through-hole encapsulation area; the auxiliary traces include inner auxiliary traces located between the winding area and the through-hole, and / or include outer auxiliary traces located between the winding area and the display area.

8. The display panel according to any one of claims 1 to 7, wherein, The display layer includes at least one gate metal layer, at least one source / drain metal layer, and a pixel electrode layer, which are sequentially stacked on one side of the substrate; the touch function layer includes a first touch metal layer and a second touch metal layer, which are sequentially stacked on one side of the display layer. The light-blocking structure includes at least one encapsulated barrier. The bottom metal structure of the encapsulation dam includes at least two of the following: a gate metal sub-dam located in the gate metal layer, a source / drain metal sub-dam located in the source / drain metal layer, and an electrode metal sub-dam located in the pixel electrode layer. The top metal structure of the encapsulation barrier includes at least one of a first touch metal sub-barrier located in the first touch metal layer and a second touch metal sub-barrier located in the second touch metal layer.

9. The display panel according to claim 8, wherein, The display layer includes multiple source and drain metal layers stacked sequentially. The bottom metal structure of the encapsulation dam has a corresponding source and drain metal sub-barrier in any source and drain metal layer, and at least part of the surfaces of two adjacent source and drain metal sub-barriers are connected to each other.

10. The display panel according to claim 9, wherein, The bottom metal structure of the encapsulation dam also includes an electrode metal sub-barrier, the electrode metal sub-barrier being at least partially interconnected with the surface of the source / drain metal sub-barrier furthest from the substrate.

11. The display panel according to claim 9, wherein, The display layer further includes a pixel definition layer or a support pillar layer located on the side of the pixel electrode layer away from the substrate. The pixel definition layer or the support pillar layer is provided with a fourth insulating structure corresponding to the encapsulation dam. The fourth insulating structure covers the bottom metal structure of the corresponding encapsulation dam.

12. The display panel according to any one of claims 1 to 7, wherein, The display panel has a transition region surrounding the through-hole in the through-hole encapsulation area; near the edge of the display area in the transition region, the step difference between the surface of the thin film encapsulation layer away from the substrate and the substrate is a first step difference; In the transition region near the edge of the via, the step difference between the surface of the thin film encapsulation layer away from the substrate and the substrate is the second step difference; The first segment difference is greater than the second segment difference; The metal layer of the touch function layer covers the transition area.

13. The display panel according to any one of claims 1 to 7, wherein, The display panel also includes a color filter layer located on the side of the touch function layer away from the substrate, and the color filter layer has a black matrix layer; The black matrix layer covers at least a portion of the through-hole packaging area.

14. A display device comprising the display panel according to any one of claims 1 to 13.

Images