Display panel and preparation method therefor, and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a display panel and a preparation method therefor, and a display apparatus. The display panel comprises a base substrate, a drive layer and a pixel layer, which are sequentially stacked, wherein the drive layer comprises a top planarization layer; and the pixel layer comprises a pixel electrode layer and a pixel defining layer, which are sequentially stacked on a surface of the top planarization layer. The display panel comprises a plurality of reflection structures, wherein any one reflection structure comprises: a reflection matrix, which is located at the top planarization layer and has a reflection groove; an electrode unit, which is disposed on the pixel electrode layer, wherein the electrode unit comprises climbing portions covering side walls of the reflection groove and a flat portion covering the bottom of the reflection groove; and a pixel defining unit, which is disposed on the pixel defining layer, wherein the pixel defining unit covers the climbing portions and exposes at least part of the flat portion; and in a direction away from the center of the reflection groove, the thickness of at least part of the pixel defining unit gradually decreases. The display panel can improve the light output efficiency.

Description

Display panel and its manufacturing method, display device

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese Patent Application No. 202510369461.4, filed on March 26, 2025, entitled “Display Panel and Method for Manufacturing Thereof, Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0004] In the field of OLED display technology, setting a reflector cup can effectively improve the light output of the display panel.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel, a method for manufacturing the same, and a display device, thereby improving the light extraction efficiency of the display panel.

[0007] According to a first aspect of this disclosure, a display panel is provided, comprising a substrate, a driving layer, and a pixel layer sequentially stacked thereon; wherein the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel definition layer sequentially stacked on the surface of the top planarization layer; the display panel includes a plurality of reflective structures, any one of the reflective structures comprising:

[0008] A reflective substrate located in the top planarization layer and having a reflective groove;

[0009] An electrode unit is disposed on the pixel electrode layer; the electrode unit includes a ramp portion covering the sidewall of the reflective groove and a flat portion covering the bottom of the reflective groove;

[0010] A pixel definition unit is disposed in the pixel definition layer; the pixel definition unit covers at least a portion of the climbing portion and exposes at least a portion of the flat portion.

[0011] Along a direction away from the center of the reflective groove, the thickness of at least a portion of the pixel definition unit gradually decreases.

[0012] According to one embodiment of the present disclosure, the pixel definition unit has a gradient portion located on the side of the critical reference plane close to the substrate; the lateral width of the gradient portion decreases sequentially along the direction away from the substrate.

[0013] The lateral width of the gradient portion refers to the distance between the inner edge and the outer edge of the gradient portion on the first reference plane; both the first reference plane and the critical reference plane are parallel to the substrate; the first reference plane is located between the critical reference plane and the flat portion.

[0014] According to one embodiment of this disclosure, the distance between the inner edge of the upper surface of the pixel definition unit and the inner edge of the lower surface of the pixel definition unit is a first dimension, the first dimension being between 1.5 and 2.4 micrometers.

[0015] According to one embodiment of this disclosure, the thickness of the pixel definition unit at its outer edge P1 is a second dimension, the second dimension being between 0.8 and 1.2 micrometers;

[0016] The orthographic projection of the outer edge of the pixel definition unit on the substrate coincides with the orthographic projection of the opening edge of the reflective groove on the substrate.

[0017] According to one embodiment of this disclosure, the distance between the inner edge of the upper surface of the pixel definition unit and the inner edge of the lower surface of the pixel definition unit is a first dimension, and the thickness of the pixel definition unit at the outer edge is a second dimension; the orthographic projection of the outer edge of the pixel definition unit on the substrate coincides with the orthographic projection of the opening edge of the reflective groove on the substrate.

[0018] The first dimension is 1.5 to 2.5 times the second dimension.

[0019] According to one embodiment of this disclosure, the depth of the reflective groove is between 2.0 and 3.0 micrometers; the component of the distance between the inner edge and the outer edge of the ramp portion in the direction parallel to the substrate is 1.8 to 2.4 times the depth of the reflective groove.

[0020] According to one embodiment of this disclosure, the thickness of the pixel definition unit at the inner edge of the lower surface is 1.3 to 1.8 times the thickness of the pixel definition unit at the outer edge of the lower surface.

[0021] According to one embodiment of this disclosure, the slope angle of the upper surface of the pixel definition unit at its inner edge is smaller than the slope angle of the lower surface of the pixel definition unit at its inner edge.

[0022] According to one embodiment of this disclosure, the slope angle of the upper surface of the pixel definition unit at its inner edge is between 40° and 55°.

[0023] The slope angle of the lower surface of the pixel definition unit at the inner edge is between 55° and 65°.

[0024] The slope angle of the upper surface of the pixel definition unit at its inner edge is at least 5° smaller than the slope angle of the lower surface of the pixel definition unit at its inner edge.

[0025] According to one embodiment of this disclosure, the slope angle of the upper surface of the pixel definition unit gradually decreases along a direction away from the center of the reflective groove.

[0026] According to one embodiment of the present disclosure, the pixel definition unit has a gradient portion located on the side of the critical reference plane close to the substrate.

[0027] The slope angle formed by the lower surface of the gradient portion and the first reference plane is greater than the slope angle formed by the upper surface of the gradient portion and the first reference plane; both the first reference plane and the critical reference plane are parallel to the substrate; the first reference plane is located between the critical reference plane and the flat portion.

[0028] According to a second aspect of this disclosure, a display device is provided, including the display panel described above.

[0029] According to a third aspect of this disclosure, a method for fabricating a display panel is provided, comprising: sequentially forming a driving layer and a pixel layer on one side of a substrate; wherein the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel definition layer sequentially stacked on the surface of the top planarization layer;

[0030] The top planarization layer forming the driving layer includes:

[0031] A top planarization layer is formed, such that the top planarization layer has multiple reflective grooves;

[0032] Forming the pixel electrode layer includes:

[0033] A pixel electrode layer is formed, such that the pixel electrode layer includes a plurality of electrode units corresponding one-to-one with the plurality of reflective grooves, and the electrode unit includes a ramp portion covering the sidewall of the corresponding reflective groove and a flat portion covering the bottom of the corresponding reflective groove;

[0034] Forming the pixel definition layer includes:

[0035] The pixel definition layer is formed such that it includes a plurality of pixel definition units corresponding one-to-one with the plurality of electrode units, the pixel definition units covering the ramp portion of the corresponding electrode unit and exposing at least a portion of the flat portion of the corresponding electrode unit; the thickness of at least a portion of the pixel definition units gradually decreases along a direction away from the center of the corresponding reflective groove.

[0036] According to one embodiment of this disclosure, forming the pixel definition layer includes:

[0037] A pixel definition material layer is formed, which covers the pixel electrode layer;

[0038] The pixel definition material layer is patterned to form pixel definition precursor units that correspond one-to-one with the plurality of electrode units. The pixel definition precursor units cover the ramp portion and part of the flat portion of the corresponding electrode unit.

[0039] This causes at least a portion of the pixel definition precursor unit to liquefy, and at least a portion of the material of the pixel definition precursor unit to deform into the reflective groove;

[0040] The deformed pixel definition precursor unit is solidified to form the pixel definition unit.

[0041] According to one embodiment of this disclosure, the material of the pixel definition precursor unit is positive adhesive;

[0042] The process of at least partially liquefying the pixel definition precursor unit includes irradiating the pixel definition precursor unit with ultraviolet light.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0045] Figure 1 is a schematic diagram of the planar structure of the display panel in one embodiment of this disclosure.

[0046] Figure 2 is a partial cross-sectional view of the display panel in one embodiment of this disclosure.

[0047] Figure 3 is a partial cross-sectional schematic diagram of the reflective structure in one embodiment of this disclosure.

[0048] Figure 4 is a schematic diagram illustrating the principle of increasing light emission efficiency through a reflective structure in one embodiment of this disclosure.

[0049] Figure 5 is a schematic diagram illustrating the principle of increasing light emission efficiency through a reflective structure in one embodiment of this disclosure.

[0050] Figure 6 is a schematic diagram showing the morphological differences before and after the improvement of the reflection structure.

[0051] Figure 7 is a partial cross-sectional schematic diagram of the reflective structure in one embodiment of this disclosure.

[0052] Figure 8 is a partial cross-sectional schematic diagram of the reflective structure in one embodiment of this disclosure.

[0053] Figure 9 is a partial cross-sectional schematic diagram of the reflective structure in one embodiment of this disclosure.

[0054] Figure 10 is a partial cross-sectional schematic diagram of a pixel definition unit in one embodiment of this disclosure.

[0055] Figure 11 is a schematic diagram of the structure of the first sublayer forming the top planarization layer in one embodiment of this disclosure.

[0056] Figure 12 is a schematic diagram of the structure of the second sublayer forming the top planarization layer in one embodiment of this disclosure.

[0057] Figure 13 is a schematic diagram of the structure of forming a pixel electrode layer and a pixel definition material layer in one embodiment of the present disclosure.

[0058] Figure 14 is a schematic diagram of the structure forming a pixel definition unit in one embodiment of this disclosure.

[0059] Figure 15 is a schematic diagram of the structure forming the support column layer in one embodiment of this disclosure. Detailed Implementation

[0060] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0061] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0062] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0063] Structural layer A is located on the side of structural layer B that faces away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate serves as the height reference.

[0064] This disclosure provides a display panel and a display device using the display panel. Figure 1 is a schematic diagram of the planar structure of the display panel PNL in one embodiment of this disclosure. Referring to Figure 1, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with an array of display units DU, each display unit DU including a sub-pixel PX and a pixel driving circuit PDC driving the sub-pixel PX. The display panel PNL does not provide display units DU in the peripheral area BB, or the provided display units DU are not used for displaying images. In the example of Figure 1, the display panel PNL provides a plurality of scan lines GL extending along the row direction DH in the display area AA, each scan line GL corresponding to a row of display units. The pixel driving circuit PDC of each display unit DU in the row of display units is electrically connected to the corresponding scan line GL. The display panel PNL also provides a plurality of data lines DL extending along the column direction DV in the display area AA, each data line DL corresponding to a column of display units. Each display unit DU in the display unit column has its pixel driving circuit PDC electrically connected to its corresponding data line DL. Thus, each display unit DU's pixel driving circuit PDC is connected to a scan line GL and a data line DL. When a scan signal is applied to the scan line GL, the driving voltage applied to the data line DL can be written into the pixel driving circuit PDC, allowing the pixel driving circuit PDC to control the brightness of the sub-pixel PX based on the written driving voltage. It is understood that in other embodiments of this disclosure, the arrangement of the display units DU and the connection methods with the data lines DL and scan lines GL may differ from the example in Figure 1.

[0065] Figure 2 is a partial cross-sectional view of a display panel PNL according to one embodiment of this disclosure. In the example of Figure 2, the display panel PNL may include a substrate SBT, a driving layer DRL, and a pixel layer PXL stacked sequentially; wherein, the pixel layer PXL is provided with sub-pixels PX for display, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixels PX. Each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image.

[0066] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can be polyimide.

[0067] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a transistor (e.g., a thin-film transistor) and a storage capacitor. Further, the transistor may be selected from top-gate thin-film transistors, bottom-gate thin-film transistors, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type thin-film transistor or a P-type thin-film transistor.

[0068] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. Exemplarily, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a LPS transistor. In other embodiments of this disclosure, some thin-film transistors are LPS transistors, and some thin-film transistors are MODS transistors.

[0069] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN, stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer SCL, gate insulating layer GI, gate layer GT, interlayer dielectric layer ILD, and source / drain metal layer SD. The positional relationship of each layer can be determined based on the thin-film transistor's layer structure. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form partial traces or conductive structures if necessary. The gate layer can be used to form one or more gate layer traces such as scan traces, reset control traces, and light emission control traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data traces, drive power supply voltage traces, or other source / drain metal layer traces, or it can be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any one of the aforementioned semiconductor layer SCL, gate layer GT, source / drain metal layer SD may be multiple layers. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Correspondingly, the insulating film layers in the driving layer DRL (e.g., gate insulating layer GI, interlayer dielectric layer ILD, planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed. Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer SD away from the substrate SBT to protect the source / drain metal layer SD.

[0070] In one embodiment of this disclosure, the film layer between the substrate SBT and the first source / drain metal layer SD1 can be referred to as a whole as a transistor layer TFTL. The transistor layer TFTL has a semiconductor layer SCL, a gate insulating layer GI, and a gate layer GT required for forming a thin-film transistor. For example, in the example of FIG2, the transistor layer TFTL includes a first inorganic buffer layer BUFA, a polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BUFB, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, and an interlayer dielectric layer ILD, which are sequentially stacked on one side of the substrate SBT. In the example of Figure 2, the driving layer DRL includes two semiconductor layers SCL (polysilicon semiconductor layer PSCL and metal oxide semiconductor layer OSCL), three gate insulating layers GI (first gate insulating layer GI1, second gate insulating layer GI2, and third gate insulating layer GI3), three gate layers GT (first gate layer GT1, second gate layer GT2, and third gate layer GT3), two source drain metal layers SD (first source drain metal layer SD1 and second source drain metal layer SD2), and two planarization layers PLN (first planarization layer PLN1 and second planarization layer PLN2). The polysilicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate layer GT1 can form low-temperature polysilicon thin-film transistors (LTPO transistors), while the second gate layer GT2, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the third gate layer GT3 can form metal oxide thin-film transistors (MTPs). Thus, this display panel PNL is a display panel employing LTPO technology. It is understood that the transistor layer TFTL of the present disclosure is not limited to the structure illustrated in FIG2; in other embodiments of the present disclosure, transistor layer TFTLs with other structures may also be used.

[0071] In one embodiment of this disclosure, the structure between the transistor layer TFTL and the pixel layer PXL can be referred to as the wiring layer MRL. One important function of the wiring layer MRL is to realize electrical connections between different devices, such as thin-film transistors, storage capacitors, and sub-pixels PX. Optionally, the wiring layer MRL may include one or more wiring unit layers, each wiring unit layer may include a source / drain metal layer SD and a planarization layer PLN located on the side of the source / drain metal layer SD away from the substrate SBT. It is understood that in some examples, the wiring unit layer may also include a passivation layer, which may be disposed between the source / drain metal layer SD and the planarization layer PLN to protect the source / drain metal layer SD.

[0072] For example, in the example of Figure 2, the wiring layer MRL includes a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, and a second planarization layer PLN2, which are sequentially stacked on the side of the transistor layer TFTL away from the substrate SBT. Thus, the wiring layer MRL includes two wiring unit layers: a first wiring unit layer (including the first source / drain metal layer SD1 and the first planarization layer PLN1) and a second wiring unit layer (including the second source / drain metal layer SD2 and the second planarization layer PLN2). When the display panel PNL requires more source / drain metal layers SD, the number of wiring unit layers can be adaptively increased (i.e., the source / drain metal layers SD and the planarization layer PLN are increased simultaneously). For example, when the display panel PNL is provided with three source / drain metal layers SD, the wiring layer MRL includes a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer, and a third planarization layer (the third source / drain metal layer and the third planarization layer serve as the third wiring unit layer) stacked in sequence.

[0073] It is understood that the routing layer MRL of the present disclosure is not limited to the structure illustrated in FIG2; in other embodiments of the present disclosure, other structures of routing layer MRL may also be used, such as routing layer MRL with one routing unit layer, three routing unit layers, four routing unit layers or five routing unit layers.

[0074] In the example of Figure 2, the driving layer DRL is provided with a transistor layer TFTL, so the display panel PNL can be an actively driven display panel. It is understood that in some other embodiments of this disclosure, the display panel PNL can also employ passive driving technology; for example, the driving layer DRL of the display panel PNL may only have a wiring layer MRL without a transistor layer TFTL.

[0075] In this embodiment of the disclosure, the wiring unit layer furthest from the substrate SBT in the wiring layer MRL can be referred to as the top wiring unit layer, the source / drain metal layer SD included in the top wiring unit layer is referred to as the top source / drain metal layer TSD, and the planarization layer PLN included in the top wiring unit layer is referred to as the top planarization layer TPLN. Thus, the top source / drain metal layer TSD is the source / drain metal layer SD furthest from the substrate SBT among the various source / drain metal layers SD in the drive layer DRL; for example, in the example of FIG2, the top source / drain metal layer TSD is the second source / drain metal layer SD2. The top planarization layer TPLN is the planarization layer PLN furthest from the substrate SBT among the various planarization layers PLN in the drive layer DRL; for example, in the example of FIG2, the top planarization layer TPLN is the second planarization layer PLN2.

[0076] In one embodiment of this disclosure, referring to FIG2, the sub-pixels in the pixel layer PXL are thin-film light-emitting elements, which may include two electrodes stacked together and a light-emitting functional unit sandwiched between the two electrodes. In the example of FIG2, the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area of ​​the display panel. The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes, with each pixel hole exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EFL), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PX. The light-emitting functional layer EFL at least covers the pixel electrodes exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrode and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EFL, causing the EFL to emit light. The portion of the EFL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrode, the common electrode layer COML, and the light-emitting functional unit form a sub-pixel PX. One of the pixel electrode and the common electrode layer COML serves as the anode of the sub-pixel PX, and the other serves as the cathode of the sub-pixel PX.

[0077] In one embodiment of this disclosure, the display panel further includes a support pillar layer (PSL) located on the side of the pixel definition layer (PDL) away from the substrate. The PSL forms a plurality of support pillars to support a precision metal mask during the vapor deposition process. In one example, the support pillar layer and the pixel definition layer (PDL) can be made of the same material and fabricated in the same process; for example, a grayscale masking process can be used to simultaneously form the pixel definition layer and the support pillar layer on the same organic material layer. In another example, after forming the pixel definition layer, a new organic material layer can be coated and patterned to form the support pillars of the support pillar layer; the materials of the pixel definition layer and the support pillar layer can be the same or different.

[0078] In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer COML serves as the cathode of the sub-pixel PX.

[0079] In the example of Figure 2, the sub-pixel PX is an organic light-emitting diode (OLED). It is understood that in other embodiments of this disclosure, the sub-pixel may also be other types of light-emitting elements, such as current-driven light-emitting elements such as QLED, PLED, Micro LED, Mini LED, etc.

[0080] In one embodiment of this disclosure, the display panel PNL may further include a thin-film encapsulation layer TFE located on the side of the pixel layer PXL away from the substrate SBT. In the example of FIG. 2, the thin-film encapsulation layer TFE may be disposed on the surface of the pixel layer PXL away from the substrate SBT, and may include alternating layers of inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the thin-film encapsulation layer TFE may also adopt other structures, such as multiple layers of inorganic encapsulation layers.

[0081] In one embodiment of this disclosure, a touch function layer TSL may be provided on the side of the thin film encapsulation layer TFE away from the substrate SBT of the display panel PNL, so that the display panel PNL has a touch function.

[0082] In one example, the touch functional layer (TSL) may include two metal layers and an insulating layer sandwiched between the two metal layers. It will be understood that in other embodiments of this disclosure, the touch functional layer (TSL) may also include more metal layers or fewer metal layers.

[0083] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may further include a color filter layer CFL located on the side of the touch functional layer TSL away from the substrate SBT. The color filter layer CFL has color filter units corresponding to sub-pixels PX. For example, a red color filter unit is disposed above a red sub-pixel, a green color filter unit is disposed above a green sub-pixel, and a blue color filter unit is disposed above a blue sub-pixel. This improves the purity of the emitted color of the display panel PNL, thereby enhancing its color gamut, and also reduces interference from ambient light on normal display. In one example, the color filter layer CFL also has a black matrix, which can be located between sub-pixels PX to reduce emitted crosstalk and further reduce reflection of ambient light.

[0084] Due to limitations in manufacturing processes and materials, the lifespan of blue subpixels is often shorter than that of red and green subpixels. This disclosed embodiment, through optimization of the display panel, can improve the light emission rate of the blue subpixels, thereby increasing their lifespan and ultimately enhancing the brightness and lifespan of the entire display panel.

[0085] In this embodiment of the disclosure, referring to Figures 2 and 3, the display panel PNL is provided with at least one reflective structure RS to improve the light extraction efficiency of the display panel PNL. Referring to Figures 2 and 3, the reflective structure RS includes a reflective substrate RB located in the top planarization layer TPLN, an electrode unit PEU located in the pixel electrode layer PEL, and a pixel definition unit PDU located in the pixel definition layer PDL. The reflective substrate RB has a reflective groove GV, the opening direction of which faces away from the substrate SBT, and the lateral dimension of the groove opening (the dimension along the direction parallel to the substrate SBT) is greater than the lateral dimension of the groove bottom (the dimension along the direction parallel to the substrate SBT). The electrode unit PEU covers the reflective groove GV and includes a ramp portion PEB covering the sidewall of the reflective groove GV and a flat portion PEA covering the bottom of the reflective groove GV. The pixel definition unit PDU covers the ramp portion PEB and exposes at least a portion of the flat portion PEA.

[0086] In this embodiment, the electrode unit PEU is part of the pixel electrode PE. Referring to FIG3, the pixel electrode PE also includes a connection portion PEC, which is used to electrically connect to the top source drain metal layer TSD via a via and to the electrode unit PEU. In a further example, the connection portion PEC may include a surrounding portion surrounding the electrode unit PEU and a lead portion electrically connected to the top source drain metal layer TSD via a via, with the surrounding portion and the lead portion being electrically connected. Thus, the pixel driving circuit PDC can apply driving current to the electrode unit PEU of the pixel electrode PE through the connection portion PEC, thereby driving the sub-pixel PX to emit light.

[0087] In this embodiment, the flat portion PEA is partially covered by the pixel definition unit (PDU) and partially exposed by the PDU. For example, referring to FIG7, the flat portion PEA includes a covered sub-portion PEA1 covered by the PDU and an exposed sub-portion PEA2 exposed by the PDU. The exposed sub-portion PEA2 can directly contact the light-emitting functional layer (EFL), and this area can serve as the effective area of ​​the pixel electrode PE. The effective area of ​​the pixel electrode PE is located at the bottom of the reflective groove GV and has high flatness. The portion of the pixel electrode PE other than the exposed sub-portion PEA2 can be covered by the pixel definition layer (PDL) and cannot directly contact the light-emitting functional layer (EFL). When the pixel driving circuit (PDC) applies a driving current to the pixel electrode PE, the driving current can flow through the exposed sub-portion PEA2 through the light-emitting functional layer (EFL) and into the common electrode layer (COML), thereby causing the portion of the light-emitting functional layer (EFL) in direct contact with the exposed sub-portion PEA2 to emit light. In other words, the sub-pixel PX is located within the reflective groove GV and is disposed at the bottom of the reflective groove GV.

[0088] Referring to Figure 4, when the sub-pixel PX emits light, specifically, when the portion of the light-emitting functional layer EFL that directly contacts the exposed sub-part PEA2 emits light, a portion of the light emitted by the sub-pixel PX can illuminate the reflective structure RS and be reflected by the reflective structure RS. For example, if the light emitted by the sub-pixel PX illuminates the substrate SBT, the light can be reflected by the flat portion PEA in a direction away from the substrate SBT. If the light emitted by the sub-pixel PX is a large-angle light (forming a large angle with the normal direction of the substrate SBT, for example, 80° to 90°), this large-angle light can partially or completely illuminate the ramp portion PEB and the pixel definition unit PDU covering the ramp portion PEB, and then be reflected by the ramp portion PEB and the pixel definition unit PDU into small-angle light. In other words, the top planarization layer TPLN is provided with a reflective groove GV corresponding to each sub-pixel PX. The sub-pixel PX is located at the bottom of the reflective groove GV, and the sidewall of the reflective groove GV is covered by the pixel electrode PE and the pixel definition layer PDL. The pixel electrode PE and the pixel definition layer PDL covering the reflective groove GV can focus the light emitted by the sub-pixel PX to the light emission direction, thereby improving the light emission rate of the display panel PNL.

[0089] Referring to Figures 4 and 5, the pixel definition unit (PDU) has an upper surface TSF and a lower surface DSF disposed opposite to each other; the upper surface TSF of the PDU is located on the side of the lower surface DSF away from the substrate SBT. In one example, within the reflective structure RS, the lower surface DSF of the PDU is attached to the ramp portion PEB, so the lower surface DSF of the PDU and the upper surface (the surface away from the substrate SBT) of the ramp portion PEB can substantially coincide. The upper surface TSF of the PDU can be the sidewall of the pixel opening formed at the reflective groove GV by the pixel definition layer PDL.

[0090] In this embodiment of the disclosure, the thickness of the pixel definition unit (PDU) can be determined using the lower surface DSF of the PDU as a reference plane. For example, the thickness of the PDU refers to the distance between the first point formed by the intersection of the thickness reference line and the lower surface DSF of the PDU, and the second point formed by the intersection of the thickness reference line and the upper surface TSF of the PDU; wherein the thickness reference line is the normal of the lower surface DSF at the first point.

[0091] Referring to Figures 3-5, in the display panel PNL provided in this embodiment, the thickness of at least a portion of the pixel definition unit (PDU) gradually decreases along the direction away from the center of the reflective groove GV, forming a convergent light-guiding space. For example, the thickness of the PDU gradually decreases as it moves away from the center of the reflective groove GV. Thus, light incident on the PDU is reflected after illuminating the ramp portion PEB; after being reflected to the upper surface TSF of the PDU, some of the light may be reflected back into the PDU, meaning some light exits from the upper surface TSF and some is reflected back into the PDU. Because the thickness of the PDU gradually decreases, the length of the reflection path decreases sequentially when light undergoes multiple reflections within the PDU; this allows light that cannot exit from the PDU to strike the upper surface TSF of the PDU more frequently, thereby increasing the overall light extraction efficiency within the PDU.

[0092] Figure 6 is a schematic diagram of a reflective structure in the related art. In the example of Figure 6, the pixel definition layer PDL0 represents the pixel definition layer in the related art; the pixel definition unit PDU0 represents the pixel definition unit in the related art; the upper surface TSF0 represents the upper surface of the pixel definition unit in the related art; and the lower surface DSF0 represents the lower surface DSF of the pixel definition unit in the related art. In this example of Figure 6, the upper surface TSF of the pixel definition unit PDU provided in the present disclosure is also represented by a dashed line. Referring to Figure 6, in the related art, the upper surface TSF0 of the pixel definition unit PDU0 is basically parallel to the lower surface DSF0, and the pixel definition unit PDU0 is set with equal thickness. Therefore, when the same incident light ray as in Figure 5 is reflected in the pixel definition unit PDU0, the total number of reflections is relatively small, and the light extraction rate in the pixel definition unit PDU0 is not as good as that of the pixel definition unit PDU in the present disclosure.

[0093] In one embodiment of this disclosure, the display panel PNL provided by this disclosure can be fabricated using the following method. Referring to Figures 11 to 15, a driving layer DRL and a pixel layer PXL are sequentially formed on one side of a substrate SBT; wherein, the driving layer DRL includes a top planarization layer TPLN, and the pixel layer PXL includes a pixel electrode layer PEL and a pixel definition layer PDL sequentially stacked on the surface of the top planarization layer TPLN.

[0094] The top planarization layer TPLN forming the driving layer DRL includes: referring to Figures 11 and 12, forming the top planarization layer TPLN such that the top planarization layer TPLN has multiple reflective grooves GV;

[0095] Forming the pixel electrode layer PEL includes: referring to FIG13, forming the pixel electrode layer PEL such that the pixel electrode layer PEL includes a plurality of electrode units PEU corresponding one-to-one with the plurality of reflective grooves GV, the electrode unit PEU includes a ramp portion PEB covering the sidewall of the corresponding reflective groove GV and a flat portion PEA covering the bottom of the corresponding reflective groove GV.

[0096] Forming the pixel definition layer (PDL) includes: referring to Figures 13-15, forming the pixel definition layer (PDL) such that the pixel definition layer (PDL) includes a plurality of pixel definition units (PDUs) corresponding one-to-one with the plurality of electrode units (PEUs), the pixel definition units (PDUs) covering the ramp portion (PEB) of the corresponding electrode unit (PEU) and exposing at least a portion of the flat portion (PEA) of the corresponding electrode unit (PEU); the thickness of at least a portion of the pixel definition unit (PDU) gradually decreases along a direction away from the center of the corresponding reflective groove (GV).

[0097] The structure of the display panel PNL according to the present disclosure and its preparation method are further explained and described below with reference to the accompanying drawings.

[0098] Figure 7 is a partial structural diagram of the display panel PNL at the reflective structure RS in one embodiment of this disclosure. In the example of Figure 7, the top planarization layer TPLN includes two sub-layers, namely, a first sub-layer TPLN1 and a second sub-layer TPLN2 of the top planarization layer disposed sequentially on the side of the top source drain metal layer TSD away from the substrate SBT. The top planarization layer TPLN may have a connection via CNT penetrating the first sub-layer TPLN1 and the second sub-layer TPLN2 of the top planarization layer. The top source drain metal layer TSD is provided with a transition pad, and at least a portion of the transition pad is exposed by the connection via CNT. Thus, when fabricating the pixel electrode PE, the pixel electrode PE can be electrically connected to the transition pad through the connection via CNT. Furthermore, the transition pad can serve as the output terminal of the pixel driving circuit PDC, which allows the driving current provided by the pixel driving circuit PDC to be applied to the pixel electrode PE. The top planarization layer TPLN also has a reflective groove GV, which penetrates the second sublayer TPLN2 of the top planarization layer and exposes the first sublayer TPLN1. Thus, the first sublayer TPLN1 provides a flat bottom for the reflective groove GV, ensuring the flatness of the planar portion PEA and improving the light emission uniformity of the display panel PNL. The second sublayer TPLN2 forms the sidewall of the reflective groove GV, providing support for the morphology of the ramp portion PEB and the pixel definition unit PDU. In this embodiment, the reflective structure RS may include a first reflective substrate RB1 formed by the first sublayer TPLN1 of the top planarization layer and a second reflective substrate RB2 formed by the second sublayer TPLN2 of the top planarization layer.

[0099] In the example of Figure 7, the driving layer DRL includes a first planarization layer PLN1 and a second planarization layer PLN2. The second planarization layer PLN2 serves as the top planarization layer TPLN, and the second source / drain metal layer SD2 serves as the top source / drain metal layer TSD. The second planarization layer PLN2 includes a first sub-layer PLN21 of the second planarization layer that serves as the first sub-layer TPLN1 of the top planarization layer, and a second sub-layer PLN22 of the second planarization layer that serves as the second sub-layer TPLN2 of the top planarization layer.

[0100] Taking the fabrication process illustrated in Figures 11 and 12 as an example, when fabricating the top planarization layer TPLN, a first sub-layer TPLN1 (e.g., the first sub-layer PLN21 of the second planarization layer in Figure 11) can be formed after forming the top source drain metal layer TSD (e.g., the second source drain metal layer SD2 in Figure 11). This first sub-layer TPLN1 has a connection via CNT that exposes the top source drain metal layer TSD, so that the pixel electrode PE is electrically connected to the top source drain metal layer TSD through the connection via CNT. Referring to Figure 12, after forming the first sublayer TPLN1 of the top planarization layer (e.g., the first sublayer PLN21 of the second planarization layer in Figure 11), a second sublayer TPLN2 of the top planarization layer (e.g., the second sublayer PLN22 of the second planarization layer in Figure 12) can be formed on the side of the first sublayer TPLN1 away from the substrate SBT. The second sublayer TPLN2 of the top planarization layer exposes the connection via CNT, thereby exposing the top source drain metal layer TSD, so that the pixel electrode PE is electrically connected to the top source drain metal layer TSD through the connection via CNT. The second sublayer TPLN2 of the top planarization layer is also provided with a reflective groove GV, which penetrates the second sublayer TPLN2 of the top planarization layer and exposes the first sublayer TPLN1 of the top planarization layer. Thus, the second sublayer TPLN2 of the top planarization layer and the first sublayer TPLN1 of the top planarization layer together form the reflective groove GV. The first sublayer TPLN1 of the top planarization layer provides a flat groove bottom for the reflective groove GV, and the second sublayer TPLN2 of the top planarization layer provides the sidewalls for the reflective groove GV. Referring to Figure 12, the opening size of the reflective groove GV is larger than the groove bottom size of the reflective groove GV.

[0101] In one embodiment of this disclosure, the thickness of the first sublayer TPLN1 of the top planarization layer is 1 to 2 micrometers to ensure that the first sublayer TPLN1 of the top planarization layer can provide a sufficiently flat surface. For example, the thickness of the first sublayer TPLN1 of the top planarization layer is 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, or 2 μm.

[0102] In the accompanying drawings and exemplary descriptions provided in this disclosure, the reflective structure RS is illustrated by taking a display panel PNL with two planarization layers PLN, and the second planarization layer PLN2 as the top planarization layer TPLN. It is understood that in other embodiments of this disclosure, the number of planarization layers PLN in the display panel PNL is not limited to two, and the top planarization layer TPLN is not necessarily limited to the second planarization layer PLN2.

[0103] In the accompanying drawings and exemplary descriptions provided in this disclosure, the top planarization layer TPLN comprises two sub-film layers: a first sub-layer TPLN1 and a second sub-layer TPLN2. The first sub-layer TPLN1 provides a flat bottom for the reflective groove GV, and the second sub-layer TPLN2 provides the required sidewalls for the reflective groove GV. It is understood that in other embodiments of this disclosure, the top planarization layer TPLN is not limited to two sub-film layers. For example, a single planarization layer can also be used to fabricate the reflective groove GV. For example, the top source drain metal layer TSD can be provided with a barrier pad corresponding one-to-one with the reflective groove GV, and the surface of the barrier pad is flat. When forming the top planarization layer TPLN (a single organic layer), the top planarization layer TPLN can form a reflective groove GV exposing a portion of the barrier pad, and a connection via CNT exposing the transition pad; the presence of the barrier pad ensures the flatness of the bottom of the formed reflective groove GV.

[0104] In one embodiment of this disclosure, referring to Figures 3 and 13, after forming the top planarization layer TPLN and the reflective groove GV on the top planarization layer TPLN, a pixel electrode layer PEL can be formed on the side of the top planarization layer TPLN away from the substrate SBT. Referring to Figures 3 and 13, the pixel electrode layer PEL includes pixel electrodes PE corresponding one-to-one with the reflective structure RS (and correspondingly, one-to-one with the sub-pixels PX), and the pixel electrodes PE cover the reflective groove GV and the connecting via CNT. In this embodiment of the disclosure, the portion of the pixel electrode PE located at the bottom of the reflective groove GV is called the planarization portion PEA, which has a flat surface and is used to connect to the light-emitting functional layer EFL. The portion of the pixel electrode PE covering the sidewall of the reflective groove GV is called the ramp portion PEB; the ramp portion PEB gradually ramps in a direction away from the center of the reflective groove GV. The remaining portion of the pixel electrode PE is called the connection portion PEC, which is connected to the ramp portion PEB and connected to the transition pad of the top source drain metal layer TSD through the connecting via CNT.

[0105] In this embodiment, the pixel electrode layer (PEL) can be made of a reflective material, such as a metal material or at least a reflective sublayer formed of a metal material. For example, the pixel electrode layer (PEL) may include a reflective sublayer and an ITO sublayer stacked sequentially, with the reflective sublayer made of silver. Thus, the portion of the light-emitting functional layer (EFL) that contacts the planar portion (PEA) can emit light under the control of the pixel driving circuit (PDC). The light emitted by the sub-pixel (PX) is reflected by the planar portion (PEA) and the ramp portion (PEB) and converges towards the light-emitting side of the display panel (PNL), improving the light extraction efficiency of the sub-pixel (PX).

[0106] In one embodiment of this disclosure, the pixel definition layer (PDL) can be prepared using the following method:

[0107] Referring to Figure 13, a pixel definition material layer (PDLX) is formed, which covers the pixel electrode layer (PEL).

[0108] Referring to Figure 13, the pixel definition material layer PDLX is patterned to form a pixel definition precursor unit PDUX corresponding to each of the multiple electrode units PEU. The pixel definition precursor unit PDUX covers the ramp portion PEB and part of the flat portion PEA of the corresponding electrode unit PEU.

[0109] Referring to Figure 14, the pixel definition precursor unit PDUX is at least partially liquefied, and at least a portion of the material of the pixel definition precursor unit PDUX is deformed into the reflective groove GV, thereby causing a change in the morphology of the pixel definition precursor unit PDUX.

[0110] Referring to Figure 14, the liquefied pixel definition material layer PDLX is cured so that the pixel definition precursor unit PDUX is cured to form the pixel definition unit PDU.

[0111] Referring to Figure 15, in one embodiment of this disclosure, after forming the pixel definition unit (PDU), a support pillar layer (PSL) can be formed on the side of the pixel definition layer (PDL) away from the substrate (SBT). This support pillar layer (PSL) has support pillars for supporting a precision metal mask. In one example, the material of the support pillar layer (PSL) is the same as the material of the pixel definition layer (PDL). Of course, the material of the support pillar layer (PSL) can also be different from the material of the pixel definition layer (PDL).

[0112] In the above preparation method, the pixel-defining material layer (PDLX) can first be patterned using an exposure-development technique to form a pixel-defining precursor unit (PDUX). Then, the PDUX is made fluid and shaped during the flow process, subsequently solidifying to form the pixel-defining unit (PDU). During the flow shaping of the PDUX, under the influence of internal stress and external gravity, it tends to flow towards the bottom of the reflective groove (GV). Thus, during the flow of the PDUX, the inner edge P1 of its upper surface TSF moves towards the center of the reflective groove (GV), and the slope angle of the upper surface TSF decreases. Furthermore, as the partially liquefied PDUX flows into the reflective groove (GV), more material accumulates at the bottom of the groove while less material is accumulated at the opening, resulting in at least a portion of the formed pixel-defining unit (PDU) having a thickness gradient.

[0113] In one example, the pixel-defining material layer (PDLX) is made of a positive adhesive; the liquefaction process of the PDLX includes irradiating it with ultraviolet light. When the pixel-defining precursor unit (PDUX) is irradiated with ultraviolet light, the ultraviolet-sensitive groups in the PDUX can break, leading to partial disruption of the intermolecular cross-links and giving the PDUX a certain degree of fluidity. After flowing, the PDUX forms the morphology of the pixel-defining unit (PDU) disclosed herein, which can then be cured using curing processes such as baking to form the pixel-defining unit (PDU).

[0114] In one example, when the pixel definition precursor unit PDUX flows after liquefaction, the inner edge P1 of the upper surface TSF moves 0.8 to 1.5 micrometers toward the center of the reflective groove GV, for example, 0.8μm, 0.9μm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm.

[0115] In one example, the material used for the pixel-defining material layer PDLX can be the same as that used for the top planarization layer TPLN, and in particular, the material used for the pixel-defining material layer PDLX can be the same as that used for the second sublayer TPLN2 of the top planarization layer. Thus, similar exposure and development conditions can be used during the fabrication of the reflective groove GV and the pixel-defining precursor unit PDUX; and the upper surface TSF of the pixel-defining precursor unit PDUX maintains approximately the same slope as the sidewall of the reflective groove GV. By making the pixel-defining precursor unit PDUX fluid and allowing it to flow into the reflective groove GV, it can be ensured that the slope angle of the upper surface TSF of the formed pixel-defining unit PDU is small.

[0116] Figures 7 and 8 are schematic diagrams of the reflective structure RS. For greater clarity, Figures 7 and 8 show the ideal morphology of the organic film layers, including the reflective groove GV and the pixel definition unit (PDU). It is understandable that due to the fabrication process, the actual morphology of the organic film layers generally follows the trend of the ideal morphology, but it is usually difficult to observe obvious turning angles as shown in Figures 7 and 8. Figures 9 and 10 are another partial structural schematic diagram of the pixel definition unit (PDU). The morphology of the PDU shown in Figures 9 and 10 is closer to the morphology of the pixel definition unit (PDU) in the actual fabrication process.

[0117] In one embodiment of this disclosure, referring to Figures 9 and 10, the pixel definition unit (PDU) has a gradient portion (PDU1) located on the side of the critical reference plane L0 close to the substrate SBT; the lateral width D2 of the gradient portion (PDU1) decreases sequentially along the direction away from the substrate SBT.

[0118] The lateral width D2 of the gradient portion PDU1 refers to the distance between the inner edge and the outer edge of the gradient portion PDU1 on the first reference plane; the first reference plane and the critical reference plane L0 are both parallel to the substrate SBT; the first reference plane is located between the critical reference plane L0 and the plane where the flat portion PEA is located.

[0119] In one example, the slope angle formed by the lower surface DSF of the gradient portion PDU1 and the first reference plane is greater than the slope angle formed by the upper surface TSF of the gradient portion PDU1 and the first reference plane; both the first reference plane and the critical reference plane L0 are parallel to the substrate SBT; the first reference plane is located between the critical reference plane L0 and the plane where the flat portion PEA is located.

[0120] Thus, along the direction away from the substrate SBT, the gradient portion PDU1 forms a gradually converging light guide channel. The lower surface DSF of the light guide channel is attached to the ramp portion PEB and has high reflectivity. The upper surface TSF of the light guide channel can emit light and also reflect a portion of the light. The reflected light continues to be reflected repeatedly in the light guide channel, and a portion of it is emitted each time it reaches the upper surface TSF of the light guide channel.

[0121] In one embodiment of this disclosure, the distance between the inner edge P1 of the upper surface TSF (the surface away from the substrate SBT, i.e., the surface forming the pixel opening) of the pixel definition unit PDU and the inner edge P2 of the lower surface DSF (the surface near the substrate SBT, i.e., the surface in contact with the ramp portion PEB) of the pixel definition unit PDU is a first dimension X1, which is between 1.5 and 2.4 micrometers. This ensures, on the one hand, that the ramp portion PEB is covered by a sufficiently thick pixel definition unit PDU, preventing insufficient insulation of the pixel definition unit PDU from causing a short circuit between the ramp portion PEB and the light-emitting functional layer EFL (which would lead to changes in the light-emitting area and light-emitting region of the sub-pixel). On the other hand, this avoids the flat portion PEA being covered by an excessively large area (i.e., avoiding an excessively large area covering the sub-part PEA1), thereby ensuring that the effective area of ​​the flat portion PEA (i.e., covering the sub-part PEA1) is as large as possible, thus guaranteeing the light-emitting area of ​​the sub-pixel.

[0122] In one example, the first dimension X1 is 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, or 2.4μm.

[0123] In one embodiment of this disclosure, the thickness of the outer edge P4 of the pixel definition unit (PDU) is a second dimension X2, which is between 0.8 and 1.2 micrometers. The orthographic projection of the outer edge P4 of the PDU onto the substrate SBT coincides with the orthographic projection of the opening edge of the reflective groove GV onto the substrate SBT. Clearly, because the pixel definition precursor unit (PDUX) flows into the reflective groove GV after liquefaction, the amount of material of the PDU at the opening of the reflective groove GV is less than the amount of material of the PDU at the bottom of the reflective groove GV, resulting in the PDU becoming thinner at the opening of the reflective groove GV.

[0124] In one example, the second dimension X2 is 0.8μm, 0.85μm, 0.9μm, 0.95μm, 1μm, 1.05μm, 1.1μm, 1.15μm, or 1.2μm.

[0125] In one embodiment of this disclosure, the distance between the inner edge P1 of the upper surface TSF of the pixel definition unit PDU and the inner edge P2 of the lower surface DSF of the pixel definition unit PDU is a first dimension X1, and the thickness of the pixel definition unit PDU at the outer edge P4 is a second dimension X2. The orthographic projection of the outer edge P4 of the pixel definition unit PDU on the substrate SBT coincides with the orthographic projection of the opening edge of the reflective groove GV on the substrate SBT. The first dimension X1 is 1.5 to 2.5 times the second dimension X2, and more particularly, the first dimension X1 is 1.6 to 2.0 times the second dimension X2. When the pixel definition precursor unit PDUX liquefies and flows, the material of the pixel definition precursor unit PDUX located at the groove opening of the reflective groove GV flows towards the bottom of the reflective groove GV, which increases the first dimension X1 and decreases the second dimension X2, thereby giving the upper surface TSF of the pixel definition unit PDU a smaller slope angle. However, the flow rate of the pixel definition unit (PDUX) needs to be controlled to avoid excessive flow rate, which would result in the second dimension (X2) being too small and the first dimension (X1) being too large. If the flow rate is too large, the ratio of the first dimension (X1) to the second dimension (X2) will be larger, which will cause the PDU to be too thin at the opening of the reflector groove (GV), making it prone to insulation defects. Furthermore, the PDU's coverage area on the planar portion (PEA) will be too large, resulting in insufficient effective area of ​​the PEA. If the flow rate is too small, the ratio of the first dimension (X1) to the second dimension (X2) will be smaller, which will reduce the difference in slope angle between the upper surface (TSF) of the PDU and the surface of the ramp portion (PEB). Along the direction away from the center of the reflector groove (GV), the convergence effect of the light refraction path caused by the thickness change of the PDU will be weakened, thus reducing the light emission enhancement effect.

[0126] In one example, the first size X1 is 1.6 times, 1.65 times, 1.7 times, 1.75 times, 1.8 times, 1.85 times, 1.9 times, 1.95 times, or 2 times the second size X2.

[0127] As an example, the first dimension X1 is 1.88 micrometers and the second dimension X2 is 1.02 micrometers.

[0128] In one embodiment of this disclosure, the thickness D1 of the pixel definition unit PDU at the inner edge P2 of the lower surface DSF is 1.3 to 1.8 times the thickness (i.e., the second dimension X2) of the pixel definition unit PDU at the outer edge P4 of the lower surface DSF. For example, it is 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, or 1.8 times.

[0129] In one embodiment of this disclosure, the depth of the reflective groove GV is a fourth dimension x4; the component of the distance between the inner edge P1 of the upper surface TSF of the pixel definition unit PDU and the outer edge P3 of the upper surface TSF of the pixel definition unit PDU in the direction parallel to the substrate SBT is a third dimension x3. The third dimension x3 is 2.5 to 3.5 times the fourth dimension x4, particularly 2.3 to 2.7 times. For example, the third dimension x3 is 2.3 times, 2.35 times, 2.4 times, 2.45 times, 2.5 times, 2.55 times, 2.6 times, 2.65 times, or 2.7 times the fourth dimension x4.

[0130] In one embodiment of this disclosure, the depth of the reflective groove GV is a fourth dimension x 4; the component of the distance between the inner edge and the outer edge of the ramp portion PEB in the direction parallel to the substrate SBT is a fifth dimension x 5, which is 1.8 to 2.4 times the fourth dimension x 4. Thus, the ramp portion PEB itself has a suitable slope angle, which can cooperate with the upper surface TSF of the pixel definition unit PDU to form a convergent light guide channel. Further, the fifth dimension x 5 is 1.8 to 2.2 times the fourth dimension x 4, for example, 1.8 times, 1.85 times, 1.9 times, 1.95 times, 2 times, 2.05 times, 2.1 times, 2.15 times, or 2.2 times.

[0131] In one example, the fourth dimension X4 is between 2.0 μm and 3.0 μm, for example, 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm or 3 μm.

[0132] In one example, the fifth dimension X5 is between 2.0 and 3.0 micrometers, for example, between 4.2 μm and 6.2 micrometers, and particularly between 4.7 μm and 5.7 μm, for example, 4.7 μm, 4.8 μm, 4.9 μm, 5 μm, 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm, 5.5 μm, 5.6 μm or 5.7 μm.

[0133] This disclosure also tested the effects of the improved and unimproved reflective structures. Figure 6 is a schematic diagram of the morphology of the reflector in the related art, where the upper surface TSF0 is the upper surface of the pixel definition unit PDU0 in the related art. The upper surface TSF, indicated by the dashed line in Figure 6, is the upper surface of the pixel definition unit PDU in this disclosure embodiment. In this test, the difference between the display panel before improvement (using the reflective structure in the related art) and the display panel after improvement (using the reflective structure provided in this disclosure embodiment) lies only in the morphology of the pixel definition unit and the shape difference of the subsequent film layer caused by this morphology difference (which basically does not affect light emission), and the actual light-emitting area of ​​the sub-pixels of the same color is the same. The test found that the improved reflective structure improves the light emission efficiency of red, green and blue sub-pixels, and the improvement in light emission efficiency for blue sub-pixels and white light efficiency is significantly stronger than that of the related art. Specifically, through improvements to the pixel definition unit, the reflective structure provided in this disclosure increases the light extraction efficiency of the blue sub-pixel from 4.9% (related technologies) to 6.% (this disclosure), an improvement of 22%; the reflective structure increases the white light efficiency from 4.9% (related technologies) to 5.6% (this disclosure), an improvement of 14%. The improved reflective structure can improve red light efficiency by 4.7% and green light efficiency by 4.0%. Thus, compared to related technologies, the reflective structure RS of this disclosure can improve both blue and white light efficiency in application, which is of great significance for improving the lifespan of blue light devices and the lifespan of the display panel PNL.

[0134] The fabrication process illustrated in Figures 13 and 14 of this disclosure employs a two-step method to fabricate the pixel definition layer (PDL): first, a pixel definition precursor unit (PDUX) is formed, and then the PDUX is shaped. It is understood that in other embodiments of this disclosure, the pixel definition layer (PDL) can also be fabricated in a one-step method. For example, when forming the pixel definition material layer (PDLX), a material different from the top planarization layer (TPLN), particularly a material different from the second sublayer (TPLN2) of the top planarization layer, can be selected. This material produces a pattern with a smaller slope angle on the sidewalls after exposure and development. Then, the pixel definition unit (PDU) is directly fabricated through exposure and development. In this way, the slope angle of the pixel definition unit (PDU) can be smaller than the slope angle of the reflective groove (GV), thereby enabling the pixel definition unit (PDU) to have a size-converging light guide channel along a direction away from the center of the reflective groove (GV).

[0135] In one embodiment of this disclosure, referring to FIG7, the slope angle θ1 of the upper surface TSF of the pixel definition unit PDU at its inner edge P1 is smaller than the slope angle θ2 of the lower surface DSF of the pixel definition unit PDU at its inner edge P2. On the one hand, this ensures that the thickness of the pixel definition unit PDU decreases sequentially near the center of the reflective groove GV. On the other hand, when light refracts back and forth between the upper surface TSF and the lower surface DSF of the pixel definition unit PDU, the incident angle with the lower surface DSF or the upper surface TSF decreases sequentially, making it easier for light to exit during refraction, thereby improving the light extraction efficiency.

[0136] In one embodiment of this disclosure, the slope angle θ1 of the upper surface TSF of the pixel definition unit PDU at its inner edge P1 is at least 5° smaller than the slope angle θ2 of the lower surface DSF of the pixel definition unit PDU at its inner edge P2, and particularly is 5° to 20° smaller. For example, the slope angle θ1 of the upper surface TSF of the pixel definition unit PDU at its inner edge P1 is at least 5°, 6°, 7°, 8°, 9°, 10°, 11°, 12°, 13°, 14°, 15°, 16°, 17°, 18°, 19°, or 20° smaller than the slope angle θ2 of the lower surface DSF of the pixel definition unit PDU at its inner edge P2.

[0137] In one example, the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is between 40° and 55°. Thus, the overall slope angle of the upper surface TSF of the pixel definition unit PDU is suitable, which is beneficial for the fabrication of the pixel definition unit PDU. For example, a pixel definition precursor unit PDUX can be fabricated first, and then the pixel definition precursor unit PDUX can be partially liquefied, allowing it to be shaped under stress and external force to change the morphology of the upper surface TSF, and then solidified into a pixel definition unit PDU. During the shaping process, the slope of the upper surface TSF of the pixel definition precursor unit PDUX decreases, resulting in a slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 between 40° and 55°, particularly between 40° and 49°. For example, the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is 40.1°, 40.6°, 41.1°, 41.6°, 42.1°, 42.6°, 43.1°, 43.6°, 44.1°, 44.6°, 45.1°, 45.6°, 46.1°, 46.6°, 47.1°, 47.6°, or 48.1°.

[0138] In one example, the slope angle of the lower surface DSF of the pixel definition unit PDU at its inner edge P2 is between 55° and 65°. The lower surface DSF of the pixel definition unit PDU substantially coincides with the upper surface of the ramp portion PEB, and the slope angle at its inner edge ensures the continuity of the pixel electrode PE. Optionally, the pixel definition precursor unit PDUX can be partially liquefied using an illumination method (e.g., ultraviolet irradiation). The second reflective substrate RB2 and the first reflective substrate RB1, protected by the pixel electrode PE, will not undergo partial liquefaction, thereby maintaining the slope angle of the sidewall of the reflective groove GV, and ultimately maintaining the slope angle of the lower surface DSF of the pixel definition unit PDU at its inner edge P2. Furthermore, the slope angle of the lower surface DSF of the pixel definition unit (PDU) at the inner edge P2 is between 55° and 62°, for example, 55.2°, 55.7°, 56.2°, 56.7°, 57.2°, 57.7°, 58.2°, 58.7°, 59.2°, 59.7°, 60.2°, 60.7°, 61.2°, 61.7°, or 62°.

[0139] In one embodiment of this disclosure, the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 is between 40° and 49°; the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 is between 55° and 62°; the difference between the slope angle of the upper surface TSF of the pixel definition unit PDU at the inner edge P1 and the slope angle of the lower surface DSF of the pixel definition unit PDU at the inner edge P2 is between 10° and 15°, especially between 13° and 14.5°, for example, between 13°, 13.1°, 13.2°, 13.3°, 13.4°, 13.5°, 13.6°, 13.7°, 13.8°, 13.9°, 14°, 14.1°, 14.2°, 14.3°, 14.4° or 14.5°.

[0140] It is understood that in other embodiments of this disclosure, the slope angle of the upper surface of the pixel definition unit (PDU) can also remain substantially consistent. For example, after forming the pixel definition material layer (PDLX), parameters such as the exposure light intensity, the size of the light-transmitting aperture on the mask, or the light transmittance of the light-transmitting aperture can be adjusted during exposure of the PDLX, or the material of the pixel definition layer (PDL) can be adjusted so that the slope angle of the upper surface of the pixel definition unit (PDU) formed after exposure is smaller than the sidewall slope angle of the reflective groove (GV) formed by the top planarization layer (TPLN).

[0141] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a substrate, a driving layer, and a pixel layer stacked sequentially; wherein the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel definition layer stacked sequentially on the surface of the top planarization layer; the display panel includes multiple reflective structures, any one of which includes: A reflective substrate located in the top planarization layer and having a reflective groove; An electrode unit is disposed on the pixel electrode layer; the electrode unit includes a ramp portion covering the sidewall of the reflective groove and a flat portion covering the bottom of the reflective groove; A pixel definition unit is disposed in the pixel definition layer; the pixel definition unit covers at least a portion of the climbing portion and exposes at least a portion of the flat portion. Along a direction away from the center of the reflective groove, the thickness of at least a portion of the pixel definition unit gradually decreases.

2. The display panel according to claim 1, characterized in that, The pixel definition unit has a gradient portion located on the side of the critical reference plane closer to the substrate; the lateral width of the gradient portion decreases sequentially along the direction away from the substrate. The lateral width of the gradient portion refers to the distance between the inner edge and the outer edge of the gradient portion on the first reference plane; both the first reference plane and the critical reference plane are parallel to the substrate; the first reference plane is located between the critical reference plane and the flat portion.

3. The display panel according to claim 1, characterized in that, The distance between the inner edge of the upper surface of the pixel definition unit and the inner edge of the lower surface of the pixel definition unit is a first dimension, which is between 1.5 and 2.4 micrometers.

4. The display panel according to claim 1, characterized in that, The thickness of the pixel definition unit at its outer edge P1 is a second dimension, which is between 0.8 and 1.2 micrometers. The orthographic projection of the outer edge of the pixel definition unit on the substrate coincides with the orthographic projection of the opening edge of the reflective groove on the substrate.

5. The display panel according to claim 1, characterized in that, The distance between the inner edge of the upper surface of the pixel definition unit and the inner edge of the lower surface of the pixel definition unit is a first dimension, and the thickness of the pixel definition unit at the outer edge is a second dimension; the orthographic projection of the outer edge of the pixel definition unit on the substrate coincides with the orthographic projection of the opening edge of the reflective groove on the substrate. The first dimension is 1.5 to 2.5 times the second dimension.

6. The display panel according to claim 1, characterized in that, The depth of the reflective groove is between 2.0 and 3.0 micrometers; the component of the distance between the inner edge and the outer edge of the ramp portion in the direction parallel to the substrate is 1.8 to 2.4 times the depth of the reflective groove.

7. The display panel according to claim 1, characterized in that, The thickness of the pixel definition unit at the inner edge of the lower surface is 1.3 to 1.8 times the thickness of the pixel definition unit at the outer edge of the lower surface.

8. The display panel according to any one of claims 1 to 7, characterized in that, The slope angle of the upper surface of the pixel definition unit at its inner edge is smaller than the slope angle of the lower surface of the pixel definition unit at its inner edge.

9. The display panel according to claim 8, characterized in that, The slope angle of the upper surface of the pixel definition unit at the inner edge is between 40° and 55°. The slope angle of the lower surface of the pixel definition unit at the inner edge is between 55° and 65°. The slope angle of the upper surface of the pixel definition unit at its inner edge is at least 5° smaller than the slope angle of the lower surface of the pixel definition unit at its inner edge.

10. The display panel according to any one of claims 1 to 7, characterized in that, Along a direction away from the center of the reflective groove, the slope angle of the upper surface of the pixel definition unit gradually decreases.

11. The display panel according to any one of claims 1 to 7, characterized in that, The pixel definition unit has a gradient portion located on the side of the critical reference plane closer to the substrate. The slope angle formed by the lower surface of the gradient section and the first reference plane is greater than the slope angle formed by the upper surface of the gradient section and the first reference plane; Both the first reference plane and the critical reference plane are parallel to the substrate. The first reference plane is located between the critical reference plane and the flat portion.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

13. A method for manufacturing a display panel, characterized in that, include: A driving layer and a pixel layer are sequentially formed on one side of a substrate; wherein, the driving layer includes a top planarization layer, and the pixel layer includes a pixel electrode layer and a pixel definition layer sequentially stacked on the surface of the top planarization layer; The top planarization layer forming the driving layer includes: A top planarization layer is formed, such that the top planarization layer has multiple reflective grooves; Forming the pixel electrode layer includes: A pixel electrode layer is formed, such that the pixel electrode layer includes a plurality of electrode units corresponding one-to-one with the plurality of reflective grooves, and the electrode unit includes a ramp portion covering the sidewall of the corresponding reflective groove and a flat portion covering the bottom of the corresponding reflective groove; Forming the pixel definition layer includes: The pixel definition layer is formed such that it includes a plurality of pixel definition units corresponding one-to-one with the plurality of electrode units, the pixel definition units covering the ramp portion of the corresponding electrode unit and exposing at least a portion of the flat portion of the corresponding electrode unit; the thickness of at least a portion of the pixel definition units gradually decreases along a direction away from the center of the corresponding reflective groove.

14. The method for manufacturing a display panel according to claim 13, characterized in that, Forming the pixel definition layer includes: A pixel definition material layer is formed, which covers the pixel electrode layer; The pixel definition material layer is patterned to form pixel definition precursor units that correspond one-to-one with the plurality of electrode units. The pixel definition precursor units cover the ramp portion and part of the flat portion of the corresponding electrode unit. This causes at least a portion of the pixel definition precursor unit to liquefy, and at least a portion of the material of the pixel definition precursor unit to deform into the reflective groove; The deformed pixel definition precursor unit is solidified to form the pixel definition unit.

15. The method for manufacturing a display panel according to claim 13, characterized in that, The material of the pixel definition precursor unit is positive adhesive; The process of at least partially liquefying the pixel definition precursor unit includes irradiating the pixel definition precursor unit with ultraviolet light.

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