Display substrate and display device

Abstract

Provided are a display substrate and a display device. The display substrate comprises a substrate, data signal lines (DL), data fan-out lines (10), and a conductive structure (20). The conductive structure (20) comprises a plurality of first power traces (21), a plurality of second power traces (22), and a plurality of transfer electrodes (23). The plurality of first power traces (21) extend in a first direction (X) and are arranged in a second direction (Y); and the plurality of second power traces (22) extend in the second direction (Y) and are arranged in the first direction (X). The plurality of first power traces (21) and the plurality of second power traces (22) are connected by means of the transfer electrodes (23) to form a mesh structure for transmitting a low-level signal. The plurality of first power traces (21) and the plurality of second power traces (22) form a plurality of overlapping regions (JD). A second area (AA2) comprises a plurality of sub-areas, each sub-area has an arrangement density of transfer electrodes (23), and the arrangement density of the transfer electrodes (23) in the plurality of sub-areas gradually increases in a direction away from a first area (AA1).

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202510361816.5, filed on March 25, 2025, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, embodiments of this disclosure provide a display substrate, including:

[0006] A substrate, including a display area, the display area including a first area and a second area;

[0007] Multiple data signal lines are located in the display area, and the multiple data signal lines are spaced apart along a first direction and extend along a second direction. The first direction and the second direction intersect and the plane formed by them is parallel to the plane where the substrate is located.

[0008] Multiple data fan-out lines are located in the first region and connected to the data signal lines;

[0009] A conductive structure is located in the second region. The conductive structure includes multiple first power lines, multiple second power lines, and multiple transition electrodes. The multiple first power lines extend along a first direction and are spaced apart along a second direction. The multiple second power lines extend along the second direction and are spaced apart along the first direction. The multiple first power lines and the multiple second power lines are interconnected via the transition electrodes to form a mesh structure for transmitting low-level signals. The orthographic projections of the multiple first power lines and the multiple second power lines onto the plane of the substrate form multiple overlapping areas.

[0010] The second region includes multiple sub-regions, each of which has a density of the transfer electrodes. The density of the transfer electrodes in the multiple sub-regions gradually increases in the direction away from the first region. The density of the transfer electrodes is the ratio of the number of transfer electrodes in the sub-region to the number of overlapping regions.

[0011] In some exemplary embodiments, the arrangement density of the transfer electrode in the sub-region furthest from the first region among the plurality of sub-regions is 1.0.

[0012] In some exemplary embodiments, the arrangement density of the transfer electrodes in the sub-regions adjacent to the first region in the plurality of sub-regions is greater than or equal to 0 and less than or equal to 0.7.

[0013] In some exemplary embodiments, the difference in arrangement density of the transfer electrodes in any pair of adjacent sub-regions in the plurality of sub-regions is less than or equal to 0.7.

[0014] In some exemplary embodiments, the display area is further provided with a plurality of sub-pixels; the plurality of sub-pixels include at least a red sub-pixel, a blue sub-pixel, and a green sub-pixel, wherein the red sub-pixel is configured to emit red light, the blue sub-pixel is configured to emit blue light, and the green sub-pixel is configured to emit green light.

[0015] In the second region, the plurality of overlapping regions are grouped with the plurality of sub-pixels; or, one of the overlapping regions is grouped with two of the sub-pixels.

[0016] In some exemplary embodiments, the first power trace and the transition electrode are located on the same conductive layer and are an integral structure interconnected, the second power trace and the first power trace are located on different conductive layers, and the orthographic projections of the second power trace and the transition electrode on the plane of the substrate at least partially overlap.

[0017] In some exemplary embodiments, the orthographic projection of at least one of the second power lines onto the plane of the substrate includes the orthographic projection of the transition electrode onto the plane of the substrate.

[0018] In some exemplary embodiments, at least one light-shielding portion is further included, and the light-shielding portion is located on the side of the conductive structure away from the substrate, and the light-shielding portion and the orthographic projection of the conductive structure on the plane where the substrate is located at least partially overlap; in the visible light range, the reflectivity of the light-shielding portion is less than the reflectivity of the conductive structure.

[0019] In some exemplary embodiments, the orthographic projection of at least one of the light-shielding portions onto the plane of the substrate includes the orthographic projection of the transfer electrode onto the plane of the substrate.

[0020] In some exemplary embodiments, the display area is further comprising a plurality of sub-pixels; the plurality of sub-pixels include at least a red sub-pixel, a blue sub-pixel, and a green sub-pixel, wherein the red sub-pixel is configured to emit red light, the blue sub-pixel is configured to emit blue light, and the green sub-pixel is configured to emit green light; each sub-pixel includes a light-emitting device located on the side of the conductive structure away from the substrate; the light-emitting device includes a stacked anode, an organic light-emitting layer, and a cathode, and the light-shielding portion is located on the same conductive layer as the anode.

[0021] In some exemplary embodiments, the light-shielding portion and the anode of the red sub-pixel are an integral structure interconnected, or the light-shielding portion and the anode of the blue sub-pixel are an integral structure interconnected.

[0022] In some exemplary embodiments, at least one of the second power supply traces is located between two adjacent data signal traces.

[0023] In some exemplary embodiments, the light-shielding portion and the anode of the green sub-pixel are an integral structure connected to each other.

[0024] In some exemplary embodiments, at least two adjacent second power supply traces are located on either side of two adjacent data signal traces along the first direction.

[0025] On the other hand, embodiments of this disclosure provide a display device including the display substrate described in any of the foregoing embodiments.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0027] Overview of the attached figures

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1 is a schematic diagram of the structure of a display device;

[0030] Figure 2 is a schematic diagram of a display substrate;

[0031] Figure 3 is a schematic diagram of the structure of a display substrate according to an embodiment of the present disclosure;

[0032] Figure 4A is a partially enlarged schematic diagram of an embodiment marked A in Figure 3;

[0033] Figure 4B is a partially enlarged schematic diagram of another embodiment marked A in Figure 3;

[0034] Figure 5A is a partial enlarged planar schematic diagram of the overlapping area of ​​a display substrate according to an embodiment of the present disclosure;

[0035] Figure 5B is a cross-sectional view of the section marked BB in Figure 5A;

[0036] Figure 5C is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0037] Figure 6 is a partial enlarged planar schematic diagram of the overlapping area of ​​the display substrate according to another embodiment of the present disclosure;

[0038] Figure 7A is a partial enlarged planar schematic diagram of the overlapping area of ​​the display substrate according to another embodiment of the present disclosure;

[0039] Figure 7B is a cross-sectional view of the area marked CC in Figure 7A;

[0040] Figure 7C is a partial cross-sectional schematic view of the overlapping area of ​​a display substrate according to another embodiment of the present disclosure;

[0041] Figure 8 is a partial enlarged planar schematic diagram of the overlapping area of ​​the display substrate according to another embodiment of the present disclosure;

[0042] Figure 9 is a partial enlarged planar schematic diagram of the anode layer of a display substrate according to an embodiment of the present disclosure;

[0043] Figure 10 is a partial planar enlarged schematic diagram of the anode layer of a display substrate according to another embodiment of the present disclosure.

[0044] Detailed Explanation

[0045] The embodiments of this disclosure will be described below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0046] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0047] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0048] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0049] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0050] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0051] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0052] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0053] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0054] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0055] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0056] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm, where m can be a natural number. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. The light-emitting driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to light-emitting signal lines E1, E2, E3, ..., Eo. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo, where o can be a natural number. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0057] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. The display area 100 may include multiple sub-pixels, multiple data signal lines D, and multiple data fan-out lines 400. The multiple data signal lines D may extend along a second direction Y and be spaced apart along a first direction X. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device. The pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0058] The display substrate can adopt a fanout-in-panel (FIP) structure, with multiple data fanout lines 400 disposed in the display area 100. One end of each data fanout line 400 is connected to multiple data signal lines D in the display area 100, and the other end of each data fanout line 400 can be located in the bonding area 200, connected to the integrated circuit via multiple data leads. Because the bonding area reduces the number of diagonal traces in the fan shape, it reduces the width of the bonding area in the second direction Y, thus narrowing the width of the bottom bezel of the display substrate, which is beneficial for a narrow bezel design.

[0059] Currently, display substrates using a Fanout in Panel (FIP) structure have uneven surface reflection between areas with and without data fanout lines due to the addition of data fanout lines in certain parts of the display area. This results in brightness differences in the display substrate when the screen is off.

[0060] Therefore, this disclosure provides a display substrate, including:

[0061] A substrate, including a display area, the display area including a first area and a second area;

[0062] Multiple data signal lines are located in the display area, and the multiple data signal lines are spaced apart along a first direction and extend along a second direction. The first direction and the second direction intersect and the plane formed by them is parallel to the plane where the substrate is located.

[0063] Multiple data fan-out lines are located in the first region and connected to the data signal lines;

[0064] A conductive structure is located in the second region. The conductive structure includes multiple first power lines, multiple second power lines, and multiple transition electrodes. The multiple first power lines extend along a first direction and are spaced apart along a second direction. The multiple second power lines extend along the second direction and are spaced apart along the first direction. The multiple first power lines and the multiple second power lines are interconnected via the transition electrodes to form a mesh structure for transmitting low-level signals. The orthographic projections of the multiple first power lines and the multiple second power lines onto the plane of the substrate form multiple overlapping areas.

[0065] The second region includes multiple sub-regions, each of which has a density of the transfer electrodes. The density of the transfer electrodes in the multiple sub-regions gradually increases in the direction away from the first region. The density of the transfer electrodes is the ratio of the number of transfer electrodes in the sub-region to the number of overlapping regions.

[0066] In this embodiment of the disclosure, by setting the second region to include multiple sub-regions and limiting the arrangement density of the transfer electrodes in the multiple sub-regions to gradually increase in the direction away from the first region, abrupt changes in the reflective area between the first region and the second region can be avoided, thereby improving the uniformity of reflected light on the surface of the display substrate and improving display quality.

[0067] Figure 3 is a schematic diagram of the structure of a display substrate according to an embodiment of the present disclosure. As shown in Figure 3, the display substrate includes a substrate, which includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA may include at least a first area AA1 and a second area AA2, which do not overlap. The second area AA2 may surround at least one side of the first area AA1. The second area AA2 may include multiple sub-areas. For example, the second area AA2 may include two sub-areas, namely a first sub-area AA2-1 and a second sub-area AA2-2.

[0068] The display substrate may include multiple sub-pixels located in the display area AA, multiple data signal lines DL, and multiple data fan-out lines 10. Each data fan-out line 10 may include a first end and a second end positioned opposite each other. The first end may be connected to the data signal line DL, and the second end is closer to the peripheral area BB than the first end. Each data fan-out line 10 may include a first fan-out line 11 and a second fan-out line 12 connected together. The first fan-out line 11 may extend along a first direction X, and the second fan-out line 12 may extend along a second direction Y. Both the first fan-out line 11 and the second fan-out line 12 include a first end and a second end positioned opposite each other. The first end of the first fan-out line 11 may be connected to the data signal line DL, and the second end of the first fan-out line 11 is connected to the first end of the second fan-out line 12. The second end of the second fan-out line 12 may be located in the peripheral area BB. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device. The pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit. Multiple data signal lines DL can extend along the second direction Y and be spaced apart along the first direction X. The first direction X intersects the second direction Y, and the plane formed by them is parallel to the plane of the substrate. As shown in Figure 3, only fifteen data signal lines DL and six data fan-out lines 10 are illustrated. The multiple data fan-out lines 10 are located in the first region AA1.

[0069] The display substrate may also include a conductive structure 20, which can be used to transmit low-level signals. The display substrate can adopt a SIP (VSS In Pixel) design, where the conductive structure 20 is connected within the second region AA2 to form a mesh structure. This reduces the voltage drop of low-level signals within the display area, improves the uniformity of voltage distribution, enhances the display effect, and reduces power consumption. The combination of SIP and FIP designs can, to some extent, improve the uniformity of reflected light on the display substrate surface and reduce brightness differences in the off-screen state.

[0070] As shown in Figure 3, the conductive structure 20 may include multiple first power lines 21 and multiple second power lines 22. The multiple first power lines 21, multiple second power lines 22, and multiple data signal lines DL are illustrated using different line types for easy identification. The multiple first power lines 21 may extend along a first direction X and be spaced apart along a second direction Y. The multiple second power lines 22 may extend along the second direction Y and be spaced apart along the first direction X. The first power lines 21 and second power lines 22 are located in different conductive layers. For example, the first power lines 21 may be closer to the substrate than the second power lines 22. For example, the first power lines 21 may be located in a first source / drain metal layer (SD1), and the second power lines 22 may be located in a second source / drain metal layer (SD2). Alternatively, the first power lines 21 may be located in a second source / drain metal layer (SD2), and the second power lines 22 may be located in a third source / drain metal layer (SD3). The first power lines 21 and the first fan-out line 11 may be located in the same conductive layer. The second power supply trace 22 and the second fan-out trace 12 can be located on the same conductive layer.

[0071] In some exemplary embodiments, the display substrate may further include a power supply line VSS located in the peripheral region BB, at least a portion of which may surround the display region AA. The power supply line VSS is configured to transmit a low-level signal. At least a portion of the plurality of first power traces 21 are connected to the power supply line VSS. At least a portion of the plurality of second power traces 22 are connected to the power supply line VSS. In embodiments of this disclosure, connecting the conductive structure 20 to the power supply line VSS can improve the uniformity of the low-level signal distribution.

[0072] In some exemplary embodiments, as shown in FIG3, the peripheral area BB may include multiple border areas, which may include a first border area B1 located on one side of the display area AA and a second border area B2 disposed opposite to the first border area B1. Along the second direction Y, the first border area B1 and the second border area B2 are respectively located on both sides of the display area AA.

[0073] The multiple border regions may further include a third border region B3 located on one side of the display region AA, and a fourth border region B4 disposed opposite to the third border region B3. Along the first direction X, the third border region B3 and the fourth border region B4 are respectively located on both sides of the display region AA. In the embodiments of this disclosure, the first border region B1 may also be referred to as the lower border of the display substrate, the second border region B2 may also be referred to as the upper border of the display substrate, the third border region B3 may also be referred to as the left border of the display substrate, and the fourth border region B4 may also be referred to as the right border of the display substrate.

[0074] The peripheral area BB may further include at least one transition area, and at least one pair of adjacent border areas are connected via a transition area. At least a portion of the boundary of the at least one transition area near the display area AA may be an arc-shaped boundary. In Figure 3, the peripheral area BB is illustrated with four transition areas: a first transition area G1, a second transition area G2, a third transition area G3, and a fourth transition area G4. The first transition area G1 is located between the first border area B1 and the third border area B3, and the first border area B1 and the third border area B3 are connected via the first transition area G1. The second transition area G2 is located between the first border area B1 and the fourth border area B4, and the first border area B1 and the fourth border area B4 are connected via the second transition area G2. The third transition area G3 is located between the second border area B2 and the fourth border area B4, and the second border area B2 and the fourth border area B4 are connected via the third transition area G3. The fourth transition region G4 is located between the second border region B2 and the third border region B3, and the second border region B2 and the third border region B3 are connected through the fourth transition region G4.

[0075] Figure 4A is a partially enlarged schematic diagram of one embodiment marked A in Figure 3, and Figure 4B is a partially enlarged schematic diagram of another embodiment marked A in Figure 3. As shown in Figures 4A and 4B, the display area AA of the display substrate may include multiple pixel units arranged in a rectangular manner. At least one pixel unit may include multiple sub-pixels, and the multiple sub-pixels may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The light-emitting unit may include at least a light-emitting device, and the circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line, the data signal line, and the light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel. The first sub-pixel P1 is configured to emit light of the first color, the second sub-pixel P2 and the fourth sub-pixel P4 are configured to emit light of the second color, and the third sub-pixel P3 is configured to emit light of the third color. For example, the first color can be red, the second color can be green, and the third color can be blue. Alternatively, the first color can be blue, and the third color can be red. Alternatively, the second sub-pixel P2 can be configured to emit light of the second color, and the fourth sub-pixel P4 can be configured to emit white light.

[0076] As shown in Figure 4A, multiple first power lines 21 can extend along a first direction X and are spaced apart along a second direction Y. Multiple second power lines 22 can extend along the second direction Y and are spaced apart along the first direction X. In the second region, the orthographic projections of the multiple first power lines 21 and the multiple second power lines 22 onto the plane of the substrate form multiple overlapping regions JD. The multiple overlapping regions JD are grouped with multiple sub-pixels, and the orthographic projections of the overlapping regions JD and the sub-pixels onto the plane of the substrate at least partially overlap. For example, the overlapping regions JD are located within the orthographic projections of the grouped sub-pixels onto the plane of the substrate. Alternatively, one overlapping region JD is grouped with two sub-pixels, and the overlapping region JD and the orthographic projections of the sub-pixels onto the plane of the substrate at least partially overlap. For example, the overlapping regions JD are located within the orthographic projections of the grouped sub-pixels onto the plane of the substrate, as shown in Figure 4B.

[0077] In some exemplary embodiments, at least one pixel unit may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.

[0078] In some exemplary embodiments, the orthographic projection of a sub-pixel onto the plane of the substrate can be rectangular, rhomboid, pentagonal, or hexagonal.

[0079] Figure 5A is a partial enlarged planar view of the overlapping area of ​​a display substrate according to an embodiment of this disclosure, and Figure 5B is a cross-sectional view at point BB in Figure 5A. As shown in Figure 5A, only a portion of the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2) is shown, taking an example where the first power line 21 is located in the first source / drain metal layer (SD1) and the second power line 22 is located in the second source / drain metal layer (SD2). In this embodiment of the disclosure, the direction perpendicular to the plane of the substrate is defined as the third direction and marked as Z.

[0080] As shown in Figures 5A and 5B, the conductive structure 20 may further include multiple transition electrodes 23. The transition electrodes 23 and the first power trace 21 may be located in the first source / drain metal layer (SD1), and the second power trace 22 and the data signal line DL may both be located in the second source / drain metal layer (SD2). The second power trace 22 may be located between two adjacent data signal lines DL. The first power trace 21 and the second power trace 22 are connected via the transition electrodes 23. As shown in Figure 5B, the transition electrodes 23 are connected to the first power trace 21, and the second power trace 22 is connected to the transition electrodes 23 via a via provided in the first planarization layer 34. The transition electrodes 23 may extend along the second direction Y. The transition electrodes 23 may include a first end and a second end disposed opposite to each other. The first end is connected to the first power trace 21, and the second end is located on the side of the first end opposite to the second direction Y. The second end may be connected to the second power trace 22. For example, the transition electrodes 23 and the first power trace 21 may be an integral structure interconnected. The orthographic projection of the adapter electrode 23 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second power supply trace 22 onto the plane of the substrate. Because the adapter electrode 23 increases the reflective surface area of ​​the second region AA2 compared to the first region AA1, uneven surface reflection occurs between the second region AA2 and the first region AA1, resulting in brightness differences in the display substrate when the screen is off.

[0081] The second region AA2 may include multiple sub-regions, which may be arranged sequentially in a direction away from the first region AA1. Each sub-region has a density of transition electrodes 23. In this embodiment, the density of transition electrodes 23 is defined as the ratio of the number of transition electrodes 23 in the region to the number of overlapping regions JD. The density of transition electrodes 23 may be greater than or equal to 0 and less than or equal to 1. In this embodiment, by setting the second region AA2 to include multiple sub-regions, and setting the density of transition electrodes in the multiple sub-regions to gradually increase in a direction away from the first region AA1, abrupt changes in the reflective surface area can be avoided, the uniformity of reflected light on the display substrate surface can be improved, and the display quality can be enhanced.

[0082] In some exemplary embodiments, the arrangement density of the transfer electrodes in the sub-region furthest from the first region among multiple sub-regions can be 1.0, which can reduce the voltage drop of low-level signals in the display area and improve the uniformity of voltage distribution.

[0083] In some exemplary embodiments, the arrangement density of the transfer electrodes in the sub-regions adjacent to the first region in the multiple sub-regions can be greater than or equal to 0 and less than or equal to 0.7, which can avoid abrupt changes in the reflective surface area of ​​the first region and the second region and improve the uniformity of reflected light on the surface of the display substrate.

[0084] In some exemplary embodiments, the difference in the arrangement density of the transfer electrodes of any two adjacent sub-regions in multiple sub-regions is less than or equal to 0.7, which can avoid abrupt changes in the reflective surface area of ​​two adjacent sub-regions and improve the uniformity of reflected light on the surface of the display substrate.

[0085] In some exemplary embodiments, the second region AA2 may include two sub-regions, or the second region AA2 may include three sub-regions, or the second region AA2 may include four sub-regions, etc. For example, as shown in FIG3, the second region AA2 may include two sub-regions, namely the first sub-region AA2-1 and the second sub-region AA2-2, which are arranged sequentially away from the first region AA1. The arrangement density of the transfer electrodes in the first sub-region AA2-1 and the second sub-region AA2-2 gradually increases. For example, the arrangement density of the transfer electrodes in the first sub-region AA2-1 may be 0.3, and the arrangement density of the transfer electrodes in the second sub-region AA2-2 may be 0.5. Alternatively, the arrangement density of the transfer electrodes in the first sub-region AA2-1 may be 0.5, and the arrangement density of the transfer electrodes in the second sub-region AA2-2 may be 0.8. Alternatively, the arrangement density of the transfer electrodes in the first sub-region AA2-1 may be 0.5, and the arrangement density of the transfer electrodes in the second sub-region AA2-2 may be 1.0.

[0086] In some exemplary embodiments, the materials of the first source / drain metal layer and the second source / drain metal layer may be the same or different. The material of the first source / drain metal layer may be a metallic material, such as any one or more of silver (Ag), aluminum (Al), gold (Au), platinum (Pt), nickel (Ni), and neodymium (Nd), or an alloy of the above metals, such as an aluminum-neodymium alloy (AlNd). The first source / drain metal layer may be a single-layer structure or a multi-layer composite structure.

[0087] Figure 5C is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 5C, in a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer, a light-emitting structure layer, and an encapsulation structure layer sequentially disposed on the substrate 30. The driving structure layer may include at least a plurality of pixel driving circuits for sub-pixels. Each sub-pixel's pixel driving circuit may include a plurality of transistors and at least one capacitor. The pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure, where the number before T represents the number of transistors and the number before C represents the number of capacitors. For example, the transistors may be thin-film transistors. The light-emitting structure layer may include at least a plurality of light-emitting devices for sub-pixels. In other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer away from the substrate 30 to integrate touch functionality.

[0088] As shown in Figure 5C, the driving structure layer may include a semiconductor layer, a first insulating layer 31, a first gate metal layer, a second insulating layer 32, a second gate metal layer, a third insulating layer 33, a first source / drain metal layer, a first planarization layer 34, a second source / drain metal layer, and a second planarization layer 35, which are stacked sequentially. The semiconductor layer of the display area may include the active layer T10 of the transistor T of the pixel driving circuit. The active layer T10 of the transistor T may include a first region, a second region, and a channel region located between the first region and the second region. The first gate metal layer of the display area may include the gate T11 of the transistor T and the first electrode C11 of the capacitor C. The second gate metal layer may include the second electrode C22 of the capacitor C. The orthographic projections of the second electrode C22 and the first electrode C11 onto the plane of the substrate 30 may at least partially overlap; for example, they may coincide. The first source / drain metal layer of the display area may also include the source T12 and the drain T13 of the transistor T. The source T12 of transistor T can be electrically connected to the first region of active layer T10, and the drain T13 can be electrically connected to the second region of active layer T10. The second source-drain metal layer of the display area may further include a connection electrode T14, and one of the source T12 and drain T13 is electrically connected to the connection electrode T14 through a via provided in the first planarization layer 34. For example, the drain T13 is electrically connected to the connection electrode T14 through a via provided in the first planarization layer 34. The connection electrode T14 is configured to be electrically connected to the light-emitting device to realize the electrical connection between the light-emitting device and the pixel driving circuit.

[0089] In some exemplary embodiments, the light-emitting structure layer may include a pixel definition layer and multiple light-emitting devices. Each light-emitting device may include a stacked first electrode, an organic light-emitting layer, and a second electrode. The first electrode of the light-emitting device may be electrically connected to the connecting electrode T14 through a via disposed in the second planarization layer 35. The pixel definition layer is disposed on the side of the first electrode away from the substrate 30, and the pixel definition layer may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode. At least a portion of the organic light-emitting layer may be disposed within a pixel opening and connected to the corresponding first electrode. The second electrode may be disposed on the side of the organic light-emitting layer away from the substrate 30 and connected to the organic light-emitting layer. The organic light-emitting layer may emit light of a corresponding color under the drive of the first electrode and the second electrode. The first electrode may also be referred to as the anode, and the second electrode may also be referred to as the cathode.

[0090] In some exemplary embodiments, the organic light-emitting layer of the light-emitting device may include at least one emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode and the second electrode, the organic light-emitting layer can emit light of a corresponding color.

[0091] In some exemplary embodiments, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0092] Figure 6 is a partial enlarged planar schematic diagram of the overlapping area of ​​a display substrate according to another embodiment of the present disclosure. As shown in Figure 6, at least a portion of the plurality of second power lines 22 and at least a portion of the plurality of data signal lines DL can be grouped together, and two second power lines 22 can be located on opposite sides of two adjacent data signal lines DL along the first direction X. A first power line 21 is connected to one of the two second power lines 22 via a transition electrode 23.

[0093] Figure 7A is a partial enlarged planar view of the overlapping area of ​​the display substrate according to another embodiment of the present disclosure; Figure 7B is a cross-sectional view at the point marked CC in Figure 7A; Figure 7C is a partial cross-sectional view of the overlapping area of ​​the display substrate according to another embodiment of the present disclosure; and Figure 8 is a partial enlarged planar view of the overlapping area of ​​the display substrate according to yet another embodiment of the present disclosure. As shown in Figures 7A and 8, the display substrate may further include at least one light-shielding portion 36 located in the second region AA2. In Figures 7A and 8, the light-shielding portion 36 is not filled with color to facilitate identification of the transfer electrode 23.

[0094] As shown in Figure 7B, due to the provision of the transition electrode 23, the surface of the second power trace 22, which overlaps with the orthographic projection of the transition electrode 23 onto the plane of the substrate 30, is relatively flat, meaning it has good flatness. As shown in Figure 7C, the surface flatness of the second power trace 22 located between two adjacent first power traces 21 is relatively poor. Flatness affects light reflectivity; a flatter surface has higher reflectivity. Therefore, in this embodiment, by providing a light-shielding portion 36, whose orthographic projection onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the conductive structure 20 onto the plane of the substrate 30, and whose reflectivity is less than that of the conductive structure 20 in the visible light range, the reflectivity of the second region can be reduced, thereby improving the uniformity of reflected light between the surfaces of the first and second regions. In the embodiments of this disclosure, the reflectivity of the light-shielding part 36 being less than that of the conductive structure 20 is relative. For example, the reflectivity of the conductive structure 20 may be 80% and the reflectivity of the light-shielding part 36 may be 70%, or the reflectivity of the conductive structure 20 may be 60% and the reflectivity of the light-shielding part 36 may be 50%, etc. This disclosure does not limit the reflectivity of the light-shielding part 36 and the conductive structure 20.

[0095] In some exemplary embodiments, the orthographic projection of the light-shielding portion 36 onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the first power line 21 onto the plane of the substrate 30; or, the orthographic projection of the light-shielding portion 36 onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the second power line 22 onto the plane of the substrate 30; or, the orthographic projection of the light-shielding portion 36 onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the transfer electrode 23 onto the plane of the substrate 30. For example, the orthographic projection of the light-shielding portion 36 onto the plane of the substrate 30 includes the orthographic projection of the transfer electrode 23 onto the plane of the substrate 30.

[0096] In some exemplary embodiments, the light-shielding part 36 and the transfer electrode 23 can be arranged in groups, and the orthographic projection of the light-shielding part 36 on the plane where the substrate 30 is located overlaps at least partially with the orthographic projection of the grouped transfer electrode 23 on the plane where the substrate 30 is located. For example, the orthographic projection of the light-shielding part 36 on the plane where the substrate 30 is located includes the orthographic projection of the grouped transfer electrode 23 on the plane where the substrate 30 is located.

[0097] In some exemplary embodiments, the orthographic projection of the light-shielding portion 36 onto the plane of the substrate 30 can be rectangular, circular, or hexagonal, etc., however, this disclosure does not limit it.

[0098] In some exemplary embodiments, the material of the light-shielding portion 36 can be a metallic material, such as copper (Cu) or molybdenum (Mo), or an alloy of the aforementioned metals. Alternatively, the material of the light-shielding portion 36 can be a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), or fluorine-doped tin oxide (FTO). Alternatively, the material of the light-shielding portion 36 can be a dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or magnesium fluoride (MgF2). The light-shielding portion 36 can be a single-layer structure or a multi-layer composite structure.

[0099] Figure 9 is a partially enlarged planar schematic diagram of the anode layer of a display substrate according to one embodiment of the present disclosure, and Figure 10 is a partially enlarged planar schematic diagram of the anode layer of a display substrate according to another embodiment of the present disclosure. As shown in Figures 9 and 10, in the direction perpendicular to the display substrate, the light-emitting structure layer may include an anode layer, a light-emitting material layer, and a cathode layer stacked sequentially. The anode layer includes multiple anodes, the light-emitting material layer includes multiple organic light-emitting layers, and the cathode layer includes multiple cathodes. The stacked anodes, organic light-emitting layers, and cathodes constitute a light-emitting device. The light-shielding portion 36 can be located in the anode layer, eliminating the need for adding a new film layer, which simplifies the fabrication process of the display substrate and reduces the fabrication cost of the display substrate.

[0100] The display area AA of the display substrate may include multiple pixel units arranged in a rectangular pattern. At least one pixel unit may include multiple sub-pixels, and the multiple sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels. The red sub-pixels are configured to emit red light, the green sub-pixels are configured to emit green light, and the blue sub-pixels are configured to emit blue light. The light-shielding portion 36 and the anode 37 of the light-emitting device of the red sub-pixel are an integral structure interconnected. Alternatively, the light-shielding portion 36 and the anode 38 of the light-emitting device of the blue sub-pixel are an integral structure interconnected. Alternatively, the light-shielding portion 36 and the anode 39 of the light-emitting device of the green sub-pixel are an integral structure interconnected. In the embodiments of this disclosure, designing the light-shielding portion as an integral structure interconnected with the anode of the light-emitting device is beneficial to increasing the area of ​​the anode and improving the light emission efficiency of the light-emitting device.

[0101] This disclosure also provides a display device, which includes the display substrate of any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and this disclosure is not limited thereto.

[0102] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A substrate, including a display area, the display area including a first area and a second area; Multiple data signal lines are located in the display area, and the multiple data signal lines are spaced apart along a first direction and extend along a second direction. The first direction and the second direction intersect and the plane formed by them is parallel to the plane where the substrate is located. Multiple data fan-out lines are located in the first region and connected to the data signal lines; A conductive structure is located in the second region. The conductive structure includes multiple first power lines, multiple second power lines, and multiple transition electrodes. The multiple first power lines extend along a first direction and are spaced apart along a second direction. The multiple second power lines extend along the second direction and are spaced apart along the first direction. The multiple first power lines and the multiple second power lines are interconnected via the transition electrodes to form a mesh structure for transmitting low-level signals. The orthographic projections of the multiple first power lines and the multiple second power lines onto the plane of the substrate form multiple overlapping areas. The second region includes multiple sub-regions, each of which has a density of the transfer electrodes. The density of the transfer electrodes in the multiple sub-regions gradually increases in the direction away from the first region. The density of the transfer electrodes is the ratio of the number of transfer electrodes in the sub-region to the number of overlapping regions.

2. The display substrate as claimed in claim 1, wherein, The arrangement density of the transfer electrode in the sub-region furthest from the first region among the plurality of sub-regions is 1.

0.

3. The display substrate as described in claim 1, wherein, The arrangement density of the transfer electrodes in the sub-regions adjacent to the first region in the plurality of sub-regions is greater than or equal to 0 and less than or equal to 0.

7.

4. The display substrate as claimed in claim 1, wherein, The difference in the arrangement density of the transfer electrodes in any pair of adjacent sub-regions in the plurality of sub-regions is less than or equal to 0.

7.

5. The display substrate according to any one of claims 1 to 4, further comprising a plurality of sub-pixels, the plurality of sub-pixels being located in the display area; the plurality of sub-pixels comprising at least a red sub-pixel, a blue sub-pixel, and a green sub-pixel, the red sub-pixel being configured to emit red light, the blue sub-pixel being configured to emit blue light, and the green sub-pixel being configured to emit green light; In the second region, the plurality of overlapping regions are grouped with the plurality of sub-pixels; or, one of the overlapping regions is grouped with two of the sub-pixels.

6. The display substrate according to any one of claims 1 to 4, wherein, The first power trace and the adapter electrode are located on the same conductive layer and are an integral structure connected to each other. The second power trace and the first power trace are located on different conductive layers, and the orthographic projections of the second power trace and the adapter electrode on the plane of the substrate at least partially overlap.

7. The display substrate as claimed in claim 6, wherein, The orthographic projection of at least one of the second power supply traces onto the plane of the substrate includes the orthographic projection of the transition electrode onto the plane of the substrate.

8. The display substrate according to any one of claims 1 to 4, further comprising at least one light-shielding portion, wherein the light-shielding portion is located on the side of the conductive structure away from the substrate, and the light-shielding portion and the orthographic projection of the conductive structure onto the plane of the substrate at least partially overlap; and in the visible light range, the reflectivity of the light-shielding portion is less than the reflectivity of the conductive structure.

9. The display substrate as claimed in claim 8, wherein, The orthographic projection of at least one of the light-shielding portions onto the plane of the substrate includes the orthographic projection of the transfer electrode onto the plane of the substrate.

10. The display substrate of claim 8, further comprising a plurality of sub-pixels located in the display area; the plurality of sub-pixels including at least a red sub-pixel, a blue sub-pixel, and a green sub-pixel, the red sub-pixel being configured to emit red light, the blue sub-pixel being configured to emit blue light, and the green sub-pixel being configured to emit green light; each of the sub-pixels including a light-emitting device located on the side of the conductive structure away from the substrate; the light-emitting device including an anode, an organic light-emitting layer, and a cathode stacked thereon, the light-shielding portion being located in the same conductive layer as the anode.

11. The display substrate as claimed in claim 10, wherein, The light-shielding part and the anode of the red sub-pixel are an integral structure connected to each other, or the light-shielding part and the anode of the blue sub-pixel are an integral structure connected to each other.

12. The display substrate as claimed in claim 11, wherein, At least one of the second power supply traces is located between two adjacent data signal traces.

13. The display substrate as claimed in claim 10, wherein, The light-shielding part and the anode of the green sub-pixel are an integral structure that are interconnected.

14. The display substrate as claimed in claim 13, wherein, At least two adjacent second power supply traces are located on either side of the two adjacent data signal traces along the first direction.

15. A display device comprising a display substrate as described in any one of claims 1 to 14.

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