Scanning circuit, display panel, and display device

Abstract

Embodiments of the present application provide a scanning circuit, a display panel, and a display device. The scanning circuit at least comprises a plurality of cascaded first shift register units; each first shift register unit comprises a first input module and a first cascade module; and an input terminal of the first input module is configured to receive a first trigger signal, and an output terminal of the first cascade module is configured to output a first cascade signal. Each first shift register unit further comprises a first voltage-stabilizing switch module, an output terminal of the first voltage-stabilizing switch module being electrically connected to an output terminal of the corresponding first input module, and / or the output terminal of the first voltage-stabilizing switch module being electrically connected to part of control terminals of the corresponding first cascade module. The present application can improve the stability of the potentials at the output terminals of the first input modules and / or the potentials at part of the control terminals of the first cascade modules, thereby improving the operating reliability of the first shift register units.

Description

A scanning circuit, a display panel, and a display device.

[0001] This invention claims priority to Chinese Patent Application No. 202510360766.9, filed with the State Intellectual Property Office of China on March 25, 2025, entitled “A Scanning Circuit, Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a scanning circuit, a display panel, and a display device. Background Technology

[0003] In the field of display technology, multiple sets of scanning circuits are usually set in the display panel to drive the pixel circuits in the display area. The scanning circuit is usually composed of multiple cascaded shift register units.

[0004] However, in existing technologies, there is a problem of abnormal node potentials in shift registers, which can easily affect the reliability of the shift registers. In view of this, a solution is urgently needed. Summary of the Invention

[0005] In view of this, embodiments of this application provide a scanning circuit, a display panel, and a display device to solve the above problems.

[0006] In a first aspect, embodiments of this application provide a scanning circuit, including at least a plurality of cascaded first shift register units. Each first shift register unit includes a first input module and a first cascade module. The input terminal of the first input module is used to receive a first trigger signal, and the output terminal of the first cascade module is used to output a first cascade signal. The first shift register unit further includes a first voltage regulator module, the output terminal of which is electrically connected to the output terminal of the first input unit; and / or, the output terminal of the first voltage regulator module is electrically connected to a portion of the control terminal of the first cascade module.

[0007] Secondly, based on the same inventive concept, embodiments of this application provide a display panel including the scanning circuit provided in the first aspect.

[0008] Thirdly, based on the same inventive concept, embodiments of this application provide a display device, including a display panel as provided in the second aspect.

[0009] In this embodiment, if the output terminal of the first voltage regulator module is electrically connected to the output terminal of the first input module, a voltage regulator signal can be provided to the output terminal of the first input module through the first voltage regulator module to compensate for the potential loss during the output process of the first input module. This is beneficial to improving the accuracy and stability of the potential at the output terminal of the first input module, thereby improving the working reliability of other modules that receive the potential at the output terminal of the first input module, and further improving the working reliability of the first shift register unit.

[0010] If the output terminal of the first voltage regulator module is electrically connected to part of the control terminal of the first cascade module, a voltage regulator signal can be provided to part of the control terminal of the first cascade module through the first voltage regulator module. This is beneficial to improving the stability of the potential of the control terminal of the first cascade module, thereby improving the working reliability of the first cascade module, and further improving the working reliability of the first shift register unit. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 is a plan view of a display panel provided in an embodiment of this application;

[0013] Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0014] Figure 3 is a partial schematic diagram of a first shift register unit provided in an embodiment of this application;

[0015] Figure 4 is a partial schematic diagram of another first shift register unit provided in an embodiment of this application;

[0016] Figure 5 is a schematic diagram of a first shift register unit provided in an embodiment of this application;

[0017] Figure 6 is a schematic diagram of one of the first shift register units shown in Figure 5;

[0018] Figure 7 is a schematic diagram of another first shift register unit provided in an embodiment of this application;

[0019] Figure 8 is a schematic diagram of the first shift register unit shown in Figure 7;

[0020] Figure 9 is a schematic diagram of another first shift register unit provided in an embodiment of this application;

[0021] Figure 10 is a schematic diagram of one of the first shift register units shown in Figure 9;

[0022] Figure 11 is a schematic diagram of another first shift register unit provided in an embodiment of this application;

[0023] Figure 12 is a schematic diagram of one of the first shift register units shown in Figure 11;

[0024] Figure 13 is a schematic diagram of another first shift register unit provided in an embodiment of this application;

[0025] Figure 14 is a schematic diagram of one of the first shift register units shown in Figure 13;

[0026] Figure 15 is a connection diagram of a pixel circuit provided in an embodiment of this application;

[0027] Figure 16 is a schematic diagram of a first shift register unit provided in an embodiment of this application;

[0028] Figure 17 is a timing diagram of the first shift register unit shown in Figure 16;

[0029] Figure 18 is a plan view of another display panel provided in an embodiment of this application;

[0030] Figure 19 is a simplified structural diagram of a second shift register unit provided in an embodiment of this application;

[0031] Figure 20 is a schematic diagram of a second shift register unit provided in an embodiment of this application;

[0032] Figure 21 is a schematic diagram of another second shift register unit provided in an embodiment of this application;

[0033] Figure 22 is a schematic diagram of another second shift register unit provided in an embodiment of this application;

[0034] Figure 23 is a timing diagram of a scanning circuit provided in an embodiment of this application;

[0035] Figure 24 is a timing diagram of another scanning circuit provided in an embodiment of this application;

[0036] Figure 25 is a connection diagram of a scanning circuit provided in an embodiment of this application;

[0037] Figure 26 is a connection diagram of another scanning circuit provided in an embodiment of this application;

[0038] Figure 27 is a connection diagram of another scanning circuit provided in an embodiment of this application;

[0039] Figure 28 is a connection diagram of another scanning circuit provided in an embodiment of this application;

[0040] Figure 29 is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0041] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0043] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this article generally indicates that the related objects before and after it have an "or" relationship.

[0045] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0046] Figure 1 is a plan view of a display panel provided in an embodiment of this application.

[0047] This application provides a scanning circuit 100 for driving a pixel circuit 02. As shown in FIG1, in one possible application scenario, both the scanning circuit 100 and the pixel circuit 02 are disposed in a display panel 200. The display panel 200 includes a display area AA and a border area NA located around the display area AA. The border area NA may surround the display area AA.

[0048] The scanning circuit 100 is located in the bezel area NA, and the pixel circuit 02 is located in the display area AA. The pixel circuit 02 is electrically connected to the light-emitting device 03 and is used to drive the light-emitting device 03 to emit light. The scanning circuit 100 is electrically connected to the pixel circuit 02 and is used to provide a gate scanning signal to the pixel circuit 02, thereby driving the pixel circuit 02 to work.

[0049] The scanning circuit 100 includes a plurality of cascaded first shift register units 101. Optionally, the first shift register units 101 are used to provide gate scan signals to the gate reset transistor and / or threshold grab transistor in the pixel circuit 02.

[0050] For example, as shown in Figure 2, which is a schematic diagram of a pixel circuit provided in an embodiment of this application, the pixel circuit 02 includes a driving transistor Md, a gate reset transistor M1, a data writing transistor M2, a threshold grabbing transistor M3, a power supply voltage writing transistor M4, a light emission control transistor M5, a light emission reset transistor M6, and a storage capacitor Cst.

[0051] The first terminal of gate reset transistor M1 is electrically connected to the first reset signal line SL1, the second terminal is electrically connected to the gate of driving transistor Md, and the gate is electrically connected to the first scan line S1N. The first reset signal line SL1 transmits the first reset voltage Vref1. The first terminal of data write transistor M2 is electrically connected to the data signal line DL1, the second terminal is electrically connected to the first terminal of driving transistor Md, and the gate is electrically connected to the second scan line SP. The data signal line DL1 transmits the data voltage Data. The first terminal of threshold grabbing transistor M3 is electrically connected to the second terminal of driving transistor Md, the second terminal is electrically connected to the gate of driving transistor Md, and the gate is electrically connected to the third scan line S2N.

[0052] The first terminal of the power supply voltage writing transistor M4 is electrically connected to the first power supply signal line DL2, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the light emission control signal line EM. The first power supply signal line DL2 transmits the first power supply voltage PVDD. The first terminal of the light emission control transistor M5 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the first terminal of the light-emitting device 03, and the gate is electrically connected to the light emission control signal line EM. The first terminal of the light emission reset transistor M6 is electrically connected to the second reset signal line SL2, the second terminal is electrically connected to the first terminal of the light-emitting device 03, and the gate is electrically connected to the second scan line SP. The second reset signal line SL2 transmits the second reset voltage Vref2. One plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor Md, and the other plate is electrically connected to the first power supply signal line DL1.

[0053] Taking the gate reset transistor M1 and threshold grabbing transistor M3 as examples, both of which are metal oxide transistors, and the gate reset transistor M1 and threshold grabbing transistor M3 are N-type transistors, while the driving transistor Md, data writing transistor M2, power supply voltage writing transistor M4, light-emitting control transistor M5, and light-emitting reset transistor M6 are P-type transistors, the first shift register unit 101 can provide a scan signal to the gate of the gate reset transistor M1 through the first scan line S1N, and / or provide a scan signal to the gate of the threshold grabbing transistor M3 through the third scan line S2N. The enable signal output by the first shift register unit 101 can be a high-level signal.

[0054] Figure 3 is a partial schematic diagram of a first shift register unit provided in an embodiment of this application, and Figure 4 is a partial schematic diagram of another first shift register unit provided in an embodiment of this application.

[0055] As shown in Figures 3 and 4, the first shift register unit 101 includes a first input module 11 and a first cascade module 12. The input terminal of the first input module 11 is used to receive the first trigger signal SN_IN, and the output terminal SN_NEXT of the first cascade module 12 is used to output the first cascade signal. The first cascade signal output by the first cascade module 12 in the previous stage first shift register unit 101 can be used as the first trigger signal SN_IN received by the first input module 11 in the next stage first shift register unit 101.

[0056] The first shift register unit 101 further includes a first voltage regulator module 13, the output terminal of which is electrically connected to the output terminal of the first input module 11, and / or the output terminal of the first voltage regulator module 13 is electrically connected to part of the control terminal of the first cascade module 12.

[0057] The first voltage regulator module 13 can transmit a voltage regulator signal to the output terminal of the first input module 11 and / or a portion of the control terminal of the first cascade module 12 to stabilize the potential of the output terminal of the first input module 11 and / or a portion of the control terminal of the first cascade module 12.

[0058] For example, as shown in FIG3, the first shift register unit 101 further includes a first control module 14. The control terminal of the first control module 14 is electrically connected to the output terminal of the first input module 11, the output terminal of the first control module 14 is electrically connected to the control terminal of the first cascade module 12, and the output terminal of the first voltage regulator module 13 is electrically connected to the output terminal of the first input module 11.

[0059] For example, as shown in FIG4, the first shift register unit 101 further includes a first control module 14, and the first cascade module 12 includes a first control terminal and a second control terminal. The first control terminal of the first cascade module 12 is electrically connected to the output terminal of the first control module 14, and the second control terminal is coupled to the output terminal of the first input module 11. A first coupling module 15 is provided between the second control terminal of the first cascade module 12 and the first input module 11.

[0060] The first control module 14 includes a first control terminal and a second control terminal. The output terminal of the first input module 11 is also electrically connected to the first control terminal of the first control module 14. The second control terminal of the first cascade module 12 is also electrically connected to the second control terminal of the first control module 14. The output terminal of the first voltage regulator module 13 is electrically connected to the second control terminal of the first cascade module 12.

[0061] It should be noted that in the first shift register unit 101 shown in Figure 4, the output terminal of the first input module 11 and the second control terminal of the first cascade module 12 can also be directly electrically connected, that is, no first coupling module 15 is provided between the output terminal of the first input module 11 and the second control terminal of the first cascade module 12. In this case, the output terminal of the first voltage regulator module 13 can be electrically connected to the second control terminal of the first cascade module 12 and also electrically connected to the output terminal of the first input module 11.

[0062] The inventors of this application have discovered through research that, in the prior art, the first trigger signal usually suffers from threshold loss after passing through the first input module, which can easily lead to inaccurate output potential of the first input module. This can cause abnormalities in the functional modules located after the first input module, affecting the normal operation of the first shift register unit.

[0063] Furthermore, when the output potential of the first input module is used as part of the control signal of the first cascade module, since there may be a first coupling module between the output of the first input module and the control terminal of the first cascade module, if only the output potential of the first input module is adjusted, the stabilization effect on the control terminal potential of the first cascade module may be limited, and the first cascade module may still malfunction.

[0064] In view of this, embodiments of this application configure the output terminal of the first voltage regulator module 13 to be electrically connected to the output terminal of the first input module 11, and / or, the output terminal of the first voltage regulator module 13 to be electrically connected to a portion of the control terminals of the first cascade module 12. This is to improve the operational reliability of the first shift register unit.

[0065] In this embodiment, if the output terminal of the first voltage regulator module 13 is electrically connected to the output terminal of the first input module 11, a voltage regulator signal can be provided to the output terminal of the first input module 11 through the first voltage regulator module 13 to compensate for the potential loss during the output process of the first input module 11. This is beneficial to improving the accuracy and stability of the potential at the output terminal of the first input module 11, thereby improving the working reliability of other modules that receive the potential at the output terminal of the first input module 11, and further improving the working reliability of the first shift register unit 101.

[0066] If the output terminal of the first voltage regulator module 13 is electrically connected to a portion of the control terminal of the first cascade module 12, a voltage regulator signal can be provided to a portion of the control terminal of the first cascade module 12 through the first voltage regulator module 13. This is beneficial to improving the stability of the potential of the control terminal of the first cascade module 12, thereby improving the working reliability of the first cascade module 12, and further improving the working reliability of the first shift register unit 101.

[0067] Figure 5 is a schematic diagram of a first shift register unit provided in an embodiment of this application, and Figure 6 is a schematic diagram of the first shift register unit shown in Figure 5.

[0068] In one embodiment of this application, as shown in FIG5, the output terminal of the first input module 11 is electrically connected to the first node N1, and the control terminal receives the first clock signal CK1. The first input terminal of the first cascade module 12 receives the first fixed potential signal VGH, the second input terminal receives the second fixed potential signal VGL, and the control terminal is electrically connected to the second node N2. The first fixed potential signal VGH is a high-level potential signal, and the second fixed potential signal VGL is a low-level potential signal.

[0069] The first shift register unit 101 also includes a first control module 14. The first input terminal of the first control module 14 receives a first fixed potential signal VGH, the second input terminal receives a second fixed potential signal VGL, the control terminal is electrically connected to the first node N1, and the output terminal is electrically connected to the second node N2.

[0070] The first voltage regulator module 13 has an input terminal that receives the second fixed potential signal VGL, an output terminal that is electrically connected to the first node N1, and a control terminal that is electrically connected to the second node N2.

[0071] For example, as shown in FIG6, the first input module 11 includes a first transistor T1, the first terminal of the first transistor T1 receives a first trigger signal SN_IN, the second terminal is electrically connected to the first node N1, and the gate receives a first clock signal CK1.

[0072] The first control module 14 includes a second transistor T2 and a third transistor T3 with different channel types. The first terminal of the second transistor T2 receives a first fixed potential signal VGH, the second terminal is electrically connected to the second node N2, and the gate is electrically connected to the first node N1. The first terminal of the third transistor T3 receives a second fixed potential signal VGL, the second terminal is electrically connected to the second node N2, and the gate is electrically connected to the first node N1. The first control module 14 transmits either the first fixed potential signal VGH or the second fixed potential signal VGL to the second node N2 in response to the potential of the first node N1. The potential levels of the first node N1 and the second node N2 can be opposite.

[0073] The first cascade module 12 includes a fourth transistor T4 and a fifth transistor T5 with different channel types. The first terminal of the fourth transistor T4 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and the gate is electrically connected to the second node N2. The first terminal of the fifth transistor T5 receives a second fixed potential signal VGL, the second terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and the gate is electrically connected to the second node N2. The first cascade module 12 outputs either the first fixed potential signal VGH or the second fixed potential signal VGL in response to the potential of the second node N2 as the first cascade signal. The potential level of the output terminal SN_NEXT of the first cascade module 12 can be opposite to the potential level of the second node N2.

[0074] The first voltage regulator switch module 13 includes a first voltage regulator transistor TF1. The first terminal of the first voltage regulator transistor TF1 receives a second fixed potential signal VGL, the second terminal is electrically connected to the first node N1, and the gate is electrically connected to the second node N2.

[0075] Among them, the second transistor T2 and the fourth transistor T4 have the same channel type, and the third transistor T3, the first Zener transistor TF1 and the fifth transistor T5 have the same channel type.

[0076] For example, the second transistor T2 and the fourth transistor T4 are both P-type transistors, while the third transistor T3, the first Zener transistor TF1, and the fifth transistor T5 are all N-type transistors.

[0077] Optionally, the third transistor T3, the first Zener transistor TF1, and the fifth transistor T5 are metal oxides, and the third transistor T3, the first Zener transistor TF1, and the fifth transistor T5 can all be top-bottom dual-gate structures.

[0078] For example, as shown in Figure 6, the bottom gate of the third transistor T3 is electrically connected to its first electrode, and the bottom gate of the first Zener transistor TF1 is electrically connected to its first electrode to improve the stability of the threshold voltage of the third transistor T3 and the first Zener transistor TF1 during long-term operation, thereby improving the operating stability of the third transistor T3 and the first Zener transistor TF1. The bottom gate of the fifth transistor T5 can be electrically connected to its top gate to improve the driving capability of the fifth transistor T5.

[0079] In this embodiment, when the low-level first trigger signal SN_IN is transmitted to the first node N1 through the first transistor T1, the second transistor T2 is turned on, and the high-level first fixed potential signal VGH is transmitted to the second node N2 through the second transistor T2. The high-level potential of the second node N2 controls the first Zener transistor TF1 to turn on, and the low-level second fixed potential VGL is transmitted to the first node N1 through the first Zener transistor TF1. This can compensate for the loss of the low-level first trigger signal SN_IN through the first transistor T1, which is beneficial to stabilizing the low-level potential of the first node N1, thereby improving the reliability of the second transistor T2 turning on and the reliability of the third transistor T3 turning off, and further improving the working reliability of the first shift register unit 101.

[0080] In one embodiment of this application, as shown in FIG5, the first shift register unit 101 further includes a first type of signal output module 16. The output terminal SN_OUT of the first type of signal output module 16 is used to output a first type of scan signal. The first type of scan signal can be the gate scan signal of the gate reset transistor and / or the threshold grab transistor transmitted to the pixel circuit 02. The enable signal in the first type of scan signal can be a high level signal.

[0081] The first type of signal output module 16 includes a first output module 161 and a second output module 162. The input terminal of the first output module 161 receives a first fixed potential signal VGH, and its output terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16. The input terminal of the second output module 162 receives a second fixed potential signal VGL, and its output terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16.

[0082] The first shift register unit 101 also includes a gating module 17, the first input terminal of which receives a first fixed potential signal VGH, and the second input terminal is electrically connected to the gating signal line CTRL.

[0083] In this configuration, at least one of the first output module 161 and the second output module 162 has its control terminal electrically connected to the output terminal of the gating module 17. That is, at least one of the first output module 161 and the second output module 162 can transmit a signal to the output terminal SN_OUT of the first type of signal output module 16 in response to the output signal of the gating module 17.

[0084] For example, as shown in FIG6, the first output module 161 includes a sixth transistor T6. The first terminal of the sixth transistor T6 receives a first fixed potential signal VGH, and the second terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16.

[0085] The second output module 162 includes a seventh transistor T7. The first terminal of the seventh transistor T7 receives the second fixed potential signal VGL, and the second terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16.

[0086] The sixth transistor T6 and the seventh transistor T7 have different channel types.

[0087] For example, the sixth transistor T6 is a P-type transistor and the seventh transistor T7 is an N-type transistor.

[0088] As one possible implementation, as shown in Figure 5, the gating module 17 includes a first submodule 171 and a second submodule 172. The input terminal of the first submodule 171 receives a first fixed potential signal VGH, the control terminal is electrically connected to the second node N2, and the output terminal is electrically connected to the control terminal of the first output module 161.

[0089] The input terminal of the second submodule 172 is electrically connected to the strobe signal line CTRL, the output terminal is electrically connected to the control terminal of the first output module 161, and the control terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12.

[0090] The control terminal of the second output module 162 is electrically connected to the output terminal SN_NEXT of the first cascade module 12.

[0091] In this implementation, the gating module 17, in response to the potential of the second node N2 and the first cascade signal output by the first cascade module 12, transmits a first fixed potential signal VGH or a signal on the gating signal line CTRL to the control terminal of the first output module 161. The first type of signal output module 16, in response to the output signal of the gating module 17 and the first cascade signal output by the first cascade module 12, outputs a first type of scanning signal.

[0092] For example, as shown in FIG6, the first submodule 171 includes an eighth transistor T8, the first terminal of the eighth transistor T8 receives a first fixed potential signal VGH, the second terminal is electrically connected to the gate of the sixth transistor T6, and the gate is electrically connected to the second node N2.

[0093] The second submodule 172 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is electrically connected to the strobe signal line CTRL, the second terminal is electrically connected to the gate of the sixth transistor T6, and the gate is electrically connected to the output terminal SN_NEXT of the first cascade module 12.

[0094] The gate of the seventh transistor T7 is electrically connected to the output terminal SN_NEXT of the first cascade module 12.

[0095] Among them, the eighth transistor T8 and the ninth transistor T9 have the same channel type, but the channel type is different from that of the seventh transistor T7.

[0096] For example, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all P-type transistors, and the seventh transistor T7 is an N-type transistor.

[0097] Optionally, the seventh transistor T7 comprises a metal oxide and can be a top-bottom dual-gate structure.

[0098] For example, the bottom gate of the seventh transistor T7 can be electrically connected to the top gate to improve the driving capability of the seventh transistor T7.

[0099] When the selected signal line CTRL transmits a high-level signal, both the eighth transistor T8 and the ninth transistor T9 can only transmit high-level signals to the sixth transistor T6. The sixth transistor T6 remains in the off state, and the output terminal SN_OUT of the first type of signal output module 16 maintains a low-level second fixed potential signal VGL. At this time, the first cascade module 12 can output the normal first-stage transmission signal.

[0100] When the selected signal line CTRL transmits a low-level signal, the eighth transistor T8 and the ninth transistor T9 can transmit high-level and low-level signals to the sixth transistor T6, respectively. The sixth transistor T6 can remain in the on or off state, and the output terminal SN_OUT of the first type of signal output module 16 can output the scan signal normally. At this time, the potential of the output terminal SN_NEXT of the first cascade module 12 is opposite to the potential of the output terminal SN_OUT of the first type of signal output module 16.

[0101] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 16 can be controlled by controlling the signal on the strobe signal line CTRL.

[0102] Figure 7 is a schematic diagram of another first shift register unit provided in an embodiment of this application, and Figure 8 is a schematic diagram of the first shift register unit shown in Figure 7.

[0103] As another possible implementation, as shown in Figure 7, the gating module 17 includes a first submodule 171 and a second submodule 172. The input terminal of the first submodule 171 receives a first fixed potential signal VGH, its control terminal is electrically connected to the second node N2, and its output terminal is electrically connected to the second branch node N2A. The second branch node N2A is electrically connected to the control terminals of the first output module 161 and the second output module 162. That is, the output terminal of the first submodule 171 is electrically connected to the control terminals of the first output module 161 and the second output module 162.

[0104] The input terminal of the second submodule 172 is electrically connected to the strobe signal line CTRL, the control terminal is electrically connected to the second node N2, and the output terminal is electrically connected to the second sub-node N2A. That is, the output terminal of the second submodule 172 is electrically connected to the control terminal of the first output module 161 and the second output module 162.

[0105] In this implementation, the gating module 17, in response to the potential of the second node N2, outputs a first fixed potential signal VGH or a signal on the gating signal line CTRL to the control terminal of the first type of signal output module 16. The first type of signal output module 16, in response to the output signal of the gating module 17, outputs a first type of scan signal, which may include the first fixed potential signal VGH and the second fixed potential signal VGL.

[0106] Specifically, the potential level of the output terminal SN_OUT of the first type of signal output module 16 can be opposite to the potential level of the output terminal of the gating module 17. Thus, during the operation of the first shift register unit 101, regardless of whether the output terminal potential of the gating module 17 is high or low, one of the first output module 161 and the second output module 162 can be turned on, and the potential of the output terminal SN_OUT of the first type of signal output module 16 will not float, which helps to improve the stability of the potential of the output terminal SN_OUT of the first type of signal output module 16.

[0107] For example, as shown in FIG8, the first submodule 171 includes an eighth transistor T8. The first terminal of the eighth transistor T8 receives a first fixed potential signal VGH, the second terminal is electrically connected to the gates of the sixth transistor T6 and the seventh transistor T7, and the gate is electrically connected to the second node N2.

[0108] The second submodule 172 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is electrically connected to the strobe signal line CTRL, the second terminal is electrically connected to the gates of the sixth transistor T6 and the seventh transistor T7, and the gate is electrically connected to the second node N2.

[0109] Among them, the eighth transistor T8 and the ninth transistor T9 have different channel types, while the eighth transistor T8 and the sixth transistor T6 have the same channel type.

[0110] For example, the sixth transistor T6 and the eighth transistor T8 are P-type transistors, and the seventh transistor T7 and the ninth transistor T9 are N-type transistors.

[0111] Optionally, both the seventh transistor T7 and the ninth transistor T9 are metal oxides, and both the seventh transistor T7 and the ninth transistor T9 can be top-bottom dual-gate structures.

[0112] For example, as shown in Figure 8, the bottom gate of the ninth transistor T9 is electrically connected to its first electrode to improve the stability of the threshold voltage during long-term operation of the ninth transistor T9. The bottom gate of the seventh transistor T7 can be electrically connected to its top gate to improve the driving capability of the seventh transistor T7.

[0113] When the selected signal line CTRL transmits a high-level signal, both the eighth transistor T8 and the ninth transistor T9 can only transmit high-level signals to the gates of the sixth transistor T6 and the seventh transistor T7. The sixth transistor T6 remains off, and the output terminal SN_OUT of the first type of signal output module 16 outputs the low-level second fixed potential signal VGL transmitted by the seventh transistor T7. At this time, the first cascade module 12 can output the normal first-stage transmission signal.

[0114] When the selected signal line CTRL transmits a low-level signal, the eighth transistor T8 and the ninth transistor T9 can transmit high-level signals and low-level signals to the gates of the sixth transistor T6 and the seventh transistor T7, respectively. The sixth transistor T6 can remain in the on or off state, and the output terminal SN_OUT of the first type of signal output module 16 can output the scan signal normally. At this time, the potential of the output terminal SN_NEXT of the first cascade module 12 is opposite to the potential of the output terminal SN_OUT of the first type of signal output module 16.

[0115] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 16 can be controlled by controlling the signal on the strobe signal line CTRL.

[0116] Optionally, as shown in Figures 5-8, the first shift register unit 101 further includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the first node N1, and the other plate receives the second fixed potential signal VGL. In this way, the potential stability of the first node N1 can be further improved by using the first capacitor C1.

[0117] Figure 9 is a schematic diagram of another first shift register unit provided in an embodiment of this application, and Figure 10 is a schematic diagram of the first shift register unit shown in Figure 9.

[0118] In one embodiment of this application, as shown in FIG9, the first output terminal of the first input module 11 is electrically connected to the first master node N1a, the second output terminal is electrically connected to the first node N1b, and the control terminal receives the first clock signal CK1. The first master node N1a is coupled to the second master node N2a, and the first node N1b is coupled to the second node N2b. A first coupling module 15 is provided between the first master node N1a and the second master node N2a, and a first coupling module 15 is provided between the first node N1b and the second node N2b.

[0119] The first cascade module 12 includes a first sub-cascade module 121 and a second sub-cascade module 122. The input terminal of the first sub-cascade module 121 receives a first fixed potential signal VGH, its output terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and its control terminal is electrically connected to the third node N3. The input terminal of the second sub-cascade module 122 receives a second fixed potential signal VGL, its output terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and its control terminal is electrically connected to the second master node N2a.

[0120] The first shift register unit 101 further includes a first control module 14, which includes a first sub-control module 141 and a second sub-control module 142. The first sub-control module 141 receives a first fixed potential signal VGH at its input terminal, is electrically connected to a third node N3 at its output terminal, and is electrically connected to a first master node N1a at its control terminal. The second sub-control module 142 receives a second fixed potential signal VGL at its input terminal, is electrically connected to a third node N3 at its output terminal, and is electrically connected to a second master node N2 at its control terminal.

[0121] In this embodiment, the first sub-control module 141 can transmit a first fixed potential signal VGH to the third node N3 in response to the potential of the first master node N1a, and the second sub-control module 142 can transmit a second fixed potential signal VGL to the third node in response to the potential of the second master node N2a. The first sub-cascade module 121 can transmit the first fixed potential signal VGH to the output terminal SN_NEXT of the first cascade module 12 in response to the potential of the third node N3, and the second sub-cascade module 122 can transmit the second fixed potential signal VGL to the output terminal SN_NEXT of the first cascade module 12 in response to the potential of the second master node N2a. The first fixed potential signal VGH or the second fixed potential signal VGL output by the output terminal SN_NEXT of the first cascade module 12 can be used as the first cascade signal.

[0122] The input terminal of the first voltage regulator module 13 is electrically connected to the second node N2b, the output terminal is electrically connected to the second main node N2a, and the control terminal is electrically connected to the second node N2b.

[0123] Based on this configuration, the first voltage regulator module 13 can transmit the potential of the second node N2b to the second master node N2a. Since the potential of the first master node N1a can be the same as the potential of the first node N1b, and the second master node N2a is coupled to the first master node N1a, while the second node N2b is coupled to the first node N1b, the potential of the second node N2b can be used to stabilize the potential of the second master node N2a, so as to avoid the problem that the potential of the second master node N2a is not low enough when the potentials of the first master node N1a and the first node N1b are low.

[0124] For example, as shown in FIG10, the first input module 11 includes a first transistor T1 and a second transistor T2. The first transistor T1 receives a first trigger signal SN_IN at its first terminal, is electrically connected to the first master node N1a at its second terminal, and receives a first clock signal CK1 at its gate. The second transistor T2 receives the first trigger signal SN_IN at its first terminal, is electrically connected to the first node N1b at its second terminal, and receives the first clock signal CK1 at its gate. During the operation of the first shift register unit 101, the potentials of the first master node N1a and the first node N1b can be substantially the same.

[0125] The first sub-cascade module 121 includes a third transistor T3. The first terminal of the third transistor T3 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and the gate is electrically connected to the third node N3. The second sub-cascade module 122 includes a fourth transistor T4. The first terminal of the fourth transistor T4 receives a second fixed potential signal VGL, the second terminal is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and the gate is electrically connected to the second master node N2a.

[0126] The first sub-control module 141 includes a fifth transistor T5. The first terminal of the fifth transistor T5 receives a first fixed potential signal VGH, the second terminal is electrically connected to the third node N3, and the gate is electrically connected to the first master node N1a. The second sub-control module 142 includes a sixth transistor T6. The first terminal of the sixth transistor T6 receives a second fixed potential signal VGH, the second terminal is electrically connected to the third node N3, and the gate is electrically connected to the second master node N2a.

[0127] The first voltage regulator switch module 13 includes a first voltage regulator transistor TF1, wherein the first terminal of the first voltage regulator transistor TF1 is electrically connected to the second node N2b, the second terminal is electrically connected to the second main node N2a, and the gate is electrically connected to the second node N2b.

[0128] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the first Zener transistor TF1 have the same channel type, but different channel type from the sixth transistor T6.

[0129] For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the first Zener transistor TF1 are all P-type transistors, and the sixth transistor T6 is an N-type transistor.

[0130] Optionally, the sixth transistor T6 comprises a metal oxide and can be a top-bottom dual-gate structure.

[0131] For example, as shown in Figure 10, the bottom gate of the sixth transistor T6 is electrically connected to its first electrode to improve the stability of the threshold voltage during long-term operation of the sixth transistor T6.

[0132] This configuration allows the first cascade module 12, which outputs the first cascade signal, to include only P-type transistors, eliminating the need for N-type transistors and thus improving its signal output capability. In particular, it avoids the problems of poor signal output capability and large space occupation associated with using metal oxide transistors (such as indium gallium zinc oxide) as signal output transistors.

[0133] Please continue to refer to Figure 10. In one embodiment of this application, a first coupling transistor TO1 is included between the first master node N1a and the second master node N2a, and a second coupling transistor TO2 is included between the first node N1b and the second node N2b. The gate of the first coupling transistor TO1 and the gate of the second coupling transistor TO2 both receive a second fixed potential signal VGL.

[0134] The first coupling transistor TO1 and the second coupling transistor TO2 have the same channel type. During the operation of the first shift register unit 101, the first coupling transistor TO1 and the second coupling transistor TO2 can remain in the on state.

[0135] For example, both the first coupling transistor TO1 and the second coupling transistor TO2 are P-type transistors.

[0136] In this implementation, the settings of the first coupling transistor TO1 and the second coupling transistor TO2 are beneficial for stabilizing the potentials of the first master node N1a and the first node N1b. When the potential of the second master node N2a is disturbed, the first coupling transistor TO1 can reduce the impact of the disturbance on the first master node N1a. When the potential of the second node N2b is disturbed, the second coupling transistor TO1 can reduce the impact of the disturbance on the first node N1b. That is, it helps to reduce the impact on the potential of the output terminal of the first input module 11, and can play a role in stabilizing the potential of the output terminal of the first input module 11.

[0137] Optionally, as shown in Figure 9, the first shift register unit 101 further includes an auxiliary voltage regulator module 18. The first input terminal of the auxiliary voltage regulator module 18 receives a first fixed potential signal VGH, the second input terminal receives a second clock signal CK2, and the output terminal is electrically connected to the second node N2b. The auxiliary voltage regulator module 18 is used to adjust the potential of the second node N2b, thereby stabilizing the potential of the second master node N2a through the first voltage regulator transistor TF1.

[0138] For example, as shown in FIG10, the auxiliary voltage regulator module 18 includes a first capacitor C1, a seventh transistor T7 and an eighth transistor T8, wherein the seventh transistor T7 and the eighth transistor T8 have the same channel type.

[0139] One plate of the first capacitor C1 is electrically connected to the second node N2b, and the other plate is electrically connected to the fourth node N4. The first terminal of the seventh transistor T7 receives the second clock signal CK2, the second terminal is electrically connected to the fourth node N4, and the gate is electrically connected to the second node N2b. The first terminal of the eighth transistor T8 receives the first fixed potential signal VGH, the second terminal is electrically connected to the fourth node N4, and the gate is electrically connected to the third node N3.

[0140] For example, both the seventh transistor T7 and the eighth transistor T8 are P-type transistors.

[0141] When the first master node N1a and the first node N1b are at a low level, the second master node N2a and the second node N2b are also at a low level. At this time, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the third node N3 is at a high level. Simultaneously, the potential of the third node N3 controls the eighth transistor T8 to turn off, and the potential of the second node N2b controls the seventh transistor T7 to turn on. The second clock signal CK2 is a pulse signal. The level change of the second clock signal CK2 can pull down the potential of the fourth node N4, then pull down the potential of the second node N2b through the first capacitor C1, and further pull down the potential of the second master node N2a through the first Zener transistor TF1, ensuring that the second master node N2a has a stable low potential. This avoids the problem of the sixth transistor T6 not turning off completely and the fourth transistor T4 not turning on sufficiently due to the insufficient potential of the second master node N2a.

[0142] In one embodiment of this application, referring to Figures 9 and 10, the first cascade module 12 is also used to output a first type of scan signal. That is, the first-stage transmission signal output by the output terminal SN_NEXT of the first cascade module 12 can be multiplexed as the first type of scan signal output by the first shift register unit 101.

[0143] The first cascade module 12 can be reused as the first type of signal output module 16 in the first shift register unit 101. The output terminal SN_NEXT of the first cascade module 12 is reused as the output terminal SN_OUT of the first type of signal output module 16, which transmits the first cascade signal to the next level first shift register unit 101 and transmits the first type of scanning signal to the pixel circuit 02.

[0144] Based on this configuration, it is beneficial to reduce the number of transistors in the first shift register unit 101, thereby reducing the area occupied by the first shift register unit 101. This simplifies the structure of the first shift register unit 101 and also helps to achieve a narrow bezel for the display panel 200.

[0145] Optionally, as shown in Figure 10, the first shift register unit 101 further includes a second capacitor C2 and a third capacitor C3. One plate of the second capacitor C2 receives the first fixed potential signal VGH, and the other plate is electrically connected to the control terminal of the first sub-cascade module 121 to stabilize the potential of the control terminal of the first sub-cascade module 121.

[0146] One plate of the third capacitor C3 is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and the other plate is electrically connected to the control terminal of the second sub-cascade module 122, so as to further stabilize the control terminal potential of the second sub-cascade module 122.

[0147] Figure 11 is a schematic diagram of another first shift register unit provided in an embodiment of this application, and Figure 12 is a schematic diagram of the first shift register unit shown in Figure 11.

[0148] In one embodiment of this application, as shown in FIG11, the first shift register unit 101 further includes a gating module 17 and a first type signal output module 16, wherein the output terminal SN_OUT of the first type signal output module 16 is used to output a first type scan signal.

[0149] The first type of signal output module 16 includes a first output module 161 and a second output module 162. The input terminal of the first output module 161 receives a first fixed potential signal VGH, the output terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16, and the control terminal is electrically connected to the output terminal of the gating module 17. The input terminal of the second output module 162 receives a second fixed potential signal VGL, the output terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16, and the control terminal is electrically connected to the second master node N2a.

[0150] The first input terminal of the gating module 17 is electrically connected to the gating signal line CTRL, the second input terminal is electrically connected to the third node N3, and the third input terminal receives the first fixed potential signal VGH. The gating module 17 transmits a control signal to the first output module 161 in response to the output potential of the first master node N1a and the first cascade module 12.

[0151] In this implementation, the first type of signal output module 16 responds to the output terminal potential of the gating module 17 and the potential of the second master node N2a, and outputs a first type of scanning signal. This is beneficial to control the frequency of the output enable signal SN_OUT of the first type of signal output module 16 by adjusting the output signal of the gating module 17.

[0152] For example, as shown in Figure 12, the first output module 161 includes a ninth transistor T9. The first terminal of the ninth transistor T9 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16, and the gate is electrically connected to the fifth node N5. The second output module 162 includes a tenth transistor T10. The first terminal of the tenth transistor T10 receives a second fixed potential signal VGL, the second terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 16, and the gate is electrically connected to the second master node N2a.

[0153] The gating module 17 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourth capacitor C4, and a fifth capacitor C5. The first terminal of the eleventh transistor T11 is electrically connected to the gating signal line CTRL, the second terminal is electrically connected to the sixth node N6, and the gate is electrically connected to the output terminal SN_NEXT of the first cascade module 12. The first terminal of the twelfth transistor T12 is electrically connected to the third node N3, the second terminal is electrically connected to the fifth node N5, and the gate is electrically connected to the sixth node N6. The first terminal of the thirteenth transistor T13 receives the first fixed potential signal VGH, the second terminal is electrically connected to the fifth node N5, and the gate is electrically connected to the first main node N1a.

[0154] The fourth capacitor C4 has one plate receiving the second fixed potential signal VGL and the other plate electrically connected to the sixth node N6 to improve the stability of the potential of the sixth node N6. The fifth capacitor C5 has one plate receiving the first fixed potential signal VGH and the other plate electrically connected to the fifth node N5 to improve the stability of the potential of the fifth node N5.

[0155] Among them, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 have the same channel type.

[0156] For example, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all P-type transistors.

[0157] When the selected signal line CTRL transmits a high-level signal, the sixth node N6 can only maintain a high level, the eleventh transistor T11 remains in the off state, the fifth node N5 can only receive the high-level first fixed potential signal VGH transmitted by the twelfth transistor T12, the eighth transistor T8 remains in the off state, and the output terminal SN_OUT of the first type of signal output module 16 can only output the low-level second fixed potential signal VGL transmitted by the ninth transistor T9.

[0158] When the selected signal line CTRL transmits a low-level signal, the eleventh transistor T11 and the twelfth transistor T12 can respectively transmit the potential of the third node N3 and the first fixed potential signal VGH to the fifth node N5. The potential of the third node N3 can be either high or low. Therefore, the fifth node N5 can maintain a high or low potential, the eighth transistor T8 can remain in the on or off state, and the output terminal SN_OUT of the first type of signal output module 16 can output the scan signal normally. The potential of the output terminal SN_OUT of the first type of signal output module 16 can be the same as the potential of the output terminal SN_NEXT of the first cascade module 12.

[0159] Thus, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 16 can be controlled by controlling the signal on the strobe signal line CTRL.

[0160] Figure 13 is a schematic diagram of another first shift register unit provided in an embodiment of this application, and Figure 14 is a schematic diagram of the first shift register unit shown in Figure 13.

[0161] In one embodiment of this application, as shown in Figures 13 and 14, the first shift register unit 101 further includes a second type of signal output module 19. The output terminal SP_OUT of the second type of signal output module 19 is used to output a second type of scan signal. The second type of scan signal can be the gate scan signal received by the data writing transistor in the pixel circuit, that is, the second type of signal output module 19 can be used to amplify the gate scan signal to the data writing transistor in the pixel circuit. The enable signal output by the output terminal SP_OUT of the second type of signal output module 19 can be a low-level signal.

[0162] For example, as shown in FIG15, FIG15 is a connection diagram of a pixel circuit provided in an embodiment of the present application. The structure of the pixel circuit shown in FIG15 can be the same as that of the pixel circuit shown in FIG3. In the first shift register unit 101, the first type of signal output module 16 is electrically connected to the first scan line S1N and the third scan line S2N in the pixel circuit 02. The first type of signal output module 16 can provide a scan signal to the gate of the gate reset transistor M1 through the first scan line S1N, and provide a scan signal to the gate of the threshold grabbing transistor M3 through the third scan line S2N.

[0163] The second type of signal output module 19 in the first shift register unit 101 is electrically connected to the second scan line SP in the pixel circuit 02. The second type of signal output module 19 can provide a scan signal to the gate of the data writing transistor M2 through the second scan line SP.

[0164] The second type of signal output module 19 includes a first scan signal output module 191 and a second scan signal output module 192. The first scan signal output module 191 and the second scan signal output module 192 can be electrically connected to the gate of the data writing transistor M2 in different row pixel circuits 02, respectively.

[0165] For example, the first scan signal output module 191 and the second scan signal output module 192 are electrically connected to the gates of the data writing transistors M2 in the two adjacent rows of pixel circuits 02. The first shift register unit 101 can drive the two adjacent rows of pixel circuits.

[0166] The first scan signal output module 191 includes a third output module 1911 and a fourth output module 1912. The input terminal of the third output module 1911 receives a first fixed potential signal VGH, its output terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and its control terminal is electrically connected to the output terminal SN_NEXT of the first cascaded module 12. The input terminal of the fourth output module 1912 receives a second clock signal CK2, and its output terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191.

[0167] The second scan signal output module 192 includes a fifth output module 1921 and a sixth output module 1922. The input terminal of the fifth output module 1921 receives a first fixed potential signal VGH, its output terminal is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and its control terminal is electrically connected to the output terminal SN_NEXT of the first cascaded module 12. The input terminal of the sixth output module 1922 receives a third clock signal CK3, and its output terminal is electrically connected to the output terminal SP_OUT1 of the second scan signal output module 192.

[0168] It should be noted that the output terminal SP1_OUT of the first scan signal output module 191 and the output terminal SP2_OUT of the second scan signal output module 192 can both be the output terminal SP_OUT of the second type of signal output module 19.

[0169] The first shift register unit 101 also includes a second input module 20 and a second voltage regulator module 21. The input terminal of the second input module 20 receives the second trigger signal SP_IN, the output terminal is electrically connected to the seventh node N7, and the control terminal receives the first clock signal CK1. The seventh node N7 is coupled to the control terminals of the fourth output module 1912 and the sixth output module 1922. A second coupling module 151 can be provided between the seventh node N7 and the control terminal of the fourth output module 1912, and a third coupling module 152 can be provided between the seventh node N7 and the control terminal of the sixth output module 1922. The signal output by the output terminal SP_OUT2 of the second scan signal output module 192 in the previous first shift register unit 101 can be the second trigger signal SP_IN received by the second input module 20 in the next first shift register unit 101.

[0170] The second voltage regulator module 21 receives the first fixed potential signal VGH at its input terminal, is electrically connected to the seventh node N7 at its output terminal, and is electrically connected to the output terminal SN_NEXT of the first cascade module 12 at its control terminal.

[0171] In this embodiment, the first shift register unit 101 can output both a first type of scan signal and a second type of scan signal, which helps to reduce the number of peripheral scan circuits required for the pixel circuit 02. When the scan circuit 100 and the pixel circuit 02 are applied in the display panel 200, it helps to reduce the area occupied by the peripheral scan circuits, thereby facilitating the achievement of a narrow bezel in the display panel 200. Moreover, reducing the number of peripheral scan circuits required for the pixel circuit 02 also reduces the number of clock signals required by the peripheral scan circuits, which helps to reduce the power consumption of the display panel 200.

[0172] Furthermore, by electrically connecting the output of the second voltage regulator module 21 to the seventh node N7, the second voltage regulator module 21 can be turned on during the period when the second input module 20 transmits a high level to the seventh node N7. This allows the second voltage regulator module 21 to transmit a high-level first fixed potential signal VGH to the seventh node N7, thereby improving the potential stability of the seventh node N7. This, in turn, improves the potential stability of the output of the second input module 16. Consequently, the control terminals of the fourth output module 1912 and the sixth output module 1922 can be stabilized at a high potential. This is beneficial for improving the coupling effect of the second clock signal CK2 on the control terminal of the output module 1912, as well as the coupling effect of the third clock signal CK3 on the control terminal of the sixth output module 1922.

[0173] For example, as shown in Figure 14, the third output module 1911 includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and the gate is electrically connected to the output terminal SN_NEXT of the first cascaded module 12. The fourth output module 1912 includes a fifteenth transistor T15. The first terminal of the fifteenth transistor T15 receives a second clock signal CK2, the second terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and the gate is coupled to the seventh node N7.

[0174] The fifth output module 1921 includes a sixteenth transistor T16. The first terminal of the sixteenth transistor T16 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the gate is electrically connected to the output terminal SN_NEXT of the first cascaded module 12. The sixth output module 1922 includes a seventeenth transistor T17. The first terminal of the seventeenth transistor T17 receives a third clock signal CK3, the second terminal is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the gate is coupled to the seventh node N7.

[0175] The second input module 20 includes an eighteenth transistor T18. The first terminal of the eighteenth transistor T18 receives the second trigger signal SP_IN, the second terminal is electrically connected to the seventh node N7, and the gate receives the first clock signal CK1.

[0176] The second voltage regulator module 21 includes a second voltage regulator transistor TF2. The first terminal of the second voltage regulator transistor TF2 receives the first fixed point signal VGH, the second terminal is electrically connected to the seventh node N7, and the gate is electrically connected to the output terminal SN_NEXT of the first cascade module 12.

[0177] Among them, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18 and the second Zener transistor TF2 have the same channel type.

[0178] For example, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, and the second Zener transistor TF2 are all P-type transistors.

[0179] Referring to Figure 14, in one embodiment of this application, the control terminal of the fourth output module 1912 is electrically connected to the seventh sub-node N7a. A third coupling transistor TO3 is disposed between the seventh node N7 and the seventh sub-node N7a, meaning that the control terminal of the fourth output module 1912 is connected to the seventh node N7 by the third coupling transistor TO3. The control terminal of the sixth output module 1922 is electrically connected to the seventh sub-node N7b. A fourth coupling transistor TO4 is disposed between the seventh node N7 and the seventh sub-node N7b, meaning that the control terminal of the sixth output module 1922 is connected to the seventh node N7 by the fourth coupling transistor TO4. The gates of both the third coupling transistor TO3 and the fourth coupling transistor TO4 receive the second fixed potential signal VGL.

[0180] The third coupling transistor TO3 and the fourth coupling transistor TO4 have the same channel type. During the operation of the first shift register unit 101, the third coupling transistor TO3 and the fourth coupling transistor TO4 can remain in the on state.

[0181] For example, both the third coupling transistor TO3 and the fourth coupling transistor TO4 are P-type transistors.

[0182] In the real-time mode of this application, the settings of the third coupling transistor TO3 and the fourth coupling transistor TO4 are beneficial to stabilizing the potential of the seventh node N7, that is, to stabilizing the output potential of the second input module 20. When the control terminal potential of the fourth output module 1912 changes, the third coupling transistor TO3 can reduce the impact of this potential change on the potential of the seventh node N7, thereby stabilizing the potential of the seventh node N7. When the control terminal potential of the sixth output module 1922 changes, the fourth coupling transistor TO4 can reduce the impact of this potential change on the potential of the seventh node N7, thereby stabilizing the potential of the seventh node N7. This, in turn, helps to ensure the accuracy of the second trigger signal SN_IN output by the second input module 20.

[0183] Referring to Figure 14, the first shift register unit 101 also includes a sixth capacitor C6 and a seventh capacitor C7. One plate of the sixth capacitor C6 is electrically connected to the control terminal of the fourth output module 1912, and the other plate is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, to stabilize the control terminal potential of the fourth output module 1912. One plate of the seventh capacitor C7 is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the other plate is electrically connected to the control terminal of the sixth output module 1922, to stabilize the control terminal potential of the sixth output module 1922.

[0184] It should be noted that in the first shift register unit shown in Figures 13 and 14, the first cascade module 12 and the first type of signal output module 16 can be set to be independent of each other. The first shift register unit may include the first type of signal output module 16 and the gating module 17 shown in Figures 11 and 12.

[0185] Figure 16 is a schematic diagram of a first shift register unit provided in an embodiment of this application. The difference between the first shift register unit shown in Figure 16 and the first shift register unit shown in Figure 14 is that the gate of the eighteenth transistor T18 receives the second clock signal CK2, the first terminal of the fifteenth transistor T15 receives the third clock signal CK3, and the first terminal of the seventeenth transistor T17 receives the fourth clock signal CK4.

[0186] Thus, compared to the first shift register unit shown in Figure 14, it is beneficial to reduce the load on the first clock signal CK1 and improve the signal output difference caused by the unbalanced clock signal load.

[0187] Referring to Figure 17, which is a timing diagram of the first shift register unit shown in Figure 16, during the signal output period Z of the first shift register unit 101, the first trigger signal SN_IN is a high-level signal, the first master node N1a, the first node N1b, the second master node N2a, and the second node N2b are all high-level signals, the third node N3 is a low-level signal, and the output terminal SN_NEXT of the first cascade module 12 (the output terminal SN_OUT of the first type of signal output module) outputs a high-level signal.

[0188] The signal output period Z of the first shift register unit 101 includes a first stage Z1, a second stage Z2 and a third stage Z3. In the first stage Z1, the second stage Z2 and the third stage Z3, the first clock signal CK1 is a high-level signal.

[0189] In the first stage Z1, the second trigger signal SP_IN is a low-level signal, the second clock signal CK2 is a low-level signal, the seventh node N7 is a low-level signal, and the third clock signal CK3 and the fourth clock signal CK4 are both high-level signals. The output terminal SP_OUT1 of the first scan signal output module 191 and the output terminal SP_OUT2 of the second scan signal output module 192 both output high-level signals.

[0190] In the second stage Z2, the second trigger signal SP_IN is a high-level signal, the second clock signal CK2 and the fourth clock signal CK4 are high-level signals, the seventh node N7 remains a low-level signal, and the third clock signal CK3 is a low-level signal. The output terminal SP_OUT1 of the first scan signal output module 191 outputs a low-level signal, and the output terminal SP_OUT2 of the second scan signal output module 192 outputs a high-level signal.

[0191] In the third stage Z3, the second trigger signal SP_IN is a high-level signal, the second clock signal CK2 and the third clock signal CK3 are high-level signals, the seventh node N7 remains a low-level signal, and the fourth clock signal CK4 is a low-level signal. The output terminal SP_OUT1 of the first scan signal output module 191 outputs a high-level signal, and the output terminal SP_OUT2 of the second scan signal output module 192 outputs a low-level signal.

[0192] Figure 18 is a schematic diagram of another display panel provided in an embodiment of this application, and Figure 19 is a simplified structural schematic diagram of a second shift register unit provided in an embodiment of this application.

[0193] In one embodiment of this application, as shown in FIG18, the scanning circuit 100 further includes a plurality of cascaded second shift register units 102, which, together with the first shift register unit 101, can provide scanning signals to different transistors in the pixel circuit.

[0194] For example, the first shift register unit 101 is used to provide a gate scan signal to the gate reset transistor and / or threshold grab transistor in the pixel circuit. The second shift register unit 102 is used to provide a gate scan signal to the data write transistor in the pixel circuit.

[0195] As shown in Figure 19, the second shift register unit 102 includes a second type of signal output module 19 and a second input module 20. The output terminal SP_OUT of the second type of signal output module 19 is used to output a second type of scan signal. The second type of scan signal can be the gate scan signal received by the data writing transistor in the pixel circuit. The enable signal output by the output terminal SP_OUT of the second type of signal output module 19 can be a low-level signal.

[0196] The second input module 20 is used to receive the second trigger signal SP_IN. The output terminal of the second input module 20 is electrically connected to the seventh node N7. The seventh node N7 is coupled to part of the control terminal of the second type of signal output module 19.

[0197] The second shift register unit 102 also includes a second voltage regulator module 21, the output of which is electrically connected to the seventh node N7.

[0198] In this implementation, the second shift register unit 102 and the first shift register unit 101 can operate independently, which improves the flexibility of their operating timing. Furthermore, electrically connecting the output of the second voltage regulator module 21 to the seventh node N7 helps improve the stability of the potential of the seventh node N7 and reduces the probability of abnormal output from the second type of signal output module 19.

[0199] Optionally, as shown in Figure 19, the control terminal of the second input module 20 receives the first clock signal CK1, and the second type of signal output module 10 includes a first scan signal output module 191 and a second scan signal output module 192. The first scan signal output module 191 and the second scan signal output module 192 can be electrically connected to the gate of the data writing transistor M2 in different row pixel circuits 02, respectively.

[0200] For example, the first scan signal output module 191 and the second scan signal output module 192 are electrically connected to the gates of the data writing transistors M2 in the adjacent two rows of pixel circuits 02. The second shift register unit 102 can drive the adjacent two rows of pixel circuits.

[0201] The first scan signal output module 191 includes a third output module 1911 and a fourth output module 1912. The input terminal of the third output module 1911 receives a first fixed potential signal VGH, its output terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and its control terminal is electrically connected to the eighth node N8. The input terminal of the fourth output module 1912 receives a second clock signal CK2, its output terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and its control terminal is coupled to the seventh node N7. For example, the control terminal of the fourth output module 1912 is electrically connected to the seventh sub-node N7a, and a second coupling module 151 is provided between the seventh node N7 and the seventh sub-node N7a.

[0202] The second scan signal output module 192 includes a fifth output module 1921 and a sixth output module 1922. The fifth output module 1921 receives a first fixed potential signal VGH at its input, its output is electrically connected to the output SP_OUT2 of the second scan signal output module 192, and its control terminal is electrically connected to the eighth node N8. The sixth output module 1922 receives a third clock signal CK3 at its input, its output is electrically connected to the output SP_OUT2 of the second scan signal output module 192, and its control terminal is coupled to the seventh node N7. For example, the control terminal of the sixth output module 1922 is electrically connected to the seventh secondary node N7b, and a third coupling module 152 is provided between the seventh node N7 and the seventh secondary node N7b.

[0203] It should be noted that the output terminal SP1_OUT of the first scan signal output module 191 and the output terminal SP2_OUT of the second scan signal output module 192 can both be the output terminal SP_OUT of the second type of signal output module 19. The signal output from the output terminal SP_OUT2 of the second scan signal output module 192 in the previous stage second shift register unit 102 can be the second trigger signal SP_IN received by the second input module 20 in the next stage second shift register unit 102.

[0204] The second shift register unit 102 also includes a second control module 22, the output of which is electrically connected to the eighth node N8 and the second voltage regulator module 21.

[0205] The first scan signal output module 191 outputs a first fixed potential signal VGH or a second clock signal CK2 in response to the potential of the eighth node N8 and the potential of the seventh node N7. The second scan signal output module 192 outputs a first fixed potential signal VGH or a third clock signal CK3 in response to the potential of the eighth node N8 and the potential of the seventh node N7.

[0206] For example, as shown in FIG20, FIG20 is a schematic diagram of a second shift register unit provided in an embodiment of the present application. The third output module 1911 includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and the gate is electrically connected to the eighth node N8.

[0207] The fourth output module 1912 includes a fifteenth transistor T15. The first terminal of the fifteenth transistor T15 receives the second clock signal CK2, the second terminal is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and the gate is coupled to the seventh node N7.

[0208] The fifth output module 1921 includes a sixteenth transistor T16. The first terminal of the sixteenth transistor T16 receives the first fixed potential signal VGH, the second terminal is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the gate is electrically connected to the eighth node N8.

[0209] The sixth output module 1922 includes a seventeenth transistor T17. The first terminal of the seventeenth transistor T17 receives the third clock signal CK3, the second terminal is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the gate is coupled to the seventh node N7.

[0210] The second input module 20 includes an eighteenth transistor T18. The first terminal of the eighteenth transistor T18 receives the second trigger signal SP_IN, the second terminal is electrically connected to the seventh node N7, and the gate receives the first clock signal CK1.

[0211] Among them, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 have the same channel type.

[0212] For example, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are all P-type transistors.

[0213] Furthermore, as shown in Figure 20, the gate of the fifteenth transistor T15 is electrically connected to the seventh node N7a. A third coupling transistor TO3 is disposed between the seventh node N7 and the seventh node N7a, meaning that the gate of the fifteenth transistor T15 is connected to the gate of the seventh node N7 via the third coupling transistor TO3. The gate of the seventeenth transistor T17 is electrically connected to the seventh node N7b. A fourth coupling transistor TO4 is disposed between the seventh node N7 and the seventh node N7b, meaning that the gate of the seventeenth transistor T17 is connected to the gate of the seventh node N7 via the fourth coupling transistor TO4. Both the gate of the third coupling transistor TO3 and the gate of the fourth coupling transistor TO4 receive the second fixed potential signal VGL.

[0214] The third coupling transistor TO3 and the fourth coupling transistor TO4 have the same channel type. During the operation of the two-shift register unit 102, the third coupling transistor TO3 and the fourth coupling transistor TO4 can remain in the on state.

[0215] For example, both the third coupling transistor TO3 and the fourth coupling transistor TO4 are P-type transistors.

[0216] The setting of the third coupling transistor TO3 and the fourth coupling transistor TO4 can reduce the impact of the potential changes of the seventh node N7a and the seventh node N7b on the seventh node N7, which is beneficial to improving the stability of the potential of the seventh node N7.

[0217] Furthermore, as shown in Figure 20, the second shift register unit 102 also includes a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. One plate of the sixth capacitor C6 is electrically connected to the gate of the fifteenth transistor T15, and the other plate is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191 to stabilize the gate potential of the fifteenth transistor T15.

[0218] One plate of the seventh capacitor C7 is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the other plate is electrically connected to the gate of the seventeenth transistor T17 to stabilize the gate potential of the seventeenth transistor T17.

[0219] One plate of the eighth capacitor C8 receives the first fixed potential signal VGH, and the other plate is electrically connected to the eighth node N8 to stabilize the potential of the eighth node N8 and improve the gate potential stability of the fourteenth transistor T14 and the sixteenth transistor T16.

[0220] As one possible implementation, as shown in Figure 20, the second control module 22 includes a nineteenth transistor T19 and a twentieth transistor T20. The nineteenth transistor T19 has a first terminal receiving a first clock signal CK1, a second terminal electrically connected to the eighth node N8, and a gate electrically connected to the seventh node N7. The twentieth transistor T20 has a first terminal receiving a second fixed potential signal VGL, a second terminal electrically connected to the eighth node N8, and a gate receiving the first clock signal. The second control module 22 can respond to the potential of the seventh node N7 and the first clock signal CK1 by transmitting either the second fixed potential signal VGL or the first clock signal CK1 to the eighth node N8.

[0221] The second voltage regulator module 21 includes a second voltage regulator transistor TF2, a third voltage regulator transistor TF3, and a fourth voltage regulator transistor TF4. The first terminal of the second voltage regulator transistor TF2 receives a first fixed potential signal VGH, the second terminal is electrically connected to the ninth node N9, and the gate is electrically connected to the eighth node N8. The first terminal of the third voltage regulator transistor TF3 is electrically connected to the ninth node N9, the second terminal is electrically connected to the seventh node N7, and the gate receives a second clock signal CK2. The first terminal of the fourth voltage regulator transistor TF4 is electrically connected to the ninth node N9, the second terminal is electrically connected to the seventh node N7, and the gate receives a third clock signal CK3.

[0222] The second voltage regulator module 21 can respond to the potential of the eighth node N8 and the second clock signal CK2 and the third clock signal CK3 to transmit the first fixed potential signal VGH to the seventh node N7.

[0223] Among them, the nineteenth transistor T19, the twentieth transistor T20, the second Zener transistor TF2, the third Zener transistor TF3, and the fourth Zener transistor TF4 have the same channel type.

[0224] For example, the nineteenth transistor T19, the twentieth transistor T20, the second Zener transistor TF2, the third Zener transistor TF3, and the fourth Zener transistor TF4 are all P-type transistors.

[0225] In this implementation, during the period when the seventh node N7 remains high, the twentieth transistor T20 can transmit the low-level second fixed potential signal VGL to the eighth node N8. The low-level signal of the eighth node N8 controls the second Zener transistor TF2 to turn on. The high-level first fixed potential signal VGH can be transmitted to the ninth node N9 through the second Zener transistor TF2. When the second clock signal CK2 transmits a low-level signal, the high level of the ninth node N9 can be transmitted to the seventh node N7 through the third Zener transistor TF3, maintaining the high-level potential of the seventh node N7 and the seventh secondary node N7a. This helps to avoid the situation where the fifteenth transistor T15 turns on multiple times due to the second clock signal CK2 switching down the potential of the seventh secondary node N7a. When the third clock signal CK3 transmits a low-level signal, the high level of the ninth node N9 can be transmitted to the seventh node N7 through the fourth Zener transistor TF4, maintaining the high-level potential of the seventh node N7 and the seventh secondary node N7b. This helps to avoid the situation where the seventeenth transistor T17 turns on multiple times due to the third clock signal CK3 switching down the potential of the seventh secondary node N7b.

[0226] As another possible implementation, as shown in Figure 21, which is a schematic diagram of another second shift register unit provided in this application embodiment, the second control module 22 includes a nineteenth transistor T19 and a twentieth transistor T20 with different channel types. The first terminal of the nineteenth transistor T19 receives a first fixed potential signal VGH, the second terminal is electrically connected to the eighth node N8, and the gate is electrically connected to the seventh node N7. The first terminal of the twentieth transistor T20 receives a second fixed potential signal VGL, the second terminal is electrically connected to the eighth node N8, and the gate is electrically connected to the seventh node N7. In response to the potential of the seventh node N7, the second control module 22 transmits either the first fixed potential signal VGH or the second fixed potential signal VGL to the eighth node N8. The potential level of the eighth node N8 can be opposite to the potential level of the seventh node N7.

[0227] The second voltage regulator module 21 includes a second voltage regulator transistor TF2 and a third voltage regulator transistor TF3 with different channel types. The first terminal of the second voltage regulator transistor TF2 receives a first fixed potential signal VGH, the second terminal is electrically connected to the seventh node N7, and the gate is electrically connected to the eighth node N8. The first terminal of the third voltage regulator transistor TF3 receives a second fixed potential signal VGL, the second terminal is electrically connected to the seventh node N7, and the gate is electrically connected to the eighth node N8. The second voltage regulator module 21 responds to the potential of the eighth node N8 by transmitting either the first fixed potential signal VGH or the second fixed potential signal VGL to the seventh node N7.

[0228] Among them, the nineteenth transistor T19 has the same channel type as the second Zener transistor TF2, and the twentieth transistor T20 has the same channel type as the third Zener transistor TF3.

[0229] For example, the nineteenth transistor T19 and the second Zener transistor TF2 are P-type transistors, and the twentieth transistor T20 and the third Zener transistor TF3 are N-type transistors.

[0230] In this implementation, during the period when the seventh node N7 remains high, the nineteenth transistor T19 is off, and the twentieth transistor T20 is on. The low-level second fixed potential signal VGL is transmitted to the eighth node N8 through the twentieth transistor T20. The eighth node N8 remains low, and the low-level potential of the eighth node N8 controls the second Zener transistor TF2 to turn on and the third Zener transistor TF3 to turn off. The high-level first fixed potential signal VGH is transmitted to the seventh node N7 through the second Zener transistor TF2, maintaining the high-level potential of the seventh node N7, the seventh secondary node N7a, and the seventh secondary node N7b. This helps to avoid the situation where the second clock signal CK2 jumps and pulls the seventh secondary node N7a low, causing the fifteenth transistor T15 to turn on multiple times, and also avoids the situation where the third clock signal CK3 jumps and pulls the seventh secondary node N7b low, causing the seventeenth transistor T17 to turn on multiple times.

[0231] During the period when the seventh node N7 is maintained at a low level, the nineteenth transistor T19 is turned on and the twentieth transistor T20 is turned off. The high-level first fixed potential signal VGH is transmitted to the eighth node N8 through the nineteenth transistor T19. The eighth node N8 is maintained at a high level. The high-level potential of the eighth node N8 controls the second Zener transistor TF2 to turn off and the third Zener transistor TF3 to turn on. The low-level second fixed potential signal VGL is transmitted to the seventh node N7 through the third Zener transistor TF3, maintaining the low-level potential of the seventh node N7, the seventh secondary node N7a, and the seventh secondary node N7b.

[0232] This implementation method can maintain a stable high or low potential for the seventh node N7, preventing the potential of the seventh node N7 from floating, which is beneficial to improving the potential stability of the seventh node N7.

[0233] Figure 22 is a schematic diagram of another second shift register unit provided in the embodiment of this application. The difference between the second shift register unit shown in Figure 22 and the second shift register unit shown in Figure 20 is that the gate of the eighteenth transistor T18, the first terminal of the nineteenth transistor T19, and the gate of the twentieth transistor T20 all receive the second clock signal CK2; the first terminal of the fifteenth transistor T15 and the gate of the third Zener transistor TF3 all receive the third clock signal CK3; and the first terminal of the seventeenth transistor T17 and the gate of the fourth Zener transistor TF4 all receive the fourth clock signal CK4.

[0234] Thus, in the scanning circuit 100 composed of the second shift register unit shown in Figure 22 and the first shift register unit 101 shown in any of Figures 6, 8, 10 and 12, the load on the first clock signal CK1 can be reduced, which is beneficial to reducing the signal output difference caused by the unbalanced clock signal load.

[0235] Figure 23 is a timing diagram of a scanning circuit provided in an embodiment of this application. The timing diagram shown in Figure 23 is a timing diagram of a scanning circuit 100 including the first shift register unit 101 shown in Figure 8 and the second shift register unit 102 shown in Figure 22.

[0236] As shown in Figure 23, during the signal output period Z of the scanning circuit 100, the first trigger signal SN_IN is a low-level signal, the first node N1 is a low-level signal, the second node N2 is a high-level signal, the second sub-node N2A is a low-level signal, the first cascade signal output by the output terminal SN_NEXT of the first cascade module 12 is a low-level signal, and the first type of scanning signal output by the output terminal SN_OUT of the first type of signal output module 16 is a high-level signal.

[0237] The signal output period Z of the scanning circuit 100 also includes a first stage Z1, a second stage Z2 and a third stage Z3. In the first stage Z1, the second stage Z2 and the third stage Z3, the first clock signal CK1 is a high-level signal.

[0238] In the first stage Z1, the second trigger signal SP_IN is low, the second clock signal CK2 is low, the seventh node N7 is low, the eighth node N8 is low, and the third clock signal CK3 and the fourth clock signal CK4 are both high. The output terminals SP_OUT1 of the first scan signal output module 191 and SP_OUT2 of the second scan signal output module 192 both output high-level signals.

[0239] In the second stage Z2, the second trigger signal SP_IN is a high-level signal, the second clock signal CK2 and the fourth clock signal CK4 are high-level signals, the seventh node N7 remains a low-level signal, the eighth node N8 is a high-level signal, and the third clock signal CK3 is a low-level signal. The output terminal SP_OUT1 of the first scan signal output module 191 outputs a low-level signal, and the output terminal SP_OUT2 of the second scan signal output module 192 outputs a high-level signal.

[0240] In the third stage Z3, the second trigger signal SP_IN is a high-level signal, the second clock signal CK2 and the third clock signal CK3 are high-level signals, the seventh node N7 remains a low-level signal, the eighth node N8 remains a high-level signal, and the fourth clock signal CK4 is a low-level signal. The output terminal SP_OUT1 of the first scan signal output module 191 outputs a high-level signal, and the output terminal SP_OUT2 of the second scan signal output module 192 outputs a low-level signal.

[0241] It should be noted that in the timing diagram shown in Figure 23, the strobe signal line CTRL transmits a low-level signal.

[0242] Figure 24 is a timing diagram of another scanning circuit provided in an embodiment of this application. The timing diagram shown in Figure 24 is a timing diagram of a scanning circuit 100 including the first shift register unit 101 shown in Figure 12 and the second shift register unit 102 shown in Figure 22.

[0243] As shown in Figure 24, during the signal output period Z of the scanning circuit 100, the first trigger signal SN_IN is a high-level signal, the first master node N1a and the second master node N2a are both high-level signals, the third node N3 is a low-level signal, the first cascade signal output by the output terminal SN_NEXT of the first cascade module 12 is a high-level signal, the sixth node N6 is a low-level signal, and the first type of scanning signal output by the output terminal SN_OUT of the first type of signal output module 16 is a high-level signal.

[0244] The signal output period Z of the scanning circuit 100 also includes a first stage Z1, a second stage Z2 and a third stage Z3. In the first stage Z1, the second stage Z2 and the third stage Z3, the first clock signal CK1 is a high-level signal.

[0245] In the first stage Z1, the second trigger signal SP_IN is low, the second clock signal CK2 is low, the seventh node N7 is low, the eighth node N8 is low, and the third clock signal CK3 and the fourth clock signal CK4 are both high. The output terminals SP_OUT1 of the first scan signal output module 191 and SP_OUT2 of the second scan signal output module 192 both output high-level signals.

[0246] In the second stage Z2, the second trigger signal SP_IN is a high-level signal, the second clock signal CK2 and the fourth clock signal CK4 are high-level signals, the seventh node N7 remains a low-level signal, the eighth node N8 is a high-level signal, and the third clock signal CK3 is a low-level signal. The output terminal SP_OUT1 of the first scan signal output module 191 outputs a low-level signal, and the output terminal SP_OUT2 of the second scan signal output module 192 outputs a high-level signal.

[0247] In the third stage Z3, the second trigger signal SP_IN is a high-level signal, the second clock signal CK2 and the third clock signal CK3 are high-level signals, the seventh node N7 remains a low-level signal, the eighth node N8 remains a high-level signal, and the fourth clock signal CK4 is a low-level signal. The output terminal SP_OUT1 of the first scan signal output module 191 outputs a high-level signal, and the output terminal SP_OUT2 of the second scan signal output module 192 outputs a low-level signal.

[0248] Figure 25 is a schematic diagram of the connection of a scanning circuit provided in an embodiment of this application.

[0249] In one embodiment of this application, as shown in Figures 8, 20, and 25, in the odd-row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the first clock signal line CL1; in the even-row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the third clock signal line CL3. That is, in the odd-row first shift register unit 101, the clock signal transmitted by the first clock signal line CL1 serves as the first clock signal CK1 received by the control terminal of the first input module 11; and in the even-row first shift register unit 101, the clock signal transmitted by the third clock signal line CL3 serves as the first clock signal CK1 received by the control terminal of the first input module 11.

[0250] In the odd-numbered row second shift register unit 102, the control terminal of the second input module 20 is electrically connected to the first clock signal line CL1, the input terminal of the fourth output module 1912 is electrically connected to the second clock signal line CL2, and the input terminal of the sixth output module 1922 is electrically connected to the third clock signal CL3.

[0251] In the even-numbered row second shift register unit 102, the control terminal of the second input module 20 is electrically connected to the third clock signal line CL3, the input terminal of the fourth output module 1912 is electrically connected to the fourth clock signal line CL4, and the input terminal of the sixth output module 1922 is electrically connected to the first clock signal CL1.

[0252] In other words, in the odd-numbered row second shift register unit 102, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the second shift register unit 102, the clock signal transmitted by the second clock signal line CL2 is used as the second clock signal CK2 received by the second shift register unit 102, and the clock signal transmitted by the third clock signal CL3 is used as the third clock signal CK3 received by the second shift register unit 102.

[0253] In the even-numbered row second shift register unit 102, the clock signal transmitted by the third clock signal CL3 serves as the first clock signal CK1 received by the second shift register unit 102, the clock signal transmitted by the fourth clock signal line CL4 serves as the second clock signal CK2 received by the second shift register unit 102, and the clock signal transmitted by the first clock signal line CL1 serves as the third clock signal CK3 received by the second shift register unit 102.

[0254] In this implementation, the first shift register unit 101 and the second shift register unit 102 can share a clock signal line, which helps to reduce the number of clock signal lines required by the scanning circuit 100 and reduce power consumption.

[0255] Figure 26 is a connection diagram of another scanning circuit provided in an embodiment of this application.

[0256] In one embodiment of this application, as shown in Figures 8, 20, and 26, in the odd-row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the first clock signal line CL1; in the even-row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the third clock signal line CL3. That is, in the odd-row first shift register unit 101, the clock signal transmitted by the first clock signal line CL1 serves as the first clock signal CK1 received by the control terminal of the first input module 11; and in the even-row first shift register unit 101, the clock signal transmitted by the third clock signal line CL3 serves as the first clock signal CK1 received by the control terminal of the first input module 11.

[0257] In the odd-numbered row second shift register unit 102, the control terminal of the second input module 20 is electrically connected to the second clock signal line CL2, the input terminal of the fourth output module 1912 is electrically connected to the third clock signal line CL3, and the input terminal of the sixth output module 1922 is electrically connected to the fourth clock signal CL4.

[0258] In the even-numbered row second shift register unit 102, the control terminal of the second input module 20 is electrically connected to the fourth clock signal line CL4, the input terminal of the fourth output module 1912 is electrically connected to the first clock signal line CL1, and the input terminal of the sixth output module 1922 is electrically connected to the second clock signal CL2.

[0259] In other words, in the odd-numbered row second shift register unit 102, the clock signal transmitted by the second clock signal line CL2 is used as the second clock signal CK2 received by the second shift register unit 102, the clock signal transmitted by the third clock signal line CL3 is used as the third clock signal CK2 received by the second shift register unit 102, and the clock signal transmitted by the fourth clock signal CL4 is used as the fourth clock signal CK4 received by the second shift register unit 102.

[0260] In the even-numbered row second shift register unit 102, the clock signal transmitted by the fourth clock signal CL4 serves as the second clock signal CK2 received by the second shift register unit 102, the clock signal transmitted by the first clock signal line CL1 serves as the third clock signal CK3 received by the second shift register unit 102, and the clock signal transmitted by the second clock signal line CL2 serves as the fourth clock signal CK3 received by the second shift register unit 102.

[0261] In this implementation, while enabling the first shift register unit 101 and the second shift register unit 102 to share the same clock signal line, it is beneficial to make the load of clock signal transmission on different clock signal lines more balanced, which is beneficial to improve the signal output difference of the shift register unit caused by the unbalanced load of the clock signal lines.

[0262] Figure 27 is a connection diagram of another scanning circuit provided in an embodiment of this application.

[0263] In one embodiment of this application, as shown in Figures 10, 20 and 27, or in Figures 12, 20 and 27, in the odd-row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the first clock signal line CL1, and the second input terminal of the auxiliary voltage regulator module 18 is electrically connected to the second clock signal line CL2.

[0264] In the even-level first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the third clock signal line CL3, and the second input terminal of the auxiliary voltage regulator module 18 is electrically connected to the fourth clock signal line CL4.

[0265] In other words, in the odd-level first shift register unit 101, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the first shift register unit 101, and the clock signal transmitted by the second clock signal line CL2 is used as the second clock signal CK2 received by the first shift register unit 101.

[0266] In the even-numbered row first shift register unit 101, the clock signal transmitted by the third clock signal line CL3 serves as the first clock signal CK1 received by the first shift register unit 101, and the clock signal transmitted by the fourth clock signal line CL4 serves as the second clock signal CK2 received by the first shift register unit 101.

[0267] In this implementation, the clock signal line connected to the first shift register unit 101 can be shared with the clock signal line connected to the second shift register unit 102 in the aforementioned scheme, for example, sharing the clock signal line with the second shift register unit 102 shown in FIG20. This is beneficial to reduce the number of clock signal lines connected to the scanning circuit 100 composed of the first shift register unit 101 and the aforementioned second shift register unit 102, and reduce power consumption.

[0268] Figure 28 is a connection diagram of another scanning circuit provided in an embodiment of this application.

[0269] In one embodiment of this application, as shown in Figures 10, 20 and 28, or Figures 12, 20 and 28, in the odd-row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the first clock signal line CL1, and the second input terminal of the auxiliary voltage regulator module 18 is electrically connected to the third clock signal line CL3 or the fourth clock signal line CL4.

[0270] In the even-numbered row first shift register unit 101, the control terminal of the first input module 11 is electrically connected to the third clock signal line CL3, and the second input terminal of the auxiliary voltage regulator module 18 is electrically connected to the first clock signal line CL1 or the second clock signal line CL2.

[0271] In other words, in the odd-numbered row first shift register unit 101, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the first shift register unit 101, and the clock signal transmitted by the third clock signal line CL3 or the fourth clock signal line CL4 is used as the second clock signal CK2 received by the first shift register unit 101.

[0272] In the even-numbered row first shift register unit 101, the clock signal transmitted by the third clock signal line CL3 serves as the first clock signal CK1 received by the first shift register unit 101, and the clock signal transmitted by the first clock signal line CL1 or the second clock signal line CL2 serves as the second clock signal CK2 received by the first shift register unit 101.

[0273] It should be noted that Figure 28 only illustrates the case where the second input terminal of the auxiliary voltage regulator module 18 in the odd-numbered row first shift register unit 101 is electrically connected to the third clock signal line CL3, and the second input terminal of the auxiliary voltage regulator module 18 in the even-numbered row first shift register unit 101 is electrically connected to the first clock signal line CL1.

[0274] In this embodiment, when the first shift register unit 101 and the second shift register unit 102 (such as the second shift register unit shown in FIG20) share a clock signal line, the clock signal line connected to the second input terminal of the auxiliary voltage regulator module 18 can be flexibly adjusted according to the load on different clock signal lines to improve the load uniformity of each clock signal line connected to the scanning circuit 100 and improve the signal output difference of the shift register unit caused by the unbalanced load of the clock signal line.

[0275] As shown in Figures 1 and 18, this application embodiment also provides a display panel 200, which includes the scanning circuit 100 provided in the above embodiments. Exemplarily, the display panel 200 can be any one of an organic light-emitting diode (OLED) display panel, a micro-light-emitting diode (Micro-LED) display panel, or a mini-LED display panel; this application does not specifically limit it.

[0276] In the display panel 200, if the output terminal of the first voltage regulator module 13 is electrically connected to the output terminal of the first input module 11, a voltage regulator signal can be provided to the output terminal of the first input module 11 through the first voltage regulator module 13 to compensate for the potential loss during the output process of the first input module 11. This is beneficial to improving the accuracy and stability of the potential at the output terminal of the first input module 11, thereby improving the working reliability of other modules that receive the potential at the output terminal of the first input module 11, and further improving the working reliability of the first shift register unit 101.

[0277] If the output terminal of the first voltage regulator module 13 is electrically connected to a portion of the control terminal of the first cascade module 12, a voltage regulator signal can be provided to a portion of the control terminal of the first cascade module 12 through the first voltage regulator module 13. This is beneficial to improving the stability of the potential of the control terminal of the first cascade module 12, thereby improving the working reliability of the first cascade module 12, and further improving the working reliability of the first shift register unit 101.

[0278] Figure 29 is a schematic diagram of a display device provided in an embodiment of this application.

[0279] As shown in Figure 29, this application embodiment provides a display device 300, including the display panel 200 as provided in the above embodiment. For example, the display device 200 can be an electronic device such as a mobile phone, computer, television, vehicle display, or wearable display; this application does not impose specific limitations.

[0280] In the display device 300, if the output terminal of the first voltage regulator module 13 is electrically connected to the output terminal of the first input module 11, a voltage regulator signal can be provided to the output terminal of the first input module 11 through the first voltage regulator module 13 to compensate for the potential loss during the output process of the first input module 11. This is beneficial to improving the accuracy and stability of the potential at the output terminal of the first input module 11, thereby improving the working reliability of other modules that receive the potential at the output terminal of the first input module 11, and further improving the working reliability of the first shift register unit 101.

[0281] If the output terminal of the first voltage regulator module 13 is electrically connected to a portion of the control terminal of the first cascade module 12, a voltage regulator signal can be provided to a portion of the control terminal of the first cascade module 12 through the first voltage regulator module 13. This is beneficial to improving the stability of the potential of the control terminal of the first cascade module 12, thereby improving the working reliability of the first cascade module 12, and further improving the working reliability of the first shift register unit 101.

[0282] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A scanning circuit, characterized in that, It includes at least a plurality of cascaded first shift register units, each first shift register unit including a first input module and a first cascade module. The input terminal of the first input module is used to receive a first trigger signal, and the output terminal of the first cascade module is used to output a first cascade signal. The first shift register unit further includes a first voltage regulator module, the output terminal of which is electrically connected to the output terminal of the first input module; And / or, the output terminal of the first voltage regulator module is electrically connected to a portion of the control terminal of the first cascaded module.

2. The scanning circuit according to claim 1, characterized in that, The output terminal of the first input module is electrically connected to the first node, and the control terminal receives the first clock signal. The first input terminal of the first cascaded module receives the first fixed potential signal, the second input terminal receives the second fixed potential signal, and the control terminal is electrically connected to the second node. The first shift register unit further includes a first control module, wherein the first input terminal of the first control module receives the first fixed potential signal, the second input terminal receives the second fixed potential signal, the control terminal is electrically connected to the first node, and the output terminal is electrically connected to the second node; The first voltage regulator module has an input terminal that receives the second fixed potential signal, an output terminal that is electrically connected to the first node, and a control terminal that is electrically connected to the second node.

3. The scanning circuit according to claim 2, characterized in that, The first input module includes a first transistor, wherein the first terminal of the first transistor receives the first trigger signal, the second terminal is electrically connected to the first node, and the gate receives the first clock signal; The first control module includes a second transistor and a third transistor with different channel types. The first terminal of the second transistor receives the first fixed potential signal, the second terminal is electrically connected to the second node, and the gate is electrically connected to the first node. The first terminal of the third transistor receives the second fixed potential signal, the second terminal is electrically connected to the second node, and the gate is electrically connected to the first node. The first cascade module includes a fourth transistor and a fifth transistor with different channel types. The first terminal of the fourth transistor receives the first fixed potential signal, the second terminal is electrically connected to the output terminal of the first cascade module, and the gate is electrically connected to the second node. The first terminal of the fifth transistor receives the second fixed potential signal, the second terminal is electrically connected to the output terminal of the first cascade module, and the control terminal is electrically connected to the second node. The first voltage regulator module includes a first voltage regulator transistor, wherein the first terminal of the first voltage regulator transistor receives the second fixed potential signal, the second terminal is electrically connected to the first node, and the gate is electrically connected to the second node; The second transistor and the fourth transistor have the same channel type, and the third transistor, the first Zener transistor, and the fifth transistor have the same channel type.

4. The scanning circuit according to claim 2, characterized in that, The first shift register unit includes a first type of signal output module, the output terminal of which is used to output a first type of scan signal; The first type of signal output module includes a first output module and a second output module. The input terminal of the first output module receives the first fixed potential signal, and the output terminal is electrically connected to the output terminal of the first type of signal output module. The input terminal of the second output module receives the second fixed potential signal, and the output terminal is electrically connected to the output terminal of the first type of signal output module. The first shift register unit further includes a gating module, wherein the first input terminal of the gating module receives the first fixed potential signal and the second input terminal is electrically connected to the gating signal line; In this configuration, at least one of the first output module and the second output module has its control terminal electrically connected to the output terminal of the gating module.

5. The scanning circuit according to claim 4, characterized in that, The first output module includes a sixth transistor, wherein the first terminal of the sixth transistor receives the first fixed potential signal, and the second terminal is electrically connected to the output terminal of the first type of signal output module; The second output module includes a seventh transistor, the first terminal of which receives the second fixed potential signal, and the second terminal of which is electrically connected to the output terminal of the first type of signal output module; The sixth transistor and the seventh transistor have different channel types.

6. The scanning circuit according to claim 5, characterized in that, The gating module includes a first submodule and a second submodule. The input terminal of the first submodule receives the first fixed potential signal, the control terminal is electrically connected to the second node, and the output terminal is electrically connected to the control terminal of the first output module. The input terminal of the second submodule is electrically connected to the strobe signal line, the output terminal is electrically connected to the control terminal of the first output module, and the control terminal is electrically connected to the output terminal of the first cascaded module. The control terminal of the second output module is electrically connected to the output terminal of the first cascaded module.

7. The scanning circuit according to claim 6, characterized in that, The first submodule includes an eighth transistor, wherein the first terminal of the eighth transistor receives the first fixed potential signal, the second terminal is electrically connected to the gate of the sixth transistor, and the gate is electrically connected to the second node; The second submodule includes a ninth transistor, the first terminal of which is electrically connected to the gating signal line, the second terminal of which is electrically connected to the gate of the sixth transistor, and the gate of which is electrically connected to the output terminal of the first cascaded module; The gate of the seventh transistor is electrically connected to the output terminal of the first cascaded module; The eighth transistor has the same channel type as the ninth transistor, but a different channel type than the seventh transistor.

8. The scanning circuit according to claim 5, characterized in that, The gating module includes a first submodule and a second submodule. The input terminal of the first submodule receives the first fixed potential signal, the control terminal is electrically connected to the second node, and the output terminal is electrically connected to the control terminals of the first output module and the second output module. The input terminal of the second submodule is electrically connected to the strobe signal line, the control terminal is electrically connected to the second node, and the output terminal is electrically connected to the control terminals of the first output module and the second output module.

9. The scanning circuit according to claim 8, characterized in that, The first submodule includes an eighth transistor, the first terminal of which receives the first fixed potential signal, the second terminal of which is electrically connected to the gates of the sixth and seventh transistors, and the gate is electrically connected to the second node; The second submodule includes a ninth transistor, the first terminal of which is electrically connected to the gating signal line, the second terminal of which is electrically connected to the gates of the sixth and seventh transistors, and the gate is electrically connected to the second node; The eighth transistor has a different channel type than the ninth transistor, and the eighth transistor has the same channel type as the sixth transistor.

10. The scanning circuit according to claim 2, characterized in that, The first shift register unit includes a first capacitor, one plate of which is electrically connected to the first node, and the other plate receives the second fixed potential signal.

11. The scanning circuit according to claim 1, characterized in that, The first output terminal of the first input module is electrically connected to the first master node, the second output terminal is electrically connected to the first node, and the control terminal receives the first clock signal. The first master node is coupled to the second master node, and the first node is coupled to the second node. The first cascade module includes a first sub-cascade module and a second sub-cascade module. The input terminal of the first sub-cascade module receives a first fixed potential signal, the output terminal is electrically connected to the output terminal of the first cascade module, and the control terminal is electrically connected to the third node. The input terminal of the second sub-cascade module receives a second fixed potential signal, the output terminal is electrically connected to the output terminal of the first cascade module, and the control terminal is electrically connected to the second master node. The first shift register unit further includes a first control module, which includes a first sub-control module and a second sub-control module. The first sub-control module receives the first fixed potential signal at its input terminal, is electrically connected to the third node at its output terminal, and is electrically connected to the first master node at its control terminal. The second sub-control module receives the second fixed potential signal at its input terminal, is electrically connected to the third node at its output terminal, and is electrically connected to the second master node at its control terminal. The input terminal of the first voltage regulator module is electrically connected to the second node, the output terminal is electrically connected to the second main node, and the control terminal is electrically connected to the second node.

12. The scanning circuit according to claim 11, characterized in that, The first input module includes a first transistor and a second transistor. The first transistor receives the first trigger signal at its first terminal, is electrically connected to the first master node at its second terminal, and receives the first clock signal at its gate. The second transistor receives the first trigger signal at its first terminal, is electrically connected to the first master node at its second terminal, and receives the first clock signal at its gate. The first sub-cascade module includes a third transistor, wherein the first terminal of the third transistor receives the first fixed potential signal, the second terminal is electrically connected to the output terminal of the first cascade module, and the gate is electrically connected to the third node. The second sub-cascade module includes a fourth transistor, wherein the first terminal of the fourth transistor receives the second fixed potential signal, the second terminal is electrically connected to the output terminal of the first cascade module, and the gate is electrically connected to the second master node. The first sub-control module includes a fifth transistor, wherein the first terminal of the fifth transistor receives the first fixed potential signal, the second terminal is electrically connected to the third node, and the gate is electrically connected to the first master node; the second sub-control module includes a sixth transistor, wherein the first terminal of the sixth transistor receives the second fixed potential signal, the second terminal is electrically connected to the third node, and the gate is electrically connected to the second master node. The first voltage regulator module includes a first voltage regulator transistor, wherein the first terminal of the first voltage regulator transistor is electrically connected to the second node, the second terminal is electrically connected to the second main node, and the gate is electrically connected to the second node; The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the first Zener transistor have the same channel type, but the channel type is different from that of the sixth transistor.

13. The scanning circuit according to claim 12, characterized in that, The first transistor is a P-type transistor, and the sixth transistor is an N-type transistor.

14. The scanning circuit according to claim 11, characterized in that, A first coupling transistor is included between the first master node and the second master node, and a second coupling transistor is included between the first node and the second node. The gate of the first coupling transistor and the gate of the second coupling transistor both receive the second fixed potential signal. The first coupling transistor and the second coupling transistor have the same channel type.

15. The scanning circuit according to claim 11, characterized in that, The first shift register unit further includes an auxiliary voltage regulator module. The first input terminal of the auxiliary voltage regulator module receives the first fixed potential signal, the second input terminal receives the second clock signal, and the output terminal is electrically connected to the second node. The auxiliary voltage regulator module is used to adjust the potential of the second node.

16. The scanning circuit according to claim 15, characterized in that, The auxiliary voltage regulator module includes a first capacitor, a seventh transistor, and an eighth transistor, wherein the seventh transistor and the eighth transistor have the same channel type. One plate of the first capacitor is electrically connected to the second node, and the other plate is electrically connected to the fourth node. The first terminal of the seventh transistor receives the second clock signal, the second terminal is electrically connected to the fourth node, and the gate is electrically connected to the second node. The first terminal of the eighth transistor receives the first fixed potential signal, the second terminal is electrically connected to the fourth node, and the gate is electrically connected to the third node.

17. The scanning circuit according to claim 16, characterized in that, Both the seventh transistor and the eighth transistor are P-type transistors.

18. The scanning circuit according to claim 11, characterized in that, The first cascaded module is also used to output a first type of scanning signal.

19. The scanning circuit according to claim 11, characterized in that, The first shift register unit further includes a second capacitor and a third capacitor. One plate of the second capacitor receives the first fixed potential signal, and the other plate is electrically connected to the control terminal of the first sub-cascade module. One plate of the third capacitor is electrically connected to the output terminal of the first cascade module, and the other plate is electrically connected to the control terminal of the second sub-cascade module.

20. The scanning circuit according to claim 11, characterized in that, The first shift register unit further includes a gating module and a first type of signal output module, wherein the output terminal of the first type of signal output module is used to output a first type of scan signal; The first type of signal output module includes a first output module and a second output module. The input terminal of the first output module receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the first type of signal output module, and the control terminal is electrically connected to the output of the gating module. The input terminal of the second output module receives the second fixed potential signal, the output terminal is electrically connected to the output terminal of the first type of signal output module, and the control terminal is electrically connected to the second master node. The first input terminal of the gating module is electrically connected to the gating signal line, the second input terminal is electrically connected to the third node, and the third input terminal receives the first fixed potential signal. The gating module transmits a control signal to the first output module in response to the output potential of the first master node and the first cascaded module.

21. The scanning circuit according to claim 20, characterized in that, The first output module includes a ninth transistor, the first terminal of which receives the first fixed potential signal, the second terminal of which is electrically connected to the output terminal of the first type of signal output module, and the gate of which is electrically connected to the fifth node. The second output module includes a tenth transistor, the first terminal of which receives the second fixed potential signal, the second terminal of which is electrically connected to the output terminal of the first type of signal output module, and the gate of which is electrically connected to the second main node. The gating module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourth capacitor, and a fifth capacitor. The first terminal of the eleventh transistor is electrically connected to the gating signal line, the second terminal is electrically connected to the sixth node, and the gate is electrically connected to the output terminal of the first cascaded module. The first terminal of the twelfth transistor is electrically connected to the third node, the second terminal is electrically connected to the fifth node, and the gate is electrically connected to the sixth node. The first terminal of the thirteenth transistor receives the first fixed potential signal, the second terminal is electrically connected to the fifth node, and the gate is electrically connected to the first main node. One plate of the fourth capacitor receives the second fixed potential signal, and the other plate is electrically connected to the sixth node; one plate of the fifth capacitor receives the first fixed potential signal, and the other plate is electrically connected to the fifth node. The ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor have the same channel type.

22. The scanning circuit according to claim 18 or 20, characterized in that, The first shift register unit further includes a second type of signal output module, the output terminal of which is used to output a second type of scan signal; The second type of signal output module includes a first scan signal output module and a second scan signal output module. The first scan signal output module includes a third output module and a fourth output module. The input terminal of the third output module receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the first scan signal output module, and the control terminal is electrically connected to the output terminal of the first cascaded module. The input terminal of the fourth output module receives a second clock signal, and the output terminal is electrically connected to the output terminal of the first scan signal output module. The second scan signal output module includes a fifth output module and a sixth output module. The input terminal of the fifth output module receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the second scan signal output module, and the control terminal is electrically connected to the output terminal of the first cascaded module. The input terminal of the sixth output module receives the third clock signal, and the output terminal is electrically connected to the output terminal of the second scan signal output module. The first shift register unit further includes a second input module and a second voltage regulator module. The input terminal of the second input module receives a second trigger signal, the output terminal is electrically connected to the seventh node, and the control terminal receives the first clock signal. The seventh node is coupled to the control terminal of the fourth output module and the control terminal of the sixth output module. The input terminal of the second voltage regulator module receives the first fixed potential signal, the output terminal is electrically connected to the seventh node, and the control terminal is electrically connected to the output terminal of the first cascaded module.

23. The scanning circuit according to claim 22, characterized in that, The third output module includes a fourteenth transistor, wherein the first electrode of the fourteenth transistor receives the first fixed potential signal, the second electrode is electrically connected to the output terminal of the first scan signal output module, and the gate is electrically connected to the output terminal of the first cascaded module. The fourth output module includes a fifteenth transistor, the first terminal of which receives the second clock signal, the second terminal of which is electrically connected to the output terminal of the first scan signal output module, and the gate of which is coupled to the seventh node; The fifth output module includes a sixteenth transistor, wherein the first electrode of the sixteenth transistor receives the first fixed potential signal, the second electrode is electrically connected to the output terminal of the second scan signal output module, and the gate is electrically connected to the output terminal of the first cascaded module. The sixth output module includes a seventeenth transistor, the first terminal of which receives the third clock signal, the second terminal of which is electrically connected to the output terminal of the second scan signal output module, and the gate of which is coupled to the seventh node; The second input module includes an eighteenth transistor, wherein the first terminal of the eighteenth transistor receives the second trigger signal, the second terminal is electrically connected to the seventh node, and the gate receives the first clock signal; The second voltage regulator module includes a second voltage regulator transistor, wherein the first terminal of the second voltage regulator transistor receives the first fixed potential signal, the second terminal is electrically connected to the seventh node, and the gate is electrically connected to the output terminal of the first cascaded module; The fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, and the second Zener transistor all have the same channel type.

24. The scanning circuit according to claim 22, characterized in that, The seventh node includes a third coupling transistor between its control terminal and the fourth output module, and the seventh node includes a fourth coupling transistor between its control terminal and the sixth output module. The gates of the third coupling transistor and the fourth coupling transistor both receive the second fixed potential signal. The third coupling transistor and the fourth coupling transistor have the same channel type.

25. The scanning circuit according to claim 22, characterized in that, The first shift register unit further includes a sixth capacitor and a seventh capacitor. One plate of the sixth capacitor is electrically connected to the control terminal of the fourth output module, and the other plate is electrically connected to the output terminal of the first scan signal output module. One plate of the seventh capacitor is electrically connected to the output terminal of the second scan signal output module, and the other plate is electrically connected to the control terminal of the sixth output module.

26. The scanning circuit according to claim 2 or 11, characterized in that, The scanning circuit also includes multiple cascaded second shift register units. Each second shift register unit includes a second input module and a second type of signal output module. The second input module is used to receive a second trigger signal, and the output terminal of the second type of signal module is used to output a second type of scanning signal. The output terminal of the second input module is electrically connected to a seventh node, and the seventh node is coupled to a portion of the control terminal of the second type of scanning signal module. The second shift register unit also includes a second voltage regulator module, the output of which is electrically connected to the seventh node.

27. The scanning circuit according to claim 26, characterized in that, The control terminal of the second input module receives a first clock signal, and the second type of signal output module includes a first scan signal output module and a second scan signal output module; The first scan signal output module includes a third output module and a fourth output module. The input terminal of the third output module receives a first fixed potential signal, the output terminal is electrically connected to the output terminal of the first scan signal output module, and the control terminal is electrically connected to the eighth node. The input terminal of the fourth output module receives a second clock signal, the output terminal is electrically connected to the output terminal of the first scan signal output module, and the control terminal is coupled to the seventh node. The second scan signal output module includes a fifth output module and a sixth output module. The input terminal of the fifth output module receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the second scan signal output module, and the control terminal is electrically connected to the eighth node. The input terminal of the sixth output module receives the third clock signal, the output terminal is electrically connected to the output terminal of the second scan signal output module, and the control terminal is coupled to the seventh node N7. The second shift register unit also includes a second control module, the output of which is electrically connected to the eighth node and the second voltage regulator module.

28. The scanning circuit according to claim 27, characterized in that, The third output module includes a fourteenth transistor, the first terminal of which receives the first fixed potential signal, the second terminal of which is electrically connected to the output terminal of the first scan signal output module, and the gate of which is electrically connected to the eighth node; The fourth output module includes a fifteenth transistor, the first terminal of which receives the second clock signal, the second terminal of which is electrically connected to the output terminal of the first scan signal output module, and the gate of which is coupled to the seventh node; The fifth output module includes a sixteenth transistor, the first electrode of which receives the first fixed potential signal, the second electrode of which is electrically connected to the output terminal of the second scan signal output module, and the gate of which is electrically connected to the eighth node; The sixth output module includes a seventeenth transistor, the first terminal of which receives the third clock signal, the second terminal of which is electrically connected to the output terminal of the second scan signal output module, and the gate of which is coupled to the seventh node; The second input module includes an eighteenth transistor, wherein the first terminal of the eighteenth transistor receives the second trigger signal, the second terminal is electrically connected to the seventh node, and the gate receives the first clock signal; The fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor have the same channel type.

29. The scanning circuit according to claim 27, characterized in that, The second control module includes a nineteenth transistor and a twentieth transistor. The first terminal of the nineteenth transistor receives a first clock signal, the second terminal is electrically connected to the eighth node, and the gate is electrically connected to the seventh node. The first terminal of the twentieth transistor receives a second fixed potential signal, the second terminal is electrically connected to the eighth node, and the gate receives the first clock signal. The second voltage regulator module includes a second voltage regulator transistor, a third voltage regulator transistor, and a fourth voltage regulator transistor. The first terminal of the second voltage regulator transistor receives the first fixed potential signal, the second terminal is electrically connected to the ninth node, and the gate is electrically connected to the eighth node. The first terminal of the third voltage regulator transistor is electrically connected to the ninth node, the second terminal is electrically connected to the seventh node, and the gate receives the second clock signal. The first terminal of the fourth voltage regulator transistor is electrically connected to the ninth node, the second terminal is electrically connected to the seventh node, and the gate receives the third clock signal. The nineteenth transistor, the twentieth transistor, the second Zener transistor, the third Zener transistor, and the fourth Zener transistor have the same channel type.

30. The scanning circuit according to claim 27, characterized in that, The second control module includes a nineteenth transistor and a twentieth transistor with different channel types. The first terminal of the nineteenth transistor receives the first fixed potential signal, the second terminal is electrically connected to the eighth node, and the gate is electrically connected to the seventh node. The first terminal of the twentieth transistor receives the second fixed potential signal, the second terminal is electrically connected to the eighth node, and the gate is electrically connected to the seventh node. The second voltage regulator module includes a second voltage regulator transistor and a third voltage regulator transistor with different channel types. The first terminal of the second voltage regulator transistor receives the first fixed potential signal, the second terminal is electrically connected to the seventh node, and the gate is electrically connected to the eighth node. The first terminal of the third voltage regulator transistor receives the second fixed potential signal, the second terminal is electrically connected to the seventh node, and the gate is electrically connected to the eighth node. The nineteenth transistor has the same channel type as the second Zener transistor, and the twentieth transistor has the same channel type as the third Zener transistor.

31. The scanning circuit according to claim 27, characterized in that, In the first shift register unit of the odd-numbered rows, the control terminal of the first input module is electrically connected to the first clock signal line; in the first shift register unit of the even-numbered rows, the control terminal of the first input module is electrically connected to the third clock signal line. In the second shift register unit of the odd row, the control terminal of the second input module is electrically connected to the first clock signal line, the input terminal of the fourth output module is electrically connected to the second clock signal line, and the output terminal of the sixth output module is electrically connected to the third clock signal line. In the second shift register unit of the even-numbered row, the control terminal of the second input module is electrically connected to the third clock signal line, the input terminal of the fourth output module is electrically connected to the fourth clock signal line, and the output terminal of the sixth output module is electrically connected to the first clock signal line.

32. The scanning circuit according to claim 27, characterized in that, In the first shift register unit of the odd-numbered rows, the control terminal of the first input module is electrically connected to the first clock signal line; in the first shift register unit of the even-numbered rows, the control terminal of the first input module is electrically connected to the third clock signal line. In the second shift register unit of the odd-numbered row, the control terminal of the second input module is electrically connected to the second clock signal line, the input terminal of the fourth output module is electrically connected to the third clock signal line, and the output terminal of the sixth output module is electrically connected to the fourth clock signal line. In the second shift register unit of the even-numbered row, the control terminal of the second input module is electrically connected to the fourth clock signal line, the input terminal of the fourth output module is electrically connected to the first clock signal line, and the output terminal of the sixth output module is electrically connected to the second clock signal line.

33. The scanning circuit according to claim 15, characterized in that, In the first shift register unit of the odd-numbered row, the control terminal of the first input module is electrically connected to the first clock signal line, and the second input terminal of the auxiliary voltage regulator module is electrically connected to the second clock signal line. In the even-numbered first shift register unit, the control terminal of the first input module is electrically connected to the third clock signal line, and the second input terminal of the auxiliary voltage regulator module is electrically connected to the fourth clock signal line.

34. The scanning circuit according to claim 15, characterized in that, In the first shift register unit of the odd row, the control terminal of the first input module is electrically connected to the first clock signal line, and the second input terminal of the auxiliary voltage regulator module is electrically connected to the third clock signal line or the fourth clock signal line. In the first shift register unit of the even-numbered row, the control terminal of the first input module is electrically connected to the third clock signal line, and the second input terminal of the auxiliary voltage regulator module is electrically connected to the first clock signal line or the second clock signal line.

35. A display panel, characterized in that, Includes the scanning circuit as described in any one of claims 1-34.

36. A display device, characterized in that, Includes the display panel as described in claim 35.

Images