Functional substrate and manufacturing method therefor

Abstract

The present application is applicable to the technical field of circuit boards. Provided are a functional substrate and a manufacturing method therefor. The functional substrate comprises: a target electric chip, wherein a side surface of the target electric chip is provided with a plurality of groups of pins; and a bypass capacitor board, which is disposed on the side of the target electric chip that is provided with the plurality of groups of pins, wherein a plurality of groups of bypass capacitors are embedded inside the bypass capacitor board, and each group of bypass capacitors is correspondingly connected to the plurality of groups of pins of the target electric chip by means of first pads on the surface of the bypass capacitor board. By means of the structure, the bypass capacitors and the target electric chip are packaged together, so as to release a layout space on a main board and increase the layout density of the main board.

Description

A functional substrate and its fabrication method

[0001] Cross-referencing of related applications

[0002] This application claims priority to Chinese Patent Application No. 2025103595322, filed on March 24, 2025, the entire contents of which are incorporated herein by reference.

[0003] [Technical Field]

[0004] This application relates to the field of circuit board technology, and in particular to a functional substrate and its manufacturing method.

[0005] [Background Technology]

[0006] Large-scale processing chips typically have numerous power supply pins, requiring bypass capacitors to be placed nearby. Bypass capacitors, also known as filter capacitors, are placed near the input pins of the power-consuming chip to filter out high-frequency harmonics in the IC's power supply and reduce interference from power supply noise. Bypass capacitors are generally small-package, small-value capacitors.

[0007] In existing technologies, most bypass capacitors and the target power chip are placed on opposite sides of the PCB motherboard, with power supply running laterally from the inner layer of the PCB motherboard to the vias on the chip's underside. This results in the target power chip occupying a large portion of the PCB motherboard's layout space, affecting the motherboard's integration density, and also leads to a longer power supply path for the target power chip, requiring consideration of voltage drop issues.

[0008] [Summary of the Invention]

[0009] The main technical problem addressed by this application is to provide a functional substrate and its manufacturing method, so as to free up layout space on the motherboard and increase the layout density of the motherboard.

[0010] This application provides a functional substrate, wherein the functional substrate includes: a target power chip, wherein a plurality of pins are disposed on one side surface of the target power chip; and a bypass capacitor plate disposed on the side of the target power chip where the plurality of pins are disposed, wherein a plurality of bypass capacitors are embedded inside the bypass capacitor plate at positions corresponding to the plurality of pins, and each of the bypass capacitors is electrically connected to the plurality of pins of the target power chip through a first pad on the surface of the bypass capacitor plate.

[0011] The bypass capacitor plate has a second pad on the side of the plate away from the target power chip. The number of the second pads is the same as the number of pins on the target power chip. The position of the second pad is the same as the position of the pins on the target power chip.

[0012] The pins include power pins and general-purpose pins. The bypass capacitor is provided corresponding to the power pin and is electrically connected to the power pin through a first pad.

[0013] The bypass capacitor board also includes multiple through holes, which are provided corresponding to and electrically connected to the ordinary pins.

[0014] The length of each group of bypass capacitors is the same as the spacing between each group of pins, and the width of each group of bypass capacitors is smaller than the spacing between two adjacent groups of pins.

[0015] This application also provides a method for fabricating a functional substrate, wherein the method includes: providing a target power chip; wherein a plurality of pins are disposed on one side surface of the target power chip; fabricating a bypass capacitor board according to the pins on the target power chip; wherein a plurality of bypass capacitors are embedded inside the bypass capacitor board, and a plurality of first pads are disposed on the side surface of the bypass capacitor board near the target power chip; and soldering the pins on the surface of the target power chip one by one to the first pads on the surface of the bypass capacitor board to form a functional substrate.

[0016] The step of soldering the pins of the target power chip to the first pad on the surface of the bypass capacitor board to form a functional substrate further includes: forming solder balls on the side of the bypass capacitor board away from the target power chip to form a second pad.

[0017] The number of the second pads is the same as the number of pins on the surface of the target power chip, and the position of the second pads is the same as the position of the pins on the surface of the target power chip.

[0018] The pins include power pins and general-purpose pins; the step of fabricating a bypass capacitor board based on the pins on the target power chip includes: providing a board; embedding bypass capacitors on the board at positions corresponding to each group of power pins, so that each group of bypass capacitors is set corresponding to each group of power pins; and fabricating a first pad on the surface of the board near the target power chip.

[0019] The step of embedding bypass capacitors at positions corresponding to each group of power supply pins on the board, so that each group of bypass capacitors is set to correspond to each group of power supply pins, further includes: drilling through holes at positions corresponding to the ordinary pins on the board, so that the through holes are set to correspond to the ordinary pins.

[0020] The beneficial effects of this application are: by integrating the bypass capacitor and the target power chip on a functional substrate, and making the arrangement of the external pins on the functional substrate consistent with the pin arrangement of the original target power chip, the layout space of the target power chip and bypass capacitor directly applied on the PCB motherboard can be reduced, thereby improving the layout density of the PCB motherboard.

[0021] [Attached Image Description]

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a structural schematic diagram of an embodiment of the functional substrate provided in this application;

[0024] Figure 2 is a top view of a specific embodiment of the functional substrate provided in this application;

[0025] Figure 3 is a flowchart illustrating a specific embodiment of the method for manufacturing a functional substrate provided in this application;

[0026] Figure 4 is a structural schematic diagram of a specific embodiment of the target power chip provided in this application;

[0027] Figure 5 is a structural schematic diagram of a specific embodiment of the bypass capacitor board provided in this application;

[0028] Figure 6 is a flowchart of a specific embodiment of step S12 in Figure 3;

[0029] Figure 7 is a structural schematic diagram of an application scenario of the functional substrate provided in this application.

[0030]

Detailed Implementation Methods

[0031] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0032] In the following description, for illustrative purposes and not for limitation, the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0034] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0035] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0037] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0038] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] This application provides a functional substrate. Please refer to FIG1 for details. FIG1 is a schematic diagram of the structure of an embodiment of the functional substrate provided in this application. As shown in FIG1, the functional substrate includes: a target power chip 10 and a bypass capacitor board 20.

[0040] The target power chip 10 has multiple sets of pins 101 on one side surface. Specifically, the target power chip 10 has multiple pins 101 on its surface, with each pair of pins 101 forming a group. One pin is grounded and used as the negative terminal of the power supply, while the other pin is used as the positive terminal of the power supply.

[0041] A bypass capacitor board 20 is disposed on one side of the target power chip 10, which has multiple sets of pins 101. The bypass capacitor board 20 contains multiple sets of bypass capacitors 201 embedded at positions corresponding to the multiple sets of pins 101. Each set of bypass capacitors 201 is electrically connected to the multiple sets of pins 101 of the target power chip 10 through a first pad 211 on the surface of the bypass capacitor board 20.

[0042] The bypass capacitor plate 20 has multiple first pads 211 on the side surface close to the target power chip 10, and multiple second pads 212 on the side surface away from the target power chip 10.

[0043] Preferably, the number of second pads 212 is the same as the number of pins 101 on the target power chip 10, and the setting position of the second pads 212 is the same as the setting position of the pins 101 on the target power chip 10, so that the formed functional substrate has the same pin definition as the original target power chip 10. It should be noted that the setting position of the second pads 212 being the same as the setting position of the pins 101 on the target power chip 10 means that the position of the second pads 212 corresponds one-to-one with the position of the pins 101, so as not to change the number and setting position of the pins 101 on the target power chip 10, that is, to maintain the original pin definition. In other embodiments, the position and number may be different, which is not limited here. In this embodiment, by setting the second pads 212 corresponding to the pins 101, the pins 101 and the second pads 212 have the shortest power supply path, thereby shortening the power supply path between the functional substrate and the PCB motherboard and reducing the power supply voltage drop.

[0044] The target power chip 10 has pins 101, including power pins and general-purpose pins (unlabeled). A bypass capacitor 201 is positioned corresponding to the power pin, and the bypass capacitor 201 inside the bypass capacitor plate 20 is electrically connected to the power pin via the first pad 211. In other words, the bypass capacitor 201 is positioned directly below the vertical projection surface of the power pin.

[0045] The bypass capacitor board 20 is also provided with multiple through holes 202, which are corresponding to the ordinary pins and are electrically connected to the ordinary pins. That is, the through holes 202 are located directly below the vertical projection surface of the ordinary pins.

[0046] Preferably, the second pad 212 consists of solder balls disposed on the side of the bypass capacitor plate 20 facing away from the target power chip 10. The number of solder balls has the same pin definition (same number and position) as the pins 101 on the target power chip 10. The number of the second pad 212 includes the sum of the number of solder balls disposed on the surface of the bypass capacitor 201 and the number of solder balls disposed on the surface of the via 202.

[0047] Preferably, the length L of the bypass capacitor 201 is the same as the spacing between each group of pins 101. Please further refer to Figure 2, which is a top view of a specific embodiment of the functional substrate provided in this application. As shown in Figure 2, preferably, the width W of the bypass capacitor 201 is smaller than the spacing between two adjacent groups of pins. Wherein, length L is the orientation of the two pins 101 in the same group, and width W is the vertical direction of length L. From the top view, the pins 101 on the target power chip 10 are arranged in a matrix. The length L of each group of bypass capacitors 201 is the same as the spacing between each group of pins 101, so that the bypass capacitor 201 is located directly below each group of pins 101. Preferably, the width W of each group of bypass capacitors 201 is smaller than the spacing between two adjacent groups of pins 101. Specifically, the width W of each group of bypass capacitors 201 is smaller than the spacing between two adjacent groups of pins 101 in the width direction. Preferably, the width W of each group of bypass capacitors 201 is less than half the distance between two adjacent groups of pins 101 in the width direction, so that the two adjacent groups of bypass capacitors 201 are spaced apart to avoid series interference between the two adjacent groups of bypass capacitors 201.

[0048] In one specific embodiment, the bypass capacitor board 20 is a PCB board, and multiple sets of bypass capacitors 201 are embedded in the PCB board at positions corresponding to multiple sets of pins 101 to form the bypass capacitor board 20. In one specific embodiment, the fabrication of the bypass capacitor board 20 includes: first, opening a window in the PCB board to accommodate the bypass capacitors 201, then covering it with a cover plate, and setting pads on the surface of the PCB board, thereby forming the bypass capacitor board 20 with multiple sets of bypass capacitors 201 embedded. No specific limitations are made here.

[0049] This application also provides a method for fabricating a functional substrate. Please refer to Figure 3 for details. Figure 3 is a flowchart illustrating a specific embodiment of the method for fabricating a functional substrate provided in this application. As shown in Figure 3, the method for fabricating a functional substrate includes:

[0050] Step S11: Provide a target power chip.

[0051] Please refer to Figure 4 for details. Figure 4 is a schematic diagram of a specific embodiment of the target power chip provided in this application. The target power chip has multiple sets of pins on one side surface, with each set consisting of two pins; this is not limited to a single set. The target power chip includes power supply pins for providing power signals.

[0052] Step S12: Fabricate a bypass capacitor board based on the pins on the target power chip.

[0053] Please refer to Figure 5 for details. Figure 5 is a schematic diagram of a specific embodiment of the bypass capacitor board provided in this application. As shown in Figure 5, multiple sets of bypass capacitors 201 are embedded inside the bypass capacitor board, and multiple sets of first pads 211 are provided on the surface of the bypass capacitor board near the target power chip. Further, multiple sets of second pads 212 are also provided on the surface of the bypass capacitor board away from the target power chip. The second pads 212 can be solder balls on the surface of the bypass capacitor board. The second pads 212 are set according to the pins on the surface of the target power chip. Preferably, the number of second pads 212 is the same as the number of pins on the surface of the target power chip. Preferably, the setting position of the second pads 212 is also the same as the setting position of the pins on the surface of the target power chip.

[0054] More preferably, the location of the bypass capacitors in the bypass capacitor board is also designed according to the pins on the surface of the target power chip. The pins on the surface of the target power chip include power pins and general-purpose pins. The power pins require the placement of bypass capacitors.

[0055] In one specific embodiment, please further refer to Figure 6, which is a flowchart illustrating a specific embodiment of step S12 in Figure 3. As shown in Figure 6, step S12 specifically includes:

[0056] Step S21: Provide a board.

[0057] The board can be a PCB board or other circuit boards.

[0058] Step S22: Bury bypass capacitors on the board at positions corresponding to each group of power supply pins, so that each group of bypass capacitors is set to correspond to each group of power supply pins.

[0059] Specifically, the bypass capacitor should be positioned directly below the power supply pin after assembly and soldering.

[0060] This step specifically includes: embedding bypass capacitors into the board using ECP technology. ECP (Embedded Chip Package) refers to embedding chips / resistors / capacitors into a substrate / PCB board, using copper-plated vias for vertical interconnection to form a single package. Specifically, this involves: embedding the bypass capacitors into the PCB board at the desired locations, and then bringing out the bypass capacitor pads on the top and bottom sides using laser-drilled holes.

[0061] In one specific embodiment, the method includes: opening a window in the board to place multiple bypass capacitors, then covering the surface of the bypass capacitors with a cover plate, and then opening a hole on the surface of the cover plate corresponding to the position of the bypass capacitor, with the hole filled with conductive metal.

[0062] In a further specific embodiment, step S22 further includes: drilling through holes at positions on the board corresponding to ordinary pins, so that the through holes are set in correspondence with ordinary pins.

[0063] Step S23: Create the first pad on the side of the board closest to the target power chip.

[0064] Preferably, the first pad is provided corresponding to multiple pins (the number and location are the same).

[0065] The first pad includes a metal layer on the surface of the through-hole and a metal layer on the surface of the bypass capacitor to achieve circuit connection.

[0066] Step S13: Solder the pins of the target power chip one by one to the first pad on the surface of the bypass capacitor board to form a functional substrate.

[0067] The pins on the surface of the target power chip are soldered together with the first pad to form a whole. Furthermore, the formed functional substrate also has pins in the same direction as the target power chip. These pins are the second pads on the bypass capacitor board, and these pins (the second pads) have the same pin definitions (the number and placement are the same) as the pins on the target power chip.

[0068] In one specific embodiment, after step S13: a second pad corresponding to the pins is formed on the surface of the bypass capacitor plate opposite to the target power chip. Specifically, a second pad corresponding to the pins on the surface of the target power chip is formed. In other embodiments, the formation of the second pad may also be after step S23 in step S12, which is not limited here. This step specifically includes: drilling a hole on the back of the bypass capacitor to expose the bypass capacitor, and filling the hole with a metal layer to form a conductive pad. Then, solder balls are formed on the surface of the conductive pad and the surface of the through hole to obtain the second pad.

[0069] Preferably, the second pad has the same number and position as the pins on the surface of the target power chip.

[0070] The second pad includes solder balls fabricated on the surface of the bypass capacitor board, so that the second pad protrudes from the surface of the bypass capacitor board (functional substrate) for easy subsequent application.

[0071] The second pad is electrically connected to the power supply pin (power pin) on the target power chip through the bypass capacitor in the bypass capacitor board, and is also electrically connected to the ordinary pin on the target power chip through the through hole in the bypass capacitor board.

[0072] This application also provides an application device for a functional substrate, as shown in Figure 7, which is a structural schematic diagram of an application scenario of the functional substrate provided in this application. As shown in Figure 7, the functional substrate can be directly mounted on the PCB motherboard, thereby reducing the space occupied on the PCB motherboard surface and increasing the layout density of the PCB motherboard surface. At the same time, power devices and other devices can be mounted on the back of the PCB motherboard, thereby greatly shortening the power supply path of the target power chip and improving the system integration.

[0073] The beneficial effect of this embodiment is that by integrating the bypass capacitor and the target power chip on a functional substrate, and making the arrangement of the external pins on the functional substrate consistent with the pin arrangement of the original target power chip, the layout space of the target power chip and bypass capacitor directly applied on the PCB motherboard can be reduced, thereby improving the layout density of the PCB motherboard.

[0074] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the description and drawings of this application, or simple reorganizations of method steps, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A functional substrate, wherein, The functional substrate includes: The target power chip has multiple sets of pins on one side surface; A bypass capacitor board is disposed on one side of the target power chip having multiple sets of pins. Multiple sets of bypass capacitors are embedded inside the bypass capacitor board at positions corresponding to the multiple sets of pins. Each set of bypass capacitors is electrically connected to the multiple sets of pins of the target power chip through a first pad on the surface of the bypass capacitor board.

2. The functional substrate according to claim 1, wherein, Each pair of pins forms a group, with one pin being the negative power supply and the other pin being the positive power supply.

3. The functional substrate according to claim 1, wherein, The first pad is disposed on the side surface of the bypass capacitor plate near the target power chip.

4. The functional substrate according to claim 1, wherein, The bypass capacitor plate has a second pad on the side of the surface away from the target power chip, and the number of the second pad is the same as the number of pins on the target power chip.

5. The functional substrate according to claim 4, wherein, The second pad is positioned in the same location as the pins of the target power chip.

6. The functional substrate according to claim 1, wherein, The pins include power pins and general-purpose pins. The bypass capacitor is provided corresponding to the power pin and is electrically connected to the power pin through a first pad.

7. The functional substrate according to claim 6, wherein, The bypass capacitor board also includes multiple through holes, which are provided corresponding to the ordinary pins and are electrically connected to the ordinary pins.

8. The functional substrate according to claim 7, wherein, The number of the second pads is the sum of the number of solder balls provided on the surface of the bypass capacitor and the number of solder balls provided on the surface of the via.

9. The functional substrate according to claim 7, wherein, The length of each group of bypass capacitors is the same as the spacing between each group of pins.

10. The functional substrate according to claim 9, wherein, The width of each group of bypass capacitors is smaller than the spacing between the pins of two adjacent groups.

11. A method for fabricating a functional substrate, wherein, The manufacturing method includes: A target power chip is provided; wherein, one side surface of the target power chip is provided with multiple sets of pins; A bypass capacitor board is fabricated based on the pins on the target power chip; wherein, multiple sets of bypass capacitors are embedded inside the bypass capacitor board, and multiple sets of first pads are provided on the surface of the bypass capacitor board near the target power chip. The pins on the surface of the target power chip are soldered one by one to the first pad on the surface of the bypass capacitor board to form a functional substrate.

12. The method for manufacturing a functional substrate according to claim 11, wherein, After the step of soldering the pins on the surface of the target power chip to the first pad on the surface of the bypass capacitor board to form a functional substrate, the method further includes: Solder balls are formed on the side of the bypass capacitor plate opposite to the target power chip to form a second solder pad.

13. The method for manufacturing a functional substrate according to claim 12, wherein, The number of the second pads is the same as the number of pins on the surface of the target power chip.

14. The method for manufacturing a functional substrate according to claim 13, wherein, The second pad is positioned in the same location as the pins on the surface of the target power chip.

15. The method for manufacturing a functional substrate according to claim 13, wherein, The pins include power pins and general-purpose pins; The step of fabricating a bypass capacitor board based on the pins on the target power chip includes: Provide a board component; Bypass capacitors are embedded on the board at positions corresponding to each group of power pins, so that each group of bypass capacitors is set to correspond to each group of power pins; A first pad is formed on the surface of the board near the target power chip.

16. The method for manufacturing a functional substrate according to claim 15, wherein, The step of fabricating a bypass capacitor board based on the pins on the target power chip includes: Bypass capacitors are embedded in the board using the ECP process.

17. The method for manufacturing a functional substrate according to claim 15, wherein, The step of embedding bypass capacitors at positions corresponding to each group of power pins on the board, so that each group of bypass capacitors corresponds to each group of power pins, further includes: Through holes are drilled at positions on the board corresponding to the ordinary pins, so that the through holes are set in a manner corresponding to the ordinary pins.

18. The method for manufacturing a functional substrate according to claim 15, wherein, The step of embedding bypass capacitors at positions corresponding to each group of power pins on the board, so that each group of bypass capacitors corresponds to each group of power pins, further includes: A window is made in the plate to accommodate multiple bypass capacitors; Cover plate on the surface of the bypass capacitor; A hole is made on the surface of the cover plate at the position corresponding to the bypass capacitor; A through hole is formed by filling the hole with conductive metal.

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