Sequence processing method, first communication node, second communication node, storage medium and program product

Abstract

The present application provides a sequence processing method, a first communication node, a second communication node, a storage medium, and a program product. The sequence processing method comprises: determining a signal sequence, the signal sequence being a complex-valued sequence, elements in the signal sequence having identical modulus values, a phase difference between any two adjacent elements in the signal sequence being qπ / 4, q being an integer greater than 2, and the phase difference being the value of the angle between the phases of any two adjacent elements in the signal sequence (S110); and transmitting the signal sequence (S120).

Description

Sequence processing method, first communication node, second communication node, storage medium and program product Technical Field

[0001] This application relates to the field of communication technology, such as sequence processing methods, first communication nodes, second communication nodes, storage media, and program products. Background Technology

[0002] In high-frequency scenarios, path loss and shadow fading are significant, resulting in very low signal-to-noise ratios (SNR) in some areas at the cell edge. Furthermore, amplifier efficiency is relatively low at high frequencies. To improve the SNR while conserving power in the user equipment (UE) battery, a low peak-to-average power ratio (PAPR) is required for the UE's transmitted signal.

[0003] Currently, in order to transmit signals with lower PAPR, waveforms that can reduce PAPR are usually selected. However, the PAPR of the reference signal sequence is still relatively high. Summary of the Invention

[0004] This application provides a sequence processing method, a first communication node, a second communication node, a storage medium, and a program product, which reduces the PAPR of the reference signal sequence.

[0005] In a first aspect, embodiments of this application provide a sequence processing method, including:

[0006] A signal sequence is defined, wherein the signal sequence is a complex sequence, the elements in the signal sequence have the same modulus, the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2, and the phase difference is the angle between the phases of any two adjacent elements in the signal sequence.

[0007] Transmit the signal sequence.

[0008] Secondly, embodiments of this application provide a sequence processing method, including:

[0009] Obtain a signal sequence that has passed through a channel. The signal sequence is a complex sequence in which the elements have the same magnitude. The phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2. The phase difference is the angle between the phases of any two adjacent elements in the signal sequence.

[0010] Channel estimation is performed based on the acquired signal sequence and the locally stored signal sequence.

[0011] Thirdly, embodiments of this application provide a first communication node, including:

[0012] One or more processors;

[0013] Storage device for storing one or more programs;

[0014] When the one or more programs are executed by the one or more processors, the one or more processors implement the sequence processing method provided in the first aspect of the present application.

[0015] Fourthly, embodiments of this application provide a second communication node, including:

[0016] One or more processors;

[0017] Storage device for storing one or more programs;

[0018] When the one or more programs are executed by the one or more processors, the one or more processors implement the sequence processing method provided in the second aspect of the present application.

[0019] Fifthly, embodiments of this application provide a storage medium storing a computer program, which, when executed by a processor, implements the sequence processing method provided in embodiments of this application.

[0020] Sixthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the sequence processing method provided in embodiments of this application.

[0021] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0022] Figure 1 is a schematic flowchart of a sequence processing method provided in an embodiment of this application;

[0023] Figure 2 is a flowchart illustrating another sequence processing method provided in an embodiment of this application;

[0024] Figure 3 is an example diagram of generating a reference signal sequence provided in an embodiment of this application;

[0025] Figure 4 is a schematic diagram of another process for generating a reference signal sequence provided in an embodiment of this application;

[0026] Figure 5 is a schematic diagram of the transmission process of a reference signal sequence provided in an embodiment of this application;

[0027] Figure 6 is a schematic diagram of the power characteristics of a Fourier transform reference signal sequence provided in an embodiment of this application;

[0028] Figure 7 is a schematic diagram of a sequence processing device provided in an embodiment of this application;

[0029] Figure 8 is a schematic diagram of another sequence processing device provided in an embodiment of this application;

[0030] Figure 9 is a schematic diagram of the structure of a first communication node provided in an embodiment of this application;

[0031] Figure 10 is a schematic diagram of the structure of a second communication node provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0033] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0034] In this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0035] To transmit signals with lower PAPR, Discrete Fourier Transform-spread Orthogonal Frequency Division Multiplexing (DFT-s-OFDM) waveforms are typically used. Because the data is mapped in the time domain, the PAPR is lower than that of Cyclic Prefix-Orthogonal Frequency Division Multiplexing (CP-OFDM). The reference signal is usually a Zadoff-Chu (ZC) sequence or a π / 2 binary phase shift keying (BPSK) sequence, which can further reduce PAPR. However, the PAPR of ZC or π / 2 BPSK sequences is still relatively high. Other sequences can be selected to achieve even lower PAPR, meeting the application scenarios requiring lower PAPR, especially when the reference signal overhead is large. Therefore, this application proposes a signal sequence with lower PAPR.

[0036] In one exemplary embodiment, FIG1 is a schematic flowchart of a sequence processing method provided in an embodiment of this application. The sequence processing method is suitable for reducing the PAPR of a signal sequence. This method can be executed by a sequence processing device, which can be implemented in software and / or hardware and integrated on a first communication node. The first communication node encompasses any suitable type of communication node transmitting a signal sequence, such as a communication node transmitting a reference signal sequence.

[0037] As shown in Figure 1, the sequence processing method provided in this embodiment includes the following steps:

[0038] S110, Determine the signal sequence.

[0039] The signal sequence is a complex sequence, in which the elements have the same modulus, and the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2. The phase difference is the angle between the phases of any two adjacent elements in the signal sequence.

[0040] The signal sequence d(i) (i = 0, 1, 2, ..., I-1) is a complex sequence in which all elements have the same magnitude, and the phase difference between any two adjacent elements is qπ / 4. Here, I is the number of elements in the signal sequence d(i). q is an integer greater than 2, such as 3, 4, 5, 6, 7, or 8. When q is greater than 8, qπ / 4 can be converted to the range [0, 2π].

[0041] In one example, the phase difference between the first element d(0) and the last element d(I-1) of the signal sequence is qπ / 4. The phase difference qπ / 4 is greater than π / 2, i.e., q>2.

[0042] In one example, the phase difference qπ / 4 between any two adjacent elements in the signal sequence is 3π / 4, i.e., q = 3. Since the phase difference between any two adjacent elements in the signal sequence is equal to 3π / 4, compared to the π / 2 BPSK sequence, this sequence, after DFT-s-OFDM waveform processing, has a smaller phase difference between adjacent elements, which can further reduce the peak-to-average power ratio (PAPR) of the reference signal.

[0043] A complex sequence can be a sequence composed of complex numbers. A signal sequence in which all elements have the same modulus is called an equal-modulus complex sequence. The modulus of elements in a signal sequence can be 1, which facilitates power normalization.

[0044] In one embodiment, the signal sequence includes a sequence from a reference signal sequence or a guard interval sequence.

[0045] In this embodiment, the signal sequence d(i) can be used as a reference signal sequence, such as a demodulation reference signal (DMRS), a phase tracking reference signal (PTRS), a sounding reference signal (SRS), etc., or it can be used as some known sequence, such as a guard interval (GI) sequence.

[0046] S120, Transmit the signal sequence.

[0047] This operation can transmit the signal sequence to the second communication node for channel estimation.

[0048] The sequence processing method provided in this application reduces the PAPR (Phase Approval Rate) by ensuring that the elements within the transmitted signal sequence have the same magnitude. For example, it can reduce the PAPR of the signal after oversampling the reference signal in DFT-s-OFDM. The phase difference between any two adjacent elements in the signal sequence is qπ / 4, which is smaller than that of Quadrature Phase Shift Keying (QPSK) sequences, further reducing the PAPR of the signal sequence.

[0049] Based on the above embodiments, modified embodiments of the above embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in the modified embodiments.

[0050] In one embodiment, the phase difference between the first and last elements of the signal sequence is qπ / 4, where q is an integer greater than 2.

[0051] In one embodiment, the phase difference between the first and last elements of the signal sequence is 3π / 4.

[0052] The phase difference between the first element d(0) and the last element d(I-1) in a signal sequence is equal to 3π / 4, which allows the sequence to be connected end-to-end, resulting in a lower peak-to-average power ratio (PAPR) after oversampling. The phase difference between the first and last elements in a signal sequence can be represented by the angle between their phases.

[0053] In one embodiment, the phase difference between any two adjacent elements in the signal sequence is 3π / 4.

[0054] In one embodiment, the signal sequence satisfies one of the following:

[0055] The number of elements contained in the signal sequence is even;

[0056] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the odd-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the even-numbered bit sequence is 0 or π / 2.

[0057] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the even-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the odd-numbered bit sequence is 0 or π / 2.

[0058] The first element in the signal sequence is formed by the last element in the signal sequence and the second element in the signal sequence;

[0059] The last element in the signal sequence is formed by the second-to-last element and the first element in the signal sequence;

[0060] The signal sequence is a sequence from the reference signal sequence or the guard interval sequence;

[0061] The odd-numbered positions in the signal sequence are a preset sequence;

[0062] The even-numbered positions in the signal sequence are a preset sequence.

[0063] The number of elements in the signal sequence d(i) (i = 0, 1, 2, ..., I-1) is even, i.e., I is even.

[0064] The signal sequence can be decomposed into an odd-numbered position sequence d(i) (i = 0, 2, 4, ..., I-2) (where i = 0 can be regarded as the first element in the signal sequence, i = 2 is the third element in the signal sequence, and so on) and an even-numbered position sequence d(i) (i = 1, 3, 5, ..., I-1) (where i = 1 can be regarded as the second element in the signal sequence, i = 3 is the fourth element in the signal sequence, and so on).

[0065] In one example, the phase difference between any two adjacent elements in an odd-numbered position sequence is π / 2. The phase difference between any two adjacent elements in an even-numbered position sequence is 0 or π / 2. The odd-numbered position sequence can be a π / 2 BPSK sequence or a QPSK sequence, and the even-numbered position sequence can be a π / 4 QPSK sequence.

[0066] In one example, the phase difference between any two adjacent elements in the even-numbered position sequence is π / 2, and the phase difference between any two adjacent elements in the odd-numbered position sequence is 0 or π / 2. The even-numbered position sequence can be a π / 2 BPSK sequence or a QPSK sequence, and the odd-numbered position sequence can be a π / 4 QPSK sequence.

[0067] Elements in a signal sequence can be generated from the remaining elements in the signal sequence. For example, the last element d(I-1) in the signal sequence d(i) is formed by the second-to-last element d(I-2) and the first element d(0) in the signal sequence d(i). The first element d(0) in the signal sequence d(i) is formed by the last element d(I-1) and the second element d(1) in the signal sequence d(i).

[0068] In one example, the odd-numbered bit sequence in the signal sequence can be a system-preset generated sequence. The even-numbered bit sequence can be a sequence generated based on the odd-numbered bit sequence.

[0069] In one example, the even-numbered bit sequence in the signal sequence can be a system-preset generated sequence. The odd-numbered bit sequence can be a sequence generated based on the even-numbered bit sequence.

[0070] In one example, a portion of the signal sequence may be a pre-generated sequence. The remaining portion of the signal sequence may be a sequence generated based on the pre-generated portion.

[0071] In one embodiment, the odd-numbered bit sequence in the signal sequence is formed by the even-numbered bit sequence in the signal sequence.

[0072] The even-numbered bits in sequence d(i) are pre-generated sequences by the system. For example, the even-numbered bits in signal sequence d(i) are pre-generated π / 2BPSK (Binary Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying) sequences. The odd-numbered bits in signal sequence d(i) are formed from the even-numbered bits. For example, the odd-numbered bits in signal sequence d(i) are formed from the even-numbered bits into a π / 4QPSK sequence.

[0073] The position of the even-numbered sequence that generates the odd-numbered sequence in the signal sequence is not limited here. For example, it can be an even-numbered sequence that is adjacent to the odd-numbered sequence, or a sequence that can determine the odd-numbered sequence based on the phase difference and magnitude of the signal sequence.

[0074] This embodiment does not limit the generation method of odd-numbered position sequences. They can be generated by combining the real and imaginary parts of even-numbered position sequences, or by combining the real and imaginary parts of even-numbered position sequences after operations.

[0075] In one embodiment, the odd-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the even-numbered bit sequence in the signal sequence.

[0076] In one embodiment, each element in the odd-numbered position sequence of the signal sequence is formed by two adjacent elements in the even-numbered position sequence.

[0077] The signal sequence d(i) is formed by alternating elements of the odd-numbered and even-numbered sequences. Each element d(i) in the odd-numbered sequence is formed by two adjacent elements d(i-1) and d(i+1) in the even-numbered sequence. The first element of the signal sequence is formed by the last and second elements of the signal sequence.

[0078] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0079] This embodiment does not limit how to form elements of an odd-numbered bit sequence based on the real and imaginary parts. For example, the real and imaginary parts can be directly combined into an element; or one or more of the real and imaginary parts can be operated on with real factors to form an element. Here, the real factor can be considered as a real number multiplied by another number; or one or more of the real and imaginary parts can be processed with rotation phase and real factors to form an element.

[0080] In an odd-numbered sequence, the real and imaginary parts of element d(i) are formed by the real and imaginary parts of element d(i-1) and element d(i+1), respectively; or, in an odd-numbered sequence, the real and imaginary parts of element d(i) are formed by the imaginary and real parts of element d(i-1) and element d(i+1), respectively.

[0081] In one example, the real and imaginary parts of element d(i) in the odd-numbered sequence are formed by the product of the real part of element d(i-1) in the even-numbered sequence and the real factor -1, and the product of the imaginary part of element d(i+1) in the even-numbered sequence and the real factor -1, respectively; or, the real and imaginary parts of element d(i) in the odd-numbered sequence are formed by the product of the real part of element d(i+1) in the even-numbered sequence and the real factor -1, and the product of the imaginary part of element d(i-1) in the even-numbered sequence and the real factor -1, respectively.

[0082] In one embodiment, each element is determined by the two adjacent elements in the even-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0083] In this embodiment, when determining the elements in the odd-numbered position sequence, the determination can be made by combining the elements in the even-numbered position sequence, the real factors, and the rotation phase.

[0084] In a signal sequence, the real and imaginary parts of each element in the odd-numbered bit sequence are determined by combining the product of the real part and a real factor of one of the two adjacent elements, and the product of the imaginary part and a real factor of the other of the two adjacent elements, with a rotation phase. This rotation phase indicates the value of the phase rotation.

[0085] The real and imaginary parts of each element in the signal sequence are determined by multiplying them with a real factor after rotating the phase of one of the two adjacent elements and multiplying them with a real factor after rotating the phase of the other of the two adjacent elements. These are then combined as the real and imaginary parts, respectively.

[0086] In one example, the element d(i) in the odd-numbered position sequence is determined by the elements d(i-1), d(i+1), real factors, and rotation phase in the even-numbered position sequence; the real factors are -1; the element d(i) is an element in the odd-numbered position sequence, and correspondingly, the elements d(i-1) and d(i+1) are elements in the even-numbered position sequence.

[0087] In one embodiment, the even-numbered bit sequence in the signal sequence is formed by the odd-numbered bit sequence in the signal sequence.

[0088] In this embodiment, when the odd-numbered position sequence is a pre-generated sequence, the even-numbered position sequence can be generated based on the odd-numbered position sequence. The generation methods for both are similar. The following describes the generation of the even-numbered position sequence based on the odd-numbered position sequence.

[0089] In this embodiment, the odd-numbered bit sequence can be a preset sequence. For example, the odd-numbered bit sequence in the signal sequence d(i) is a preset π / 2 BPSK sequence or a QPSK sequence; the even-numbered bit sequence can be generated by the real and imaginary parts of the odd-numbered bit sequence. The even-numbered bit sequence in the signal sequence d(i) is a π / 4 QPSK sequence formed by the odd-numbered bit sequence.

[0090] The position of the odd-numbered sequence in the signal sequence is not restricted here. For example, it can be an odd-numbered sequence that is adjacent to the even-numbered sequence, or a sequence that can determine the even-numbered sequence based on the phase difference and magnitude of the signal sequence.

[0091] This embodiment does not limit how to generate even-numbered digit sequences. It can generate even-numbered digit sequences by combining the real and imaginary parts of odd-numbered digit sequences, or by performing operations on the real and imaginary parts of odd-numbered digit sequences and then combining them.

[0092] In one embodiment, the even-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the odd-numbered bit sequence in the signal sequence.

[0093] In one embodiment, each element in the even-numbered position sequence of the signal sequence is formed by two adjacent elements in the odd-numbered position sequence.

[0094] The sequence d(i) is formed by alternating elements of the odd-numbered and even-numbered sequences. Each element d(i) in the even-numbered sequence is formed by two adjacent elements d(i-1) and d(i+1) in the odd-numbered sequence. The last element in the sequence is formed by the first and second-to-last elements. The formation of the last element is analogous to the formation of the other elements.

[0095] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0096] This embodiment does not limit how to form an even-numbered sequence of elements based on the real and imaginary parts. For example, the real and imaginary parts can be directly combined into an element, or one or more of the real and imaginary parts can be operated with real factors to form an element.

[0097] In an even-numbered sequence, the real and imaginary parts of element d(i) are formed by the real and imaginary parts of element d(i-1) and element d(i+1), respectively; or, in an even-numbered sequence, the real and imaginary parts of element d(i) are formed by the imaginary and real parts of element d(i-1) and element d(i+1), respectively.

[0098] In one example, the real and imaginary parts of element d(i) in the even-numbered sequence are formed by rotating one or more of the products of the real part of element d(i-1) and the real factor -1 and the imaginary part of element d(i+1) and the real factor -1, respectively; or, the real and imaginary parts of element d(i) in the even-numbered sequence are formed by rotating one or more of the products of the real part of element d(i+1) and the real factor -1 and the imaginary part of element d(i-1) and the real factor -1, respectively.

[0099] In this application, the real part and imaginary part of element d(i) are formed by rotating the phase of the product of the real part of element d(i-1) and the real factor -1 and the product of the imaginary part of element d(i+1) and the real factor -1, respectively; or, the real part and imaginary part of element d(i) are formed by rotating the phase of one or more of the products of the real part of element d(i+1) and the real factor -1, and the products of the imaginary part of element d(i-1) and the real factor -1, respectively.

[0100] In this embodiment, the real part and / or imaginary part can be combined with real factors after operation, or the real part and imaginary part can be combined and then operated with real factors. For example, the real part a and the imaginary part b can be multiplied by real factors respectively, and -a and -bj form a complex number. Alternatively, the real part and imaginary part can be combined first to get a+bj, and then multiplied by -1 to form a complex number.

[0101] This embodiment does not limit the values ​​of the real factors multiplied by the real and imaginary parts.

[0102] In one embodiment, each element is determined by the two adjacent elements in the odd-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0103] In this embodiment, when determining the elements in the even-numbered position sequence, the elements in the odd-numbered position sequence, the real factors, and the rotation phase can be combined.

[0104] In a signal sequence, the real and imaginary parts of each element in the even-numbered bit sequence are determined by the product of the real part and a real factor of one of the two adjacent elements, and the product of the imaginary part and a real factor of the other of the two adjacent elements, respectively. At least one of these products is combined with a rotation phase. For example, either of the two products can be rotated.

[0105] The real and imaginary parts of each element in the signal sequence are determined as follows: one of the two adjacent elements is rotated in phase and then multiplied by a real factor; the other of the two adjacent elements is rotated in phase and then multiplied by a real factor; finally, the two products are combined to obtain the real and imaginary parts of the element.

[0106] In one example, the element d(i) in the even-numbered sequence is determined by the elements d(i-1), d(i+1), real factors, and rotation phase of the odd-numbered sequence; the real factors are -1; the element d(i) is an element in the even-numbered sequence, and correspondingly, the elements d(i-1) and d(i+1) are elements in the odd-numbered sequence.

[0107] In one embodiment, the real factor is -1.

[0108] In one embodiment, determining the signal sequence includes:

[0109] Generate a signal sequence based on a random sequence.

[0110] The signal sequence d(i) can be generated from the random sequence b(k). The generation method is not limited here; it can be generated using formulas. For example, the odd-numbered and even-numbered positions in the signal sequence are calculated using different formulas. Elements in the signal sequence can be generated from two adjacent elements in the random sequence. The number of bits in the two adjacent elements in the random sequence is related to the position of the generated element in the signal sequence. For example, the signal sequence d(i) can be generated from random sequences b(k) and b(k+1), or from only b(k). The formula for calculating element d(i) from elements b(k) and b(k+1) is not limited.

[0111] The random sequence b(k) is a bit sequence, or a pseudo-random sequence, such as a pseudo-noise (PN) sequence, a gold sequence, or a maximum length sequence (such as an m-sequence).

[0112] This embodiment generates a signal sequence based on a random sequence, which enables the phase of the reference signal to have sufficient randomness and the power in the frequency domain to be relatively stable.

[0113] In one embodiment, generating the signal sequence based on the random sequence includes:

[0114] Generate a signal sequence using one of the following formulas:

[0115] Where mod is the modulo operator, k = 0, 1, 2, ..., I / 2-1, I is the number of elements in the signal sequence, b(k) is the random sequence, and d(i) is the signal sequence.

[0116] In one embodiment, transmitting the signal sequence includes:

[0117] Perform a Discrete Fourier Transform (DFT) on the signal sequence to obtain the DFT-transformed sequence;

[0118] The DFT-transformed sequence is processed and then transmitted together with the data sequence.

[0119] When the signal sequence d(i) is the reference signal sequence, the generated signal sequence d(i) is processed in the same way as the data sequence, including DFT transformation, resource mapping, frequency domain shaping, power normalization, IFFT (inverse fast Fourier transform), and then transmitted together with the data sequence.

[0120] A data sequence can be considered as data exchanged between a first communication node and a second communication node. Transmitting a signal sequence along with the data sequence can be done by transforming the signal sequence before transmission; the transformed signal sequence can also undergo frequency domain shaping. Transmitting them together facilitates estimation of the channel effects experienced by the data sequence during transmission, thus achieving channel estimation.

[0121] In one embodiment, the signal sequence and the data sequence transmitted together are subjected to frequency domain shaping operation;

[0122] In the frequency domain shaping process, a root-raised cosine filter function is used, and the non-zero values ​​of the frequency domain shaping satisfy one or more of the following:

[0123] The width of the non-zero value is less than or equal to the width of the frequency domain sequence of the signal sequence;

[0124] The non-zero value width range is a set multiple of the width range of the frequency domain sequence of the signal sequence, and the set multiple can be [1 / 3, 3 / 4] or [1 / 2, 3 / 4].

[0125] The frequency domain sequence of the reference signal sequence d(i) is directly mapped onto the 0th to I-1th subcarriers.

[0126] The frequency domain sequence of the reference signal sequence d(i) and the data sequence are both subjected to frequency domain spectrum shaping (FDSS).

[0127] FDSS uses a root-raised cosine filter function.

[0128] The non-zero width of FDSS is less than or equal to the width of the frequency domain sequence.

[0129] The non-zero width range of FDSS is a predetermined multiple of the width range of the frequency domain sequence of the signal sequence, and the predetermined multiple ranges from [1 / 3, 3 / 4]. That is, the ratio of the non-zero width range of FDSS to the width range of the frequency domain sequence of the signal sequence is located in [1 / 3, 3 / 4].

[0130] Both the signal sequence d(i) and the data sequence undergo FDSS operation, experiencing the same FDSS as the data sequence. This allows for transparent FDSS estimation and can further reduce the peak-to-average power ratio of the reference signal.

[0131] In one exemplary embodiment, this application also provides a sequence processing method. Figure 2 is a flowchart illustrating another sequence processing method provided in an embodiment of this application. This method is applicable to reducing the PAPR of a signal sequence. The method can be executed by a sequence processing device, which can be implemented in software and / or hardware, and can be integrated on a second communication node. The second communication node can be a communication node capable of acquiring and processing the signal sequence that has passed through a channel. Details not covered in this embodiment can be found in the above embodiments and will not be elaborated upon here.

[0132] As shown in Figure 2, the sequence processing method provided in this application includes the following steps:

[0133] S210, Obtain the signal sequence that has passed through the channel.

[0134] The signal sequence is a complex sequence, in which the elements have the same modulus, and the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2. The phase difference is the angle between the phases of any two adjacent elements in the signal sequence.

[0135] This operation can obtain the signal sequence transmitted by the first communication node. It can also obtain the data sequence transmitted along with the signal sequence.

[0136] If the signal sequence has been transformed during transmission, the received data can be processed to recover the original signal sequence.

[0137] S220. Channel estimation is performed based on the acquired signal sequence and the locally stored signal sequence.

[0138] After acquiring the signal sequence that has passed through the channel, the second communication node can perform channel estimation based on the locally stored signal sequence and the received signal sequence. Since the signal is affected by the channel during transmission, the receiving end needs to estimate the channel characteristics using the signal sequence (such as a reference signal) to compensate for the data sequence. The specific methods of channel estimation are not limited here.

[0139] The sequence processing method provided in this application performs channel estimation based on a signal sequence that has experienced a channel and a locally stored signal sequence. The obtained signal sequence has a low PAPR, thus achieving channel estimation using a signal sequence with a low PAPR.

[0140] Based on the above embodiments, modified embodiments of the above embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in the modified embodiments.

[0141] In one embodiment, the phase difference between the first and last elements of the signal sequence is qπ / 4.

[0142] In one embodiment, the phase difference between the first and last elements of the signal sequence is 3π / 4.

[0143] In one embodiment, the phase difference between any two adjacent elements in the signal sequence is 3π / 4.

[0144] In one embodiment, the signal sequence satisfies one of the following:

[0145] The number of elements contained in the signal sequence is even;

[0146] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the odd-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the even-numbered bit sequence is 0 or π / 2.

[0147] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the even-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the odd-numbered bit sequence is 0 or π / 2.

[0148] The first element in the signal sequence is formed by the last element in the signal sequence and the second element in the signal sequence;

[0149] The last element in the signal sequence is formed by the second-to-last element and the first element in the signal sequence;

[0150] The signal sequence is a sequence from the reference signal sequence or the guard interval sequence;

[0151] The odd-numbered positions in the signal sequence are a preset sequence;

[0152] The even-numbered positions in the signal sequence are a preset sequence.

[0153] In one embodiment, the odd-numbered bit sequence in the signal sequence is formed by the even-numbered bit sequence in the signal sequence.

[0154] In one embodiment, the odd-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the even-numbered bit sequence in the signal sequence.

[0155] In one embodiment, each element in the odd-numbered position sequence of the signal sequence is formed by two adjacent elements in the even-numbered position sequence.

[0156] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0157] In one embodiment, each element is determined by the two adjacent elements in the even-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0158] In one embodiment, the even-numbered bit sequence in the signal sequence is formed by the odd-numbered bit sequence in the signal sequence.

[0159] In one embodiment, the even-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the odd-numbered bit sequence in the signal sequence.

[0160] In one embodiment, each element in the even-numbered position sequence of the signal sequence is formed by two adjacent elements in the odd-numbered position sequence.

[0161] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0162] In one embodiment, each element is determined by the two adjacent elements in the odd-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0163] In one embodiment, the real factor is -1.

[0164] In one embodiment, the signal sequence is generated based on a random sequence.

[0165] In one embodiment, a signal sequence is generated from a random sequence using one of the following formulas:

[0166] Where mod is the modulo operator, k = 0, 1, 2, ..., I / 2-1, I is the number of elements in the signal sequence, b(k) is the random sequence, and d(i) is the signal sequence.

[0167] In one embodiment, the signal sequence and the data sequence transmitted together are subjected to frequency domain shaping operation;

[0168] In the frequency domain shaping process, a root-raised cosine filter function is used, and the non-zero values ​​of the frequency domain shaping satisfy one or more of the following:

[0169] The width of the non-zero value is less than or equal to the width of the frequency domain sequence of the signal sequence;

[0170] The non-zero value width range is a set multiple of the width range of the frequency domain sequence of the signal sequence, and the set multiple ranges from [1 / 3, 3 / 4].

[0171] The following is an exemplary description of this application. The signal sequence provided in this application can be considered as a low PAPR signal sequence. This signal sequence can be a reference signal sequence. The following description uses a reference signal sequence as an example:

[0172] Figure 3 is an example diagram of generating a reference signal sequence provided in an embodiment of this application; referring to Figure 3, this embodiment involves three sequences: odd-numbered bit sequence [d(0),d(2),…,d(I-2)], even-numbered bit sequence [d(1),d(3),…,d(I-1)] and complete reference signal sequence [d(0),d(1),…,d(I-1)].

[0173] In this embodiment, the odd-numbered position sequence adopts a preset sequence, and the even-numbered position sequence elements are formed by the odd-numbered position sequence elements.

[0174] Specifically, each element d(i) in the even-numbered position sequence is formed by the elements d(i-1) and d(i+1) in the two adjacent odd-numbered position sequences. For example, when i = 1, the element d(1) in the even-numbered position sequence is formed by the elements d(0) and d(2) in the two adjacent odd-numbered position sequences, and so on. Furthermore, the last element d(i-1) in the even-numbered position sequence is formed by the last element d(i-2) and the first element d(0) in the odd-numbered position sequence.

[0175] This generation method can be achieved through a simple linear combination, such as d(i) = α·d(i-1) + β·d(i+1), where α and β are preset coefficients that can be adjusted according to actual needs.

[0176] This generation method creates a certain correlation between the even-numbered and odd-numbered sequences, which helps to reduce PAPR.

[0177] The reference signal sequence is formed by alternating elements of the odd-numbered bit sequence and elements of the even-numbered bit sequence.

[0178] Specifically, the 1st, 3rd, 5th... bits of the reference signal sequence d(i) are elements of the odd-numbered bit sequence, and the 2nd, 4th, 6th... bits are elements of the even-numbered bit sequence. For example, if the odd-numbered bit sequence is [d(0), d(2), d(4), ..., d(1-2)], that is, the 1st, 3rd, 5th... bits of the signal sequence, and the even-numbered bit sequence is [d(1), d(3), d(5), ..., d(1-1)], that is, the 2nd, 4th, 6th... bits of the signal sequence, then the reference signal sequence d(i) can be represented as [d(0), d(1), d(2), d(3), d(4), d(5), ..., d(1-2), d(1-1)].

[0179] At the transmitting end, the reference signal sequence d(i) is generated according to the above method. At the receiving end, the reference signal sequence d(i) is used for channel estimation.

[0180] Figure 4 is a schematic diagram of another process for generating a reference signal sequence provided in an embodiment of this application; referring to Figure 4, the embodiment involves three sequences: an odd-numbered sequence [d(0), d(2), ..., d(I-2)], an even-numbered sequence [d(1), d(3), ..., d(I-1)], and a complete reference signal sequence [d(0), d(1), ..., d(I-1)].

[0181] In this embodiment, the even-numbered position sequence adopts a preset sequence, and the elements of the odd-numbered position sequence are formed by the elements of the even-numbered position sequence.

[0182] Specifically, each element d(i) in the odd-numbered position sequence is formed by the elements d(i-1) and d(i+1) of the two adjacent even-numbered position sequences. For example, when i = 2, the element d(2) in the odd-numbered position sequence is formed by the elements d(1) and d(3) of the two adjacent even-numbered position sequences, and so on. Furthermore, the first element d(0) in the odd-numbered position sequence is formed by the last element d(i-1) and the first element d(2) of the even-numbered position sequence.

[0183] The reference signal sequence is formed by alternating elements of the odd-numbered bit sequence and elements of the even-numbered bit sequence.

[0184] Specifically, the 1st, 3rd, 5th... bits of the reference signal sequence d(i) are elements of the odd-numbered bit sequence, and the 2nd, 4th, 6th... bits are elements of the even-numbered bit sequence.

[0185] The following describes how elements are generated, using three consecutive elements (element d(i-1), element d(i), and element d(i+1)) as an example:

[0186] In this embodiment, the element d(i) is formed by the element d(i-1) and the element d(i+1), the real part of the element d(i) is equal to the real part of the element d(i-1), and the imaginary part of the element d(i) is equal to the imaginary part of the element d(i+1).

[0187] Assuming that the elements d(i-1) and d(i+1) are a preset π / 2BPSK sequence:

[0188] The elements d(i-1) and d(i+1) are respectively When the element d(i) is -j;

[0189] The elements d(i-1) and d(i+1) are respectively When the element d(i) is -1;

[0190] The elements d(i-1) and d(i+1) are respectively When , the element d(i) is 1;

[0191] The elements d(i-1) and d(i+1) are respectively When the element d(i) is -j;

[0192] The elements d(i-1) and d(i+1) are respectively When the element d(i) is j;

[0193] The elements d(i-1) and d(i+1) are respectively When , the element d(i) is 1;

[0194] The elements d(i-1) and d(i+1) are respectively When the element d(i) is -1;

[0195] The elements d(i-1) and d(i+1) are respectively When the element d(i) is j.

[0196] In this embodiment, the reference signal sequence d(i) is obtained by combining the method of generating the reference signal sequence in Figure 4 and the method of generating the above elements.

[0197] Assuming the odd-numbered position sequence is a preset π / 2BPSK sequence, the odd-numbered position sequence is as follows:

[0198] The even-numbered position sequence is then:

[0199] [d(1)=-j, d(3)=-j, d(5)=-1, d(7)=-1];

[0200] The reference signal sequence is then:

[0201] The phase difference between two adjacent elements in the odd-numbered bit sequence is π / 2; the phase difference between two adjacent elements in the even-numbered bit sequence formed by the odd-numbered bit sequence is 0 or π / 2; the phase difference between two adjacent elements in the reference signal sequence formed by alternating elements of the odd-numbered bit sequence and the even-numbered bit sequence is 3π / 4.

[0202] In one embodiment, given a sequence b(k), k = 0, 1, 2, 3, ... 1 / 2-1, which is a pseudo-random sequence of length 1 / 2 (including PN sequence, gold sequence, m sequence), a reference signal sequence d(i) (i = 0, 1, 2, 3, ... 1-1) is obtained from the sequence b(k). The generation expression of the reference signal sequence d(i) is:

[0203] Here, mod is the modulo operator.

[0204] Assume [b(0)=0,b(1)=1,b(2)=0,b(3)=1], then [d(1)=-1, d(3)=j, d(5)=1, d(7)=-j].

[0205] In one embodiment, given a sequence b(k), k = 0, 1, 2, 3, ... 1 / 2-1, which is a pseudo-random sequence (PN sequence, gold sequence, m sequence) of length 1 / 2, a reference signal sequence d(i), i = 0, 1, 2, 3, ... 1-1, is obtained from the sequence b(k). The generation expression of the reference signal sequence d(i) is:

[0206] Here, mod is the modulo operator.

[0207] Assume [b(0)=0,b(1)=1,b(2)=0,b(3)=1], then [d(1)=-j, d(3)=1, d(5)=j, d(7)=-1].

[0208] Figure 5 is a schematic diagram of the transmission process of a reference signal sequence provided in an embodiment of this application. Referring to Figure 5, the frequency domain sequence of the DMRS can be obtained by performing a DFT transform on the generated reference signal sequence d(i). This DMRS is then placed in the time-frequency resources of the DMRS in the DFT-S-OFDM and transmitted as a DMRS. This DMRS has a lower PAPR.

[0209] The phase difference between any two adjacent elements in the generated reference signal sequence d(i) is 3π / 4. The obtained DMRS frequency domain data sequence and data sequence are directly mapped onto the 0th to the (i-1)th subcarrier. Correspondingly, the real factor takes the value -1.

[0210] In one embodiment, the reference signal sequence and the data sequence undergo Fourier transform and frequency domain shaping. In this embodiment, it is assumed that the reference signal sequence undergoes Fourier transform to form a Fourier-transformed reference signal sequence, and then the Fourier-transformed reference signal sequence is frequency-domain shaped and mapped onto time-frequency resources for transmission.

[0211] Figure 6 is a schematic diagram of the power characteristics of a Fourier transform reference signal sequence provided in an embodiment of this application. The power characteristics of the Fourier transform reference signal sequence are shown in Figure 6. In Figure 6, the length of the horizontal axis is the number of points N in the Fourier transform, the horizontal axis value is the position index of the data after the Fourier transform, and the vertical axis value is the statistical average power value of the Fourier transform reference signal sequence. The frequency domain shaping is a dot product operation. The non-zero width of the frequency domain shaping function is a set multiple of the width range of the frequency domain sequence of the signal sequence. The set multiple ranges from [1 / 3N, 3 / 4N]. The frequency domain shaping function is a root raised cosine function or a raised cosine function. Frequency domain shaping can extract the portion with relatively high power and map it onto the frequency domain resources.

[0212] In one exemplary embodiment, this application provides a sequence processing apparatus that can be integrated on a first communication node. Figure 7 is a schematic diagram of the structure of a sequence processing apparatus provided in an embodiment of this application; as shown in Figure 7, the sequence processing apparatus includes:

[0213] The determining module 710 is configured to determine a signal sequence, wherein the signal sequence is a complex sequence, the elements in the signal sequence have the same modulus, the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2, and the phase difference is the angle between the phases of any two adjacent elements in the signal sequence.

[0214] The transmission module 720 is configured to transmit the signal sequence.

[0215] The sequence processing device provided in this embodiment is used to implement the sequence processing method shown in Figure 1. The implementation principle and technical effect of the sequence processing device provided in this embodiment are similar to those of the sequence processing method shown in Figure 1, and will not be repeated here.

[0216] Based on the above embodiments, modified embodiments of the above embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in the modified embodiments.

[0217] In one embodiment, the phase difference between the first and last elements of the signal sequence is qπ / 4.

[0218] In one embodiment, the phase difference between the first and last elements of the signal sequence is 3π / 4.

[0219] In one embodiment, the phase difference between any two adjacent elements in the signal sequence is 3π / 4.

[0220] In one embodiment, the signal sequence satisfies one of the following:

[0221] The number of elements contained in the signal sequence is even;

[0222] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the odd-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the even-numbered bit sequence is 0 or π / 2.

[0223] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the even-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the odd-numbered bit sequence is 0 or π / 2.

[0224] The first element in the signal sequence is formed by the last element in the signal sequence and the second element in the signal sequence;

[0225] The last element in the signal sequence is formed by the second-to-last element and the first element in the signal sequence;

[0226] The signal sequence is a sequence from the reference signal sequence or the guard interval sequence;

[0227] The odd-numbered positions in the signal sequence are a preset sequence;

[0228] The even-numbered positions in the signal sequence are a preset sequence.

[0229] In one embodiment, the odd-numbered bit sequence in the signal sequence is formed by the even-numbered bit sequence in the signal sequence.

[0230] In one embodiment, the odd-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the even-numbered bit sequence in the signal sequence.

[0231] In one embodiment, each element in the odd-numbered position sequence of the signal sequence is formed by two adjacent elements in the even-numbered position sequence.

[0232] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0233] In one embodiment, each element is determined by the two adjacent elements in the even-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0234] In one embodiment, the even-numbered bit sequence in the signal sequence is formed by the odd-numbered bit sequence in the signal sequence.

[0235] In one embodiment, the even-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the odd-numbered bit sequence in the signal sequence.

[0236] In one embodiment, each element in the even-numbered position sequence of the signal sequence is formed by two adjacent elements in the odd-numbered position sequence.

[0237] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0238] In one embodiment, each element is determined by the two adjacent elements in the odd-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0239] In one embodiment, the real factor is -1.

[0240] In one embodiment, the determining module 710 includes a generating unit, configured as follows:

[0241] Generate a signal sequence based on a random sequence.

[0242] In one embodiment, the generating unit is specifically configured as follows:

[0243] Generate a signal sequence using one of the following formulas:

[0244] Where mod is the modulo operator, k = 0, 1, 2, ..., I / 2-1, I is the number of elements in the signal sequence, b(k) is the random sequence, and d(i) is the signal sequence.

[0245] In one embodiment, the transmission module 720 is specifically configured as follows:

[0246] Perform a Discrete Fourier Transform (DFT) on the signal sequence to obtain the DFT-transformed sequence;

[0247] The DFT-transformed sequence is processed and then transmitted together with the data sequence.

[0248] In one embodiment, the signal sequence and the data sequence transmitted together are subjected to frequency domain shaping operation;

[0249] In the frequency domain shaping process, a root-raised cosine filter function is used, and the non-zero values ​​of the frequency domain shaping satisfy one or more of the following:

[0250] The width of the non-zero value is less than or equal to the width of the frequency domain sequence of the signal sequence;

[0251] The non-zero value width range is a set multiple of the width range of the frequency domain sequence of the signal sequence, and the set multiple ranges from [1 / 3, 3 / 4].

[0252] In one exemplary embodiment, this application also provides a sequence processing apparatus, which can be integrated into a second communication node. Figure 8 is a schematic diagram of another sequence processing apparatus provided in this application; as shown in Figure 8, the apparatus includes:

[0253] The acquisition module 810 is configured to acquire a signal sequence that has passed through a channel. The signal sequence is a complex sequence in which the elements have the same modulus. The phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2. The phase difference is the angle between the phases of any two adjacent elements in the signal sequence.

[0254] The estimation module 820 is configured to perform channel estimation based on the acquired signal sequence and the locally stored signal sequence.

[0255] The sequence processing device provided in this embodiment is used to implement the sequence processing method shown in Figure 2. The implementation principle and technical effect of the sequence processing device provided in this embodiment are similar to those of the sequence processing method shown in Figure 2, and will not be repeated here.

[0256] Based on the above embodiments, modified embodiments of the above embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in the modified embodiments.

[0257] In one embodiment, the phase difference between the first and last elements of the signal sequence is qπ / 4.

[0258] In one embodiment, the phase difference between the first and last elements of the signal sequence is 3π / 4.

[0259] In one embodiment, the phase difference between any two adjacent elements in the signal sequence is 3π / 4.

[0260] In one embodiment, the signal sequence satisfies one of the following:

[0261] The number of elements contained in the signal sequence is even;

[0262] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the odd-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the even-numbered bit sequence is 0 or π / 2.

[0263] The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the even-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the odd-numbered bit sequence is 0 or π / 2.

[0264] The first element in the signal sequence is formed by the last element in the signal sequence and the second element in the signal sequence;

[0265] The last element in the signal sequence is formed by the second-to-last element and the first element in the signal sequence;

[0266] The signal sequence is a sequence from the reference signal sequence or the guard interval sequence;

[0267] The odd-numbered positions in the signal sequence are a preset sequence;

[0268] The even-numbered positions in the signal sequence are a preset sequence.

[0269] In one embodiment, the odd-numbered bit sequence in the signal sequence is formed by the even-numbered bit sequence in the signal sequence.

[0270] In one embodiment, the odd-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the even-numbered bit sequence in the signal sequence.

[0271] In one embodiment, each element in the odd-numbered position sequence of the signal sequence is formed by two adjacent elements in the even-numbered position sequence.

[0272] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0273] In one embodiment, each element is determined by the two adjacent elements in the even-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0274] In one embodiment, the even-numbered bit sequence in the signal sequence is formed by the odd-numbered bit sequence in the signal sequence.

[0275] In one embodiment, the even-numbered bit sequence in the signal sequence is a π / 4 quadrature phase shift keying sequence formed by the odd-numbered bit sequence in the signal sequence.

[0276] In one embodiment, each element in the even-numbered position sequence of the signal sequence is formed by two adjacent elements in the odd-numbered position sequence.

[0277] In one embodiment, the real part and imaginary part of each element are formed by the real part and imaginary part of the two elements adjacent to each element, respectively.

[0278] In one embodiment, each element is determined by the two adjacent elements in the odd-numbered bit sequence of the signal sequence, a real factor, and a rotation phase.

[0279] In one embodiment, the real factor is -1.

[0280] In one embodiment, the signal sequence is generated based on a random sequence.

[0281] In one embodiment, a signal sequence is generated from a random sequence using one of the following formulas:

[0282] Where mod is the modulo operator, k = 0, 1, 2, ..., I / 2-1, I is the number of elements in the signal sequence, b(k) is the random sequence, and d(i) is the signal sequence.

[0283] In one embodiment, the signal sequence and the data sequence transmitted together are subjected to frequency domain shaping operation;

[0284] In the frequency domain shaping process, a root-raised cosine filter function is used, and the non-zero values ​​of the frequency domain shaping satisfy one or more of the following:

[0285] The width of the non-zero value is less than or equal to the width of the frequency domain sequence of the signal sequence;

[0286] The non-zero value width range is a set multiple of the width range of the frequency domain sequence of the signal sequence, and the set multiple ranges from [1 / 3, 3 / 4].

[0287] In one exemplary embodiment, this application also provides a first communication node. FIG9 is a schematic diagram of the structure of a first communication node provided in this application embodiment. As shown in FIG9, the first communication node provided in this application includes one or more processors 91 and a storage device 92. The processors 91 in the first communication node may be one or more, and FIG9 takes one processor 91 as an example. The storage device 92 is used to store one or more programs. The one or more programs are executed by the one or more processors 91, so that the one or more processors 91 implement the sequence processing method as described in the embodiment of this application.

[0288] The first communication node also includes: a communication device 93, an input device 94, and an output device 95.

[0289] The processor 91, storage device 92, communication device 93, input device 94, and output device 95 in the first communication node can be connected by a bus or other means. Figure 9 shows an example of connection via a bus.

[0290] Input device 94 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the first communication node. Output device 95 may include display devices such as a display screen.

[0291] The communication device 93 may include a receiver and a transmitter. The communication device 93 is configured to perform information transmission and reception communication under the control of the processor 91.

[0292] Storage device 92, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as program instructions / modules corresponding to the sequence processing method described in the embodiments of this application (e.g., the determining module 710 and the transmission module 720 in the sequence processing apparatus). Storage device 92 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required for at least one function; the data storage area may store data created based on the use of the first communication node, etc. Furthermore, storage device 92 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, storage device 92 may further include memory remotely located relative to processor 91, and these remote memories can be connected to the first communication node via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0293] In one exemplary embodiment, this application also provides a second communication node. FIG10 is a schematic diagram of the structure of a second communication node provided in this application embodiment. As shown in FIG10, the second communication node provided in this application includes one or more processors 101 and a storage device 102; the processors 101 in the second communication node may be one or more, and FIG10 uses one processor 101 as an example; the storage device 102 is used to store one or more programs; the one or more programs are executed by the one or more processors 101, so that the one or more processors 101 implement the sequence processing method as described in the embodiment of this application.

[0294] The second communication node also includes: a communication device 103, an input device 104, and an output device 105.

[0295] The processor 101, storage device 102, communication device 103, input device 104, and output device 105 in the second communication node can be connected by a bus or other means. Figure 10 shows an example of connection via a bus.

[0296] Input device 104 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the second communication node. Output device 105 may include display devices such as a display screen.

[0297] The communication device 103 may include a receiver and a transmitter. The communication device 103 is configured to perform information transmission and reception communication under the control of the processor 101.

[0298] Storage device 102, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as program instructions / modules corresponding to the sequence processing method described in the embodiments of this application (e.g., acquisition module 810 and estimation module 820 in the sequence processing apparatus). Storage device 102 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required for at least one function; the data storage area may store data created based on the use of the second communication node, etc. Furthermore, storage device 102 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, storage device 102 may further include memory remotely located relative to processor 101, and these remote memories can be connected to the second communication node via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0299] In one exemplary embodiment, this application also provides a storage medium storing a computer program that, when executed by a processor, implements any of the methods described in this application. The storage medium also stores a computer program that, when executed by a processor, implements any of the sequence processing methods described in the embodiments of this application.

[0300] For example, a sequence processing method applied to a first communication node and a sequence processing method applied to a second communication node, wherein the sequence processing method applied to the first communication node includes: determining a signal sequence, wherein the signal sequence is a complex sequence, the elements in the signal sequence have the same modulus, the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2, and the phase difference is the angle between the phases of any two adjacent elements in the signal sequence; and transmitting the signal sequence.

[0301] The sequence processing method applied to the second communication node includes: acquiring a signal sequence that has passed through the channel, wherein the signal sequence is a complex sequence, the elements in the signal sequence have the same modulus, the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2, and the phase difference is the angle between the phases of any two adjacent elements in the signal sequence; and performing channel estimation based on the acquired signal sequence and the locally stored signal sequence.

[0302] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device, or any suitable combination thereof. The computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0303] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0304] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0305] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0306] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0307] Those skilled in the art will understand that the term terminal equipment covers any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicle-mounted mobile stations.

[0308] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0309] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0310] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and processors based on multi-core processor architectures.

Claims

1. A sequence processing method, comprising: A signal sequence is defined, wherein the signal sequence is a complex sequence, the elements in the signal sequence have the same modulus, the phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2, and the phase difference is the angle between the phases of any two adjacent elements in the signal sequence. Transmit the signal sequence.

2. The method according to claim 1, wherein, The phase difference between the first and last elements in the signal sequence is qπ / 4.

3. The method according to claim 2, wherein, The phase difference between the first and last elements in the signal sequence is 3π / 4.

4. The method according to claim 1, wherein, The phase difference between any two adjacent elements in the signal sequence is 3π / 4.

5. The method according to claim 1, wherein, The signal sequence satisfies one of the following: The number of elements contained in the signal sequence is even; The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the odd-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the even-numbered bit sequence is 0 or π / 2. The signal sequence includes an odd-numbered bit sequence and an even-numbered bit sequence. The phase difference between any two adjacent elements in the even-numbered bit sequence is π / 2, and the phase difference between any two adjacent elements in the odd-numbered bit sequence is 0 or π / 2. The first element in the signal sequence is formed by the last element in the signal sequence and the second element in the signal sequence; The last element in the signal sequence is formed by the second-to-last element and the first element in the signal sequence; The signal sequence is a sequence from the reference signal sequence or the guard interval sequence; The odd-numbered positions in the signal sequence are a preset sequence; The even-numbered positions in the signal sequence are a preset sequence.

6. The method according to claim 1, wherein, The odd-numbered bit sequence in the signal sequence is formed by the even-numbered bit sequence in the signal sequence.

7. The method according to claim 6, wherein, The odd-numbered bit sequence in the signal sequence is a π / 4 orthogonal phase shift keying sequence formed by the even-numbered bit sequence in the signal sequence.

8. The method according to claim 6, wherein, Each element in the odd-numbered position sequence of the signal sequence is formed by two adjacent elements in the even-numbered position sequence.

9. The method according to claim 8, wherein, The real part of each element is formed by the real parts of the two even-numbered digit sequence elements adjacent to each element, and the imaginary part of each element is formed by the imaginary parts of the two even-numbered digit sequence elements adjacent to each element.

10. The method according to claim 9, wherein, Each element is determined by the two adjacent elements in the even-numbered bit sequence of the signal sequence, the real factor, and the rotation phase.

11. The method according to claim 1, wherein, The even-numbered bit sequence in the signal sequence is formed by the odd-numbered bit sequence in the signal sequence.

12. The method according to claim 11, wherein, The even-numbered bit sequence in the signal sequence is a π / 4 orthogonal phase shift keying sequence formed by the odd-numbered bit sequence in the signal sequence.

13. The method according to claim 11, wherein, Each element in the even-numbered position sequence of the signal sequence is formed by two adjacent elements in the odd-numbered position sequence.

14. The method according to claim 13, wherein, The real part of each element is formed by the real parts of the two odd-numbered sequence elements adjacent to each element, and the imaginary part of each element is formed by the real and imaginary parts of the two odd-numbered sequence elements adjacent to each element.

15. The method according to claim 14, wherein, Each element is determined by the two adjacent elements in the odd-numbered bit sequence of the signal sequence, the real factor, and the rotation phase.

16. The method according to claim 10 or 15, wherein, The real factor is -1.

17. The method according to claim 1, wherein, The determined signal sequence includes: Generate a signal sequence based on a random sequence.

18. The method according to claim 17, wherein, The step of generating a signal sequence based on a random sequence includes: Generate a signal sequence using one of the following formulas: Where mod is the modulo operator, k = 0, 1, 2, ..., I / 2-1, I is the number of elements in the signal sequence, b(k) is the random sequence, and d(i) is the signal sequence.

19. The method according to claim 1, wherein, The transmission of the signal sequence includes: Perform a Discrete Fourier Transform (DFT) on the signal sequence to obtain the DFT-transformed sequence; The DFT-transformed sequence is processed and then transmitted together with the data sequence.

20. The method according to claim 1, wherein, The signal sequence and the data sequence transmitted together are respectively subjected to frequency domain shaping operations; In the frequency domain shaping process, a root-raised cosine filter function is used, and the non-zero values ​​of the frequency domain shaping satisfy at least one of the following: The width of the non-zero value is less than or equal to the width of the frequency domain sequence of the signal sequence; The non-zero value width range is a set multiple of the width range of the frequency domain sequence of the signal sequence, and the set multiple ranges from [1 / 3, 3 / 4].

21. A sequence processing method, comprising: Obtain a signal sequence that has undergone channel transmission. The signal sequence is a complex sequence in which the elements have the same modulus. The phase difference between any two adjacent elements in the signal sequence is qπ / 4, where q is an integer greater than 2. The phase difference is the angle between the phases of any two adjacent elements in the signal sequence. Channel estimation is performed based on the acquired signal sequence and the locally stored signal sequence.

22. A first communication node, comprising: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-20.

23. A second communication node, comprising: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in claim 21.

24. A storage medium storing a computer program that, when executed by a processor, implements the method of any one of claims 1-21.

25. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-21.

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