Chip packaging structure and manufacturing method therefor, circuit board assembly, and electronic device
Patent Information
- Application Number
- PCT/CN2026/081832
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-24
- Filing Date
- 2026-03-06
- Publication Date
- 2026-10-01
Smart Images
Figure CN2026081832_01102026_PF_FP_ABST
Abstract
Description
Chip packaging structure and its fabrication method, circuit board assembly and electronic equipment
[0001] This application claims priority to Chinese Patent Application No. 202510352211.X, filed on March 24, 2025, entitled “Chip Packaging Structure and Manufacturing Method Thereof, Circuit Board Assembly and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to a chip packaging structure and its manufacturing method, a circuit board assembly, and an electronic device. Background Technology
[0003] As chip size increases, the size of chip packaging structures also becomes larger. However, the larger the chip packaging structure, the greater the stress at its corners, making it prone to delamination or cracks at the corners, which may ultimately affect the performance of the chip packaging structure or even cause it to fail. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides a chip packaging structure and its manufacturing method, a circuit board assembly, and an electronic device, which can reduce the phenomenon of delamination.
[0005] A first aspect of this application provides a chip packaging structure, including: a substrate, a chip, and a second molding compound layer. The chip includes an interposer, a chip structure, and a first molding compound layer. The interposer is disposed on the substrate, and the chip structure is disposed on the side of the interposer facing away from the substrate. The chip structure may include one or more chip groups, each chip group including one or more chips, and the number of chips in different chip groups may be different. When a chip group includes multiple chips, the multiple chips may be stacked sequentially along the thickness direction. The first molding compound layer at least partially covers multiple sides of the interposer.
[0006] The second molding compound is disposed on the substrate and is located on the same side as the chip. A portion of the second molding compound is located between the interposer and the substrate, and a portion of the second molding compound is located between the first molding compound and the substrate. Furthermore, the coefficient of thermal expansion of the first molding compound is greater than that of the interposer and less than that of the second molding compound.
[0007] It is understandable that after the chip packaging structure is manufactured, it needs to undergo temperature cycling testing, that is, testing the performance of the chip packaging structure under repeated high and low temperature environments. In practical applications, the chip packaging structure may be in a continuous high-temperature environment. The substrate, the second molding layer, and the interposer will all deform when heated. Since the materials of the three are different, their coefficients of thermal expansion are different, and the amount of deformation after heating is different. When the substrate deforms, it will exert a tensile force on the second molding layer and the interposer. In this application, since the chip includes a first molding layer that covers multiple sides of the interposer, and the coefficient of thermal expansion of the first molding layer is greater than that of the interposer but less than that of the second molding layer, the amount of deformation of the first molding layer when heated is between that of the interposer and the second molding layer. This avoids the large difference in the coefficients of thermal expansion between the two connected structures, which would lead to a large difference in the amount of deformation and thus delamination. Therefore, this application can better absorb the tensile force generated by the substrate, alleviate the stress at the corners of the chip packaging structure, and thus reduce the delamination between the interlayer and the first molding layer and the second molding layer.
[0008] Furthermore, since the first molding layer covers multiple sides of the intermediate layer, it provides physical protection for the intermediate layer, preventing it from being directly impacted by external forces, thereby reducing the likelihood of damage from external impacts.
[0009] In some embodiments of this application, at least a portion of the length and / or width dimensions of the interlayer gradually increase from the side facing the core structure to the other side. Correspondingly, at least a portion of the length and / or width dimensions of the surface of the first molding layer in contact with the interlayer gradually decrease from the side facing the core structure to the other side. This avoids right angles at the corners of the interlayer, thereby reducing excessive stress caused by right angles and further reducing delamination due to excessive stress at the corners of the interlayer. Furthermore, the interlayer can be cut using a beveling process, facilitating processing.
[0010] Furthermore, in one possible implementation, the interposer has a rectangular cross-sectional shape, wherein the cross-section is a plane cut along a surface parallel to the thickness direction of the chip.
[0011] In another possible implementation, the interposer has a trapezoidal cross-sectional shape. That is, the sides of the interposer are sloping planes. For example, one side of the interposer is a sloping plane; or both sides of the interposer are sloping planes; or three sides of the interposer are sloping planes; or all four sides of the interposer are sloping planes. Compared to an interposer with a rectangular cross-sectional shape, an interposer with a trapezoidal cross-sectional shape has a larger side area, and therefore a larger surface area in contact with the first molding layer, thereby increasing the bonding force between the two and better resisting the tensile force from the substrate.
[0012] In another possible implementation, the sides of the interposer include outwardly projecting curved surfaces. Compared to an interposer with a rectangular cross-sectional shape, an interposer with curved surfaces has a larger side area, and therefore a larger surface area in contact with the first molding layer, thereby increasing the bonding force between the two and better resisting the tensile forces from the substrate.
[0013] Furthermore, the sides of the interposer include multiple curved surfaces arranged circumferentially. Therefore, compared to an interposer with a rectangular cross-sectional shape, the interposer with curved surfaces has a larger side area, resulting in a larger contact surface area with the first molding layer. This increases the bonding strength between the two, thereby better resisting the tensile forces from the substrate.
[0014] In some embodiments of this application, the chip further includes a third molding compound layer disposed on one side of the interposer layer and encapsulating the chip structure. The first molding compound layer also encapsulates the third molding compound layer. Thus, the first molding compound layer can provide better physical protection for the third molding compound layer and the chip structure.
[0015] In some embodiments of this application, the interposer includes a first surface, the first surface including a first region and a second region surrounding the first region; the chip also includes a third molding compound layer, the third molding compound layer being disposed on the first region, and a portion of the first molding compound layer being disposed on the second region. That is, the third molding compound layer is disposed on a portion of the first surface. Typically, the third molding compound layer is more expensive than the first molding compound layer. When the third molding compound layer is disposed on a portion of the first surface, it indicates that the area occupied by the third molding compound layer on the interposer layer is smaller, and the volume of the third molding compound layer is smaller, thereby reducing the cost of the third molding compound layer and thus reducing the cost of the chip.
[0016] In some embodiments of this application, the material of the first molding compound includes epoxy molding compound. The epoxy molding compound has a strong bond with the interlayer, thereby better resisting the tensile force from the substrate and preventing delamination between the second molding compound and the interlayer.
[0017] In some embodiments of this application, the second molding layer surrounds and encapsulates a portion of the first molding layer. Thus, the second molding layer is connected not only to the bottom surface of the first molding layer but also to its side surface. This increases the bonding area between the second and first molding layers, thereby improving their adhesion and better resisting the tensile force from the substrate, thus reducing delamination between the second and first molding layers.
[0018] In some embodiments of this application, the interposer includes a first wiring layer, a connector chip, and a second wiring layer sequentially stacked between the substrate and the chip structure. The first wiring layer is closer to the substrate, and there is a gap between the second wiring layer and the connector chip. The first molding compound also covers the sides of the first wiring layer, the sides of the second wiring layer, and the sides of the connector chip, with a portion of the first molding compound located between the connector chip and the second wiring layer. This results in a larger connection area between the first molding compound and the interposer, thereby increasing the bonding strength between them.
[0019] In some embodiments of this application, both the first molding compound and the second molding compound are made of organic materials. This makes the material compositions of the first and second molding compounds more similar, thereby increasing the bonding strength between them and better resisting the tensile force from the substrate. This, in turn, reduces delamination between the first and second molding compounds, and consequently reduces delamination between the interlayer and the second molding compound.
[0020] A second aspect of this application also provides a method for fabricating a chip package structure, comprising: providing a chip structure, the chip structure including an interposer structure and a plurality of die structures spaced apart on the interposer structure; forming a groove in the interposer structure, the groove being located between adjacent die structures; fabricating a first molding compound structure, at least a portion of the first molding compound structure being located within the groove; cutting the first molding compound structure and the interposer structure along the location of the groove to obtain a chip, the chip including an interposer, die structures, and a first molding compound layer; and placing the chip on a substrate and fabricating a second molding compound layer surrounding the chip. The coefficient of thermal expansion of the first molding compound layer is greater than that of the interposer and less than that of the second molding compound layer.
[0021] It is understandable that after the chip packaging structure is manufactured, it needs to undergo temperature cycling testing, that is, testing the performance of the chip packaging structure under repeated high and low temperature environments. In practical applications, the chip packaging structure may be in a continuous high-temperature environment. The substrate, the second molding layer, and the interposer will all deform when heated. Since the materials of the three are different, their coefficients of thermal expansion are different, and the amount of deformation after heating is different. When the substrate deforms, it will exert a tensile force on the second molding layer and the interposer. In this application, since the chip includes a first molding layer that covers multiple sides of the interposer, and the coefficient of thermal expansion of the first molding layer is greater than that of the interposer but less than that of the second molding layer, the amount of deformation of the first molding layer when heated is between that of the interposer and the second molding layer. This avoids the large difference in the coefficients of thermal expansion between the two connected structures, which would lead to a large difference in the amount of deformation and thus delamination. Therefore, this application can better absorb the tensile force generated by the substrate, alleviate the stress at the corners of the chip packaging structure, and thus reduce the delamination between the interlayer and the first molding layer and the second molding layer.
[0022] Furthermore, since the first molding layer covers multiple sides of the intermediate layer, it provides physical protection for the intermediate layer, preventing it from being directly impacted by external forces, thereby reducing the likelihood of damage from external impacts.
[0023] In some embodiments of this application, the core structure further includes a plurality of third molding compound structures spaced apart on one side of the intermediate layer structure, the plurality of third molding compound structures respectively surrounding the plurality of core structures. Fabricating the first molding compound structure includes: fabricating the first molding compound structure within a groove and between adjacent third molding compounds. The first molding compound structure can be obtained by cutting it. Thus, the first molding compound can encapsulate the third molding compound, and since the third molding compound encapsulates the core structure, the first molding compound can provide better physical protection for both the third molding compound and the core structure.
[0024] A third aspect of this application also provides a circuit board assembly, including a circuit board and a chip packaging structure according to any of the above embodiments, wherein the chip packaging structure is disposed on the circuit board. The circuit board assembly can achieve all the effects of the chip packaging structure.
[0025] A fourth aspect of this application also provides an electronic device, including a housing and the aforementioned circuit board assembly, the circuit board assembly being disposed within the housing. The electronic device is capable of achieving all the effects of the circuit board assembly. Attached Figure Description
[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 is a perspective view of the electronic device in an embodiment of this application;
[0028] Figure 2 is a schematic diagram of the disassembled structure of the electronic device shown in Figure 4;
[0029] Figure 3 is a schematic diagram of the circuit board assembly in the first embodiment of this application;
[0030] Figure 4 is a schematic diagram of the chip packaging structure in the circuit board assembly shown in Figure 3.
[0031] Figure 5 is a schematic diagram of the chip packaging structure in the second embodiment of this application;
[0032] Figure 6 is a schematic diagram of the chip packaging structure in the third embodiment of this application;
[0033] Figure 7 is a schematic diagram of the interposer and chip structure in the chip packaging structure shown in Figure 6.
[0034] Figure 8 is a schematic diagram of the chip packaging structure in the fourth embodiment of this application;
[0035] Figure 9 is a schematic diagram of the chip packaging structure in the fifth embodiment of this application;
[0036] Figure 10 is a schematic diagram of the chip packaging structure in the sixth embodiment of this application;
[0037] Figure 11 is a schematic diagram of the chip packaging structure in the seventh embodiment of this application;
[0038] Figure 12 is a flowchart illustrating a method for fabricating the chip packaging structure in the embodiment shown in Figure 4.
[0039] Figure 13 is a schematic diagram of a part of the manufacturing process of the manufacturing method shown in Figure 12;
[0040] Figure 14 is a schematic diagram of another part of the manufacturing process of the manufacturing method shown in Figure 12;
[0041] Figure 15 is a schematic diagram of another part of the manufacturing process of the manufacturing method shown in Figure 12;
[0042] Figure 16 is a schematic diagram of another process for manufacturing the chip packaging structure in the embodiment shown in Figure 4;
[0043] Figure 17 is a schematic diagram of a part of the manufacturing process of the manufacturing method shown in Figure 16;
[0044] Figure 18 is a schematic diagram of another part of the manufacturing process of the method shown in Figure 16;
[0045] Figure 19 is a flowchart illustrating the fabrication method of the chip packaging structure in the embodiment shown in Figure 11;
[0046] Figure 20 is a schematic diagram of a part of the manufacturing process of the manufacturing method shown in Figure 19;
[0047] Figure 21 is a schematic diagram of another part of the manufacturing process of the manufacturing method shown in Figure 19;
[0048] Figure 22 is a schematic diagram of another part of the manufacturing process of the method shown in Figure 19.
[0049] Icons: 1000 - Electronic device; 101 - Screen; 102 - Mid-frame; 103 - Back cover; 104 - Circuit board assembly; 105 - Camera; 1041 - Circuit board; 1042 - Chip packaging structure; 1 - Chip; 2 - Substrate; 3 - Second molding layer; 4 - Pressing structure; 41 - Metal ring; 42 - Metal cover; 5 - Adhesive; 6 - Thermal pad; 10 - Intermediate layer; 101 - Side; 1010 - Curved surface; 100 - Intermediate layer structure; 11 - Silicon substrate; 110 - Silicon substrate structure; 111 - Through-silicon via; 12 - Electrical connection layer; 120 - Electrical connection layer structure; 121 - Dielectric structure; 122 - Conductive structure; 13 - First surface; 131 - First region; 132 - Second region ; 14-Wiring layer; 140-Wiring layer structure; 15-Redistribution line; 16-Conductive pillar; 17-Connecting chip; 18-First wiring layer; 180-First wiring layer structure; 19-Second wiring layer; 190-Second wiring layer structure; 20-Core structure; 21-Core group; 211-Core; 30-First molding compound layer; 300-First molding compound layer structure; 301-First sub-molding compound layer structure; 302-First sub-molding compound layer; 303-Second sub-molding compound layer structure; 40-Solder ball; 50-Third molding compound layer; 60-Pad; 501-Carrier board; 502-Adhesive layer; 5021-Groove; 503-First carrier board; 504-First adhesive layer; 505-Second carrier board; 506-Second adhesive layer. Detailed Implementation
[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0051] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, while "more" refers to two or more. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0052] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.
[0053] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.
[0054] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0055] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.
[0056] This application provides an electronic device, which can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, a communication electronics product, a medical device, etc., and this application does not limit the scope of the application. Indicatively, the aforementioned consumer electronics products can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can be in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can be automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can be servers, storage devices, radar, base stations, and other communication equipment.
[0057] This application does not impose any special limitations on the specific form of the above-described electronic device 1000. For ease of explanation, the following description uses the mobile phone shown in Figures 1 and 2 as an example.
[0058] Please refer to Figures 1 and 2. Figure 1 is a perspective view of an electronic device 1000 provided in some embodiments of this application, and Figure 2 is a disassembled structural diagram of the electronic device 1000 shown in Figure 1. The electronic device 1000 may include a screen 101, a mid-frame 102, a rear shell 103, and a circuit board assembly 104 fixed on the mid-frame 102, as shown in Figure 2. The screen 101, mid-frame 102, and rear shell 103 together form a housing for fixing the circuit board assembly 104.
[0059] It is understood that Figures 1 and 2 only schematically illustrate some components included in the electronic device 1000, and the actual shape, size, location, and construction of these components are not limited by Figures 1 and 2. In some other examples, the electronic device 1000 may not include the screen 101. Alternatively, the electronic device 1000 may also include the camera 105 as shown in Figure 2.
[0060] As shown in Figure 3, the circuit board assembly 104 may include a circuit board 1041 and a chip package structure 1042. The chip package structure 1042 is disposed on the circuit board 1041 and electrically connected to the circuit board 1041. For example, the chip package structure 1042 may be a 2.5D package structure. The chip package structure 1042 may be electrically connected to the circuit board 1041 via a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPBs), thereby enabling the chip package structure 1042 to transmit signals with other chips or other chip package structures on the circuit board 1041.
[0061] It is understood that circuit board 1041 can be a printed circuit board (PCB) or a flexible circuit board.
[0062] As chip size increases, the size of the chip package structure 1042 also becomes larger. However, the larger the size of the chip package structure 1042, the greater the stress at its corners, which can easily lead to delamination, cracks at the corners, or failure of connections between chips. Ultimately, this may affect the performance of the chip package structure 1042 or even cause it to fail.
[0063] In related technologies, stress problems are addressed by selecting materials with low stress or strong bonding strength. However, when the material's limits are reached, the stress at the corners of the chip package structure 1042 remains high, and the entire chip package structure 1042 will still fail.
[0064] Based on this, this application provides a chip packaging structure 1042. As shown in FIG3, the chip packaging structure 1042 may include a chip 1, a substrate 2, and a second molding compound 3. The substrate 2 may be a PCB substrate, a glass substrate, or any other type of substrate.
[0065] Here, chip 1 can be a pre-packaged functional module. For example, chip 1 can be a system-on-a-chip (SOC), a test or dummy chip, a central processing unit (CPU), a graphics processing unit (GPU), memory, an input / output (I / O) chip, an integrated passive device (IPD), etc. It can also integrate other pre-packaged functional modules, such as high-bandwidth memory (HBM).
[0066] For ease of description, three directions are defined here: X (first direction), Y (second direction), and Z (third direction). X represents the length direction of the chip package structure 1042, Y represents the width direction of the chip package structure 1042, and Z represents the thickness direction of the chip package structure 1042. The X, Y, and Z directions are perpendicular to each other.
[0067] As shown in Figure 4, chip 1 may include an interposer 10, a die structure 20, and a first molding compound 30. The interposer 10 may be a silicon bridge. Specifically, the interposer 10 may include a silicon substrate 11 and an electrical connection layer 12 stacked together, with the silicon substrate 11 located between the electrical connection layer 12 and the substrate 2. The electrical connection layer 12 may include a dielectric structure 121 and a conductive structure 122 located within the dielectric structure 121, with the conductive structure 122 exposed from the top and bottom surfaces of the dielectric structure 121, respectively. It is understood that in this embodiment, "top surface" may refer to the surface away from the substrate 2, and "bottom surface" may refer to the surface facing the substrate 2. The material of the dielectric structure 121 may include silicon nitride, silicon oxide, tantalum (Ta) compound, or titanium (Ti) compound, etc.
[0068] As shown in Figure 4, the silicon substrate 11 can be disposed on the substrate 2 by solder balls 40. Moreover, the silicon substrate 11 has through-silicon vias 111 inside, which are electrically connected to the conductive structure 122 and the substrate 2 respectively.
[0069] As shown in Figure 4, the core structure 20 is disposed on the side of the interposer 10 facing away from the substrate 2. The core structure 20 may include one or more core groups 21, each core group 21 including one or more cores 211, and the number of cores 211 in different core groups 21 may be different. When a core group 21 includes multiple cores 211, the multiple cores 211 may be stacked sequentially along the thickness direction.
[0070] As shown in Figure 4, each chip assembly 21 is disposed on the electrical connection layer 12 of the interposer layer 10 via a pad 60 and is electrically connected to the conductive structure 122. Thus, each chip assembly 21 can be electrically connected to the substrate 2 in sequence via the pad 60, the conductive structure 122 of the electrical connection layer 12, the silicon via 111 of the silicon substrate 11, and the solder ball 40.
[0071] As shown in Figure 3, a first molding compound 30 is disposed on the side of the interposer 10 away from the substrate 2, and at least a portion of the first molding compound 30 covers a plurality of side surfaces 101 of the interposer 10. The bottom surface of the first molding compound 30 may be flush with the bottom surface of the interposer 10.
[0072] As shown in Figure 3, the second molding compound 3 is disposed on the substrate 2 and is located on the same side as the chip 1. Part of the second molding compound 3 is located between the interposer 10 and the substrate 2, and part of the second molding compound 3 is located between the first molding compound 30 and the substrate 2.
[0073] In this embodiment, the coefficient of thermal expansion of the first molding compound 30 is greater than that of the interposer 10 and less than that of the second molding compound 3. Thus, the coefficients of thermal expansion from largest to smallest are: second molding compound 3 - first molding compound 30 - interposer 10. After fabrication, the chip package structure 1042 needs to undergo temperature cycling testing, i.e., its performance is tested under conditions of repeated high and low temperature changes. In practical applications, the chip package structure 1042 may be exposed to continuous high temperatures. The substrate 2, the second molding compound 3, and the interposer 10 all deform when heated. Because they are made of different materials, their coefficients of thermal expansion differ, resulting in different amounts of deformation. When the substrate 2 deforms, it exerts tensile force on the second molding compound 3 and the interposer 10. In this embodiment, since the chip 1 includes a first molding compound 30 that encapsulates multiple sides 101 of the interposer 10, and the coefficient of thermal expansion of the first molding compound 30 is greater than that of the interposer 10 and less than that of the second molding compound 3, the deformation of the first molding compound 30 when heated is between the deformation of the interposer 10 and the deformation of the second molding compound 3. This avoids a large difference in the coefficients of thermal expansion between the two connected structures, which could lead to a large difference in deformation and thus delamination. Therefore, this embodiment can better absorb the tensile force generated by the substrate 2, alleviate the stress at the corners of the chip packaging structure 1042, and reduce the possibility of delamination between the interposer 10 and the first molding compound 30 and the second molding compound 3.
[0074] Furthermore, since the first molding layer 30 covers multiple sides 101 of the interposer layer 10, the first molding layer 30 can provide physical protection for the interposer layer 10, preventing it from being directly impacted by external forces, thereby reducing the possibility of damage caused by external impacts.
[0075] Furthermore, the coefficient of thermal expansion of the first molding layer 30 is essentially the same. As a result, the second molding layer 3 can also produce a large amount of deformation, thereby absorbing part of the tensile force on the substrate 2 and reducing delamination between the interlayer 10 and the second molding layer 3.
[0076] As shown in Figure 4, the second molding layer 3 also surrounds and wraps around a portion of the first molding layer 30. That is, the second molding layer 3 can wrap around a portion of the side surface of the first molding layer 30, meaning the top surface of the second molding layer 3 is lower than the top surface of the first molding layer 30. In this way, the second molding layer 3 is connected not only to the bottom surface of the first molding layer 30 but also to its side surface. This increases the connection area between the second molding layer 3 and the first molding layer 30, thereby improving the bonding strength between them and better resisting the tensile force from the substrate 2, thus reducing delamination between the second molding layer 3 and the first molding layer 30.
[0077] Furthermore, both the first molding layer 30 and the second molding layer 3 are made of organic materials. This makes the material compositions of the first molding layer 30 and the second molding layer 3 more similar, thereby increasing the bonding strength between them and better resisting the tensile force from the substrate 2. This, in turn, reduces delamination between the first molding layer 30 and the second molding layer 3, and consequently reduces delamination between the interposer layer 10 and the second molding layer 3.
[0078] Specifically, in one example, the first molding compound 30 is made of epoxy molding compound. The epoxy molding compound has a strong bond with the interposer 10, thereby better resisting the tensile forces from the substrate 2 and preventing delamination between the second molding compound 3 and the interposer 10. The epoxy molding compound may include epoxy resin and silicon dioxide; in application, the proportion of epoxy resin can be adjusted to reduce warpage of the chip package structure 1042. In another example, the first molding compound 30 is made of silicon oxide compounds or silicon-containing inorganic materials.
[0079] As shown in Figure 4, the interposer 10 may further include a wiring layer 14. That is, the interposer 10 comprises a three-layer structure: a silicon substrate 11, an electrical connection layer 12, and a wiring layer 14. The wiring layer 14 is located on the side of the silicon substrate 11 opposite to the electrical connection layer 12. In this way, the chip structure 20 can be electrically connected to the substrate 2 sequentially through the pads 60, the conductive structure 122 in the electrical connection layer 12, the silicon vias 111 in the silicon substrate 11, the wiring layer 14, and the solder balls 40.
[0080] As shown in Figure 5, the length of at least a portion of the interposer layer 10 gradually increases from one side toward the core structure 20 to the other. Correspondingly, the length of at least a portion of the surface of the first molding layer 30 that contacts the interposer layer 10 gradually decreases from one side toward the core structure 20 to the other. Here, the length dimension can refer to the dimension in the X direction.
[0081] Alternatively, at least a portion of the width dimension of the interposer 10 gradually increases from one side toward the core structure 20 to the other. Correspondingly, at least a portion of the width dimension of the surface of the first molding layer 30 that contacts the interposer 10 gradually decreases from one side toward the core structure 20 to the other. Here, the width dimension may refer to the dimension along the Y direction.
[0082] Alternatively, at least a portion of the length and width dimensions of the interposer 10 gradually increase from one side toward the core structure 20 to the other. Correspondingly, at least a portion of the length and width dimensions of the surface of the first molding layer 30 that contacts the interposer 10 gradually decrease from one side toward the core structure 20 to the other.
[0083] Therefore, on the one hand, right angles can be avoided at the corners of the interposer layer 10, thereby reducing the phenomenon of excessive stress caused by right angles, and thus reducing the phenomenon of delamination caused by excessive stress at the corners of the interposer layer 10. On the other hand, the interposer layer 10 can be cut using a beve cut process, which facilitates processing.
[0084] Regarding the cross-sectional shape of the interposer 10, as shown in FIG4, in one possible embodiment, the cross-sectional shape of the interposer 10 is rectangular, wherein the cross-section is a plane intercepted along a surface parallel to the Z direction.
[0085] In another possible implementation, as shown in FIG5, the cross-sectional shape of the interposer 10 includes a trapezoidal shape. That is, the side surfaces 101 of the interposer 10 include inclined planes. For example, one side surface 101 of the interposer 10 includes an inclined plane; or both side surfaces 101 of the interposer 10 include inclined planes; or all three side surfaces 101 of the interposer 10 include inclined planes; or all four side surfaces 101 of the interposer 10 include inclined planes. Compared to an interposer 10 with a rectangular cross-sectional shape, the side surfaces 101 of the interposer 10 with a trapezoidal cross-sectional shape have a larger area, and therefore the surface area in contact with the first molding layer 30 is also larger, thereby increasing the bonding force between the two and thus better resisting the tensile force from the substrate 2.
[0086] Furthermore, the cross-sectional shape of the interposer 10 may include a trapezoidal shape, meaning that at least one layer of the interposer 10 has a trapezoidal cross-sectional shape. For example, as shown in FIG5, in this embodiment, two layers of the interposer 10 have trapezoidal cross-sectional shapes, and the remaining layer has a rectangular cross-sectional shape. Specifically, the silicon substrate 11 and the electrical connection layer 12 have trapezoidal cross-sectional shapes. In other embodiments, the silicon substrate 11 and the wiring layer 14 have trapezoidal cross-sectional shapes; or, the electrical connection layer 12 and the wiring layer 14 have trapezoidal cross-sectional shapes.
[0087] In other embodiments, the cross-sectional shape of the three layers in the interposer 10 is trapezoidal. Specifically, the cross-sectional shapes of the silicon substrate 11, the electrical connection layer 12, and the wiring layer 14 are all trapezoidal.
[0088] In other embodiments, one layer of the interposer 10 has a trapezoidal cross-sectional shape, while the other two layers have rectangular cross-sectional shapes. Specifically, the silicon substrate 11 has a trapezoidal cross-sectional shape; or, the electrical connection layer 12 has a trapezoidal cross-sectional shape; or, the wiring layer 14 has a trapezoidal cross-sectional shape.
[0089] In another possible implementation, as shown in FIG6, the side surface 101 of the interposer 10 includes an outwardly projecting arcuate surface 1010. For example, one side surface 101 of the interposer 10 includes an arcuate surface 1010; or, both sides 101 of the interposer 10 include arcuate surfaces 1010; or, all three sides 101 of the interposer 10 include arcuate surfaces 1010; or, all four sides 101 of the interposer 10 include arcuate surfaces 1010. Compared to an interposer 10 with a rectangular cross-sectional shape, the interposer 10 with arcuate surfaces 1010 on its side surface 101 has a larger side area, and therefore a larger surface area in contact with the first molding layer 30, thereby increasing the bonding force between the two and better resisting the tensile force from the substrate 2.
[0090] Furthermore, the inclusion of an outwardly projecting arcuate surface 1010 on the side surface 101 of the interposer 10 can mean that at least one layer of the interposer 10 has an arcuate surface 1010 on its side surface. For example, as shown in FIG6, in this embodiment, the side surface of one layer of the interposer 10 is an arcuate surface 1010; specifically, the side surface of the silicon substrate 11 is an arcuate surface 1010. In other embodiments, the side surfaces of other layers in the interposer 10 are arcuate surfaces 1010; for example, the side surface of the electrical connection layer 12 is an arcuate surface 1010; or, the side surface of the wiring layer 14 is an arcuate surface 1010.
[0091] In other embodiments, the sides of the two-layer structure in the interposer 10 are curved surfaces 1010. For example, the sides of the silicon substrate 11 and the electrical connection layer 12 are both curved surfaces 1010; or, the sides of the silicon substrate 11 and the wiring layer 14 are both curved surfaces 1010; or, the sides of the electrical connection layer 12 and the wiring layer 14 are both curved surfaces 1010.
[0092] In other embodiments, the three-layer structure of the intermediary layer 10 has curved sides 1010, that is, the entire side 101 is curved.
[0093] Furthermore, as shown in FIG7, the side surface 101 of the interposer 10 includes a plurality of arc surfaces 1010 arranged circumferentially. Thus, compared to the interposer 10 with a rectangular cross-sectional shape, the interposer 10 with the arc surfaces 1010 on its side surface 101 has a larger side area, and therefore the surface area in contact with the first molding layer 30 shown in FIG6 is also larger, thereby increasing the bonding force between the two and thus better resisting the tensile force from the substrate 2 shown in FIG6.
[0094] As shown in Figure 4, the intermediary layer 10 includes a first surface 13, the first surface 13 includes a first region 131 and a second region 132 surrounding the first region 131.
[0095] As shown in Figure 4, chip 1 also includes a third molding compound 50, which is disposed on the first region 131 and located on the side where the chip structure 20 is located. That is, the third molding compound 50 is disposed on a portion of the first surface 13. The third molding compound 50 covers the side of the chip structure 20 and part of the gap between adjacent chip structures 20.
[0096] As shown in Figure 4, a portion of the first molding compound 30 is disposed on the second region 132. The first molding compound 30 also encapsulates the third molding compound 50. In this way, on the one hand, the first molding compound 30 can provide better physical protection for the third molding compound 50 and the chip structure 20. On the other hand, the third molding compound 50 is usually more expensive than the first molding compound 30. When the third molding compound 50 is disposed on a portion of the first surface 13, it indicates that the area occupied by the third molding compound 50 on the interposer 10 is smaller, and the volume of the third molding compound 50 is smaller, thereby reducing the cost of the third molding compound 50 and thus reducing the cost of the chip 1.
[0097] As shown in Figure 3, the chip packaging structure 1042 may further include a clamping structure 4 and an adhesive 5. The clamping structure 4 is disposed on the substrate 2 via the adhesive 5, and the clamping structure 4 surrounds the second molding compound 3 and the first molding compound 30. There is a gap between the clamping structure 4 and the second molding compound 3. In one example, as shown in Figure 4, the clamping structure 4 may be a metal ring 41. In another example, as shown in Figure 8, the clamping structure 4 may be a metal cap 42. Moreover, a thermal pad 6 may be disposed between the metal cap 42 and the first molding compound 30 to conduct heat generated by the chip 1. Since the chip 1 needs to be disposed on the substrate 2 in a soldering direction during the fabrication of the chip packaging structure 1042, the substrate 2 may deform after soldering. When the chip packaging structure 1042 also includes the clamping structure 4, the clamping structure 4 can provide pressure to the substrate 2, thereby suppressing the deformation of the substrate 2, that is, suppressing the warping of the substrate 2, and thus improving the flatness of the substrate 2.
[0098] In other embodiments of this application, as shown in FIG. 9, the difference from the embodiment shown in FIG. 4 lies in the structure of the interposer 10. Specifically, as shown in FIG. 9, in this embodiment, the interposer 10 may include redistribution lines 15. The redistribution lines 15 include a dielectric structure 121 and a conductive structure 122 disposed within the dielectric structure 121, with the conductive structure 122 exposed from the top and bottom surfaces of the dielectric structure 121, respectively. The core structure 20 may be electrically connected to the conductive structure 122, thereby being electrically connected to the substrate 2 through the conductive structure 122 and the solder balls 40.
[0099] In other embodiments of this application, as shown in FIG10, the difference between this embodiment and the one shown in FIG4 lies in the structure of the interposer 10. Specifically, as shown in FIG10, in this embodiment, the interposer 10 may include conductive pillars 16 and a connector chip 17, a first wiring layer 18, and a second wiring layer 19 sequentially stacked between the substrate 2 and the third molding compound 50. The first wiring layer 18 is closer to the substrate 2 than the connector chip 17 and the second wiring layer 19. The conductive pillars 16 are located between the first wiring layer 18 and the second wiring layer 19. There is a gap between the connector chip 17 and the second wiring layer 19. Part of the pads 60 of the chip structure 20 are electrically connected to the connector chip 17 through the second wiring layer 19 and the conductive pillars 16, while the remaining pads 60 are electrically connected to the substrate 2 through the second wiring layer 19, the conductive pillars 16, and the first wiring layer 18.
[0100] As shown in Figure 10, a portion of the first molding compound 30 is located between the connector chip 17 and the second wiring layer 19, and the first molding compound 30 also covers the sides and bottom of the first wiring layer 18. The first molding compound 30 also covers the sides and top of the second wiring layer 19 where the connector chip 17 is not located. The first molding compound 30 also covers the sides and top of the connector chip 17. Thus, the connection area between the first molding compound 30 and the first wiring layer 18, the second wiring layer 19, and the connector chip 17 is relatively large, thereby increasing the bonding strength and better reducing delamination.
[0101] In other embodiments of this application, as shown in FIG11, the difference between this embodiment and the one shown in FIG10 lies in the structure of the connecting chip 17 in the interposer layer 10 and the manner of electrical connection between the chip structure 20 and the substrate 2. Specifically, as shown in FIG11, in this embodiment, a portion of the pads 60 of the chip structure 20 are electrically connected to the connecting chip 17 through the second wiring layer 19 and conductive pillars 16, and the connecting chip 17 is also electrically connected to the substrate 2. The remaining pads 60 of the chip structure 20 are electrically connected to the substrate 2 through the second wiring layer 19, conductive pillars 16, and the first wiring layer 18.
[0102] This application embodiment also provides a method for fabricating a chip package structure 1042, which can be applied to the chip package structure 1042 shown in FIG. 4. As shown in FIG. 12, the fabrication method includes:
[0103] S121 provides an intermediary layer structure.
[0104] As shown in Figure 13(a), the interposer structure 100 includes a silicon substrate structure 110 and an electrical interconnect structure 120 stacked together. The silicon substrate structure 110 has a through-silicon via 111. The electrical interconnect structure 120 includes a conductive structure 122, and the through-silicon via 111 is electrically connected to the conductive structure 122.
[0105] S122, bonding the intermediate layer structure to the carrier plate.
[0106] As shown in Figure 13(b), the interposer structure 100 is bonded to the carrier plate 501 via the adhesive layer 502, and the silicon substrate structure 110 is connected to the adhesive layer 502. The carrier plate 501 can be a glass carrier plate. In one example, the adhesive layer 502 may include an adhesive. In another example, the adhesive layer 502 may include a film.
[0107] S123, pads are fabricated on the interposer structure.
[0108] As shown in Figure 13(c), pads 60 are fabricated on the side of the interposer structure 100 away from the carrier plate 501.
[0109] S124 places the core structure on the pad.
[0110] As shown in Figure 13(d), the core structure 20 can be disposed on the side of the pad 60 opposite to the carrier board 501. The core structure 20 may include one or more core groups 21, each core group 21 including one or more cores 211, and the number of cores 211 in different core groups 21 may be different. When a core group 21 includes multiple cores 211, the multiple cores 211 may be stacked sequentially along the Z direction.
[0111] S125, create the third sealing layer.
[0112] As shown in Figure 13(e), a third molding layer 50 is fabricated on the side of the intermediate layer structure 100 away from the carrier plate 501. The third molding layer 50 wraps the bottom and side surfaces of the core particle structure 20, and its top surface is flush with the top surface of the core particle structure 20.
[0113] S126, cut the intermediate layer structure.
[0114] Intermediate layer structure 100 as shown in FIG13(e) is cut along the gap between adjacent core structures 20 to form trench 5021 and intermediate layer 10 as shown in FIG13(f). Intermediate layer 10 includes silicon substrate 11 and electrical connection layer 12. Part of trench 5021 is located between adjacent intermediate layers 10, and the remainder is located within adhesive layer 502.
[0115] S127, Fabricate the first molding layer structure.
[0116] As shown in Figure 14(a), a first molding layer structure 300 is fabricated on a carrier plate 501. A portion of the first molding layer structure 300 is located within a groove 5021 and wraps the side surface of the adhesive layer 502, the side surface of the intermediate layer 10, the side surface and top surface of the third molding layer 50, and the top surface of the core structure 20.
[0117] S128, Grinding the first molding layer structure.
[0118] The top surface of the first encapsulation layer 300 is ground, as shown in Figure 14(b), to expose the core structure 20.
[0119] S129, Remove the carrier board.
[0120] Debonding is performed to remove the carrier plate 501 and adhesive layer 502 shown in Figure 14(b) to obtain the structure shown in Figure 14(c).
[0121] S1210, for processing the first molding layer structure.
[0122] The first molding layer structure 300 is processed from the side of the first molding layer structure 300 away from the core particle structure 20 to obtain the structure shown in Figure 14(d). The distance d1 between the surface of the first molding layer structure 300 away from the core particle structure 20 and the core particle structure 20 is smaller than the distance d2 between the surface of the intermediate layer 10 away from the core particle structure 20 and the core particle structure 20.
[0123] S1211, grinding the first molding layer structure and silicon substrate.
[0124] The first molding layer structure 300 and the silicon substrate 11 shown in Figure 14(d) are polished, as shown in Figure 14(e), to expose the silicon via 111 in the silicon substrate 11.
[0125] S1212, solder balls are fabricated on the side of the interlayer away from the core structure.
[0126] As shown in Figure 15(a), a wiring layer 14 is first fabricated on the side of the interposer 10 away from the core structure 20, and then solder balls 40 are fabricated on the side of the wiring layer 14 away from the interposer 10. The solder balls 40 can be electrically connected to the interposer 10 through the wiring layer 14.
[0127] S1213, cut the first molding layer structure.
[0128] The first molding layer structure 300 can be cut along the gap between the chip structures 20 as shown in Figure 15(a) (i.e., the location of the cutting line in the figure) to obtain multiple chips 1 as shown in Figure 15(b).
[0129] S1214, placing the chip on the substrate.
[0130] As shown in Figure 15(c), chip 1 can be mounted on substrate 2, wherein solder balls 40 are connected to substrate 2.
[0131] S1215, Create the second molding layer.
[0132] As shown in Figure 15(d), a second molding compound 3 is fabricated on the substrate 2. A portion of the second molding compound 3 is located between the interposer 10 and the substrate 2 and wraps around the solder ball 40. A portion of the second molding compound 3 surrounds and wraps around a portion of the first molding compound 30.
[0133] S1216, The pressing structure is set on the substrate.
[0134] As shown in Figure 15(e), the clamping structure 4 can be fixed to the substrate 2. The clamping structure 4 is located on the same side as the chip 1 and surrounds the chip 1.
[0135] This application embodiment also provides another method for fabricating a chip package structure 1042, which can be applied to the chip package structure 1042 shown in FIG. 4. As shown in FIG. 16, the fabrication method includes:
[0136] S161 provides an intermediary layer structure.
[0137] Refer to step S121 in Figure 12.
[0138] S162, fabricate pads on the interposer structure.
[0139] As shown in Figure 17(b), pads 60 are fabricated on the side of the electrical connection layer structure 120 in the interposer layer structure 100.
[0140] S163, the intermediate layer structure is bonded to the first carrier.
[0141] As shown in Figure 17(c), the interposer structure 100 is bonded to the first substrate 503 through the first adhesive layer 504, and the silicon substrate structure 110 in the interposer structure 100 is connected to the first adhesive layer 504, and the pads 60 are embedded in the first adhesive layer 504.
[0142] S164, grinding interlayer structure.
[0143] The interposer structure 100 shown in Figure 17(c) is ground from the side opposite to the first substrate 503, as shown in Figure 17(d), to expose the through silicon via 111.
[0144] S165, solder balls are fabricated on the side of the interlayer structure away from the first carrier plate.
[0145] As shown in Figure 17(e), a wiring layer structure 140 is first fabricated on the side of the interposer structure 100 opposite to the first carrier board 503, and then solder balls 40 are fabricated on the side of the wiring layer structure 140 opposite to the interposer structure 100. The solder balls 40 can be electrically connected to the interposer structure 100 through the wiring layer structure 140.
[0146] S166, Remove the first carrier board and bond the interlayer structure and solder balls to the second carrier board 505.
[0147] First, the first carrier plate 503 and the first adhesive layer 504 shown in Figure 17(e) can be removed. Then, as shown in Figure 17(f), the interlayer structure 100 and the solder ball 40 are bonded to the second carrier plate 505 through the second adhesive layer 506, with the solder ball 40 facing the second carrier plate 505 and embedded in the second adhesive layer 506.
[0148] S167 places the core structure on the pad.
[0149] As shown in Figure 18(a), the core structure 20 can be set on the side of the pad 60 away from the interposer structure 100 by welding.
[0150] S168, Create the third molding layer.
[0151] As shown in Figure 18(b), a third molding layer 50 is fabricated on the side of the intermediate layer structure 100 away from the second carrier plate 505. The third molding layer 50 wraps the bottom and side surfaces of the core particle structure 20, and its top surface is flush with the top surface of the core particle structure 20.
[0152] S169, cut the intermediate layer structure.
[0153] Intermediate layer structure 100 and wiring layer structure 140 are cut along the gap between adjacent core structures 20 (where the cut line is located) as shown in Figure 18(b) to form an intermediate layer 10 as shown in Figure 18(c). The intermediate layer 10 includes a silicon substrate 11, an electrical connection layer 12 and a wiring layer 14.
[0154] S1610, fabricating the first molding layer structure.
[0155] As shown in Figure 18(d), a first molding layer structure 300 is fabricated on the second carrier plate 505. The first molding layer structure 300 wraps the side surface of the second adhesive layer 506, the side surface of the intermediate layer 10, the side surface and top surface of the third molding layer 50, and the top surface of the core structure 20.
[0156] S1611, grinding the first molding layer structure.
[0157] The top surface of the first encapsulation layer 300 is ground, as shown in Figure 18(e), to expose the core structure 20.
[0158] S1612, Remove the second carrier board.
[0159] Debonding is performed to remove the second carrier plate 505 and the second adhesive layer 506 shown in Figure 18(e) to obtain the structure shown in Figure 15(a).
[0160] S1613, cut the first molding layer structure.
[0161] The first molding layer structure 300 can be cut along the gap between the chip structures 20 to obtain multiple chips 1 as shown in Figure 15(b).
[0162] S1614, placing the chip on the substrate.
[0163] As shown in Figure 15(c), chip 1 can be mounted on substrate 2, wherein pad 60 is connected to substrate 2.
[0164] S1615, Create the second molding layer.
[0165] As shown in Figure 15(d), a second molding compound 3 is fabricated on the substrate 2. A portion of the second molding compound 3 is between the intermediate layer 10 and the substrate 2 and encapsulates the solder ball 40. A portion of the second molding compound 3 surrounds and encapsulates a portion of the first molding compound 30.
[0166] S1616, the pressing structure is set on the substrate.
[0167] As shown in Figure 15(e), the clamping structure 4 can be fixed to the substrate 2. The clamping structure 4 is located on the same side as the chip 1 and surrounds the chip 1.
[0168] This application also provides a method for fabricating a chip package structure 1042, which can be applied to the chip package structure 1042 shown in FIG11. As shown in FIG19, the fabrication method includes:
[0169] S191, fabricate the first wiring layer structure on the carrier board.
[0170] As shown in Figure 20(a), a first wiring layer structure 180 is fabricated on one side of the carrier board 501.
[0171] S192, the connection chip is placed on the first wiring layer structure.
[0172] As shown in Figure 20(b), multiple connecting chips 17 can be respectively disposed on the side of the first wiring layer structure 180 away from the carrier board 501, and conductive pillars 16 are made on the side of the first wiring layer structure 180 and the connecting chips 17 away from the carrier board 501.
[0173] S193, fabricate the first sub-molding layer structure on the first wiring layer structure.
[0174] As shown in Figure 20(c), a first sub-molding layer structure 301 is fabricated on the side of the first wiring layer structure 180 opposite to the carrier board 501. The first sub-molding layer structure 301 encapsulates the connecting chip 17 and the conductive pillar 16.
[0175] S194, fabricate a second wiring layer structure on the first sub-molding layer structure.
[0176] As shown in Figure 20(d), a second wiring layer structure 190 is fabricated on the side of the first sub-molding layer structure 301 away from the carrier plate 501. The conductive structure 122 in the second wiring layer structure 190 is in contact with and electrically connected to the conductive post 16.
[0177] S195, the core structure is placed on the second wiring layer structure and a third molding layer is formed.
[0178] As shown in Figure 20(e), multiple core structures 20 can be first placed on the second wiring layer structure 190. Next, a third molding layer 50 is formed on the side of the second wiring layer structure 190 away from the carrier board 501. The third molding layer 50 covers the bottom and side surfaces of the core structure 20, and its top surface is flush with the top surface of the core structure 20.
[0179] S196, cut the first wiring layer structure, the first sub-molding layer structure and the second wiring layer structure.
[0180] Cut the first wiring layer structure 180, the first sub-molding layer structure 301 and the second wiring layer structure 190 along the gap between adjacent core structures 20 as shown in Figure 20(e) to obtain the first wiring layer 18, the first sub-molding layer 302 and the second wiring layer 19 as shown in Figure 20(f).
[0181] S197, fabricate the second sub-molding layer structure.
[0182] As shown in Figure 21(a), a second sub-molding layer structure 303 is fabricated on the carrier board 501. The second sub-molding layer structure 303 covers the sides of the first wiring layer 18, the sides of the second wiring layer 19, and the sides of the first sub-molding layer 302, and also covers the sides and top surface of the third molding layer 50, as well as the top surface of the core structure 20. The material of the second sub-molding layer structure 303 and the first sub-molding layer 302 can be the same, and the two together constitute the first molding layer structure 300.
[0183] S198, Grinding the first molding layer structure.
[0184] The top surface of the first encapsulation layer structure 300 is ground, as shown in Figure 21(b), to expose the core structure 20.
[0185] S199, solder balls are fabricated on the first wiring layer.
[0186] As shown in Figure 21(c), solder balls 40 are fabricated on the side of the first wiring layer 18 away from the core structure 20.
[0187] S1910, cut the first molding layer structure.
[0188] The first molding layer structure 300 can be cut along the gap between the chip structures 20 as shown in Figure 21(c) (where the cutting line is located) to obtain multiple chips 1 as shown in Figure 21(d).
[0189] S1911, placing the chip on the substrate.
[0190] As shown in Figure 22(a), chip 1 can be mounted on substrate 2, wherein solder balls 40 are connected to substrate 2.
[0191] S1912, Create the second molding layer.
[0192] As shown in Figure 22(b), a second molding compound 3 is fabricated on the substrate 2. A portion of the second molding compound 3 is located between the interposer 10 and the substrate 2 and wraps around the solder ball 40. A portion of the second molding compound 3 also surrounds and wraps around a portion of the first molding compound 30.
[0193] S1913, the pressing structure is set on the substrate.
[0194] As shown in Figure 22(c), the pressure block structure 4 can be fixed to the substrate 2. The pressure block structure 4 is located on the same side as the chip 1 and surrounds the chip 1.
[0195] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A chip packaging structure, characterized in that, include: substrate; The chip includes an interposer, a chip structure, and a first molding compound. The interposer is disposed on the substrate, the chip structure is disposed on the side of the interposer away from the substrate, and the first molding compound at least partially covers multiple sides of the interposer. A second molding layer is disposed on the substrate, a portion of the second molding layer is located between the interlayer and the substrate, and a portion of the second molding layer is located between the first molding layer and the substrate. The coefficient of thermal expansion of the first molding layer is greater than that of the interlayer and less than that of the second molding layer.
2. The chip packaging structure according to claim 1, characterized in that, At least a portion of the length and / or width dimensions of the intermediate layer gradually increase from one side toward the core structure to the other side; The length and / or width dimensions of at least a portion of the surface of the first molding layer that contacts the intermediate layer gradually decrease from one side toward the core structure to the other.
3. The chip packaging structure according to claim 1 or 2, characterized in that, The cross-sectional shape of the interposer includes a trapezoid, and the cross-section is a plane cut along a surface parallel to the thickness direction of the chip.
4. The chip packaging structure according to claim 1 or 2, characterized in that, The sides of the intermediary layer include outwardly projecting curved surfaces.
5. The chip packaging structure according to claim 1 or 2, characterized in that, The sides of the intermediary layer include multiple arc surfaces arranged circumferentially.
6. The chip packaging structure according to any one of claims 1-5, characterized in that, The chip also includes a third molding layer, which is disposed on one side of the interposer and encapsulates the chip structure. The first molding layer also encapsulates the third molding layer.
7. The chip packaging structure according to any one of claims 1-6, characterized in that, The intermediate layer includes a first surface, the first surface including a first region and a second region surrounding the first region; The chip further includes a third molding compound layer, which is disposed on the first region, and a portion of the first molding compound layer is disposed on the second region.
8. The chip packaging structure according to any one of claims 1-7, characterized in that, The material of the first molding compound includes epoxy resin molding compound.
9. The chip packaging structure according to any one of claims 1-8, characterized in that, The second molding layer surrounds and encapsulates a portion of the first molding layer.
10. The chip packaging structure according to any one of claims 1-9, characterized in that, The intermediate layer includes a first wiring layer, a connecting chip, and a second wiring layer sequentially stacked between the substrate and the chip structure. The first wiring layer is closer to the substrate, and the second wiring layer has a gap with the connecting chip. The first molding compound also covers the side of the first wiring layer, the side of the second wiring layer and the side of the connection chip, and a portion of the first molding compound is located between the connection chip and the second wiring layer.
11. The chip packaging structure according to any one of claims 1-10, characterized in that, Both the first molding layer and the second molding layer are made of organic materials.
12. A method for fabricating a chip packaging structure, characterized in that, include: A chip structure is provided, the chip structure including an interposer structure and a plurality of chip structures spaced apart on the interposer structure; Grooves are formed in the intermediate layer structure, the grooves being located between adjacent core structures; A first molding compound structure is fabricated, wherein at least a portion of the first molding compound structure is located within the groove; Cut the first molding layer structure and the interposer structure along the location of the groove to obtain a chip, the chip including an interposer, a chip structure and a first molding layer; The chip is disposed on a substrate and a second molding layer is formed around the chip. The coefficient of thermal expansion of the first molding layer is greater than that of the interlayer and less than that of the second molding layer.
13. The manufacturing method according to claim 12, characterized in that, The core structure further includes a plurality of third molding layers spaced apart on one side of the intermediate layer structure, the plurality of third molding layers surrounding the plurality of core structures; The fabrication of the first molding layer structure includes: The first molding layer structure is formed within the groove and between the adjacent third molding layer.
14. A circuit board assembly, characterized in that, The invention includes a circuit board and a chip packaging structure as described in any one of claims 1-11, wherein the chip packaging structure is disposed on the circuit board.
15. An electronic device, characterized in that, It includes a housing and the circuit board assembly of claim 14, the circuit board assembly being disposed within the housing.