Time synchronization method and apparatus, and management controller, medium and product

Abstract

Disclosed in the present application are a time synchronization method and apparatus, and a management controller, a medium and a product. A processor, a first clock source and a second clock source are deployed in a management controller, wherein the time precision of the first clock source is higher than that of the second clock source. In response to detecting that an external network time protocol server is in an unavailable state, a clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates current time data on the basis of the clock signal output by the first clock source, and monitors a frequency deviation of the first clock source in real time. In the case of a large frequency deviation, which indicates that the precision of the clock signal of the first clock source has degraded, a switch is made to use an internal phase-locked loop of the second clock source to provide a clock signal, and the current time data is updated on the basis of the clock signal. By means of a dynamic master-slave clock switching mechanism involving the first clock source and the second clock source, it is ensured that even when the external network time protocol server is unavailable, precise time information can still be provided for the server by means of the management controller.

Description

Time synchronization methods, devices, management controllers, media and products

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510386741.6, filed on March 28, 2025, entitled "Time Synchronization Method, Apparatus, Management Controller, Medium and Product", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of server design technology, and in particular to time synchronization methods, devices, management controllers, media, and products. Background Technology

[0004] In computer systems, servers are the core of the entire network system and computing platform, storing much important data. The Baseboard Management Controller (BMC) acts as the server's steward, providing overall control. In data centers, industrial automation, and communication management controllers, time synchronization accuracy directly impacts server system log consistency, transaction processing order, and the accuracy of fault diagnosis.

[0005] In related technologies, BMC primarily synchronizes time with an external NTP server via a Network Time Protocol (NTP) client mode. However, this method relies on the external network conditions; when the external network fails, it cannot provide accurate time information to the server. Therefore, how to provide accurate time information to the server when the external network fails is a pressing problem that needs to be solved. Summary of the Invention

[0006] This application provides a time synchronization method, apparatus, management controller, medium, and product to at least solve the problem in the related art of being unable to provide accurate time information to the server when the external network fails.

[0007] This application provides a time synchronization method applied to a management controller included in a target server. The management controller includes a processor, a first clock source, and a second clock source. The time accuracy of the first clock source is higher than that of the second clock source. The method is executed by the processor and includes:

[0008] In response to the detection that an external network time protocol server is unavailable, it enters timekeeping mode;

[0009] In timekeeping mode, the clock signal output by the first clock source is transmitted to the second clock source;

[0010] Control the second clock source to update the current time data according to the clock signal output by the first clock source; and

[0011] In response to the detection that the frequency deviation of the first clock source is not within the preset deviation range, the second clock source is controlled to update the current time data using the clock signal output by the phase-locked loop.

[0012] In some embodiments, the first clock source includes at least one of a temperature-compensated crystal oscillator and a temperature-controlled crystal oscillator; and the second clock source is a real-time clock.

[0013] In some embodiments, before entering the timekeeping mode step in response to detecting that an external network time protocol server is unavailable, the method further includes:

[0014] The management controller sends a time query request to the Network Time Protocol server; and

[0015] If no valid response is received or the response times out after several consecutive attempts, it is determined that the external network time protocol server is unavailable.

[0016] In some embodiments, before entering the timekeeping mode step in response to detecting that an external network time protocol server is unavailable, the method further includes:

[0017] The management controller detects the connectivity status of physical links through the underlying network interface; and

[0018] In response to the detection of a physical link disconnection through the network interface, it is determined that the external network time protocol server is unavailable.

[0019] In some embodiments, enabling the processor's external network time protocol server functionality includes:

[0020] The firmware layer of the management controller stores the software program that implements the functionality of an external network time protocol server; and

[0021] The processor's external network time protocol server function is enabled by launching a software program.

[0022] In some embodiments, the external network time protocol server is a dedicated time server deployed in the network to provide standard time data.

[0023] This application also provides a time synchronization device applied to a management controller included in a target server. The management controller includes a processor, a first clock source, and a second clock source. The time accuracy of the first clock source is higher than that of the second clock source. The device is deployed in the processor and includes:

[0024] The monitoring module is used to enter timekeeping mode in response to the detection that an external network time protocol server is unavailable;

[0025] The output module is used to control the transmission of the clock signal output by the first clock source to the second clock source in timekeeping mode.

[0026] The control module is used to control the second clock source to update the current time data according to the clock signal output by the first clock source; and

[0027] The update module is used to control the second clock source to update the current time data using the clock signal output by the phase-locked loop in response to the detection that the frequency deviation of the first clock source is not within the preset deviation range.

[0028] This application also provides a management controller, comprising: a first clock source; a second clock source, wherein the time accuracy of the first clock source is higher than that of the second clock source; a memory for storing a computer program; and a processor for implementing the steps of any of the above time synchronization methods when executing the computer program.

[0029] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described time synchronization methods.

[0030] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described time synchronization methods.

[0031] This application deploys a processor, a first clock source, and a second clock source in the management controller. The first clock source has a higher time accuracy than the second clock source. In response to detecting that an external network time protocol server is unavailable, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source and monitors the frequency deviation of the first clock source in real time. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the system switches to using the internal phase-locked loop of the second clock source to provide the clock signal and updates the current time data based on the clock signal. This is achieved through a master-slave clock dynamic switching mechanism between the first and second clock sources. Attached Figure Description

[0032] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 is a schematic diagram of the hardware architecture for a time synchronization method provided in an embodiment of this application;

[0034] Figure 2 is a flowchart illustrating one of the time synchronization methods provided in this application embodiment;

[0035] Figure 3 is a second schematic flowchart of a time synchronization method provided in an embodiment of this application;

[0036] Figure 4 is a third schematic flowchart of a time synchronization method provided in an embodiment of this application;

[0037] Figure 5 is a fourth flowchart illustrating a time synchronization method provided in an embodiment of this application;

[0038] Figure 6 is a schematic diagram of a time synchronization device provided in an embodiment of this application;

[0039] Figure 7 is a schematic diagram of the structure of a management controller provided in an embodiment of this application;

[0040] Figure 8 is a schematic diagram of the structure of a non-volatile computer-readable storage medium provided in an embodiment of this application;

[0041] Figure 9 is a schematic diagram of the structure of a computer program product provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0043] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or management controller that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or management controller. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0044] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0045] Terminology Explanation:

[0046] BMC: Baseboard Management Controller, is a server-specific management controller used to manage and monitor the server's hardware status and operation. The BMC is typically a standalone microcontroller running on the server motherboard and communicates with other server hardware components (such as the Central Processing Unit, CPU, memory, hard drive, etc.) via a dedicated bus (I / O bus). 2 C. System Management Bus (SMBus) connection. The BMC has its own firmware and network interface, and can run independently of the server operating system.

[0047] RTC: Real-Time Clock, used to provide a precise time reference for the management controller. The RTC typically operates independently of the processor and continues timing even when the management controller is powered off or in sleep mode.

[0048] TCXO (Temperature Compensated Crystal Oscillator) is a crystal oscillator that reduces the impact of temperature changes on its oscillation frequency through a built-in temperature compensation circuit. TCXOs maintain high frequency stability over a wide temperature range and are widely used in applications requiring high frequency accuracy. The working principle of a TCXO is as follows: a temperature sensor monitors the ambient temperature and converts this information into a digital signal. This signal is used to adjust the load capacitance in the oscillation circuit, thereby compensating for frequency shifts caused by temperature changes. This compensation mechanism allows the TCXO to provide a stable frequency output under different temperature conditions.

[0049] I 2 C-bus: Inter-Integrated Circuit, a serial communication protocol bus primarily used in low-speed communication scenarios, such as communication between sensors, RTCs, and other management controllers and microcontrollers or microprocessors. 2 The C bus uses only two lines for communication: SDA (Serial Data) and SCL (Serial Clock).

[0050] NTP (Network Time Protocol) is a network protocol used to synchronize the clocks of computer systems. It is widely used in the Internet and enterprise networks to ensure time consistency between management controllers. NTP transmits time information on port 123 via the User Datagram Protocol (UDP), achieving high-precision time synchronization and tolerating network latency and clock drift.

[0051] RDMA (Remote Direct Memory Access) is a technology that allows direct memory-to-memory data transfer between two management controllers without the intervention of the CPU, cache, and operating system. This technology significantly reduces latency, decreases CPU load, and improves data transfer efficiency, making it particularly suitable for high-performance computing scenarios.

[0052] PPS: Pulse Per Second. The PPS alignment mechanism is a high-precision time synchronization technique. The PPS signal is a precise time synchronization signal, typically generated by a high-precision clock source, producing one pulse per second, with the rising edge precisely corresponding to an integer second in Coordinated Universal Time (UTC). The core of the PPS alignment mechanism is to adjust the local clock to achieve high-precision synchronization by comparing the difference between the PPS signal and the local clock.

[0053] In related technologies, there are two main time synchronization schemes. One scheme involves most current BMCs using an internal low-precision crystal oscillator as the clock source, with a frequency accuracy range between ±50ppm and ±100ppm, synchronized with an external NTP server using the NTP protocol. This scheme has a low implementation cost but significant limitations. First, it is highly dependent on the network; the NTP synchronization process is greatly affected by network latency, jitter, and interruptions. For example, when the network is unstable, the NTP client cannot obtain time updates in a timely manner, causing the local clock to continuously accumulate offsets due to the inherent error of the low-precision crystal oscillator, with synchronization errors potentially exceeding 10 milliseconds. Furthermore, the synchronization interval of the NTP protocol itself is typically on the order of minutes; within the synchronization gap, the frequency deviation of the crystal oscillator directly translates into time errors. More seriously, the performance of low-precision crystal oscillators is easily affected by ambient temperature fluctuations; a 10°C change in temperature can introduce a frequency offset of ±5ppm. If the server to which the BMC belongs operates in an environment with large temperature differences, such as the alternating hot and cold aisle areas of a data center, the long-term accumulated time error will be further amplified, even affecting the reliability of basic functions such as system log recording and task scheduling. For time-sensitive scenarios such as financial transactions and industrial control, such errors have exceeded the acceptable range.

[0054] Another approach involves using an independent high-precision clock source, such as an Oven-Controlled Crystal Oscillator (OCXO) or an atomic clock, in conjunction with the PTP protocol for time synchronization. OCXOs achieve crystal frequency stability to below ±0.1ppm through temperature control, while atomic clocks can reach nanosecond-level accuracy, enabling sub-microsecond synchronization when combined with the PTP protocol. However, this approach faces challenges in both hardware integration and cost. OCXOs require additional circuitry to maintain a constant temperature environment, typically consuming over 1W, and are physically large, making them difficult to embed in space-constrained embedded modules like BMCs. Atomic clocks, on the other hand, cost tens of thousands of yuan and are only suitable for specialized applications.

[0055] The specific application environment architecture or specific hardware architecture on which the execution of the time synchronization method depends is described here.

[0056] This application provides a hardware architecture for operating a time synchronization method. Referring to FIG1, the hardware architecture includes a target server cluster 100 consisting of a target server 101 and at least one external server (in this embodiment, the external servers include server 102, ..., server N). The target server 101 includes a management controller 11. The management controller 11 includes a processor 111, a first clock source 112, and a second clock source 113. In response to detecting that an external network time protocol server is unavailable, the processor 111 enters a timekeeping mode. In timekeeping mode, the processor 111 controls the clock signal output by the first clock source 112 to be transmitted to the second clock source 113, and controls the second clock source 113 to update the current time data according to the clock signal output by the first clock source 112. In response to detecting that the frequency deviation of the first clock source 112 is not within a preset deviation range, the processor 113 controls the second clock source 113 to update the current time data using the clock signal output by a phase-locked loop. Through the master-slave clock dynamic switching mechanism of the first clock source 112 and the second clock source 113, it is ensured that even when the external network time protocol server is unavailable, the management controller 11 can still act as an external network time protocol server to provide accurate time information to the target server 101.

[0057] Furthermore, referring to Figure 1, the target server 101 also includes at least one internal component (in this embodiment, the target server 101 includes internal components 12, 13, and 14 as an example). When the external network time protocol server function of the processor 111 is enabled, the time data output from the second clock source is synchronized to at least one internal component via the integrated circuit bus. In this embodiment, by using the processor 111 of the target server 101 as a primary NTP server to provide time synchronization services to other components of the target server 101, the dependence on external NTP requests is reduced, and the internal network time synchronization latency is significantly reduced.

[0058] Furthermore, referring to Figure 1, the target server cluster 100 includes a target server 101 and at least one external server (in this embodiment, the external servers include server 102, ..., server N). When the processor's external network time protocol server function is enabled, the time data output by the second clock source 113 of the target server 101 is synchronized to the other external servers of the target server cluster 100. In this embodiment, by using the processor 111 of the target server 101 as an NTP server to provide time synchronization services to other servers within the local area network, the problem of inaccurate time synchronization of server clusters in a network isolation environment is solved.

[0059] To address the aforementioned issues, embodiments of this application provide a time synchronization method, and the method is described in detail below in conjunction with its execution flow.

[0060] The time synchronization method provided in this disclosure is mainly applied in a management controller, which is a server component with network service functions, including but not limited to a BMC, an integrated management module, an NTP server, network management software, a virtualization management module, and a security module. These components ensure the efficient operation and management of the server by providing network connectivity, management functions, time synchronization, storage access, and security functions. The first clock source is a high-precision clock source, including but not limited to a temperature-compensated crystal oscillator (TCXO) and a temperature-controlled crystal oscillator (OCXO). The time accuracy of the second clock source is slightly lower than that of the first clock source, and includes but is not limited to various types of clock units, such as a real-time clock (RTC).

[0061] In the following disclosed embodiments, the management controller is a BMC, the first clock source is a temperature-compensated crystal oscillator, and the second clock source is a real-time clock. The BMC includes a temperature-compensated crystal oscillator, a real-time clock, and a processor.

[0062] Among them, the temperature-compensated crystal oscillator (TCXO) is a clock source that reduces the impact of frequency variations with temperature by incorporating a built-in temperature sensor and compensation circuitry. Its core principle is to monitor the ambient temperature in real time and dynamically adjust the crystal oscillator's output frequency based on a pre-stored temperature-frequency characteristic curve, thereby improving frequency stability to within the range of ±0.5ppm to ±2ppm. In a BMC, the TCXO provides the system with a highly stable reference clock signal, significantly reducing the cumulative time error caused by temperature fluctuations.

[0063] A real-time clock is a standalone timing module, typically powered by a backup battery, ensuring continuous recording of time data, such as year, month, day, hour, minute, and second, even when the BMC mains power is disconnected. The real-time clock integrates a low-frequency crystal oscillator, and its time accuracy depends on the stability of the crystal oscillator.

[0064] The processor is the core processor of the BMC, responsible for running firmware, managing hardware resources, and executing time synchronization logic.

[0065] Furthermore, the temperature-compensated crystal oscillator and real-time clock are integrated into the BMC's hardware layer, wherein the temperature-compensated crystal oscillator communicates with the processor via I / O. 2 The clock unit is connected to the processor via the C bus. 2 C-bus connection enables high-precision time synchronization between server components.

[0066] By integrating a clock unit into the BMC hardware layer and working in conjunction with a temperature-compensated crystal oscillator as a high-precision clock source, and utilizing I... 2 The C-speed bus connects to the BMC processor to achieve high-precision time synchronization between server components.

[0067] Using BMC related I 2 The C-bus connects the temperature-compensated crystal oscillator and the clock unit, eliminating the need for additional dedicated clock wiring and reducing the cost of board modification.

[0068] Referring to Figure 2, the time synchronization method provided in this embodiment includes the following steps:

[0069] S21. In response to the detection that the external network time protocol server is unavailable, enter timekeeping mode.

[0070] An external NTP server can be understood as a dedicated time server deployed in the network, providing standard time data according to the NTP protocol. Its role is to provide an authoritative time reference for the BMC, typically communicating via UDP port 123. Its externality lies in its physical location being independent of the local management controller and dependent on network link reachability.

[0071] An unavailable state refers to a state where the NTP server cannot respond to requests normally. This may be caused by network interruptions (such as routing failures or firewall blocking), server downtime, high latency (exceeding the protocol's tolerance threshold), or configuration errors (such as IP address changes). In an unavailable state, the BMC cannot obtain time updates via the NTP protocol, and the local clock will become detached from the external time base.

[0072] The timekeeping mode refers to the mode in which the BMC continues to provide time synchronization services by relying on a local high-precision crystal oscillator or RTC (Real-Time Clock) when it loses an external high-precision time source (such as the Global Positioning System (GPS) or BeiDou satellite signals). Timekeeping mode is a local time preservation mechanism whose core objective is to reduce the accumulation of errors caused by external synchronization interruptions. It can also be understood as the generation of time data through the combined efforts of hardware and / or software integrated within the BMC. The hardware includes providing a low-drift clock signal using a TCXO or OCXO, and the software algorithm includes drift prediction and real-time compensation based on historical synchronization data.

[0073] In some embodiments, detecting that an external NTP server is unavailable includes: the BMC periodically sending time query requests (NTP messages) to the NTP server, and determining that the external NTP server is unavailable in response to multiple consecutive failures to receive a valid response or response timeout.

[0074] In some embodiments, detecting that an external NTP server is unavailable includes: the BMC detects the physical link connectivity status through the underlying network interface, and in response to detecting that the physical link connection is disconnected (such as the network cable being unplugged) through the network interface, determines that the external NTP server is unavailable without the need for upper-layer protocol detection.

[0075] In some embodiments, in response to the external NTP server being available, time data provided by the external NTP server is obtained; in response to the external NTP server being unavailable, timekeeping mode is entered, subsequent processes are executed, and accurate time data is obtained.

[0076] In some embodiments, BMC network configuration and NTP synchronization can be achieved in the following ways:

[0077] Enable the BMC network interface and choose either static IP address binding or DHCP dynamic acquisition according to actual needs. Specify the external NTP server address in the BMC system settings to ensure that the BMC's own time is accurately synchronized with the standard time, and write the standard time into the clock unit.

[0078] By following the steps above, we can ensure that the BMC network interface is working properly and achieve high-precision time synchronization through an external authoritative NTP server. At the same time, we can write the standard time into the clock unit to ensure the accuracy and reliability of the server time.

[0079] In some embodiments, before performing step S21 (entering timekeeping mode in response to detecting that an external network time protocol server is unavailable), the following steps may also be performed:

[0080] After detecting that the target server is powered on, the timestamp is obtained from the second clock source.

[0081] The timestamp is transmitted to the first clock source, and the first clock source is controlled to generate and output a clock signal with the timestamp as the initial time reference.

[0082] In some embodiments, before utilizing the temperature-compensated crystal oscillator and clock unit to provide high-precision time data, the temperature-compensated crystal oscillator and clock unit need to be initialized upon server power-up. Specifically, after detecting that the target server has powered on, a timestamp is obtained from the clock unit and transmitted to the temperature-compensated crystal oscillator, enabling the temperature-compensated crystal oscillator to generate and output a clock signal using the timestamp as an initial time reference. The clock unit has a built-in independent power supply, which can continuously maintain a 32.768kHz clock signal during system power outages, with its error normally controllable within ±5ppm.

[0083] Here, the target server refers to the server belonging to the baseboard management controller, which can be a computer, network management controller, or other electronic system. Server power-on refers to the process of connecting the server to power; this is the physical condition that triggers subsequent operations and belongs to the initial stage of system startup.

[0084] A timestamp is precise time data generated by a clock unit, reflecting the absolute time value of the moment the management controller is powered on, and serving as a time reference for system synchronization.

[0085] In some embodiments, after the server is powered on, the temperature-compensated crystal oscillator starts working first. When the temperature-compensated crystal oscillator is working, the internal crystal oscillator generates an oscillation signal. Because the physical properties of a crystal are affected by temperature, its frequency will drift with changes in temperature. The temperature-compensated crystal oscillator incorporates a temperature compensation circuit that monitors the ambient temperature in real time and adjusts the oscillation frequency according to a pre-stored temperature-frequency characteristic curve, ensuring that the output frequency remains relatively stable over a wide temperature range, with a frequency stability ≤ ±0.5ppm.

[0086] While the temperature-compensated crystal oscillator is powered on, the BMC communicates via I... 2The C bus reads the initial time base stored in the real-time clock. The real-time clock is transmitted via I... 2 The C interface provides a second-level timestamp to the BMC as an initial time reference before the temperature-compensated crystal oscillator frequency stabilizes, ensuring time continuity during the cold start phase. The temperature-compensated crystal oscillator transmits the stabilized clock signal through I... 2 The SCL line of the C bus transmits data to the BMC processor, providing the BMC with a high-precision reference clock signal.

[0087] S22. In timekeeping mode, control the clock signal output by the first clock source to be transmitted to the second clock source.

[0088] The first clock source is a temperature-compensated crystal oscillator, and the second clock source is a clock unit.

[0089] The timekeeping mode refers to the system's operation in which it maintains time accuracy autonomously by relying on a local clock source when an external NTP server fails. In this mode, the BMC stops requesting time synchronization from the external server and instead continues to keep track of time through internal highly stable hardware such as the TCXO and algorithm compensation mechanisms.

[0090] The clock signal refers to the periodic electrical signal generated by the TCXO. It can be a square wave or a sine wave, serving as the time reference for the BMC.

[0091] In timekeeping mode, the clock signal output by the temperature-compensated crystal oscillator is sent to the clock input pin of the clock unit via a buffer, driving the internal counter of the clock unit to increment in order to generate accurate time data.

[0092] Controlling the transmission of the clock signal output by the temperature-compensated crystal oscillator to the clock unit may include outputting a control command to the temperature-compensated crystal oscillator, which instructs the temperature-compensated crystal oscillator to act as the master clock source and transmit its output clock signal to the clock unit.

[0093] In some embodiments, a temperature compensation circuit is provided in the temperature-compensated crystal oscillator. The temperature compensation circuit is used to detect the ambient temperature in real time and compensate the frequency of the temperature-compensated crystal oscillator based on the ambient temperature and a pre-stored temperature-frequency specific curve.

[0094] A temperature-compensated crystal oscillator is an electronic component that maintains frequency stability through temperature compensation technology. Its internal components include a crystal oscillator and a temperature compensation circuit. The crystal oscillator generates an oscillation signal based on the piezoelectric effect, but its frequency drifts with changes in ambient temperature. The temperature compensation circuit, as a key compensation module, includes a temperature detection unit, a storage unit, and a compensation signal generation unit.

[0095] Ambient temperature refers to the real-time temperature of the operating environment of the oscillator and is a major external variable affecting frequency stability. The temperature detection unit collects ambient temperature data in real time through an integrated temperature sensor, generating a temperature detection signal. The pre-stored temperature-frequency specific curve is a set of compensation parameters calibrated experimentally, usually stored in memory in the form of a table or function, reflecting the compensation values ​​required for this type of crystal oscillator at different temperature points.

[0096] In some embodiments, the temperature detection unit first acquires the ambient temperature parameter as the input to the compensation system. Secondly, the compensation algorithm calls the stored temperature-frequency correspondence data to calculate the compensation coefficient corresponding to the current temperature. Finally, a compensation signal is generated through digital-to-analog conversion or a variable capacitor network and superimposed on the oscillation loop to offset temperature drift. The entire system forms a closed-loop control, using a feedforward compensation mechanism to correct the oscillation frequency in real time, stabilizing the output frequency near the nominal value. Each functional module coordinates data acquisition, parameter matching, and physical quantity adjustment through a signal chain, ensuring that temperature changes and compensation actions remain synchronized in real time.

[0097] Because the physical properties of crystals are affected by temperature, their frequency will drift with changes in temperature. Temperature-compensated crystal oscillators have a built-in temperature compensation circuit that monitors the ambient temperature in real time and adjusts the oscillation frequency according to a pre-stored temperature-frequency characteristic curve, so that the output frequency remains relatively stable over a wide temperature range, with a frequency stability of ≤±0.5ppm.

[0098] The high-stability clock source of the temperature-compensated crystal oscillator is calibrated in real time through a temperature compensation circuit, which controls the local clock frequency stability within ±0.5ppm, thereby improving the timing accuracy of the NTP server from the millisecond level to the sub-millisecond level, meeting the microsecond-level time synchronization requirements of scenarios such as financial transactions and scientific computing.

[0099] S23. Control the second clock source to update the current time data according to the clock signal output by the first clock source.

[0100] The clock unit is an independent timing module that typically integrates a 32.768kHz low-frequency crystal oscillator and a backup power supply. It is used to continuously record time data, such as year, month, day, hour, minute, and second, when the system is powered off.

[0101] The clock unit stores the current time value through an internal timing register. The clock unit receives a periodic clock signal from an external temperature-compensated crystal oscillator, which drives the timing register to increment, thereby updating the time data.

[0102] Updating time data refers to the operation by which the clock unit corrects its internal timing value using the periodic clock signal output by the temperature-compensated crystal oscillator. The process is as follows: the periodic clock signal output by the temperature-compensated crystal oscillator is divided into low-frequency pulses, and each pulse triggers the timing register inside the clock unit to increment. In other words, the TCXO provides a highly stable clock signal, driving the counter of the clock unit to increment at a fixed frequency.

[0103] The control clock unit updates time data based on the clock signal output by the temperature-compensated crystal oscillator. This may include outputting a control command to the clock unit, which instructs the clock unit to use the clock signal output by the temperature-compensated crystal oscillator as the input clock signal to drive the timing register of the clock unit to increment at a fixed frequency.

[0104] S24. In response to detecting that the frequency deviation of the first clock source is not within the preset deviation range, control the second clock source to update the current time data using the clock signal output by the phase-locked loop.

[0105] Frequency deviation can be understood as the difference between the actual output frequency of a TCXO and its nominal frequency (e.g., 26MHz), usually quantified in ppm (parts per million). For example, if the nominal frequency is 26,000,000Hz and the actual output is 25,999,948Hz, the deviation is -62Hz, or -2ppm.

[0106] The preset deviation range refers to a predefined acceptable frequency error threshold, which can be determined according to actual needs and is not limited here. For example, if the allowable deviation is set to ±5ppm, the anomaly handling process will be triggered in response to the detection of a TCXO frequency deviation of ±7ppm.

[0107] A phase-locked loop (PLL) is a circuit or module that synchronizes the phase of an input signal with a reference signal through a feedback mechanism, outputting a stable clock signal. In a clock unit, a PLL may be used to multiply a low-frequency reference signal (e.g., 32.768kHz) to a higher frequency (e.g., 1MHz) to improve timing resolution. It also filters out phase noise from the input clock signal to ensure uniform counting pulse intervals.

[0108] In some embodiments, controlling the clock unit to update time data using the clock signal output by its phase-locked loop (PLL) may include sending instructions to the clock unit via the processor I2C bus to adjust its operating mode or input clock source. For example, sending a configuration command to switch the clock unit to the clock signal generated by the PLL.

[0109] This application provides a time synchronization method. A processor, a first clock source, and a second clock source are deployed in a management controller. The first clock source has higher time accuracy than the second clock source. In response to detecting that an external network time protocol server is unavailable, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data based on the clock signal output by the first clock source and monitors the frequency deviation of the first clock source in real time. When the frequency deviation is large, it indicates that the accuracy of the clock signal from the first clock source has decreased. At this time, the method switches to using the internal phase-locked loop of the second clock source to provide the clock signal and updates the current time data based on this clock signal. Through the dynamic master-slave clock switching mechanism between the first and second clock sources, it ensures that even when the external network time protocol server is unavailable, the management controller can still act as an external network time protocol server, providing accurate time information to the server.

[0110] Based on the above embodiments, this application provides a time synchronization example. Referring to FIG3, the process of the time synchronization example of this application mainly includes steps S301-309.

[0111] S301. In response to the server power-on, initialize the temperature-compensated crystal oscillator and clock unit.

[0112] S302. Determine whether the external NTP server is in an available state. If the external NTP server is in an available state, execute S309. If the external NTP server is in an unavailable state, execute S303.

[0113] S303, Enter timekeeping mode.

[0114] S304. Set the temperature-compensated crystal oscillator as the master clock source and output the clock signal.

[0115] S305. Determine whether the frequency deviation of the temperature-compensated crystal oscillator is within the set deviation range. If the frequency deviation of the temperature-compensated crystal oscillator is not within the set deviation range, execute S306. If the frequency deviation of the temperature-compensated crystal oscillator is within the set deviation range, execute S307-S308.

[0116] S306. The control clock unit updates the time data according to the clock signal output by the temperature-compensated crystal oscillator.

[0117] S307: The control clock unit takes over the clock distribution function and generates alarm signals.

[0118] S308, the control clock unit updates time data using the clock signal output by its phase-locked loop.

[0119] S309, BMC obtains time data provided by an external NTP server.

[0120] The processes in S301-S309 can be referred to the description in the above embodiments, and will not be repeated in the embodiments of this application.

[0121] In this embodiment, a dual-redundancy timekeeping mechanism is provided. When the frequency deviation of the temperature-compensated crystal oscillator exceeds ±5ppm due to sudden environmental changes (such as a temperature change of ±20℃), it automatically switches to the compensation clock of the clock unit and generates a replacement signal through a phase-locked loop to ensure clock continuity. This mechanism reduces the interruption time of critical services to less than 50ms.

[0122] The time synchronization method in this application embodiment can also extend the autonomous timekeeping period. The temperature-compensated crystal oscillator provides 24-hour high-precision timekeeping (error <1ms), and the clock unit maintains basic timekeeping for 7 days through an independent power supply (error <±2ppm). The combined time synchronization scheme of the two ensures that the cumulative monthly error of the system does not exceed ±1 second in the case of network outage, which has better stability than the single RTC scheme.

[0123] In some embodiments, based on FIG2 and referring to FIG4, after performing the above step S24 (in response to detecting that the frequency deviation of the first clock source is not within the preset deviation range, controlling the second clock source to update the current time data using the clock signal output by the phase-locked loop), the following steps may also be performed:

[0124] S25. Enable the processor's external network time protocol server function.

[0125] The external network time protocol server function is used to provide time synchronization services for the target server cluster.

[0126] The NTP server function is implemented in the BMC firmware layer. That is, the software program that implements the NTP server function is stored in the BMC firmware layer. In response to the unavailability of the external NTP server, the software program is started to implement the processor's NTP server function.

[0127] After enabling the processor's NTP server function, the processor, i.e., the BMC, is used as an NTP server to synchronize time data with the target node.

[0128] The target node includes, but is not limited to, other servers in the target server cluster and other internal components in the target server, such as central processing units, graphics processing units, switches, storage nodes, etc.

[0129] In some embodiments, step S25 (enabling the processor's external network time protocol server function) can be implemented in the following manner:

[0130] (1) Activate the built-in external network time protocol service process in the processor through a preset command.

[0131] The NTP service process, implemented in software using the Network Time Protocol (NTP), runs within the processor's firmware. It receives and sends time synchronization requests and maintains the synchronization of the controller clock with the standard time. Configuration commands are input through specific interfaces (such as serial ports, SSH, or APIs) and are used to activate, modify, or disable functional modules of the processor.

[0132] In some embodiments, the built-in NTP service process is activated via the systemctl command.

[0133] (2) Enable access permissions for the preset network ports in the processor.

[0134] The default port refers to the network port that the NTP server (BMC) listens on, usually UDP port 123. External access needs to be controlled through firewalls or access control policies to prevent unauthorized access by the management controller. Access permissions define the rules for opening the port, including the allowed range of Internet Protocol (IP) addresses, protocol type (e.g., UDP only), and operation permissions (e.g., read-only or read-write).

[0135] In some embodiments, firewall or system policies that block UDP port 123 are lifted, allowing an external management controller to communicate with the processor through that port.

[0136] (3) Configure the processor's access control list and enable the network time protocol.

[0137] The access control list is used to manage the time synchronization access permissions of at least one external server in the target server cluster to the target server.

[0138] Network Time Protocol (NTP) is a standard protocol used to synchronize the time of various management controllers in a computer network. It achieves high-precision time synchronization through a hierarchical structure and clock source selection algorithm.

[0139] In some embodiments, as the time synchronization node within the target server cluster, the BMC needs to be configured with an access control list to restrict time synchronization requests to only server nodes within a specified IP address range on the same network segment. Furthermore, a rule-based network filtering mechanism uses whitelists / blacklists to restrict which servers can send time synchronization requests to the processor, enhancing security. Only server nodes within a specified IP address range on the same network segment are allowed to initiate time synchronization requests to the processor, preventing unauthorized access.

[0140] After completing the above configuration, the NTP service process in the BMC will be officially started, responding to legitimate requests and participating in the time synchronization network. The operating systems of other servers in the cluster need to modify the ` / etc / ntp.conf` configuration file to set the BMC's IP address as the preferred time source. At this point, the BMC will act as a primary time server, broadcasting precise time signals to registered nodes via the local area network, with synchronization accuracy controllable to the millisecond level.

[0141] S26. Synchronize the time data output from the second clock source to the target server cluster.

[0142] The target server cluster comprises the target server and at least one external server. That is, the target server cluster is a collaborative system composed of multiple servers that share resources and work together to improve computing power, reliability, or load balancing. At least one external server is a member node in the cluster other than the target server, and it needs to maintain communication and data synchronization with the master node or management unit.

[0143] By integrating the TCXO module and clock unit in the BMC and combining them with a layered NTP service architecture, the BMC embedded system achieves full-stack high-precision time synchronization and autonomous timekeeping capabilities within the server cluster at a limited cost, relying on cross-layer collaboration between physical layer clock distribution and protocol layer time synchronization.

[0144] Furthermore, at least one external server in the target server cluster is connected to the management controller of the target server via a local area network. Step S26 (synchronizing the time data output from the second clock source to the target server cluster) can be implemented as follows:

[0145] The time data output from the second clock source is synchronized to the target server cluster via the local area network.

[0146] Local area network (LAN) refers to a private network within a local area that connects member nodes within a cluster, providing a low-latency, high-bandwidth communication channel for internal data exchange.

[0147] In some embodiments, servers within the target server cluster (including the BMC) are interconnected via a local area network (LAN) to form a unified communication environment, ensuring direct communication between management controllers. The BMC, as the cluster's management core, shares the same network with the servers, facilitating centralized monitoring and control. The clock unit serves as the cluster's time reference, providing high-precision time data. The BMC broadcasts or unicasts the time data from its clock unit to other servers in the cluster via the LAN, potentially using NTP (Network Time Protocol) or a proprietary protocol. Upon receiving the time data, the servers adjust their local clocks to ensure time consistency across the entire cluster.

[0148] In this embodiment, BMC is used as an NTP server to provide time synchronization services to other servers within the local area network, thus solving the problem of inaccurate time synchronization of server clusters in a network isolation environment.

[0149] In some embodiments, in response to the number of servers in the target server cluster exceeding a first preset value, the processor's external network time protocol logging function is enabled to record various events during the time data synchronization process.

[0150] The number of servers refers to the total number of physical or virtual server nodes currently running in the target server cluster, which is a core indicator for measuring the cluster size.

[0151] The first preset value is a preset threshold parameter (e.g., 50 units) used to determine whether the cluster size meets the conditions for enabling specific functions (e.g., NTP logging).

[0152] The NTP logging function refers to the log generation and storage module of the Network Time Protocol (NTP), which records event details (such as timestamps, source IPs, and synchronization results) for time synchronization requests, responses, and deviation adjustments.

[0153] The time data synchronization process involves servers within a cluster using the NTP protocol to calibrate their clocks with the processor's time source, including steps such as request sending, response receiving, and local clock correction.

[0154] Multiple events refer to key behaviors or state changes during the synchronization process, such as synchronization success / failure, clock offset exceeding limits, abnormal network latency, master-slave switching, etc.

[0155] In some embodiments, in large-scale cluster environments, enabling the BMC's NTP service logging function to track and alert on time synchronization anomalies is a key measure to ensure high availability and stability of cluster time synchronization. When the number of servers exceeds a first preset value, indicating a significant increase in the complexity and failure risk of time synchronization in a large-scale cluster, enhanced monitoring needs to be enabled. The processor's NTP logging module switches from a disabled or low-priority state to active logging mode, beginning to capture synchronization events.

[0156] The recorded content covers the entire time synchronization process, including but not limited to: the frequency and timing of server-initiated synchronization requests; processor response latency and clock skew compensation values; and reasons for synchronization failures (such as network packet loss or unreachable clock source).

[0157] By tracing back through logs, the root cause of synchronization anomalies (such as clock drift on a specific server or network congestion) can be located, and synchronization strategies can be optimized or cluster management resources can be expanded.

[0158] Furthermore, in some embodiments, the rising edge timestamp of the pulse signal per second from the first clock source and the rising edge timestamp of the interrupt signal per second from the second clock source are obtained.

[0159] If the difference between the rising edge timestamp of the pulse signal per second from the first clock source and the rising edge timestamp of the interrupt signal per second from the second clock source is greater than a second preset value, a switching command is sent to any server in the target server cluster other than the target server.

[0160] The switching instruction is used to indicate that the object to be used for time synchronization operation should be switched from the target server to any server in the target server cluster other than the target server.

[0161] In some embodiments, while synchronizing the time data of the clock unit with other servers in the cluster via a local area network, the method further includes: acquiring the rising edge timestamp of the pulse signal per second from the temperature-compensated crystal oscillator and the rising edge timestamp of the interrupt signal per second from the clock unit. In response to the rising edge timestamp of the pulse signal per second and the rising edge timestamp of the interrupt signal per second being greater than a second preset value, a switching command is sent to any other server in the cluster.

[0162] A temperature-compensated crystal oscillator (TCS) is a clock source that uses a temperature-compensated circuit to stabilize its output frequency. Its accuracy is less affected by ambient temperature and it is typically used in systems requiring high-precision timing. The number of pulses per second (PPS) is a quantitative indicator of the frequency of the periodic electrical signal output by the TPS, measured in Hz (Hertz). For example, 32.768 kHz indicates that 32,768 PPS are generated per second, which is fundamental to system timing.

[0163] The clock unit's second interrupt signal refers to a hardware interrupt signal generated once per second by the clock unit. It is used to trigger system time updates or execute periodic tasks and has strict time base characteristics. Specifically, the TCXO provides the number of pulses per second to reflect clock frequency stability, while the RTC provides the second interrupt signal to reflect time base reliability.

[0164] The second preset value is a preset threshold parameter used to determine if the absolute value of the rising edge time difference between the TCXO's PPS pulse signal and the RTC second interrupt signal exceeds the second preset value, thus indicating a clock source abnormality. In some embodiments, the second preset value is 1 millisecond.

[0165] Any other server in the cluster refers to any other node in the same cluster besides the current server. It must have redundancy capabilities to receive instructions and take over tasks to ensure high system availability.

[0166] A switching instruction is a control command sent via an internal cluster communication protocol (such as TCP / IP or a custom message) to instruct the target server to initiate a specific operation (such as instructing the target of a time synchronization operation to switch).

[0167] The rising edge timestamps of the PPS pulse signal and the second interrupt signal are recorded using a dedicated internal timer or an external clock source, and the difference between them is calculated. The driver periodically reads the status registers of the two signals and determines the deviation based on the timestamp difference. An alarm is triggered when the deviation exceeds 1ms multiple times consecutively, or when a single deviation exceeds the limit. The processor disables the clock source output of the current BMC and enables another server in the cluster as the NTP server. After the switch, a clock source change notification is broadcast to other nodes in the cluster, forcibly starting the time synchronization protocol to eliminate residual deviations.

[0168] Upon detecting an anomaly, the current server sends a switchover command to any available node in the cluster, prioritizing servers with lower loads or higher priority. The switchover command includes the synchronization request type, time source identifier (such as the primary RTC address), and synchronization protocol parameters. The receiving server initiates the time synchronization process, which may include pausing the current task, obtaining the latest time data from the specified time source, adjusting the local clock, and resuming service. The synchronization process relies on the low-latency communication of the cluster network and the reliability of the time source; synchronization failures may trigger retries or alarms.

[0169] To ensure service reliability, a primary-backup NTP service architecture can be constructed using dual BMC nodes to achieve automatic failover. The BMC simultaneously monitors the 10MHz high-frequency signal of the temperature-compensated crystal oscillator and the second-level interrupt signal of the clock unit. Through the PPS alignment mechanism, the sensitivity of clock source deviation detection is improved to 1ms, resulting in a faster time jump alarm response speed compared to a single clock source solution.

[0170] In some embodiments, the target server includes at least one internal component. A first clock source is connected to at least one internal component via an integrated circuit bus. Based on FIG2 and referring to FIG5, after performing step S25 above, step S27 can also be performed:

[0171] S27. Synchronize the time data output from the second clock source to at least one internal component via the integrated circuit bus.

[0172] In some embodiments, the target node also includes internal components within the target server. The BMC broadcasts or unicasts time data from its clock unit to these internal components on the target server via a local area network, potentially using NTP (Network Time Protocol) or a proprietary protocol. Upon receiving the time data, the internal components adjust their local clocks to ensure time consistency across the entire cluster. These internal components include a central processing unit (CPU), a graphics processing unit (GPU), a switch, and storage nodes.

[0173] By employing a temperature-compensated crystal oscillator and a dynamic master-slave clock switching mechanism (RTC), the BMC can still function as an NTP server, providing accurate time information to the server cluster and components even when external NTP services are unavailable. The dual-redundancy timekeeping mechanism formed by the real-time clock and the temperature-compensated crystal oscillator ensures full-stack clock consistency between the BMC and all components, achieving high-precision time synchronization.

[0174] Using the BMC as an NTP server to send time synchronization information to the server cluster and between its components, other server components with network service capabilities can also be considered for this function. Meanwhile, in scenarios where satellite navigation signals are available, a temperature-compensated crystal oscillator can be integrated with a GPS / BeiDou receiver module, and calibration can be assisted by PPS signals to further improve timekeeping accuracy.

[0175] This application provides a hierarchical time synchronization architecture. A BMC (Brain Clock Controller) serves as the system-level time source, and a high-precision temperature-compensated crystal oscillator is used as the core clock reference to construct the hierarchical time synchronization architecture. Specifically, when transmitting data to internal components in the target server via a local area network, the temperature-compensated crystal oscillator communicates with the internal components in the target server via I / O. 2 C-bus connection. The target server is the server belonging to the baseboard management controller, and the temperature-compensated crystal oscillator is connected via I-bus. 2 The C bus synchronizes clock signals to internal components in the target server.

[0176] In some embodiments, in response to at least one internal component being a central processing unit, the above step S27 (synchronizing the time data output from the second clock source to at least one internal component via the integrated circuit bus) can be implemented in the following manner:

[0177] The time data output from the second clock source is synchronized to at least one central processing unit via an integrated circuit bus, so that the digital phase-locked loop in the at least one central processing unit calibrates its internal clock counter based on the time data output from the second clock source.

[0178] The central processing unit (CPU) is the core computing unit of a server, responsible for executing instructions, processing data, and coordinating other components. Its operation depends on precise clock signals.

[0179] In the target server's internal components, the CPU is the core computing unit, and the TCXO is the high-precision clock source; the two are connected via I / O. 2 The TCXO is connected via the C bus. 2 The C bus transmits clock signals to the CPU and supports bidirectional communication (such as configuring TCXO parameters or reading status).

[0180] TCXO generates a clock signal and passes it through I... 2 The clock signal is sent to the CPU via the C bus. The CPU's internal DPLL module receives the clock signal, compares it with the local oscillator frequency, calculates the deviation, and adjusts the frequency and phase of the clock counter. The calibrated clock counter provides the CPU with a precise timing reference, ensuring the accuracy of instruction execution, interrupt handling, and task scheduling.

[0181] In some embodiments, in response to at least one internal component being a graphics processor, step S27 (synchronizing the time data output from the second clock source to at least one internal component via the integrated circuit bus) can be implemented as follows:

[0182] The timing data output from the second clock source is synchronized to at least one graphics processor via an integrated circuit bus, so that at least one graphics processor performs time alignment based on the timing data output from the second clock source during remote direct memory access network operations.

[0183] Among them, the graphics processing unit (GPU) is a hardware accelerator in the target server used for parallel computing or graphics processing. It is usually a multi-card configuration such as 4-way or 8-way GPUs, which supports large-scale data parallel tasks.

[0184] The target server's GPU serves as the computing acceleration unit, and the TCXO is the high-precision clock source; the two are connected via I / O. 2 The TCXO is connected via the C bus. 2 The C bus transmits clock signals to multiple GPUs and supports bidirectional communication.

[0185] TCXO generates a clock signal and passes it through I... 2 The C-bus broadcasts to multiple GPUs, and the signal frequency and phase must meet the GPU's input requirements (such as using a high-frequency clock for task scheduling). Multiple GPUs adjust their local timers based on the received clock signal to ensure that data transmission in the RDMA network remains synchronized with task execution, avoiding calculation errors or data inconsistencies caused by clock skew.

[0186] The technical solution of this application embodiment ensures time alignment of multiple GPUs in an RDMA network, thereby improving parallel computing efficiency and data transmission reliability.

[0187] In this embodiment, clock alignment for heterogeneous hardware such as CPU and GPU is supported, with a clock alignment function adaptation rate of 99%, significantly reducing the workload of cross-platform time synchronization development.

[0188] In some embodiments, in response to at least one internal component being a switch or a storage node, step S27 (synchronizing the time data output from the second clock source to at least one internal component via the integrated circuit bus) can be implemented as follows:

[0189] The time data output from the second clock source is synchronized to at least one switch or storage node via an integrated circuit bus, so that at least one switch or storage node can perform time synchronization based on the time data output from the second clock source.

[0190] A switch is a network management controller within the server used for data exchange. It is responsible for forwarding data packets between different components to ensure efficient communication. A storage node is a hardware module within the server used for data storage. It may be a hard disk drive, a solid-state drive, or a storage controller, and supports data read / write and persistence.

[0191] I 2 The C-bus is a serial communication bus protocol that supports a multi-master / slave architecture. It is used to connect low-speed peripherals (such as switches and storage nodes) to the processor of the baseboard management controller, transmitting control commands and data. A bridge is a hardware or software module used to connect different buses or protocols, enabling signal conversion and data transmission. The clock bus is a high-precision clock signal transmission channel provided by the BMC, used to distribute a unified clock signal to internal server components, ensuring timing consistency.

[0192] The target server's switch or storage node connects to the BMC via I / O. 2 C-bus and bridge connection. Switches or storage nodes are connected via I-bus and bridge. 2 The C bus sends a request, the bridge converts the signal into a clock bus protocol, and the BMC responds and distributes the clock signal.

[0193] In some embodiments, the switch or storage node communicates via I 2 The C bus sends a clock signal request to the BMC, which may include the management controller identifier and clock parameters. The bridge will then... 2 The C-bus signal is converted to a clock bus protocol to ensure signal format and electrical compatibility. The BMC transmits the clock signal to the switch or storage node via the clock bus to ensure that its local clock is consistent with the server's global time base.

[0194] Furthermore, the timekeeping capability of the temperature-compensated crystal oscillator ensures continuous high-precision time synchronization even when the external authoritative clock source is interrupted. In response to the detection that the frequency deviation of the temperature-compensated crystal oscillator exceeds the ±5ppm threshold, it automatically switches to the compensated clock of the clock unit and generates a replacement clock signal via a PLL, utilizing a dual-redundancy timekeeping mechanism to guarantee clock signal accuracy.

[0195] In this embodiment, dual protection is achieved at the physical layer and protocol layer. The temperature-compensated crystal oscillator is connected via I... 2 The C-bus implements hardware-level clock distribution, avoiding latency jitter in the software protocol stack. Meanwhile, the NTPv4 protocol supports encrypted time synchronization via I... 2 The dual protection mechanism of C hardware-level distribution and NTPv4 encryption protocol effectively prevents man-in-the-middle attacks.

[0196] The time synchronization method provided in this disclosure deploys a processor, a first clock source, and a second clock source in a management controller. The time accuracy of the first clock source is higher than that of the second clock source. In response to detecting that an external network time protocol server is unavailable, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source and monitors the frequency deviation of the first clock source in real time. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the method switches to using the internal phase-locked loop of the second clock source to provide the clock signal and updates the current time data based on the clock signal. Through the master-slave clock dynamic switching mechanism of the first and second clock sources, it is ensured that even when the external network time protocol server is unavailable, the management controller can still act as an external network time protocol server, providing accurate time information to the server.

[0197] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus a general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0198] The embodiments of this application also provide a time synchronization device. For any omitted virtual device claims, the description should be expanded in the specification, corresponding one-to-one with the method claims.

[0199] Figure 6 is a structural schematic diagram of a time synchronization device 600 provided in this disclosure. As shown in Figure 6, the device in this embodiment includes: a monitoring module 610, an output module 620, a control module 630, and an update module 640, wherein...

[0200] The monitoring module 610 is used to enter timekeeping mode in response to the detection that the external network time protocol server is unavailable.

[0201] The output module 620 is used to control the transmission of the clock signal output by the first clock source to the second clock source in timekeeping mode.

[0202] The control module 630 is used to control the second clock source to update the current time data according to the clock signal output by the first clock source.

[0203] The update module 640 is used to control the second clock source to update the current time data using the clock signal output by the phase-locked loop in response to the detection that the frequency deviation of the first clock source is not within the preset deviation range.

[0204] As some embodiments of this disclosure, a first clock source is connected to the processor via an integrated circuit bus, and a second clock source is connected to the processor via an integrated circuit bus.

[0205] As some embodiments of this disclosure, the apparatus further includes an initialization module, which is configured to:

[0206] After detecting that the target server is powered on, the timestamp is obtained from the second clock source.

[0207] The timestamp is transmitted to the first clock source, and the first clock source is controlled to generate and output a clock signal with the timestamp as the initial time reference.

[0208] As some embodiments of this disclosure, the apparatus further includes:

[0209] The first function enable module is used to enable the processor's external network time protocol server function.

[0210] The first synchronization module is used to synchronize the time data output from the second clock source to the target server cluster.

[0211] The external network time protocol server function is used to provide time synchronization services for the target server cluster. The target server cluster includes the target server and at least one external server.

[0212] As some embodiments of this disclosure, the first function enabling module is used for:

[0213] The built-in external network time protocol service process in the processor is activated by a preset command.

[0214] Enable access permissions for the default network ports in the processor.

[0215] Configure the processor's access control list and enable the Network Time Protocol (NTP). The access control list is used to manage time synchronization access permissions of at least one external server in the target server cluster to the target server.

[0216] As some embodiments of this disclosure, at least one external server in the target server cluster is connected to the management controller of the target server via a local area network. A first synchronization module is used for:

[0217] The time data output from the second clock source is synchronized to the target server cluster via the local area network.

[0218] As some embodiments of this disclosure, the apparatus further includes:

[0219] The second function activation module is used to enable the processor's external network time protocol logging function in response to the number of servers in the target server cluster being greater than a first preset value.

[0220] The recording module is used to record various events during the time data synchronization process.

[0221] As some embodiments of this disclosure, the apparatus further includes a switching module, used for:

[0222] Obtain the rising edge timestamp of the pulse signal per second from the first clock source and the rising edge timestamp of the interrupt signal per second from the second clock source.

[0223] If the difference between the rising edge timestamp of the second pulse signal from the first clock source and the rising edge timestamp of the second interrupt signal from the second clock source is greater than a second preset value, a switching command is sent to any server in the target server cluster other than the target server. The switching command is used to indicate that the object to be used for time synchronization operation is switched from the target server to any server in the target server cluster other than the target server.

[0224] As some embodiments of this disclosure, the target server includes at least one internal component. A first clock source is connected to at least one internal component via an integrated circuit bus. The apparatus also includes a second synchronization module for:

[0225] The time data output from the second clock source is synchronized to at least one internal component via an integrated circuit bus.

[0226] As some embodiments of the present disclosure, in response to at least one internal component being a central processing unit, the second synchronization module is configured to:

[0227] The time data output from the second clock source is synchronized to at least one central processing unit via an integrated circuit bus, so that the digital phase-locked loop in the at least one central processing unit calibrates its internal clock counter based on the time data output from the second clock source.

[0228] As some embodiments of the present disclosure, in response to at least one internal component being a graphics processor, the second synchronization module is configured to:

[0229] The timing data output from the second clock source is synchronized to at least one graphics processor via an integrated circuit bus, so that at least one graphics processor performs time alignment based on the timing data output from the second clock source during remote direct memory access network operations.

[0230] For a description of the features in the embodiment corresponding to the time synchronization device 600, please refer to the relevant description in the embodiment corresponding to the time synchronization method, which will not be repeated here.

[0231] The time synchronization device provided in this embodiment deploys a processor, a first clock source, and a second clock source in the management controller. The time accuracy of the first clock source is higher than that of the second clock source. In response to detecting that the external network time protocol server is unavailable, the clock signal output by the first clock source is transmitted to the second clock source. The second clock source updates the current time data according to the clock signal output by the first clock source and monitors the frequency deviation of the first clock source in real time. When the frequency deviation is large, it indicates that the accuracy of the clock signal of the first clock source has decreased. At this time, the device switches to using the internal phase-locked loop of the second clock source to provide the clock signal and updates the current time data based on the clock signal. Through the master-slave clock dynamic switching mechanism of the first and second clock sources, it is ensured that even when the external network time protocol server is unavailable, the management controller can still act as an external network time protocol server, providing accurate time information to the server.

[0232] As shown in Figure 7, an embodiment of this application also provides a management controller, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described time synchronization method embodiments.

[0233] As shown in Figure 8, an embodiment of this application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described time synchronization method embodiments when running.

[0234] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0235] As shown in Figure 9, an embodiment of this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described time synchronization method embodiments.

[0236] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described time synchronization method embodiments.

[0237] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0238] The time synchronization method provided in this application has been described in detail above. Examples have been used to illustrate the principles and implementation methods of this application, and the descriptions of the embodiments above are intended to help understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A time synchronization method, characterized in that, The method is applied to a management controller included in a target server, the management controller including: a processor, a first clock source, and a second clock source, wherein the time accuracy of the first clock source is higher than that of the second clock source, the method is executed by the processor, and the method includes: In response to the detection that an external network time protocol server is unavailable, it enters timekeeping mode; In response to the timekeeping mode, the clock signal output by the first clock source is controlled to be transmitted to the second clock source; Control the second clock source to update the current time data according to the clock signal output by the first clock source; and In response to the detection that the frequency deviation of the first clock source is not within the preset deviation range, the second clock source is controlled to update the current time data using the clock signal output by the phase-locked loop.

2. The time synchronization method according to claim 1, characterized in that, The first clock source is connected to the processor via an integrated circuit bus, and the second clock source is connected to the processor via an integrated circuit bus.

3. The time synchronization method according to claim 1, characterized in that, In response to the detection that an external network time protocol server is unavailable, before entering timekeeping mode, the method further includes: After detecting that the target server has been powered on, a timestamp is obtained from the second clock source; and The timestamp is transmitted to the first clock source, and the first clock source is controlled to generate and output a clock signal with the timestamp as the initial time reference.

4. The time synchronization method according to claim 1, characterized in that, After controlling the second clock source to update the current time data using the clock signal output by the phase-locked loop, the method further includes: Enable the processor's external network time protocol server function; and Synchronize the time data output from the second clock source to the target server cluster; The external network time protocol server function is used to provide time synchronization services for the target server cluster; the target server cluster includes the target server and at least one external server.

5. The time synchronization method according to claim 4, characterized in that, The function of enabling the processor's external network time protocol server includes: The built-in external network time protocol service process in the processor is activated by a preset command; Enable access permissions for a preset network port in the processor; and Configure the access control list of the processor and enable the network time protocol; the access control list is used to manage the time synchronization access permissions of at least one external server in the target server cluster to the target server.

6. The time synchronization method according to claim 4, characterized in that, At least one external server in the target server cluster is connected to the management controller of the target server via a local area network; as well as The step of synchronizing the time data output from the second clock source to the target server cluster includes: The time data output by the second clock source is synchronized to the target server cluster via the local area network.

7. The time synchronization method according to claim 6, characterized in that, The method further includes: In response to the number of servers in the target server cluster exceeding a first preset value, the processor's external network time protocol logging function is enabled; and Record various events during the time data synchronization process.

8. The time synchronization method according to claim 7, characterized in that, The method further includes: Obtain the rising edge timestamp of the pulse signal per second from the first clock source and the rising edge timestamp of the interrupt signal per second from the second clock source; and In response to the difference between the rising edge timestamp of the pulse signal per second from the first clock source and the rising edge timestamp of the interrupt signal per second from the second clock source being greater than a second preset value, a switching instruction is sent to any server in the target server cluster other than the target server; the switching instruction is used to indicate that the object to be used for time synchronization operation is switched from the target server to any server in the target server cluster other than the target server.

9. The time synchronization method according to claim 4, characterized in that, The target server includes at least one internal component; the first clock source is connected to the at least one internal component via an integrated circuit bus. as well as After enabling the processor's external network time protocol server function, the method further includes: The time data output from the second clock source is synchronized to the at least one internal component via the integrated circuit bus.

10. The time synchronization method according to claim 9, characterized in that, In response to the at least one internal component being a central processing unit, the step of synchronizing the time data output from the second clock source to the at least one internal component via the integrated circuit bus includes: The time data output from the second clock source is synchronized to the at least one central processing unit via the integrated circuit bus, so that the digital phase-locked loop in the at least one central processing unit calibrates its internal clock counter based on the time data output from the second clock source.

11. The time synchronization method according to claim 9, characterized in that, In response to the at least one internal component being a graphics processor, the step of synchronizing the time data output from the second clock source to the at least one internal component via the integrated circuit bus includes: The time data output from the second clock source is synchronized to the at least one graphics processor via the integrated circuit bus, so that the at least one graphics processor performs time alignment based on the time data output from the second clock source during remote direct memory access network operations.

12. The time synchronization method according to claim 1, characterized in that, The first clock source includes at least one of a temperature-compensated crystal oscillator and a temperature-controlled crystal oscillator; and the second clock source is a real-time clock.

13. The time synchronization method according to claim 1, characterized in that, Before the step of entering timekeeping mode in response to detecting that an external network time protocol server is unavailable, the method further includes: The management controller sends a time query request to the Network Time Protocol server; and If no valid response is received or the response times out after multiple consecutive attempts, it is determined that the external network time protocol server is in an unavailable state.

14. The time synchronization method according to claim 1, characterized in that, Before the step of entering timekeeping mode in response to detecting that an external network time protocol server is unavailable, the method further includes: The management controller detects the connectivity status of physical links through the underlying network interface; and In response to the detection of a physical link disconnection via the network interface, it is determined that the external network time protocol server is unavailable.

15. The time synchronization method according to claim 4, characterized in that, The step of enabling the processor's external network time protocol server function includes: The firmware layer of the management controller stores software programs that implement the functions of an external network time protocol server; and The processor's external network time protocol server function is enabled by launching the software program.

16. The time synchronization method according to claim 1, characterized in that, The external network time protocol server is a dedicated time server deployed in the network to provide standard time data.

17. A time synchronization device, characterized in that, An application is made to a management controller included in a target server, the management controller comprising: a processor, a first clock source, and a second clock source, wherein the time accuracy of the first clock source is higher than that of the second clock source, the device being deployed in the processor, the device comprising: The monitoring module is used to enter timekeeping mode in response to the detection that an external network time protocol server is unavailable; The output module is used to control the transmission of the clock signal output by the first clock source to the second clock source in the timekeeping mode. The control module is used to control the second clock source to update the current time data according to the clock signal output by the first clock source; and The update module is used to control the second clock source to update the current time data using the clock signal output by the phase-locked loop in response to the detection that the frequency deviation of the first clock source is not within the preset deviation range.

18. A management controller, characterized in that, The management controller includes: First clock source; A second clock source, wherein the time accuracy of the first clock source is higher than that of the second clock source; Memory, used to store computer programs; and A processor for executing the computer program to implement the steps of the time synchronization method as described in any one of claims 1 to 16.

19. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the time synchronization method as described in any one of claims 1 to 16.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the time synchronization method as described in any one of claims 1 to 16.

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