CML-to-CMOS logic circuit, chip, and electronic device

Abstract

A CML-to-CMOS logic circuit, a chip, and an electronic device. The CML-to-CMOS logic circuit comprises: a CML signal-to-CMOS signal module, configured to convert an inputted CML differential clock into a CMOS differential clock and output the CMOS differential clock; and a duty cycle correction module, connected to a common-mode node of the CML signal-to-CMOS signal module and configured to adjust a common-mode voltage of the CML signal-to-CMOS signal module so as to correct a duty cycle deviation of the CMOS differential clock. By directly adjusting the common-mode voltage of the CML signal-to-CMOS signal module, a duty cycle adjustment process is not affected by a CMOS transmission path, thereby avoiding the problem of an increase in duty cycle adjustment power consumption caused by an increase in the length of the CMOS transmission path.

Description

CML to CMOS logic circuits, chips and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510354072.4, filed on March 24, 2025, entitled "CML to CMOS Logic Circuit, Chip and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, specifically to a CML-to-CMOS logic circuit, chip, and electronic device. Background Technology

[0003] High-speed interface chips for long-distance clock transmission often use a combination of CML (Current Model Logic) and CMOS (Complementary Metal-Oxide-Semiconductor) to achieve high-speed clock transmission. Among them, the C2C (CML logic to CMOS logic) circuit is a necessary link in the combination of CML and CMOS. Technical issues

[0004] The C2C circuit is used to convert the CML differential clock into a CMOS differential clock and provide it to the subsequent CMOS transmission path. However, due to matching problems, power supply noise crosstalk, circuit aging, etc. between each CMOS transmission path, the duty cycle of the CMOS differential clock will deteriorate. Therefore, the duty cycle needs to be adjusted between or after each CMOS transmission path. Furthermore, since the driving capability required by the CMOS transmission path increases step by step, its load and power consumption also increase step by step. This also results in a large power consumption required to adjust the CMOS duty cycle between or after the CMOS transmission path. Technical solutions

[0005] In view of the above problems, this application provides a CML-to-CMOS logic circuit, chip, and electronic device to solve the above technical problems.

[0006] In a first aspect, this application provides a CML-to-CMOS logic circuit, comprising:

[0007] The CML signal to CMOS signal module is used to convert the input CML differential clock into a CMOS differential clock output.

[0008] The duty cycle correction module is connected to the common-mode node of the CML signal to CMOS signal module and is used to adjust the common-mode voltage of the CML signal to CMOS signal module to correct the duty cycle deviation of the CMOS differential clock.

[0009] Secondly, this application provides a chip including the CML-to-CMOS logic circuit described in the first aspect above.

[0010] Thirdly, this application also provides an electronic device, including a device body and a chip as described in the second aspect above disposed on the device body. Beneficial effects

[0011] This application provides a CML-to-CMOS logic circuit, chip, and electronic device. The CML-to-CMOS logic circuit includes a CML signal to CMOS signal module and a duty cycle correction module. The duty cycle correction module is connected to the common-mode node of the CML signal to CMOS signal module. By adjusting the voltage of this common-mode node, the duty cycle deviation of the CMOS differential clock is corrected, thus solving the problem of CMOS differential clock duty cycle degradation with lower power consumption. Because this application directly adjusts the common-mode voltage of the CML signal to CMOS signal module, the duty cycle adjustment process is not affected by the CMOS transmission path, thereby avoiding the problem of increased power consumption for duty cycle adjustment as the CMOS transmission path lengthens. This achieves correction of CMOS differential clock duty cycle deviation with lower power consumption.

[0012] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 shows a schematic diagram of the CML to CMOS logic circuit provided in an embodiment of this application.

[0015] Figure 2 shows a schematic diagram of the CML signal to CMOS signal module provided in an embodiment of this application.

[0016] Figure 3 shows a schematic diagram of the duty cycle correction module provided in an embodiment of this application.

[0017] Figure 4 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiment of this application.

[0018] Figure 5 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiment of this application.

[0019] Figure 6 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiment of this application.

[0020] Figure 7 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiment of this application.

[0021] Figure 8 shows another schematic diagram of the CML signal to CMOS signal module provided in the embodiments of this application.

[0022] Figure 9 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiment of this application.

[0023] Figure 10 shows a schematic diagram of the chip provided in an embodiment of this application.

[0024] Figure 11 shows a schematic diagram of an electronic device provided in an embodiment of this application. Embodiments of the present invention

[0025] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0027] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0028] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0029] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0030] This application provides a CML to CMOS logic circuit. Figure 1 shows a schematic diagram of the CML to CMOS logic circuit provided in this application. As shown in Figure 1, the circuit includes a CML signal to CMOS signal module and a duty cycle correction module.

[0031] The CML signal to CMOS signal module converts the input CML differential clock into a CMOS differential clock output. A duty cycle correction module is connected to the common-mode node of the CML signal to CMOS signal module and is used to adjust the common-mode voltage of the CML signal to CMOS signal module to correct the duty cycle deviation of the CMOS differential clock. Optionally, the common-mode voltage of the differential signal is the average of its positive and negative signals; therefore, adjusting the common-mode voltage of the CML signal to CMOS signal module can control the positive and negative signals of the differential signal separately, thereby correcting its duty cycle deviation.

[0032] The CML-to-CMOS logic circuit provided in this application includes a CML signal to CMOS signal module and a duty cycle correction module. The duty cycle correction module is connected to the common-mode node of the CML signal to CMOS signal module. By adjusting the voltage of this common-mode node, the duty cycle deviation of the CMOS differential clock is corrected, thus solving the problem of CMOS differential clock duty cycle variation with lower power consumption. Compared with traditional C2C circuits, because this application directly adjusts the common-mode voltage of the CML signal to CMOS signal module, the duty cycle adjustment process is not affected by the CMOS transmission path. Regardless of how many CMOS transmission paths the CMOS differential clock output from the CML signal to CMOS signal module traverses, the power consumption of the duty cycle correction module does not increase with the length of the CMOS transmission path. This achieves correction of CMOS differential clock duty cycle deviation with lower power consumption.

[0033] In some embodiments, FIG2 shows a schematic diagram of a CML signal to CMOS signal module provided in the present application. As shown in FIG2, the CML signal to CMOS signal module includes a first AC coupling unit C1, a first inverting unit INV1, a first resistor network R1, a second AC coupling unit C2, a second inverting unit INV2, and a second resistor network R2.

[0034] A first AC coupling unit C1 and a first inverting unit INV1 are used. The input of the first AC coupling unit C1 is used to receive the positive signal CMLP of the CML differential clock. The output of the first AC coupling unit C1 is connected to the input of the first inverting unit INV1, and the output of the first inverting unit INV1 is used to output the negative signal CMOSN of the CMOS differential clock. Optionally, the first AC coupling unit C1 is used to isolate the DC common-mode level of the CML differential clock, so that the first inverting unit INV1 only processes small AC signals. The first inverting unit INV1 then converts the positive signal CMLP of the CML differential clock into the negative signal CMOSN of the CMOS differential clock.

[0035] The first resistor network R1 is connected to the input and output terminals of the first inverting unit INV1, respectively, and includes a first common-mode node VP connected to the duty cycle correction module. Optionally, the first resistor network R1 is used to form a negative feedback voltage divider network to stabilize the gain of the first inverting unit INV1. The first common-mode node VP is one of the common-mode nodes generated during the conversion of the CML differential clock to the CMOS differential clock. When the voltage of the first common-mode node VP is adjusted, such as by injecting or extracting current into or from the first common-mode node VP, the potential at the first common-mode node VP will rise or fall, thereby adjusting the duty cycle of the negative signal CMOSN of the CMOS differential clock through the feedback of the first resistor network R1.

[0036] The second AC coupling unit C2 and the second inverting unit INV2 are configured such that the input of the second AC coupling unit C2 receives the negative signal CMLN of the CML differential clock, and the output of the second AC coupling unit C2 is connected to the input of the second inverting unit INV2, which outputs the positive signal CMOSP of the CMOS differential clock. Optionally, the second AC coupling unit C2 is used to isolate the DC common-mode level of the CML differential clock, allowing the second inverting unit INV2 to process only small AC signals. The second inverting unit INV2 then converts the negative signal CMLN of the CML differential clock into the positive signal CMOSP of the CMOS differential clock.

[0037] The second resistor network R2 is connected to the input and output terminals of the second inverting unit INV2, respectively, and includes a second common-mode node VN connected to the duty cycle correction module. Optionally, the second resistor network R2 is used to form a negative feedback voltage divider network to stabilize the gain of the second inverting unit INV2. The second common-mode node VN is one of the common-mode nodes generated during the CML differential clock to CMOS differential clock conversion process. When the voltage of the second common-mode node VN is adjusted, such as by injecting or extracting current into the second common-mode node VN, the potential at the second common-mode node VN will rise or fall, thereby adjusting the duty cycle of the positive signal CMOSP of the CMOS differential clock through the feedback of the second resistor network R2.

[0038] It is understood that, in the embodiments of this application, the circuit structures of the first AC coupling unit C1, the second AC coupling unit C2, the first inverting unit INV1, the second inverting unit INV2, the first resistor network R1, and the second resistor network R2 are not limited, as long as they can achieve the corresponding AC coupling, inversion, and feedback functions. For example, the first AC coupling unit C1 and the second AC coupling unit C2 can each be set as two capacitor elements with the same capacitance value, the first inverting unit INV1 and the second inverting unit INV2 can be implemented by inverters, and the first resistor network R1 and the second resistor network R2 can be implemented by multiple resistor elements, and the first common-mode node VP and the second common-mode node VN can be led out from the multiple resistor elements.

[0039] The CML-to-CMOS logic circuit provided in this application embodiment only needs to adjust the potential of the first common-mode node and the second common-mode node to correct the duty cycle deviation of the CMOS differential clock. Adjusting the potential of the first common-mode node and the second common-mode node will not generate a large power consumption. For example, when adjusting the potential by injecting or extracting current into the first common-mode node and the second common-mode node, only a current injection circuit and a current extraction circuit need to be set. The current injection circuit and the current extraction circuit can be implemented by simple MOS devices. Obviously, this application embodiment can significantly reduce the power consumption required to correct the duty cycle deviation of the CMOS differential clock.

[0040] In some embodiments, FIG3 shows a schematic diagram of the duty cycle correction module provided in this application embodiment. As shown in FIG3, the duty cycle correction module includes:

[0041] The first PMOS transistor array MP1 is used to inject current into the first common-mode node VP. In the first PMOS transistor array MP1, the source of each PMOS transistor is connected to the power supply VDDA through the first current mirror IS1, the drain of each PMOS transistor is connected to the first common-mode node VP, and the gate of each PMOS transistor receives an independent level signal to control the number of PMOS transistors turned on.

[0042] The first NMOS transistor array MN1 is used to draw current from the first common-mode node VP. In the first NMOS transistor array MN1, the source of each NMOS transistor is grounded through the second current mirror IS2, the drain of each NMOS transistor is connected to the first common-mode node VP, and the gate of each NMOS transistor receives an independent level signal to control the number of NMOS transistors turned on.

[0043] The second PMOS transistor array MP2 is used to inject current into the second common-mode node VN. In the second PMOS transistor array MP2, the source of each PMOS transistor is connected to the power supply VDDA through the third current mirror IS3, and the drain of each PMOS transistor is connected to the second common-mode node VN. The gate of each PMOS transistor receives an independent level signal to control the number of PMOS transistors turned on.

[0044] The second NMOS transistor array MN2 is used to draw current from the second common-mode node VN. In the second NMOS transistor array MN2, the source of each NMOS transistor is grounded through the fourth current mirror IS4, the drain of each NMOS transistor is connected to the second common-mode node VN, and the gate of each NMOS transistor receives an independent level signal to control the number of NMOS transistors turned on.

[0045] Optionally, in this embodiment, when the duty cycle of the negative signal of the CMOS differential clock is higher than the duty cycle of its positive signal, current is injected into the first common-mode node VP through the first PMOS transistor array MP1 to increase the potential of the first common-mode node VP, thereby reducing the duty cycle of the negative signal of the CMOS differential clock. Alternatively, current is drawn from the second common-mode node VN through the second NMOS transistor array MN2 to reduce the potential of the second common-mode node VN, thereby increasing the duty cycle of the positive signal of the CMOS differential clock. Or, current is injected into the first common-mode node VP through the first PMOS transistor array MP1 and current is drawn from the second common-mode node VN through the second NMOS transistor array MN2, thereby reducing the duty cycle of the negative signal of the CMOS differential clock and increasing the duty cycle of the positive signal of the CMOS differential clock. Conversely, when the duty cycle of the positive signal of the CMOS differential clock is higher than that of its negative signal, current is injected into the second common-mode node VN through the second PMOS transistor array MP2 to increase the potential of the second common-mode node VN, thereby decreasing the duty cycle of the positive signal of the CMOS differential clock. Alternatively, current is drawn from the first common-mode node VP through the first NMOS transistor array MN1 to decrease the potential of the second common-mode node VN, thereby increasing the duty cycle of the negative signal of the CMOS differential clock. Another possible scenario is where current is injected into the second common-mode node VN through the second PMOS transistor array MP2 and drawn from the first common-mode node VP through the first NMOS transistor array MN1, thus decreasing both the duty cycle of the positive and negative signals of the CMOS differential clock. The values ​​of the injected and drawn currents of each MOS transistor array are controlled by the number of MOS transistors turned on in their respective arrays.

[0046] It is understood that in the embodiments of this application, the "power supply" and "ground" mentioned have a relative potential relationship, where "power supply" refers to the side with a higher potential relative to "ground".

[0047] The CML-to-CMOS logic circuit provided in this application adjusts the common-mode voltage by injecting / extracting current into the first common-mode node and adjusting its potential by extracting / injecting current into the second common-mode node, thereby correcting the duty cycle deviation of the CMOS differential clock. This application can correct the duty cycle deviation of the CMOS differential clock simply by setting up a MOS transistor array, significantly reducing the power consumption required for correcting the CMOS differential clock duty cycle deviation. Furthermore, each MOS transistor array in this application receives an independent level signal to control the number of MOS transistors turned on in the corresponding MOS transistor array, thereby controlling the magnitude of the injected / extracted current of each MOS transistor array, greatly improving the flexibility and controllability of the circuit.

[0048] In some embodiments, FIG4 shows another module schematic diagram of the CML-to-CMOS logic circuit provided in the embodiments of this application. As shown in FIG4, the circuit further includes:

[0049] The duty cycle detection module is used to acquire the DC components of the positive signal CMOSP and the negative signal CMOSN of the CMOS differential clock, respectively. Based on the voltage difference between the DC components of the positive signal CMOSP and the negative signal CMOSN of the CMOS differential clock, it outputs at least one independent level signal to the first PMOS array MP1 and / or the second NMOS array MN2, or outputs at least one independent level signal to the first NMOS array MN1 and / or the second PMOS array MP2. As shown in Figure 4, the multiple independent level signals corresponding to the first PMOS array MP1 are Code_1. <0> Code_1 <1> ... Code_1 <n>The multiple independent level signals corresponding to the first NMOS array MN2 are Code_2. <0> Code_2 <1> ... Code_2 <n>The multiple independent voltage levels corresponding to the second PMOS array MP2 are signal Code_3. <0> Code_3 <1> ... Code_3 <n>The multiple independent voltage levels corresponding to the second NMOS array MN2 are signal Code_4. <0> Code_4 <1> ... Code_4 <n>Optionally, when the voltage difference between the DC components of the positive signal CMOSP and the negative signal CMOSN of the CMOS differential clock is zero, it indicates that the duty cycle of the CMOS differential clock is normal; when the positive signal CMOSP of the CMOS differential clock is higher than the negative signal CMOSN, it indicates that the duty cycle of the positive signal CMOSP of the CMOS differential clock is higher than the duty cycle of its negative signal CMOSN. In this case, at least one independent level signal is output to the second PMOS array MP2 to control the conduction of a corresponding number of MOS transistors in the second PMOS array MP2, or at least one independent level signal is output to the first NMOS array MN1 to control the conduction of a corresponding number of MOS transistors in the first NMOS array MN1. The OS transistor is turned on, or at least one independent level signal is output to both the second PMOS transistor array MP2 and the first NMOS transistor array MN1. These three control methods respectively realize injecting current into the second common-mode node VN to increase the potential of the second common-mode node VN, extracting current into the first common-mode node VP to decrease the potential of the first common-mode node VP, and increasing the potential of the second common-mode node VN and decreasing the potential of the first common-mode node VP. The purpose is to make the potential of the first common-mode node VP and the potential of the second common-mode node VN equal, thereby solving the problem that the positive signal CMOSP of the CMOS differential clock is higher than the negative signal CMOSN. Conversely, when the negative signal CMOSN of the CMOS differential clock is higher than the positive signal CMOSP, it indicates that the duty cycle of the negative signal CMOSN of the CMOS differential clock is higher than the duty cycle of its positive signal CMOSP. Similarly, current can be injected into the first common-mode node VP by controlling the first PMOS transistor array MP1, or current can be drawn into the second common-mode node VN by controlling the second NMOS transistor array MN2, or current can be injected into the first common-mode node VP and current can be drawn into the second common-mode node VN.

[0050] It is understood that the duty cycle detection module in this application is used to determine the amount of current to be injected / extracted into the first common-mode node and / or the second common-mode node based on the duty cycle detection result of the CMOS differential clock. Specifically, as long as the voltage difference between the DC components of the positive and negative signals of the CMOS differential clock is obtained, the amount of current to be injected / extracted into the first common-mode node and / or the second common-mode node can be determined based on this voltage difference. The means of implementing the duty cycle detection module can be conventional methods in the field of integrated circuits. Therefore, this application does not limit the specific structure of the duty cycle detection module, as long as it can achieve the function of the duty cycle detection module in the above embodiment. For example, the duty cycle detection module can be configured to consist of a differential filter circuit, a comparison circuit, and a processing circuit. The differential filter circuit is used to extract the DC component of the CMOS differential clock, the comparison circuit is used to compare the DC components of the positive and negative signals to obtain the voltage difference between them, and the processing circuit determines the amount of current to be injected / extracted into the first common-mode node and / or the second common-mode node based on the voltage difference output by the comparison circuit. For example, comparator circuits can be implemented using operational amplifiers, and processing circuits can be implemented using digital circuits.

[0051] In some embodiments, FIG5 shows another module schematic diagram of the CML-to-CMOS logic circuit provided in the embodiments of this application. As shown in FIG5, the circuit further includes:

[0052] The first PMOS transistor PM1 and the first NMOS transistor NM1 are connected. The source of the first PMOS transistor PM1 is connected to the power supply VDDA, and the drain is connected to the input terminal of the first inverting unit INV1. The source of the first NMOS transistor NM1 is grounded to VSSA, and the drain is connected to the input terminal of the first inverting unit INV1.

[0053] The second PMOS transistor PM2 and the second NMOS transistor NM2 are connected. The source of the second PMOS transistor PM2 is connected to the power supply VDDA, and the drain is connected to the input terminal of the second inverting unit INV2. The source of the second NMOS transistor NM2 is grounded to VSSA, and the drain is connected to the input terminal of the second inverting unit INV2.

[0054] The gates of the first PMOS transistor PM1 and the first NMOS transistor PM2 are configured such that when the CML signal to CMOS signal module is in operation, they receive a first high level and a first low level respectively to control the first PMOS transistor and the first NMOS transistor to be turned off. When the CML signal to CMOS signal module is in idle state, they both receive a positive signal of a preset differential clock to control the first PMOS transistor and the first NMOS transistor to be turned on alternately. At this time, the first PMOS transistor PM1 and the first NMOS transistor NM1 form an inverter, thereby inverting the positive signal of the preset differential clock and outputting it to the first inverting unit INV1. The second PMOS transistor PM2 and the second NMOS transistor NM2 are configured such that: when the CML signal to CMOS signal module is in operation, they receive a second high level and a second low level respectively to control the second PMOS transistor and the second NMOS transistor to be turned off; when the CML signal to CMOS signal module is in idle state, they both receive a negative signal of a preset differential clock to control the second PMOS transistor and the second NMOS transistor to conduct alternately, and output the negative signal of the preset differential clock to the second inverting unit INV2 after inverting it. Similarly, at this time, the second PMOS transistor PM2 and the second NMOS transistor NM2 form an inverter, thereby interfering with the output of the negative signal of the preset differential clock after inverting it to the second inverting unit. The preset differential clock is a differential clock with a frequency lower than the CML differential clock.

[0055] Traditional C2C circuits, when not performing CML differential clock conversion to CMOS differential clock, set the output to a high-speed level comparable to the CML differential clock frequency. However, in traditional C2C circuits, long-term transmission of high-speed levels can cause bias temperature instability in the MOSFETs, leading to problems such as increased absolute threshold voltage, decreased drain current, and reduced transconductance. This interferes with and reduces CMOS transmission speed, shortens device lifespan, and lowers device reliability. Furthermore, the negative bias temperature instability of PMOS has a greater impact on PMOS than the positive bias temperature instability of NMOS, further causing PMOS-NMOS mismatch and affecting the clock duty cycle.

[0056] Therefore, in this embodiment, if the first AC coupling unit C1 and the second AC coupling unit C2 do not receive the CML differential clock signal, it indicates that the current CML signal to CMOS signal module is in a non-working state. At this time, the transmission frequency of the CML signal to CMOS signal module is lower than the preset differential clock of the CML differential clock. In this way, the CML signal to CMOS signal module always transmits a low-speed "high level-low level-high level-low level...", thereby effectively reducing the impact of the MOS transistor BTI effect on the threshold voltage, drain current, transconductance, etc., extending the device life and enhancing the device reliability.

[0057] It is understood that, in the embodiments of this application, the method of detecting whether the CML signal to CMOS signal module is in working or idle state is not limited. For example, the designer can determine its current state by detecting whether the CML signal to CMOS signal module receives the CML differential clock, or the designer can extract the voltage of a certain node of the CML signal to CMOS signal module when it is working / idle, and determine its current state by detecting the voltage.

[0058] In some embodiments, FIG6 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiments of this application. As shown in FIG6, the circuit further includes a first selection unit MUX1, a second selection unit MUX2, a third selection unit MUX3 and a fourth selection unit MUX4.

[0059] The first selection unit MUX1 receives a first high-level signal TIEH1 and a positive signal LSCLKP from a preset differential clock, and selects either the first high-level signal TIEH1 or the positive signal LSCLKP from the preset differential clock for output based on the selection signal SEL. The second selection unit MUX2 receives a first low-level signal TIEL1 and a positive signal LSCLKP from the preset differential clock, and selects either the first low-level signal TIEH1 or the positive signal LSCLKP from the preset differential clock for output based on the selection signal SEL. The third selection unit MUX3 receives a second high-level signal TIEH2 and a negative signal LSCLKN from the preset differential clock, and selects either the second high-level signal TIEH2 or the negative signal LSCLKN from the preset differential clock for output based on the selection signal SEL. The fourth selection unit MUX4 receives a second low-level signal TIEL2 and a negative signal LSCLKN from the preset differential clock, and selects either the second low-level signal TIEH2 or the negative signal LSCLKN from the preset differential clock for output based on the selection signal SEL. Optionally, the first selection unit MUX1, the second selection unit MUX2, the third selection unit MUX3, and the fourth selection unit MUX4 can be configured as multiplexers. The selection signal SEL received by each selection unit can be configured to be output by an external control module such as a processor / controller / FPGA. This control circuit is used to control each selection unit to output a preset differential clock when the CML signal to CMOS signal module is not working, and to control each selection unit to output a first high level TIEH1, a first low level TIEL1, a second high level TIEH2, and a second low level TIEL2 respectively when the CML signal to CMOS signal module is working.

[0060] In some embodiments, FIG7 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiments of this application. As shown in FIG7, the circuit further includes a clock generation unit and a single-ended to differential unit.

[0061] The clock generation unit generates and outputs a single-ended clock. The single-ended to differential unit receives the single-ended clock, converts it into a preset differential clock, outputs the positive signal of the preset differential clock to the first and second selection units, and outputs the negative signal of the preset differential clock to the third and fourth selection units.

[0062] It is understood that the embodiments of this application do not limit the specific structure of the clock generation unit and the single-ended to differential conversion unit, and they can be implemented in various ways. For example, the clock generation unit can be implemented using components such as a phase-locked loop, a crystal oscillator, or even a counter / timer. The single-ended to differential conversion unit can also be constructed using logic gates, such as using a transmission gate and an inverter. The transmission gate is used to delay the output of the single-ended clock, and the inverter is used to invert the output of the single-ended clock. The output signal of the transmission gate and the inverter is the preset differential clock.

[0063] In some embodiments, FIG8 shows another schematic diagram of the CML signal to CMOS signal module provided in the present application. As shown in FIG8, the CML signal to CMOS signal module further includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG33 and a fourth transmission gate TG4.

[0064] The first transmission gate TG1 and the second transmission gate TG2 are respectively located at both ends of the first common-mode node VP, and the third transmission gate TG3 and the fourth transmission gate TG4 are respectively located at both ends of the second common-mode node VN. Furthermore, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are all configured to be turned on when the CML signal to CMOS signal module is in operation, and turned off when the CML signal to CMOS signal module is in idle state.

[0065] Optionally, when the CML signal to CMOS signal module is in operation, it receives the CML differential clock and converts it into a CMOS differential clock. Conversely, when the CML signal to CMOS signal module is idle, it stops receiving the CML differential clock. In this embodiment, the first resistor network R1 and the second resistor network R2 are disconnected from the signal transmission paths of the first inverting unit INV1 and the second inverting unit INV2 by controlling the transmission gates, thereby reducing the module power consumption when the CML signal to CMOS signal module is idle.

[0066] In some embodiments, the on and off states of each transmission gate are controlled by an external control module such as a processor / controller / FPGA. This control module is used to turn off each transmission gate when the CML signal to CMOS signal module is idle, and to turn on each transmission gate when the CML signal to CMOS signal module is working.

[0067] In one implementation, the embodiments of this application control the on / off state of the first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate through a pair of complementary logic levels. Specifically, when the complementary logic levels make the input and output of the transmission gate present a low impedance state, the transmission gate is in the on state; conversely, when the complementary logic levels make the input and output of the transmission gate present a high impedance state, the transmission gate is in the off state.

[0068] In some embodiments, FIG9 shows another module schematic diagram of the CML to CMOS logic circuit provided in the embodiments of this application. As shown in FIG9, the circuit further includes at least one CMOS differential clock transmission path.

[0069] The CML-to-CMOS logic circuit provided in this application converts the CML differential clock into a CMOS differential clock via a CML signal-to-CMOS signal module. This CMOS differential clock is used in subsequent CMOS differential clock transmission paths. Compared to traditional C2C circuits where adjusting the duty cycle between or after each CMOS transmission path results in high power consumption, this application directly adjusts the common-mode voltage of the CML-to-CMOS signal module. Therefore, the duty cycle adjustment process is unaffected by the CMOS transmission path, avoiding the problem of increased power consumption for duty cycle adjustment as the CMOS transmission path lengthens. This achieves correction of CMOS differential clock duty cycle deviation with lower power consumption.

[0070] This application also provides a chip 100. Figure 10 shows a schematic diagram of the chip provided in this application embodiment. The chip 100 includes the above-mentioned CML to CMOS logic circuit. A chip (Integrated Circuit, IC) is also called a chip. The chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0071] This application also provides an electronic device. Figure 11 shows a schematic diagram of the electronic device provided in this application embodiment. The electronic device includes a device body 110 and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0072] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.< / n> < / n> < / n> < / n>

Claims

A CML to CMOS logic circuit, characterized in that, include: The CML signal to CMOS signal module is used to convert the input CML differential clock into a CMOS differential clock output. The duty cycle correction module is connected to the common-mode node of the CML signal to CMOS signal module and is used to adjust the common-mode voltage of the CML signal to CMOS signal module to correct the duty cycle deviation of the CMOS differential clock. The CML to CMOS logic circuit as described in claim 1 is characterized in that, The CML signal to CMOS signal module includes: A first AC coupling unit and a first inverting unit, wherein the input terminal of the first AC coupling unit is used to receive the positive signal of the CMOS differential clock, the output terminal of the first AC coupling unit is connected to the input terminal of the first inverting unit, and the output terminal of the first inverting unit is used to output the negative signal of the CMOS differential clock. A first resistor network, the two ends of which are respectively connected to the input and output terminals of the first inverting unit, and the first resistor network includes a first common-mode node connected to the duty cycle correction module; The second AC coupling unit and the second inverting unit are used to receive the negative signal of the CMOS differential clock at the input terminal of the second AC coupling unit and the output terminal of the second AC coupling unit is connected to the input terminal of the second inverting unit. The output terminal of the second inverting unit is used to output the positive signal of the CMOS differential clock. The second resistor network has its two ends connected to the input and output terminals of the second inverting unit, respectively, and the second resistor network includes a second common-mode node connected to the duty cycle correction module. The CML to CMOS logic circuit as described in claim 2 is characterized in that, The duty cycle correction module includes: The first PMOS transistor array is used to inject current into the first common-mode node. In the first PMOS transistor array, the source of each PMOS transistor is connected to the power supply through the first current mirror, the drain of each PMOS transistor is connected to the first common-mode node, and the gate of each PMOS transistor receives an independent level signal to control the number of PMOS transistors turned on. The first NMOS transistor array is used to draw current from the first common-mode node. In the first NMOS transistor array, the source of each NMOS transistor is grounded through a second current mirror, the drain of each NMOS transistor is connected to the first common-mode node, and the gate of each NMOS transistor receives an independent level signal to control the number of NMOS transistors that are turned on. The second PMOS transistor array is used to inject current into the second common-mode node. In the second PMOS transistor array, the source of each PMOS transistor is connected to the power supply through a third current mirror, the drain of each PMOS transistor is connected to the second common-mode node, and the gate of each PMOS transistor receives an independent level signal to control the number of PMOS transistors turned on. The second NMOS transistor array is used to draw current from the second common-mode node. In the second NMOS transistor array, the source of each NMOS transistor is grounded through a fourth current mirror, the drain of each NMOS transistor is connected to the second common-mode node, and the gate of each NMOS transistor receives an independent level signal to control the number of NMOS transistors that are turned on. The CML to CMOS logic circuit as described in claim 3 is characterized in that, Also includes: The duty cycle detection module is used to acquire the DC components of the positive and negative signals of the CMOS differential clock, and output at least one independent level signal to the first PMOS array and / or the second NMOS array based on the voltage difference between the DC components of the positive and negative signals of the CMOS differential clock, or output at least one independent level signal to the first NMOS array and / or the second PMOS array. The CML to CMOS logic circuit as described in claim 2 is characterized in that, Also includes: The first PMOS transistor and the first NMOS transistor are connected, with the source of the first PMOS transistor connected to the power supply and the drain connected to the input terminal of the first inverting unit. The source of the first NMOS transistor is grounded and the drain is connected to the input terminal of the first inverting unit. The second PMOS transistor and the second NMOS transistor are connected. The source of the second PMOS transistor is connected to the power supply, and the drain is connected to the input terminal of the second inverting unit. The source of the second NMOS transistor is grounded, and the drain is connected to the input terminal of the second inverting unit. The gates of the first PMOS and the first NMOS transistors are configured such that: when the CML signal to CMOS signal module is in operation, they receive a first high level and a first low level respectively to control the first PMOS and the first NMOS transistors to be turned off; when the CML signal to CMOS signal module is in idle state, they both receive a positive signal of a preset differential clock to control the first PMOS and the first NMOS transistors to conduct alternately, and the positive signal of the preset differential clock is inverted and output to the first inverting unit. The second PMOS and the second NMOS transistors are configured such that: when the CML signal to CMOS signal module is in operation, they receive a second high level and a second low level respectively to control the second PMOS and the second NMOS transistors to be turned off; when the CML signal to CMOS signal module is in idle state, they both receive a negative signal of the preset differential clock to control the second PMOS and the second NMOS transistors to conduct alternately, and the negative signal of the preset differential clock is inverted and output to the second inverting unit. The preset differential clock is a differential clock with a frequency lower than that of the CML differential clock. The CML to CMOS logic circuit as described in claim 5 is characterized in that, Also includes: The first selection unit is used to receive the first high level and the positive signal of the preset differential clock, and select the first high level or the positive signal of the preset differential clock to output according to the selection signal. The second selection unit is used to receive the first low level and the positive signal of the preset differential clock, and select the first low level or the positive signal of the preset differential clock to output according to the selection signal. The third selection unit is used to receive the second high level and the negative signal of the preset differential clock, and select the second high level or the negative signal of the preset differential clock to output according to the selection signal; The fourth selection unit is used to receive the second low level and the negative signal of the preset differential clock, and select the second low level or the negative signal of the preset differential clock to output according to the selection signal. The CML to CMOS logic circuit as described in claim 6 is characterized in that, Also includes: Clock generation unit, used to generate and output a single-ended clock; A single-ended to differential unit is used to receive the single-ended clock, convert the single-ended clock into the preset differential clock, output the positive signal of the preset differential clock to the first selection unit and the second selection unit, and output the negative signal of the preset differential clock to the third selection unit and the fourth selection unit. The CML to CMOS logic circuit as described in claim 5 is characterized in that, The CML signal to CMOS signal module further includes a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate; The first transmission gate and the second transmission gate are respectively disposed at both ends of the first common-mode node, and the third transmission gate and the fourth transmission gate are respectively disposed at both ends of the second common-mode node; The first transmission gate, the second transmission gate, the third transmission gate, and the fourth transmission gate are all configured to be turned on when the CML signal to CMOS signal module is in working state, and turned off when the CML signal to CMOS signal module is in idle state. The CML to CMOS logic circuit as described in claim 4 is characterized in that, The duty cycle detection module and the CML signal to CMOS signal module also include: At least one level of CMOS differential clock transmission path. A chip characterized in that, Includes the CML to CMOS logic circuit described in any one of claims 1 to 9 above. An electronic device, characterized in that, It includes a device body and a chip as described in claim 10 disposed on the device body.

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