Control method, control apparatus, in-memory computing system, and electronic device

Abstract

Provided are a control method, a control apparatus (410), an in-memory computing system (100), and an electronic device (1600). The control method is used for the in-memory computing system (100). The in-memory computing system (100) comprises the control apparatus (410) and a memory circuit (420). The memory circuit (420) comprises a plurality of memory cell sets, and the plurality of memory cell sets include a first memory cell set and a second memory cell set. The control method may be executed by the control apparatus (410), and comprises: controlling first programming of the first memory cell set, wherein the first programming comprises at least one writing and verification process; and during the first programming of the first memory cell set, controlling the working state of the second memory cell set. Thus, the programming efficiency is improved, or a computing task is responded to in advance, thereby improving the working efficiency of the in-memory computing system (100).

Description

Control methods, control devices, computing systems and electronic equipment Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to control methods, control devices, memory computing systems, and electronic devices. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their overall efficiency still needs improvement. Summary of the Invention

[0004] This application provides a control method, control device, in-memory computing system, and electronic device that can improve the working efficiency of in-memory computing architecture.

[0005] In a first aspect, a control method is provided for an in-memory computing system, the in-memory computing system including a control device and a storage circuit, the storage circuit including multiple sets of storage cells, the multiple sets of storage cells including a first set of storage cells and a second set of storage cells. The control method can be executed by the control device and includes: controlling a first programming of the first set of storage cells, the first programming including at least one write and verification; and controlling the operating state of the second set of storage cells during the first programming of the first set of storage cells.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, controlling the first programming of the first storage cell set includes: inputting a first command to the storage circuit, the first command including first indication information and first write data, the first indication information being used to indicate the first storage cell array of the first storage cell set, and the first write data being used for the first data writing of the first storage cell array of the first storage cell set; and verifying based on the result of the first data writing.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, controlling the working state of the second storage unit set during the first programming of the first storage unit set includes: controlling the second programming of the second storage unit set during the first programming of the first storage unit set, wherein the second programming includes at least one of writing and verification.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, during the first programming process of the first storage cell set, controlling the second programming of the second storage cell set includes: during the first data writing process of the first storage cell array of the first storage cell set, inputting a second command to the storage circuit, the second command including second indication information and second write data, the second indication information being used to indicate the first storage cell array of the second storage cell set, and the second write data being used for the second data writing of the first storage cell array of the second storage cell set.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information and the second indication information are used to indicate a storage cell array whose location is different from that of the first storage cell set and the second storage cell set.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the control method further includes: during the first data writing process, inputting a third command to the storage circuit, the third command including third indication information and third write data, the third indication information being used to indicate the second storage cell array of the first storage cell set, and the third write data being used for the third data writing of the second storage cell array of the first storage cell set.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information and the third indication information are used to indicate a storage cell array with different central locations of the first storage cells.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the control method further includes: inputting a fourth command to the storage circuit, the fourth command including fourth indication information and fourth write data, the fourth indication information being used to indicate the second storage cell array of the second storage cell set, and the fourth write data being used for the fourth data write of the second storage cell array of the second storage cell set, wherein the first data write and the fourth data write are performed in parallel; and verification is performed based on the result of the fourth data write.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information and the fourth indication information are used to indicate a storage cell array in which the first storage cell set and the second storage cell set are located.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, verification based on the result of the first data writing and verification based on the result of the fourth data writing are performed in parallel.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, during the first programming of the first storage unit set, the working state of the second storage unit set is controlled, including: during the first programming of the first storage unit set, the computation of the second storage unit set is controlled.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the first programming includes multiple writes and verifications, the multiple writes and verifications include a first write and a first verification, as well as a second write and a second verification. During the first programming of the first storage cell set, controlling the computation of the second storage cell set includes: controlling the computation of the second storage cell set after the first write and the first verification and before the second write and the second verification.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the first programming includes a first write and a first verification. During the first programming of the first storage cell set, the computation of the second storage cell set is controlled, including: controlling the computation of the second storage cell set after the first write and before the first verification.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the control method further includes: controlling the computation of the second storage cell subset of the first storage cell set during the first programming process of the first storage cell subset of the first storage cell set.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the first programming includes multiple writes and verifications, the multiple writes and verifications include a first write and a first verification, as well as a second write and a second verification. In the first programming process of the first storage cell subset of the first storage cell set, controlling the computation of the second storage cell subset of the first storage cell set includes: controlling the computation of the second storage cell subset after the first write and the first verification of the first storage cell subset and before the second write and the second verification.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the first programming includes multiple writes and verifications, the multiple writes and verifications include a first write and a first verification, as well as a second write and a second verification. During the first programming of the first storage cell subset of the first storage cell set, controlling the computation of the second storage cell subset of the first storage cell set includes: controlling the computation of the second storage cell subset after the first write and before the first verification of the first storage cell subset.

[0021] In a second aspect, a control device is provided, comprising at least one processor and an interface circuit, the interface circuit being electrically connected to a storage circuit, and the at least one processor being used to execute a control method as described in any of the first aspects.

[0022] Thirdly, a storage computing system is provided, comprising: a storage circuit including a plurality of storage cell sets, the plurality of storage cell sets including a first storage cell set and a second storage cell set; and a control device electrically connected to the storage circuit for executing a control method as described in any of the first aspects.

[0023] Fourthly, an electronic device is provided, including a storage and computing system as described in the third aspect.

[0024] Based on the above technical solution, the storage circuit can be programmed and controlled according to the storage cell set. During the programming process of one storage cell set, the working state of other storage cell sets can be controlled, so that other storage cell sets can adapt to the current needs of the in-memory computing system. For example, if the current priority of the in-memory computing system is to complete the programming of the storage circuit as soon as possible, the programming process of other storage cell sets can be used to improve the overall programming efficiency of the storage circuit. As another example, if the current priority of the in-memory computing system is to complete business processing as soon as possible, the computing tasks of other storage cell sets can be inserted during the programming process of the current storage cell set, thereby improving the response speed of the in-memory computing system to business. Attached Figure Description

[0025] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0026] Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0027] Figure 3 shows a schematic flowchart of a control method according to an exemplary embodiment of this application.

[0028] Figure 4 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0029] Figure 5 shows a timing diagram of a programming command according to an exemplary embodiment of this application.

[0030] Figure 6 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application.

[0031] Figure 7 illustrates a programming flow diagram according to an exemplary embodiment of this application.

[0032] Figure 8 illustrates another programming flow diagram according to an exemplary embodiment of this application.

[0033] Figure 9 illustrates another programming flow diagram according to an exemplary embodiment of this application.

[0034] Figure 10 illustrates another programming flow diagram according to an exemplary embodiment of this application.

[0035] Figure 11 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0036] Figure 12 shows a schematic diagram of the workflow of an in-memory computing system according to an exemplary embodiment of this application.

[0037] Figure 13 illustrates a schematic diagram of the workflow of another in-memory computing system according to an exemplary embodiment of this application.

[0038] Figure 14 shows a schematic flowchart of a programming method according to an exemplary embodiment of this application.

[0039] Figure 15 shows a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0040] Figure 16 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0042] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0043] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0044] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0045] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0046] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0047] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.

[0048] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0049] The storage unit includes a semiconductor device and can utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit can utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element can be connected to the semiconductor device, and the stored energy can act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0050] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0051] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0052] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0053] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data w ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0054] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0055] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in the example of Figure 2, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0056] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly along columns, and the output terminals can be connected collinearly along rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, a memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A storage cell may include multiple transistors; for example, a storage cell may include a first transistor and a second transistor, wherein the gate of the first transistor and the source or drain of the second transistor are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0057] In-memory computing systems can use storage circuits to store data, which can then be read by control circuits for near-in-memory computation. Alternatively, the system can use storage circuits to store data (e.g., weight data) and provide input data to these circuits for in-memory computation. The process of writing data to the storage circuits is called programming. To improve the accuracy of data writing, this process may require multiple write and verification steps, especially when performing in-memory computations. The accuracy requirements for weight data are high, necessitating multiple write and verification processes to enhance computational accuracy. Therefore, the programming process for in-memory computing systems can be time-consuming, leading to lower system efficiency (e.g., programming efficiency).

[0058] Alternatively, frequent operations on the storage circuitry during operation may degrade the accuracy of the stored data, thus affecting the computational accuracy of the in-memory computing system. Therefore, the in-memory computing system may require frequent reprogramming of the storage circuitry, i.e., rewriting data, to ensure the accuracy of the computational results. However, during programming, the execution or response of other tasks is interrupted, thus affecting the system's response speed and resulting in lower efficiency. For example, programming the storage circuitry slows down its response to computational tasks, thereby reducing the system's overall responsiveness. For instance, if the in-memory computing system performs frequent read operations on the storage cells during computation, the number of reads may reach the limit within a short time. If the storage cells are not reprogrammed, the accuracy of the data read from the storage circuitry will be affected, consequently impacting the accuracy of the computational results. For example, the accuracy of the weight data stored in the storage circuit decreases as the number of calculations performed by the storage circuit increases, thus affecting the calculation accuracy of the in-memory computing system. Therefore, the storage circuit may need to be reprogrammed during the operation of the in-memory computing system. This programming process will affect the response speed of the in-memory computing system to other tasks, such as calculation tasks, resulting in lower efficiency of the in-memory computing system (e.g., response efficiency to calculation tasks).

[0059] Based on this, the embodiments of this application improve the working efficiency of the in-memory computing system by inserting control over the working state of other storage cell sets in the storage circuit during the programming process of the storage cell set in the storage circuit. For example, inserting the programming of other storage cell sets can improve the overall programming efficiency of the in-memory computing system. Similarly, inserting the calculation of other storage cell sets can improve the response speed of the in-memory computing system to calculation tasks.

[0060] For example, Figure 3 shows a schematic flowchart of a control method according to an exemplary embodiment of this application. This control method 300 can be used in a memory computing system, such as the memory computing system shown in Figure 1 or Figure 2, which includes a control device and a storage circuit, wherein the storage circuit may include multiple sets of storage cells, each set of storage cells including multiple storage cells. The control method 300 can be executed by a control device, for example, by the control circuit shown in Figure 1 or Figure 2.

[0061] As shown in Figure 3, the control method 300 may include the following steps.

[0062] S310: Controlling the first programming of the first set of storage cells. The first programming includes at least one write and verification.

[0063] S320: During the first programming of the first memory cell set, control the working state of the second memory cell set.

[0064] In the above control methods, the storage circuit can be programmed and controlled according to storage cell sets. During the programming process of one storage cell set, the working state of other storage cell sets can be controlled, allowing other storage cell sets to adapt to the current needs of the in-memory computing system. For example, if the current priority of the in-memory computing system is to complete the programming of the storage circuit as soon as possible, the programming of other storage cell sets can be inserted during the programming process of the current storage cell set, thereby improving the overall programming efficiency of the storage circuit. Similarly, if the current priority of the in-memory computing system is to complete business processing as soon as possible, the computing tasks of other storage cell sets can be inserted during the programming process of the current storage cell set, thereby improving the response speed of the in-memory computing system to business.

[0065] This application embodiment can set the main control and verification of programming in the control device, thereby facilitating the control device to perform programming control that is more in line with the current needs of the in-memory computing system based on the current situation of the in-memory computing system, improving the flexibility of the in-memory computing system, enabling the in-memory computing system to respond to business needs in a timely manner and perform calculations in the face of high-priority business needs, and insert programming operations of other storage unit sets in the absence of business needs or high-priority business needs, thereby improving the overall programming efficiency and preparing for the business needs of the in-memory computing system as soon as possible.

[0066] Taking NAND flash memory as an example, the programming (also known as data writing) process of NAND flash memory is currently a serial write process, and write control and verification can be performed internally within the NAND flash memory. During write control, boost control is performed internally within the NAND flash memory. The charge pump circuit converts the chip's normal operating voltage (for example, 3.3V or 1.8V) to a higher voltage (for example, 15-20V) through capacitor charging and discharging, preparing for electron injection. This higher voltage is referred to as the injection voltage below. Then, electron injection is performed. For memory cells to be written with the first logic value (e.g., 0), the injection voltage is applied to the control gate, causing channel electrons to tunnel into the floating gate. For memory cells to be written with the second logic value (e.g., 1), the above electron injection process is not performed. After electron injection is completed, a verification process is performed. During verification, the data in the memory cell is read and compared with the original data. If the comparison result matches, the write is successful; if the comparison result does not match, error correction or rewriting can be performed. The write and verification process may require multiple iterations to achieve accurate data writing. For example, due to factors such as the working environment or manufacturing process, it may require 5-10 write and verification processes to achieve accurate data writing. If verification fails, the storage circuit can control the voltage, for example, by further increasing the injection voltage and performing electron injection and verification again.

[0067] In this embodiment, the control and verification of the injection voltage can be set in the control device. The injection voltage in the storage circuit is controlled by the control device, and the verification is performed in the control device. In this way, the entire programming process can be divided into more granular stages. Parallel operations between different sets of storage units can be achieved by using different stages, which improves the flexibility of the in-memory computing system and enhances the working efficiency of the in-memory computing system. For example, by inserting the programming of other sets of storage units into the programming process of one set of storage units, the overall programming efficiency of the in-memory computing system can be improved. Similarly, by inserting the computation of other sets of storage units into the programming process of one set of storage units, the response speed of the in-memory computing system to computational tasks can be improved.

[0068] By programming a set of storage cells, data (referred to as target data for distinction) can be written into the storage cells of that set (referred to as the target storage cell set for distinction). This programming process of writing target data into the target storage cell set can be achieved through at least one write and verification operation. In one write operation, the data provided by the control device to the storage circuit (referred to as write data for distinction) can be the same as or different from the target data. In different write operations, the write data provided by the control device to the storage circuit can be the same as or different from the target data. For example, in one write operation of the programming, the control device provides write data to the storage circuit, causing the storage circuit to write the write data into the target storage cell set. This write operation can be the first write operation of the target data, and the write data can be the same as the target data, or it can be the x-th write operation of the target data, where x is a positive integer greater than or equal to 2, and the write data can be the same as or different from the target data. In one verification operation of the programming, the target storage cell set outputs a signal. This output signal reflects the result of the corresponding write operation and can be compared with the target data to determine whether the target data has been correctly written into the target storage cell set, i.e., verifying whether the programming was successful. The aforementioned single write operation and corresponding verification can be referred to as a write and verification process in programming. According to some embodiments of this application, programming may include multiple write and verification processes. For example, in programming, after a write and verification process is completed, if the output signal does not match the written data or the matching degree is below a threshold, another write and verification process can be executed. At this time, the same or different written data can be provided to the target storage unit set, and the output signal can be obtained for verification. The above process can be repeated multiple times, for example, until the output signal matches the written data or the matching degree is equal to or higher than the threshold.

[0069] Writing and verification can be performed on a per-cell array basis. A cell set can include multiple cell arrays. During a single write control operation, the control device can provide the storage circuit with write data for one cell array.

[0070] For example, in one write operation, the control device inputs write data d1 to the first storage cell array of the first storage cell set. Write data d1 is used to write the first data (i.e., target data) of the first storage cell array, that is, to write the first data into the first storage cell set. An output signal reflecting the result of this write operation is acquired. Based on this output signal, verification is performed to determine whether the write operation successfully wrote the first data into the first storage cell array. When the first data is successfully written into the first storage cell array, the programming of the first storage cell array is complete, and programming of other storage cell arrays can continue. If the first data is not successfully written into the first storage cell array, in the next write operation, the control device inputs write data d2 to the first storage cell array of the first storage cell set. Write data d2 is used to write the first data into the first storage cell array, that is, to write the first data into the first storage cell set. An output signal reflecting the result of this write operation is acquired. Based on this output signal, verification is performed to determine whether the write operation successfully wrote the first data into the first storage cell array. When the first data is successfully written to the first storage cell array, the programming of the first storage cell array is complete. If the first data is not successfully written to the first storage cell array, the above operation is repeated to continue the next write and verification. The written data can include the first data. For example, the first write data can include the first data, or the write data of each subsequent write can include the first data, thus simplifying the verification and control logic. Alternatively, the first write data can include the first data, and the write data of each subsequent write can include the data of the storage cells that have not been written, thus saving programming power consumption.

[0071] According to some embodiments of this application, the writing and verification of the programming of the storage circuit can be controlled by a control device. As an example, controlling the first programming of a first set of storage cells by the control device can include: the control device controlling the storage circuit to write first write data into the first storage cell array; and the control device verifying the result of the first data writing, whereby the result of the first data writing is the result of this writing operation. Controlling the first programming of the first set of storage cells, or controlling the storage circuit to write the first write data into the first storage cell array, can include: inputting a first command to the storage circuit, the first command including first indication information and first write data, the first indication information indicating the first storage cell array of the first set of storage cells, and the first write data being used for the first data writing of the first storage cell array of the first set of storage cells. Verifying the result of the first data writing can include: the first storage cell array outputting an analog signal, which can be converted into digital feedback data by a conversion circuit (e.g., an analog-to-digital converter, ADC) and then sent to the control device; the control device comparing the target data and the feedback data for consistency; when the target data and the feedback data are consistent, it indicates that the first data writing was successful; when the target data and the feedback data are inconsistent, it indicates that the first data writing failed or was unsuccessful.

[0072] For example, please refer to Figure 4, which shows a schematic diagram of another in-memory computing system 400 according to an exemplary embodiment of this application. As shown in Figure 4, programming writing may include the control device 410 inputting a programming command (e.g., a first command) to the storage circuit 420, wherein the write data included in the programming command is determined based on target data in the control device 410, and the write data may be the same as or different from the target data. The storage circuit writes the write data to the corresponding storage cell array according to the programming command. Programming verification may include the storage circuit 420 outputting an output signal from the corresponding storage cell array, the output signal being converted into feedback data by the conversion circuit 430 and input to the control device, and the control device 410 comparing the target data and the feedback data to perform verification. Thus, the control device can count the number of writes and verifications that have been performed for programming the target data, and control the stage of the storage circuit in the programming accordingly, thereby refining the control device's control over the programming of the storage circuit, improving the flexibility of the control device in controlling the programming process, and providing a basis for the control device to insert control over the working state of other storage cell sets during the programming process of the storage cell set.

[0073] As an example, Figure 5 illustrates a timing diagram of a programming command according to an exemplary embodiment of this application. For example, the timing of a programming command input by the control device 410 to the storage circuit 420 can be as shown in Figure 5. The programming command may include a programming command start indication 510 and a programming command end indication 540, used to indicate the resources occupied by inputting the programming command. For example, in the time domain, the programming command start indication 510 is input in the first cycle, and the programming command end indication 540 is input in the nth cycle. The cycle between the programming command start indication 510 and the programming command end indication 540 is used to input other content of the programming command. The programming command may also include a write address 520, used to indicate a storage cell array in a storage cell set in the storage circuit via the address. For example, the write address 520 may be the first indication information in the aforementioned first command. The programming command may also include multiple data 530s, used to indicate the data to be written to the storage cell array indicated by the write address 520. For example, the first write data in the first command may include multiple data 530s. When executing the programming command, the data can be written to the memory cells in the memory cell array in a preset positional order. For example, the data to be written includes sub-data of Y memory cells in the memory cell array. The order of the sub-data has a predefined relationship with the positional order of the memory cells in the memory cell array. The data to be written can be written to the memory cells in the memory cell array indicated by the write address 520 according to the predefined relationship, and the sub-data in the data to be written is written to memory cells at different positions. This application does not limit the writing time order between memory cells and can perform the writes in parallel or serially.

[0074] According to some embodiments, there may be a time interval between the address input and the data input, which can be used for the storage circuit to switch from receiving address signaling to receiving data signaling. For example, there may be an interval between the second cycle and the third cycle, such as the address-data interval.

[0075] Figure 6 illustrates a schematic diagram of a storage circuit according to an exemplary embodiment of this application. By way of example and not limitation, the control method 300 can be used to control, for example, the storage circuit 600 shown in Figure 6. The storage circuit 600 may include multiple sets of storage cells, which may be, for example, storage planes or banks arranged along a second direction as shown in Figure 6. Hereinafter, storage cell sets are described using storage planes as an example, but are not limited thereto; storage cell sets may be replaced by storage banks. For example, the storage circuit 600 may include storage cell sets plane_0 to plane_a, where a is a positive integer greater than or equal to 1. To facilitate illustrating the structure of the storage cell sets, the extensions of storage cell sets plane_1 to plane_a in the third direction are omitted, so that the structure of the storage cell set is shown through plane_0. In some possible implementations, a storage cell set may include multiple subsets of storage cells, which may include, for example, multiple blocks arranged along a first direction within a storage cell set as shown in Figure 6. For example, the storage cell set plane_0 may include storage cell subsets block_0 to block_b, where b is an integer greater than or equal to 1. In some possible implementations, a storage cell subset may include multiple storage arrays, which may be arranged along a first direction, and the storage cells in a storage array may be arranged along a second and a third direction. That is, the storage cell subset may include multiple storage arrays, which may include two-dimensional arrays, the arrangement directions of which include the second and third directions, and the multiple storage arrays are arranged along the first direction. For ease of illustration, Figure 6 only shows the structure of the storage array in block_0 of plane_0; the arrangement of storage cells in other storage cell subsets can be referenced from block_0 of plane_0. In some possible implementations, multiple storage cells arranged along the second direction in a storage array may be referred to as a storage page, and the storage array may include multiple storage pages arranged along a third direction.

[0076] In some embodiments of this application, the first storage cell array may include storage pages, and the first indication information may include address information for indicating storage pages. The address information may include the address of a storage cell set, the address of a storage cell subset, and the address of a storage page. Thus, the storage page addresses of different storage cell sets and storage cell subsets may be the same. By combining the addresses of the storage cell set and storage cell subset to locate the storage page, the bit requirement for the storage page address information can be reduced, saving the resource overhead of address information.

[0077] In some embodiments of this application, memory cells located at different coordinates (layers or positions) in a third direction can be connected by different word lines. For example, as shown in FIG6, the memory circuit 600 may include word lines wl_0 to wl_c along a third direction, where c is an integer greater than or equal to 1; the word line can be used to enable or disable memory cells in that layer or memory cells within a set of memory cells in that layer. Within a set of memory cells, on the plane formed by a first direction and a second direction selected by a word line, a subset of memory cells may include multiple memory pages, such as memory pages page_0 to page_d, where d is an integer greater than or equal to 1.

[0078] In some embodiments of this application, programming can be performed on a unit basis: a memory cell array, which may include a one-dimensional array or a two-dimensional array, for example, programming on a unit basis: memory pages. For instance, the first set of memory cells described in the above embodiments can be any set of memory cells in a memory circuit, such as the memory cell set plane_0. The first memory cell array can be any memory page of any subset of memory cells, for example, the memory page page_0 corresponding to word line wl_0 in the memory cell subset block_0 of the memory cell set plane_0; or, for example, the memory page page_1 corresponding to wl_1 in the memory cell subset block_1 of the memory cell set plane_1, and so on.

[0079] Taking the storage circuit 600 as an example, during the programming process of the storage cell set plane_0, the control device can control the working state of other storage cell sets (e.g., storage cell set plane_k, k∈[1,a]) in the storage circuit 600. For example, the control device can control the programming of storage cell set plane_k during the programming process of the first storage cell set plane_0, thereby improving the parallelism of programming and increasing programming efficiency. This reduces the time required for the entire storage circuit to complete programming. If there are computational tasks during the programming process, it also reduces the time for computational tasks to wait for programming completion, improving the response speed of the in-memory computing system to computational tasks. For another example, the control device can control the computation of storage cell set plane_k during the programming process of storage cell set plane_0, thereby advancing the execution of computational tasks to before programming completion, thereby reducing the waiting time for computational tasks and improving the response speed of the in-memory computing system to computational tasks. The following describes, in conjunction with embodiments, methods for inserting the programming or computation of other storage cell sets during the programming process of storage cell sets.

[0080] According to some embodiments of this application, controlling the operating state of the second storage cell set during the first programming process of the first storage cell set may include: controlling the second programming of the second storage cell set during the first programming process of the first storage cell set, wherein the second programming includes at least one of writing and verification. For example, at least one of the write control or verification control of the second storage cell set can be inserted into the execution process of the first programming to improve the overall programming efficiency. Taking the storage circuit 600 as an example, for example, during the programming process of the storage cell set plane_0, the control device can also control the storage cell set plane_1 to be programmed. This application does not limit the number of storage cell sets controlled for programming during the programming process of the first storage cell set; for example, more than two storage cell sets can be controlled for programming. In addition, during the programming process of one storage cell array of storage cell set plane_0, the control device can also control other storage cell arrays of storage cell set plane_0 to be programmed. Taking storage circuit 600 as an example, during the programming process of storage page 0 of storage cell set plane_0, the programming of some or all of the storage cell sets in multiple storage cell sets plane_0, plane_1, ..., plane_a can be controlled. For example, programming commands for the storage cell array of these storage cell sets for the next programming can be input.

[0081] According to some embodiments of this application, the programming of a memory cell set can be controlled by a control device through programming commands. For example, during the first programming process of a first memory cell set, controlling the second programming of a second memory cell set includes: during the first data writing process of the first memory cell array of the first memory cell set, inputting a second command to the storage circuit. The second command includes second indication information and second write data. The second indication information is used to instruct the first memory cell array of the second memory cell set, and the second write data is used for the second data writing of the first memory cell array of the second memory cell set. The first data writing process may include the process of writing based on any input write data during the first data writing process. The second data is the target data for programming the first memory cell array of the second memory cell set, and the second write data may include any input write data during the second data writing process.

[0082] According to some embodiments of this application, the control device can input programming commands for multiple sets of storage cells to the storage circuit, thereby controlling the multiple sets of storage cells to perform programming in parallel, such as performing a data write and / or verification in parallel. Multiple programming commands for the multiple sets of storage cells to be programmed in parallel can be sequentially input to the storage circuit by the control device; after the multiple programming commands are input, the storage circuit can execute the corresponding programming command in the corresponding set of storage cells, and the multiple programming commands are executed in parallel in the multiple sets of storage cells to further improve programming efficiency. For example, please refer to Figure 7, which shows a schematic diagram of a programming flow according to an exemplary embodiment of this application. As shown in Figure 7, within time period T1, the storage circuit can sequentially receive multiple programming commands, such as receiving programming command #0 in sub-time period T1_0, receiving programming command #1 in sub-time period T1_1, receiving programming command #a1 in sub-time period T1_a1, etc., where a1 is a positive integer greater than 1 and less than or equal to a. In this system, the write addresses of multiple programming commands indicate different sets of memory cells. For example, the write address of programming command #0 could indicate a specific array of memory cells in the set plane_0, the write address of programming command #1 could indicate a specific array of memory cells in the set plane_1, and the write address of programming command #a1 could indicate a specific array of memory cells in the set plane_a1. During time period T2, the memory circuit operates in programming mode, where multiple programming commands can be executed in parallel. For instance, in programming mode, the memory circuit can write the data from programming command #0 to a specific array of memory cells in the set plane_0, simultaneously write the data from programming command #1 to a specific array of memory cells in the set plane_1, and simultaneously write the data from programming command #a1 to a specific array of memory cells in the set plane_a1.

[0083] For example, in some embodiments of this application, the control method may further include: inputting a fourth command to the storage circuit, the fourth command including fourth indication information and fourth write data, the fourth indication information being used to indicate the second storage cell array of the second storage cell set, and the fourth write data being used for the fourth data write of the second storage cell array of the second storage cell set, wherein the first data write and the fourth data write can be performed in parallel; and verification based on the result of the fourth data write. The first command and the fourth command can be any two programming commands shown in Figure 7.

[0084] The programming flow shown in Figure 7 is just an example. The input and execution order of programming commands for different memory cell sets can be arbitrary. That is, programming commands for different memory cell sets can be input and executed at any time. The input and execution of programming commands for a certain memory cell set can not affect the input and execution of programming commands for other memory cell sets.

[0085] According to some embodiments of this application, the first indication information and the fourth indication information are used to indicate the memory cell arrays at the same location in the first memory cell set and the second memory cell set. That is, the write address of the parallel-executed programming command can indicate the memory cell array at the same location in different memory cell sets. Taking the structure shown in FIG6 and the process shown in FIG7 as an example, assuming that the memory pages arranged along the first direction in the memory array include page_0, page_1, ..., page_d, the write address of programming command #0 can indicate the memory page page_0 of the memory cell subset block_0 in memory cell set plane_0, the write address of programming command #1 can indicate the memory page page_0 of the memory cell subset block_0 in memory cell set plane_1, and the write address of programming command #a1 can indicate the memory page page_0 of the memory cell subset block_0 in memory cell set plane_a1. This can reduce the control difficulty of the control device controlling the programming process of multiple memory cell sets in parallel.

[0086] The above embodiments save the total time required to complete multiple programming operations by performing multiple parallel programming operations on multiple sets of memory cells in the memory circuit. If computational tasks exist during programming, the waiting time for these tasks can also be reduced. In the same set of memory cells or the same subset of memory cells, programming of multiple memory cell arrays is still performed serially. To address this, the control method provided in this application can further shorten the total time for programming multiple memory cell arrays within the same set of memory cells, further improving programming efficiency. If computational tasks exist during programming, the waiting time for these tasks can also be further reduced.

[0087] According to some embodiments of this application, during the first data writing process, the control device may further input a third command to the storage circuit. The third command includes third indication information and third write data. The third indication information is used to instruct the second storage cell array of the first storage cell set, and the third write data is used for the third data writing of the second storage cell array of the first storage cell set. The first data writing process may include the writing process based on any input write data during the first data writing process. The third data is the target data for programming the second storage cell array of the first storage cell set, and the third write data may include any input write data during the third data writing process.

[0088] For example, please refer to Figure 8, which illustrates another programming flow diagram according to an exemplary embodiment of this application. As shown in Figure 8, during time period T1, the storage circuit can receive programming command #00 input by the control device. The write address of programming command #00 may indicate the storage page_0 of the storage cell subset block_0 in the storage cell set plane_0. During time period T2, the storage circuit operates in programming state, and the storage circuit executes programming command #00, writing the write data of programming command #00 to the storage page_0 of the storage cell subset block_0 in the storage cell set plane_0. During time period T2, when the storage circuit operates in programming state, the storage circuit can also simultaneously receive programming command #01 input by the control device. The write address of programming command #01 may indicate the storage page_1 of the storage cell subset block_0 in the storage cell set plane_0. By way of example and not limitation, the storage circuit may include a first register and a second register. Programming command #00 input in time period T1 can be stored in the first register and read out in time period T2 to execute the corresponding programming, while programming command #01 input in time period T2 can be stored in the second register, thus avoiding mutual interference between programming commands. During time period T3, after programming command #00 is executed, the storage circuit can directly begin executing programming command #01, writing the write data of programming command #01 to page_1 of the storage page_0 of the storage page_0 subset of storage page_0 in the storage page_0 set. Similarly, during time period T3, when the storage circuit is in programming mode, it can also simultaneously receive programming command #02 input from the control device. The write address of programming command #02 may indicate page_2 of the storage page_0 of the storage page_0 subset of storage page_0 in the storage page_0 set. Furthermore, during time period T4, after programming command #01 is executed, the storage circuit can directly begin executing programming command #02. Therefore, the input and execution of programming commands alternate, saving time spent waiting for command input and further improving the programming efficiency of the memory circuit. Figure 8 only describes the time period T1-T4 as an example; in practice, more time periods can be included to program more memory cell arrays.

[0089] According to some embodiments of this application, the above-described control method for saving waiting time for command input is also applicable to scenarios where programming involves multiple writes and verifications. For example, please refer to FIG9, which shows another programming flow diagram according to an exemplary embodiment of this application. As shown in FIG9, during time period T1, the storage circuit can receive programming command #00 input by the control device, and the write address of programming command #00 may indicate the storage page page_0 of the storage cell subset block_0 in the storage cell set plane_0. During time period T2, the storage circuit operates in programming state, and the storage circuit executes the first write of programming command #00, writing the write data of programming command #00 to the storage page page_0 of the storage cell subset block_0 in the storage cell set plane_0; at the same time, the storage circuit can also receive programming command #01 input by the control device, and the write address of programming command #01 may indicate the storage page page_1 of the storage cell subset block_0 in the storage cell set plane_0. During time period T3, the verification of programming command #00 is executed. The storage circuit can output feedback data of page_0, a storage page of the storage cell subset block_0 in the storage cell set plane_0, and the control device verifies the execution result of programming command #00 based on this feedback data. During time period T4, the storage circuit operates in programming mode. The storage circuit executes the first write of programming command #01, writing the write data of programming command #01 to page_1, a storage page of the storage cell subset block_0 in the storage cell set plane_0. Simultaneously, the storage circuit can also receive programming command #00' from the control device for another write and verification process of the above storage page page_0. The write data of programming command #00' can be the same as or different from the write data of programming command #00. During time period T5, the verification of programming command #01 is executed. The storage circuit can output feedback data of page_1, a storage page of the storage cell subset block_0 in the storage cell set plane_0, and the control device verifies the execution result of programming command #01 based on this feedback data. Similar to time periods T2 and T3, during time period T6, the storage circuit can execute the writing of programming command #00', writing the data of programming command #00' into storage page page_0 of storage cell subset block_0 in storage cell set plane_0; at the same time, the storage circuit can also receive programming command #01' input from the control device for another write and verification process of the above storage page page_1, preparing for subsequent programming command #01' to write and verify the above storage page page_1.During time period T7, the verification of programming command #00' is executed. The storage circuit can output the feedback data of the above storage page_0 again, and the control device verifies the execution result of the programming for storage page_0, i.e. the execution result of programming command #00', based on the feedback data.

[0090] According to some embodiments of this application, the start time of writing programming command #01 may differ from that in Figure 9. The writing time of programming command #01 may be longer than the time of receiving programming command #00'. During time period T3, the storage circuit executes the writing of programming command #01, writing the write data of programming command #01 to page_1 of storage page_1 in storage page_0 of storage page_0 in storage page_0 of storage page_0. For example, the writing of programming command #01 may start simultaneously with the verification of programming command #00; or, the writing of programming command #01 may start during the verification process of programming command #00. The writing of programming command #01 may be executed until the end of time period T4.

[0091] According to some embodiments of this application, the start time of writing programming command #00' may differ from that in Figure 9. The writing time of programming command #00' may be longer than the time of receiving programming command #01'. During time period T5, the storage circuit executes the writing of programming command #00', writing the write data of programming command #00' to page_0 of the storage ...

[0092] According to some embodiments of this application, during time period T7, the storage circuit executes the write of programming command #01', writing the write data of programming command #01' to page_1 of storage page_1 in storage page_0 of storage page_0 in storage page_0 of storage page_0. For example, the write of programming command #01' can start simultaneously with the verification of programming command #00'; or, the write of programming command #01' can start during the verification process of programming command #00'.

[0093] According to some embodiments of this application, the control method described above for saving waiting time for command input is also applicable to parallel programming schemes involving multiple memory cell sets. That is, the embodiments shown in Figures 7 and 8 above can be combined. For example, please refer to Figure 10, which shows another programming flow diagram according to an exemplary embodiment of this application. As shown in Figure 10, during time period T1, the storage circuit can sequentially receive multiple programming commands. The write addresses of the multiple programming commands indicate different memory cell sets. For example, the write address of programming command #00 may indicate memory cell set plane_0, the write address of programming command #10 may indicate memory cell set plane_1, and so on. The write address of programming command #p0 may indicate a memory cell array in plane_p, where p is an integer greater than or equal to 1. Optionally, the memory cell arrays in different memory cell sets are in the same position, which simplifies the control logic of the control device for programming. For example, the write address of programming command #00 could indicate page_0 of the memory cell subset block_0 in memory cell set plane_0, the write address of programming command #10 could indicate page_0 of the memory cell subset block_0 in memory cell set plane_1, and so on. The write address of programming command #p0 could indicate page_0 of the memory cell subset block_0 in memory cell set plane_p. During time period T2, the memory circuit operates in programming state, at which time programming commands #00, #10, ..., and #p0 are executed. During time period T2, the storage circuit can also simultaneously receive programming commands #01, #11, ..., and #p1 input from the control device. For example, the write address of programming command #01 could indicate page_1 of the storage cell subset block_0 in storage cell set plane_0; the write address of programming command #11 could indicate page_1 of the storage cell subset block_0 in storage cell set plane_1; and so on. Similarly, the write address of programming command #p1 could indicate page_1 of the storage cell subset block_0 in storage cell set plane_p. That is, while executing programming commands for storage cell arrays at the same location in storage cell sets plane_1 to plane_p, programming commands for different storage cell arrays within the same storage cell set can be input simultaneously. During time period T3, after programming commands #00, #10, ..., and #p0 are executed, programming commands #01, #11, ..., and #p1 are executed. At the same time, the storage circuit can also receive programming commands #02, #12, and #p2 input from the control device, and so on, and can input and execute more programming commands.As an example, the write address of programming command #0q can indicate the storage page page_q of the storage cell subset block_0 in storage cell set plane_0, the write address of programming command #1q can indicate the storage page page_q of the storage cell subset block_0 in storage cell set plane_1, and the write address of programming command #pq can indicate the storage page page_q of the storage cell subset block_0 in storage cell set plane_p, where q is an integer greater than or equal to 1.

[0094] As can be seen, in some embodiments of this application, the first and second indication information can indicate a storage cell array where the first storage cell set and the second storage cell set are located differently. The first and third indication information can indicate a storage cell array where the first storage cell set is located differently.

[0095] As described above, programming a set of memory cells can include multiple writes and multiple verifications. In some embodiments of this application, the control device can control each write and each verification and record the number of writes and verifications during programming. For example, please refer to FIG11, which shows a schematic diagram of another in-memory computing system 1100 according to an exemplary embodiment of this application. As shown in FIG11, the control device 1110 may include a control module (or control circuit) 1111 and a register module (or control circuit) 1112. The target data to be written to the memory circuit 1120 can be registered in the register module 1112. The control module 1111 can input programming commands to the memory circuit 1120, causing the memory circuit 1120 to write data to the corresponding memory cell array according to the programming commands.

[0096] The storage circuit 1120 can output an output signal from the aforementioned storage cell array, and the output signal is converted into feedback data by the conversion circuit 1130 and fed back to the register module 1112. The register module 1112 is used to store the feedback data. The control module 1111 can perform verification based on the target data and feedback data stored in the register module 1112. For example, the control module 1111 can control the bitwise XOR operation between the target data and the feedback data. The register module 1112 can feed back the verification result to the control module 1111, and the control module 1111 can control subsequent writing and / or verification based on the verification result.

[0097] According to some embodiments of this application, the control device 1110 also includes a counting function, which records the number of times the memory cell array has been written. The control module 1111 controls the parameters of the memory circuit during writing, such as the injection voltage, based on this number of writes; or the control module 1111 can send count information indicating the number of writes to the memory circuit, which can then control the parameters of the current write operation, such as the injection voltage, based on this count. This application does not limit the location of the counting function. For example, the control device 1110 may include a counting module to implement the above counting function. The control module 1111 is connected to the counting module and can obtain the number of writes recorded by the counting module, generate count information indicating the number of writes based on this number, and send it to the memory circuit. Alternatively, the control module 1111 integrates a counting function, generates count information indicating the number of writes based on locally recorded counts, and sends it to the memory circuit.

[0098] According to some embodiments of this application, the above-mentioned number information can be carried in the programming command start indication 510 or the programming command end indication 540, which can simplify the complexity of the programming command.

[0099] According to some embodiments of this application, the control device 1110 can perform parallel verification of feedback data from memory cell sets programmed in parallel. For example, in the above embodiments, verification based on the result of the first data write and verification based on the result of the fourth data write can be performed in parallel. For example, the control device instructs the addresses of memory cell sets plane_0 to plane_a1 through programming commands, and programs the memory cell arrays within memory cell sets plane_0 to plane_a1 in parallel. The target data stored in the register module 1112 may include the target data of the memory cell arrays within memory cell sets plane_0 to plane_a1. The feedback data may include the feedback data of the memory cell arrays within memory cell sets plane_0 to plane_a1. In this case, verification of the write results of multiple memory cell sets can be achieved through a single verification, further improving programming efficiency.

[0100] According to some embodiments of this application, the control device 1110 can be configured with multiple register modules, thereby enabling time-sharing verification of the write results through multiple register modules, further improving programming efficiency. Taking two register modules as an example, referring to FIG11, one register module 1112 is used to store target data 1, and the other register module 1112 is used to store target data 2. In this way, it can be coordinated with the execution of alternating programming to further perform alternating verification, so that during the verification of one feedback data, the reception of another feedback data can be carried out simultaneously, preparing in advance for the verification of the next feedback data, further improving programming efficiency. For example, referring to the embodiment shown in FIG10, when the execution result of programming command #00, programming command #10, ..., and programming command #p0, i.e., feedback data 1, is stored in one of the register modules 1112, the verification process of the execution result can be controlled. At the same time, the other register module 1112 can receive the execution results of programming command #01, programming command #11, ..., and programming command #p1, so as to utilize the current verification time to prepare for the next verification, further improving programming efficiency.

[0101] The above embodiments illustrate the implementation method of inserting the programming process of other storage unit sets into the programming process of the storage unit set. The following embodiments illustrate the implementation method of inserting the calculation process of other storage unit sets into the programming process of the storage unit set.

[0102] According to some embodiments of this application, controlling the operating state of the second memory cell set during the first programming process of the first memory cell set may include: controlling the calculation of the second memory cell set during the first programming process of the first memory cell set. The second memory cell set may be any one or more memory cell sets in the memory circuit that are different from the first memory cell set, and this application does not specifically limit this. For example, the second memory cell set may be one or more memory cell sets in the memory circuit that have been programmed.

[0103] According to some embodiments of this application, the first programming includes multiple writes and verifications, which include a first write and a first verification, as well as a second write and a second verification. Controlling the computation of the second storage unit set during the first programming process of the first storage unit set can include controlling the computation of the second storage unit set after the first write and the first verification and before the second write and the second verification. That is, a single write and verification can be used as a unit for inserting computation tasks, and computation tasks can be inserted between two writes and verifications. For example, during the first write or the first verification process, if the control device obtains a computation task requirement, it can suspend the first programming after the first write and the first verification, begin executing the computation task, and after the computation task is completed, control the second write and the second verification of the first programming to continue execution.

[0104] For example, please refer to Figure 12, which illustrates a schematic diagram of the workflow of a memory computing system according to an exemplary embodiment of this application. As shown in Figure 12, during time period T1, the first memory cell set plane_0 performs a first write and a first verification. The specific processes of writing and verification can be referred to the previous embodiments and will not be repeated here. During time period T3, the first memory cell set plane_0 performs a second write and a second verification. A time period T2 can be spaced between the end of the first verification and the start of the second write. During time period T2, the memory circuit switches from a programming state to a computing state, and the second memory cell set plane_1 can perform a first calculation.

[0105] According to some embodiments of this application, multiple calculations can be inserted during the programming process of the storage circuit. For example, as shown in Figure 12, during time period T5, the first storage cell set plane_0 can perform a third write and a third verification. The third write and the third verification can be any write and verification process in the first programming that is different from the first write and first verification and the second write and second verification. A time period T4 can be spaced between the end of the second verification and the start of the third write. During time period T4, the storage circuit switches from the programming state to the calculation state, and the third storage cell set plane_2 can perform a second calculation. The third storage cell set plane_2 can be any storage cell set in the storage circuit that is different from the first storage cell set plane_0. For example, the third storage cell set plane_2 can be the same storage cell set as the second storage cell set plane_1 or a storage cell set different from the second storage cell set plane_1.

[0106] The above is just an example. The timing of the computation insertion can be related to the arrival time of the computation task. For example, the computation task can be inserted after the current write and verification of the memory array that is being programmed when the computation task arrives.

[0107] Therefore, the computation process can be inserted between one write and verification process and another write and verification process in the programming process, so that the computation task can be performed in advance without waiting for all the write and verification processes included in the programming process to be completed, thereby improving the response speed of the computation task.

[0108] According to some embodiments of this application, the first programming may include a first write and a first verification. Controlling the computation of the second storage unit set during the first programming process of the first storage unit set may include controlling the computation of the second storage unit set after the first write and before the first verification. The first write may be a write within any write and verification process of the first programming, and the first verification may be a verification within that write and verification process. That is, a single write and verification can be broken down into finer granularities as units for inserting computation tasks; for example, a computation task can be inserted between a single write and verification. For example, during the first write process, if the control device obtains a computation task requirement, it may suspend the first programming after the first write and begin executing the computation task; after the computation task is completed, it may control the first verification to continue execution.

[0109] For example, please refer to Figure 13, which illustrates a schematic diagram of the workflow of another in-memory computing system according to an exemplary embodiment of this application. As shown in Figure 13, during time period T1, the first memory cell set plane_0 performs a first write, and during time period T3, the first memory cell set plane_0 performs a first verification. A time period T2 may be spaced between the completion of the first write and the start of the first verification. During time period T2, the memory circuit transitions from a programming state to a computation state, at which point the memory circuit can perform a first computation, which can be performed by any memory cell set in the memory circuit other than the first memory cell set plane_0. This arbitrary memory cell set may include memory cell sets that have already been programmed.

[0110] According to some embodiments of this application, multiple calculations can be inserted during the programming process. For example, as shown in Figure 13, during time period T5, the first storage cell set plane_0 performs a second write, and during time period T7, the first storage cell set plane_0 performs a second verification. A time period T6 can be spaced between the completion of the second write and the start of the second verification. During time period T6, the storage circuit transitions from a programming state to a calculation state, at which point the storage circuit can perform a third calculation. This third calculation can be performed by any storage cell set in the storage circuit other than the first storage cell set plane_0. This arbitrary storage cell set is a set of storage cells that has already been programmed.

[0111] Therefore, the computation process can be inserted between the write and verification processes in the programming process, so that the computation task can be performed in advance without waiting for all the write and verification processes included in the programming process to be completed, thereby improving the response speed of the computation task.

[0112] According to some embodiments of this application, the two control methods for the insertion calculation process described above can be used in combination. For example, as shown in Figure 13, a time interval T4 can be used between the end of the first verification and the start of the second write. During time interval T4, the storage circuit switches from the programming state to the calculation state, at which time the storage circuit can perform the second calculation, which can be performed by any set of storage cells in the storage circuit other than the first storage cell set plane_0.

[0113] According to some embodiments of this application, the insertion calculation process can also be performed by different subsets of storage cells in the same storage cell set of the programming process. For example, in the first programming process of the first subset of storage cells in the first storage cell set, the calculation of the second subset of storage cells in the first storage cell set is controlled. The second subset of storage cells can be any one or more subsets of storage cells in the first storage cell set that are different from the first subset of storage cells, and this application does not specifically limit this. For example, the second subset of storage cells can be one or more subsets of storage cells in the storage circuit that have been programmed. As an example, in the programming flow shown in FIG12 or FIG13, the writing and verification shown in the figure can be performed by the first subset of storage cells block_0 in the first storage cell set plane_0, and the calculation shown in the figure can be performed by the second subset of storage cells block_1 in the first storage cell set plane_0.

[0114] This application does not limit the number of calculations inserted during programming. One or more calculations may be inserted between a write and a verification and a subsequent write and verification, or between a write and a verification. For example, the first calculation shown in Figure 12 may include one or more calculations, or the second calculation may include one or more calculations. For example, the first calculation shown in Figure 13 may include one or more calculations, or the second calculation may include one or more calculations. Furthermore, whether calculations are inserted during programming, the number of calculations inserted, and the timing of the insertions can be flexibly adjusted according to actual business needs or business priorities. As an example, no calculation may be inserted between the first write and the first verification, one or more calculations may be inserted between the first verification and the second write, and one or more calculations may be inserted between the second write and the second verification; this application does not specifically limit this.

[0115] This application also provides a programming method. For example, FIG14 shows a schematic flowchart of a programming method 1400 according to an exemplary embodiment of this application. This programming method can be used in, for example, the in-memory computing system shown in FIG1 or FIG2, which includes a control device and a storage circuit, wherein the storage circuit may include multiple sets of storage cells, each set of storage cells including multiple storage cells. The programming method 1400 can be executed by the storage circuit.

[0116] As shown in Figure 14, the programming method 1400 may include the following steps.

[0117] S1410: Perform the first write of the first programming of the first memory cell set.

[0118] S1420: During the first programming of the first memory cell set, the working state of the second memory cell set is executed.

[0119] According to some embodiments of this application, the working state includes a programming write state or a computation state.

[0120] The programming method 1400 and its possible implementations can be found in the description of the aforementioned control method 300 and its related embodiments, and will not be repeated here or below.

[0121] According to some embodiments of this application, performing a first write to a first storage cell set includes: receiving a first command, the first command including first indication information and first write data, the first indication information being used to indicate a first storage cell array of the first storage cell set, and the first write data being used for first data writing to the first storage cell array of the first storage cell set; and performing the first write according to the first command, the first write being used to write the first data.

[0122] According to some embodiments of this application, during the first programming of the first storage unit set, the working state of the second storage unit set is executed, including: during the first programming of the first storage unit set, the second programming of the second storage unit set is written.

[0123] According to some embodiments of this application, in the process of first programming of a first storage cell set, performing a second programming of a second storage cell set includes: in the process of performing a first write according to a first command, receiving a second command, the second command including second indication information and second write data, the second indication information being used to indicate the first storage cell array of the second storage cell set, and the second write data being used for second data writing of the first storage cell array of the second storage cell set; and performing a second write according to the second command, the second write being used to write the second data.

[0124] According to some embodiments of this application, the first indication information and the second indication information are used to indicate a storage cell array with a different location than the first storage cell set and the second storage cell set.

[0125] According to some embodiments of this application, the programming method further includes: during the process of writing first data according to a first command, receiving a third command, the third command including third indication information and third write data, the third indication information being used to indicate a second storage cell array of the first storage cell set, and the third write data being used for writing third data to the second storage cell array of the first storage cell set; and performing a third write based on the third command, the third write being used to write third data.

[0126] According to some embodiments of this application, the first indication information and the third indication information are used to indicate a storage cell array with different central locations of the first storage cells.

[0127] According to some embodiments of this application, the programming method further includes: receiving a fourth command, the fourth command including fourth indication information and fourth write data, the fourth indication information being used to indicate a second storage cell array of a second storage cell set, and the fourth write data being used for a fourth data write of the second storage cell array of the second storage cell set; and performing a fourth write based on the fourth command, the fourth write being used to write the fourth data.

[0128] According to some embodiments of this application, the first write and the fourth write are performed in parallel.

[0129] According to some embodiments of this application, during the first programming process of the first storage unit set, the working state of the second storage unit set is executed, including: during the first programming process of the first storage unit set, the calculation of the second storage unit set is executed.

[0130] According to some embodiments of this application, the first programming includes multiple writes and outputs. Each write corresponds to a single output; the write operation is used to write data into a target storage cell array within a target storage cell set or a subset of target storage cells, and the corresponding output operation is used to output data from the target storage cell array. The multiple writes and outputs include a first write and a first output, as well as a second write and a second output. During the first programming process of the first storage cell set, the computation of the second storage cell set is performed, including performing the computation of the second storage cell set after the first write and the first output and before the second write and the second output.

[0131] According to some embodiments of this application, the first programming includes multiple writes and outputs, the multiple writes and outputs including a first write and a first output, as well as a second write and a second output. In the first programming process of the first storage cell set, the calculation of the second storage cell set is performed, including: performing the calculation of the second storage cell set after the first write and before the first output.

[0132] According to some embodiments of this application, the programming method further includes: performing calculations on a second subset of the first storage unit set during a first programming process of a first storage unit set.

[0133] According to some embodiments of this application, the first programming includes multiple writes and outputs, the multiple writes and outputs including a first write and a first output, and a second write and a second output. In the first programming process of a first subset of a first set of storage cells, the calculation of a second subset of the first set of storage cells is performed, including: performing the calculation of the second subset of storage cells after the first write and the first output of the first subset of storage cells and before the second write and the second output.

[0134] According to some embodiments of this application, the first programming includes multiple writes and outputs, the multiple writes and outputs including a first write and a first output, as well as a second write and a second output. In the first programming process of a first subset of a first set of storage cells, the calculation of a second subset of the first set of storage cells is performed, including: performing the calculation of the second subset of storage cells after the first write and before the first output of the first subset of storage cells.

[0135] This application does not limit the number of calculations inserted during programming. One or more calculations may be inserted between a write and an output and the next write and output, or between a write and an output. Furthermore, whether to insert calculations during programming, the number of calculations inserted, and the timing of the calculations can be flexibly adjusted according to actual business needs or business priorities.

[0136] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0137] This application also provides a control device that may be located within or include the control circuit 120 / 220 shown in FIG1 or FIG2 above, or may be independent of the control circuit 120 / 220. This control device can be used to perform the control methods provided in any of the embodiments described above.

[0138] The control device may include units or means for performing the above control methods.

[0139] This application also provides a control device, as shown in FIG15. FIG15 shows a schematic diagram of a control device according to an exemplary embodiment of this application. As shown in FIG15, the control device 1500 includes: at least one processor 1510 and an interface circuit 1520, the interface circuit 1520 being electrically connected to the storage circuit in the above embodiments, and the at least one processor 1510 being used to execute the control method provided in any of the above embodiments.

[0140] This application embodiment also provides a storage circuit including multiple sets of storage cells, including a first set of storage cells and a second set of storage cells. The storage circuit is used to execute the programming method provided in the above embodiments.

[0141] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0142] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0143] This application also provides an in-memory computing system, which includes a storage circuit and a control device. The storage circuit receives an input signal and converts the input signal into an output signal based on stored weight data. The storage circuit can be a storage cell array. The storage circuit may include multiple storage cell sets, including a first storage cell set and a second storage cell set. The control device is connected to the storage circuit and is used to execute the control method provided in any of the above embodiments.

[0144] This application also provides an electronic device, as shown in FIG16. FIG16 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG16, the electronic device 1600 may include any of the above-described in-memory computing systems 1610 for processing data of the electronic device. The electronic device may also include an input / output device 1620 for receiving user input or outputting processing results. This application does not limit the input type and output type. For example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 1630, which may process data provided to the in-memory computing system 1610 or process output data of the in-memory computing system 1610. The output of the input / output device 1620 may be based on the output of the processor 1630 or the output of the in-memory computing system 1610.

[0145] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0146] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method for an in-memory computing system, the in-memory computing system comprising a control device and a storage circuit, the storage circuit comprising a plurality of storage cell sets, the plurality of storage cell sets comprising a first storage cell set and a second storage cell set, the control method being executed by the control device and comprising: Controlling the first programming of the first set of storage cells, the first programming including at least one write and verification; During the first programming process of the first storage unit set, the working state of the second storage unit set is controlled.

2. The control method according to claim 1, wherein controlling the first programming of the first storage unit set comprises: A first command is input to the storage circuit. The first command includes first indication information and first write data. The first indication information is used to indicate the first storage cell array of the first storage cell set, and the first write data is used to write the first data to the first storage cell array of the first storage cell set. Verification is performed based on the results of the first data writing.

3. The control method according to claim 2, wherein controlling the working state of the second storage unit set during the first programming process of the first storage unit set includes: During the first programming process of the first storage cell set, a second programming of the second storage cell set is controlled, the second programming including at least one of writing and verification.

4. The control method according to claim 3, wherein controlling the second programming of the second storage unit set during the first programming process of the first storage unit set includes: During the first data writing process of the first storage cell array of the first storage cell set, a second command is input to the storage circuit. The second command includes second indication information and second write data. The second indication information is used to indicate the first storage cell array of the second storage cell set, and the second write data is used for the second data writing of the first storage cell array of the second storage cell set.

5. The control method according to claim 4, wherein the first indication information and the second indication information are used to indicate a storage cell array whose location is different from that of the first storage cell set and the second storage cell set.

6. The control method according to any one of claims 2 to 5, wherein the control method further comprises: During the first data writing process, a third command is input to the storage circuit. The third command includes third indication information and third write data. The third indication information is used to indicate the second storage cell array of the first storage cell set, and the third write data is used for the third data writing of the second storage cell array of the first storage cell set.

7. The control method according to claim 6, wherein the first indication information and the third indication information are used to indicate a storage cell array with different central locations of the first storage cells.

8. The control method according to any one of claims 2 to 7, wherein the control method further comprises: A fourth command is input to the storage circuit. The fourth command includes fourth indication information and fourth write data. The fourth indication information is used to indicate the second storage cell array of the second storage cell set. The fourth write data is used for the fourth data write of the second storage cell array of the second storage cell set. The first data write and the fourth data write are performed in parallel. Verification is performed based on the results of the fourth data writing.

9. The control method according to claim 8, wherein the first indication information and the fourth indication information are used to indicate a storage cell array in the same location as the first storage cell set and the second storage cell set.

10. The control method according to claim 8 or 9, wherein the verification based on the result of the first data writing and the verification based on the result of the fourth data writing are performed in parallel.

11. The control method according to claim 1 or 2, wherein controlling the operating state of the second storage unit set during the first programming process of the first storage unit set includes: During the first programming process of the first storage cell set, the computation of the second storage cell set is controlled.

12. The control method according to claim 11, wherein the first programming includes multiple writes and verifications, the multiple writes and verifications including a first write and a first verification, and a second write and a second verification, and wherein controlling the computation of the second storage unit set during the first programming of the first storage unit set includes: The calculation of the second set of storage cells is controlled after the first write and the first verification, and before the second write and the second verification.

13. The control method according to claim 11 or 12, wherein the first programming includes a first write and a first verification, and the step of controlling the computation of the second storage unit set during the first programming of the first storage unit set includes: The calculation of the second set of storage cells is controlled after the first write and before the first verification.

14. The control method according to any one of claims 1 to 13, further comprising: During the first programming process of the first subset of the first storage cell set, the computation of the second subset of the first storage cell set is controlled.

15. A control device comprising at least one processor and an interface circuit, the interface circuit being electrically connected to a storage circuit, the at least one processor being configured to perform the control method as claimed in any one of claims 1 to 14.

16. An in-memory computing system, comprising: A storage circuit includes multiple sets of storage cells, wherein the multiple sets of storage cells include a first set of storage cells and a second set of storage cells. A control device, electrically connected to the storage circuit, is used to execute the control method as described in any one of claims 1 to 14.

17. An electronic device comprising the in-memory computing system as described in claim 16.

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