Memory array, static random access memory and electronic device

Abstract

The present application relates to the technical field of semiconductors. Disclosed are a memory array, a static random access memory and an electronic device. The memory array comprises a memory cell, a channel of each FET in the memory cell comprising a semiconductor material, wherein a hole mobility of the semiconductor material is greater than or equal to an electron mobility of the semiconductor material, a channel width of a first pull-up FET and a channel width of a second pull-up FET are respectively greater than a channel width of a first access FET and a channel width of a second access FET, and the channel width of the first access FET and the channel width of the second access FET are respectively greater than a channel width of a first pull-down FET and a channel width of a second pull-down FET. Therefore, by means of optimizing the magnitude relationships among channel widths, each FET in a memory cell can achieve a higher driving capability without additionally increasing the area of the memory cell, thereby reducing the costs, improving the performance, reducing the power consumption, and enhancing the performance of the memory cell.

Description

A storage array, static random access memory, and electronic device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510391347.1, filed on March 28, 2025, with the State Intellectual Property Office of the People's Republic of China, entitled "A Storage Array, Static Random Access Memory and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a memory array, static random access memory, and electronic device. Background Technology

[0004] Static random access memory (SRAM) is a type of memory device that allows for static access without requiring a refresh circuit. It is widely used in the design of digital and various electronic circuit products. Typically, an SRAM array has multiple memory cells, and the structure of a conventional memory cell usually includes two N-type access transistors, two P-type pull-up transistors, and two N-type pull-down transistors. In semiconductor materials, the mobility of electrons and holes is a key factor affecting transistor performance. Traditionally, many semiconductor materials (such as silicon) have higher electron mobilities than hole mobilities. However, with the development of semiconductor materials, some semiconductor materials have emerged with hole mobilities greater than or equal to electron mobilities, providing new possibilities for memory cell design. However, when using semiconductor materials with hole mobilities greater than or equal to electron mobilities to form the transistors in a memory cell, directly adopting the existing memory cell structure can lead to a decrease in memory cell performance. Summary of the Invention

[0005] This application provides a memory array, a static random access memory, and an electronic device to provide a memory cell structure that improves the performance of the memory cell when each transistor in the memory cell is formed using a semiconductor material with a hole mobility greater than or equal to the electron mobility.

[0006] In a first aspect, embodiments of this application provide a memory array, which includes a substrate and a plurality of memory cells located on the substrate. Each memory cell includes: a first access field-effect transistor (FET), a second access FET, a first pull-up FET, a second pull-up FET, a first pull-down FET, and a second pull-down FET. The channel of any one of the first access FET, second access FET, first pull-up FET, second pull-up FET, first pull-down FET, and second pull-down FET comprises a semiconductor material, and the hole mobility of the semiconductor material is greater than or equal to the electron mobility of the semiconductor material. Furthermore, the first access FET, second access FET, first pull-up FET, and second pull-up FET are P-type FETs, and the first pull-down FET and second pull-down FET are N-type FETs. The width of the channel of the first pull-up FET and the width of the channel of the second pull-up FET are respectively greater than the width of the channel of the first access FET and the width of the channel of the second access FET, and the width of the channel of the first access FET and the width of the channel of the second access FET are respectively greater than the width of the channel of the first pull-down FET and the width of the channel of the second pull-down FET.

[0007] In this embodiment, based on using a semiconductor material with a hole mobility greater than or equal to the electron mobility to form the channel of the FET in the memory cell, by setting the first access FET and the second access FET as P-type FETs, the advantages of simpler P-type FET technology and stronger driving capability can be fully utilized, reducing process complexity and enabling a larger memory window (i.e., a wider range of stored voltages), thereby improving the performance of the memory cell. Furthermore, by optimizing the relationship between the widths of the channels, the on-resistances of the P-type FET and the N-type FET can be matched, thus satisfying the matching relationship of the FET driving capabilities. This meets the voltage division requirements of the corresponding FETs in the memory cell after being turned on during read and write operations, thereby enabling each FET in the memory cell to achieve higher driving capability without increasing the memory cell area, reducing cost, improving performance, and reducing power consumption.

[0008] In one possible implementation, the semiconductor material includes carbon nanotubes, thereby enabling each FET in the memory cell to be a carbon nanotube field-effect transistor (CNTFET). This allows for sufficient drive current with a smaller gate capacitance, resulting in a lower overall load and advantages in SRAM read / write time and noise margin. Furthermore, the number of carbon nanotubes in the channel of the first pull-up FET and the second pull-up FET is greater than the number of carbon nanotubes in the channel of the first access FET, and the number of carbon nanotubes in the channel of the first access FET and the second access FET is greater than the number of carbon nanotubes in the channel of the first pull-down FET, and the number of carbon nanotubes in the channel of the first access FET and the second access FET is greater than the number of carbon nanotubes in the channel of the first pull-down FET, and the number of carbon nanotubes in the channel of the second pull-down FET is greater than the number of carbon nanotubes in the channel of the first pull-down FET. This satisfies the aforementioned channel width relationship, further improving the performance of the memory cell.

[0009] In one possible implementation, the semiconductor material includes, but is not limited to, tellurium, graphene, silicon, germanium, or group III-V semiconductor materials.

[0010] In one possible implementation, the memory cell includes a first region, a second region, and a third region arranged along a first direction. A first pull-down FET and a second pull-down FET are located in the second region. Two of the first access FET, the second access FET, the first pull-up FET, and the second pull-up FET are located in the first region, and the other two FETs are located in the third region. The first direction is the same as the width direction of the channel. This allows for a more efficient arrangement of the FETs within the memory cell, facilitating a more compact memory cell layout and improving integration density.

[0011] In one possible implementation, the first access FET and the first pull-up FET are located in the first region and arranged along the second direction. Thus, by placing the two P-type FETs, the first access FET MA1 and the first pull-up FET MP1, which require direct electrical connection, in the first region, not only can the interconnect length between the two P-type FETs be shortened, parasitic capacitance and resistance be reduced, and signal transmission delay be reduced, but the memory cell layout can also be simplified and the wiring complexity reduced.

[0012] Furthermore, the second access FET and the second pull-up FET are located in the third region and arranged along the second direction. Therefore, placing the two P-type FETs, the second access FET MA2 and the second pull-up FET MP2, which require direct electrical connection, in the third region not only shortens the interconnect length between these two P-type FETs, reduces parasitic capacitance and resistance, and reduces signal transmission delay, but also simplifies the memory cell layout and reduces wiring complexity. The second direction intersects the first direction.

[0013] In one possible implementation, the channel of the first access FET is shared with at least a portion of the channel of the first pull-up FET, which can save area, reduce parasitic capacitance, reduce power consumption, and optimize signal transmission.

[0014] In one possible implementation, the channel of the second access FET is shared with at least a portion of the channel of the second pull-up FET, which can save area, reduce parasitic capacitance, reduce power consumption, and optimize signal transmission.

[0015] In one possible implementation, the first pull-down FET and the second pull-down FET are staggered in the second direction.

[0016] In one possible implementation, the first pull-up FET and the second access FET are arranged along the first direction, which can save area, optimize signal transmission, and simplify wiring.

[0017] In one possible implementation, the second pull-up FET and the first access FET are arranged along the first direction, which can save area, optimize signal transmission, and simplify wiring.

[0018] In one possible implementation, the gates of the first pull-down FET, the first pull-up FET, and the second access FET are arranged along a first direction, which can further optimize the layout.

[0019] In one possible implementation, the gates of the second pull-down FET, the second pull-up FET, and the first access FET are arranged along a first direction, which can further optimize the layout.

[0020] In one possible implementation, the gate of the first pull-down FET extends along a first direction and is disposed in the channel of the second pull-down FET and connected to a first portion region of the channel of the second pull-down FET, which can further optimize the layout.

[0021] In one possible implementation, the gate of the second pull-down FET extends along a first direction and is disposed in the channel of the first pull-down FET and connected to a first portion of the channel of the first pull-down FET, which can further optimize the layout.

[0022] In one possible implementation, the first pull-up FET and the second pull-up FET are located in a first region and arranged along a second direction. This arrangement of the two P-type FETs, first pull-up FET MP1 and second pull-up FET MP2, which implement the pull-up function, in the first region reduces the difference between the first pull-up FET MP1 and second pull-up FET MP2, improves the matching of electrical characteristics, and enhances the stability of the memory cell 100 performance. Furthermore, the first access FET and the second access FET are located in a third region and arranged along a second direction. This arrangement of the two P-type FETs, first access FET MA1 and second access FET MA2, which implement the gating function, in the third region reduces the difference between the first access FET MA1 and second access FET MA2, improves the matching of electrical characteristics, and enhances the stability of the memory cell 100 performance. The second direction intersects the first direction.

[0023] In one possible implementation, the first pull-up FET, the first pull-down FET, and the first access FET are arranged along a first direction, which can save area, optimize signal transmission, and simplify wiring.

[0024] In one possible implementation, the second pull-up FET, the second pull-down FET, and the second access FET are arranged along the first direction, which can save area, optimize signal transmission, and simplify wiring.

[0025] In one possible implementation, the gates of the first pull-up FET, the first pull-down FET, and the first access FET are arranged along a first direction, which can further optimize the layout.

[0026] In one possible implementation, the gates of the second pull-up FET, the second pull-down FET, and the second access FET are arranged along a first direction, which can further optimize the layout.

[0027] In one possible implementation, the gate of the first pull-down FET and the gate of the first pull-up FET are integrated into one structure, which can shorten the signal transmission path, reduce delay, and simplify the manufacturing process.

[0028] In one possible implementation, the gate of the second pull-down FET and the gate of the second pull-up FET are integrated into one structure, which can shorten the signal transmission path, reduce delay, and simplify the manufacturing process.

[0029] In one embodiment of this application, the structures of two adjacent memory cells along the second direction are symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs.

[0030] In one embodiment of this application, the structures of two adjacent memory cells along the first direction are symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs.

[0031] In one possible implementation, the first terminals of the first pull-up FET, the first terminal of the first pull-down FET, and the first terminal of the first access FET are connected via a first electrode interconnect to achieve signal transmission between the first terminals of the first pull-up FET, the first terminal of the first pull-down FET, and the first terminal of the first access FET. Furthermore, the first terminals of the second access FET, the second pull-up FET, and the second pull-down FET are connected via a second electrode interconnect to achieve signal transmission between the first terminals of the second access FET, the second pull-up FET, and the second pull-down FET.

[0032] In one possible implementation, the memory array further includes a first bit line (BL), a second bit line, and a word line (WL). The first bit line is connected to the second terminal of a first access FET, the second bit line is connected to the second terminal of a second access FET, and the word line is connected to the gates of both the first and second access FETs. Thus, data can be transmitted via the first and second bit lines, and signals transmitted via the WL can drive the first and second access FETs to turn on and off.

[0033] In one possible implementation, the layer containing the first bit line and the second bit line is different from the layer containing the word line. Furthermore, the word line extends along a first direction, while the first bit line and the second bit line extend along a second direction and are arranged along the first direction.

[0034] In one possible implementation, the layer containing the first bit line and the second bit line is different from the layer containing the word line. Furthermore, the word line extends along a second direction, while the first bit line and the second bit line extend along a first direction and are arranged along the second direction. This arrangement, where the word line intersects with the first and second bit lines, simplifies addressing, increases integration density, reduces wiring length, enhances stability, optimizes read / write speed, reduces power consumption, and simplifies manufacturing processes.

[0035] In one possible implementation, the word line layer is located on the side of the first and second bit lines facing away from the substrate, and the first and second electrode interconnect layers are located between the first and second bit lines and the substrate. This arrangement, where the word lines intersect with the first and second bit lines, simplifies addressing, increases integration density, reduces wiring length, enhances stability, optimizes read / write speed, reduces power consumption, and simplifies manufacturing processes.

[0036] In one possible implementation, the first and second bit lines are straight lines, while the word lines are either zigzag or straight. This simplifies design and manufacturing, reduces parasitic effects, optimizes layout density, improves read / write speed, reduces power consumption, enhances reliability and stability, and facilitates expansion and optimization.

[0037] In one possible implementation, the memory array further includes a first power line, a second power line, and a third power line. The first power line is connected to the second terminal of a first pull-up FET to transmit a first power supply voltage to the second terminal of the first pull-up FET. The third power line is connected to the second terminal of a second pull-up FET to transmit the first power supply voltage to the second terminal of the second pull-up FET. The second power line is connected to the second terminals of a first pull-down FET and a second pull-down FET, respectively, to transmit a second power supply voltage to the second terminals of both the first and second pull-down FETs.

[0038] In one possible implementation, the first power line, second power line, and third power line are respectively disposed on the same layer as the first bit line and the second bit line, simplifying wiring design, improving integration, and facilitating expansion and optimization. Furthermore, the orthographic projection of the first bit line onto the substrate lies between the orthographic projections of the first and second power lines onto the substrate, and the orthographic projection of the second bit line onto the substrate lies between the orthographic projections of the second and third power lines onto the substrate. Thus, using the second power line can reduce the coupling effect of the sum of the first and second bit lines connected in the same memory cell, reducing signal interference and improving signal read / write accuracy.

[0039] In one possible implementation, the memory array further includes: a first power line and a second power line. The first power line is connected to the second terminals of a first pull-up FET and a second pull-up FET, respectively, to transmit a first power supply voltage to the second terminals of the first and second pull-up FETs via the first power line. Furthermore, the second power line is connected to the second terminals of a first pull-down FET and a second pull-down FET, respectively, to transmit a second power supply voltage to the second terminals of the first and second pull-down FETs via the second power line.

[0040] In one possible implementation, the layers containing the first power line and the second power line are located between the layers containing the first power line and the second power line and the substrate.

[0041] In one possible implementation, the first power line and the second power line are arranged sequentially along a first direction and extend along a second direction respectively. Furthermore, the orthographic projection of the first power line onto the substrate is located on the side where the orthographic projection of the first region onto the substrate faces away from the orthographic projection of the second region onto the substrate, and the orthographic projection of the second power line onto the substrate is located between the orthographic projections of the second region onto the substrate and the orthographic projections of the third region onto the substrate. This simplifies wiring design, improves integration, and facilitates expansion and optimization.

[0042] Secondly, this application provides a static random access memory (SRAM), comprising: a controller and at least one memory array, wherein the controller is electrically connected to any memory array. The memory array is the memory array described in the first aspect or in various embodiments of the first aspect. Because the memory array in the embodiments of this application has good performance, the SRAM including this memory array also has good performance.

[0043] Thirdly, this application provides an electronic device comprising: a circuit board and a static random access memory (SRAM), wherein the SRAM is electrically connected to the circuit board. The SRAM is the SRAM described in the second aspect or in various embodiments of the second aspect. Because the SRAM in the embodiments of this application has better performance, the electronic device including the SRAM also has better performance.

[0044] Furthermore, the technical effects of the corresponding solutions in the second and third aspects can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0045] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0046] Figure 2 is a structural block diagram of a storage array provided in an embodiment of this application;

[0047] Figure 3 is a circuit diagram of a storage unit provided in an embodiment of this application;

[0048] Figure 4 is a top view of a storage array in an embodiment of this application;

[0049] Figure 5 is a top view of another storage array structure in an embodiment of this application;

[0050] Figure 6 is a top view of another storage array structure in an embodiment of this application;

[0051] Figure 7 is a top view of another storage array structure in an embodiment of this application;

[0052] Figure 8A is a top view of the semiconductor device layer in Figure 7;

[0053] Figure 8B is a top view of the first wiring layer in Figure 7.

[0054] Figure 8C is a top view of the second wiring layer in Figure 7.

[0055] Figure 8D is a top view of the third wiring layer in Figure 7.

[0056] Figure 9A is a schematic cross-sectional view of the structure along the AA' direction in Figure 7;

[0057] Figure 9B is a schematic cross-sectional view of the structure along the BB' direction in Figure 7;

[0058] Figure 9C is a schematic cross-sectional view of the structure along the CC' direction in Figure 7;

[0059] Figure 9D is a schematic cross-sectional view of the structure along the DD' direction in Figure 7;

[0060] Figure 9E is a schematic cross-sectional view of the structure along the EE' direction in Figure 7;

[0061] Figure 10 is a top view of another storage array structure in an embodiment of this application;

[0062] Figure 11A is a top view of the semiconductor device layer in Figure 10;

[0063] Figure 11B is a top view of the fourth wiring layer in Figure 10.

[0064] Figure 11C is a top view of the first wiring layer in Figure 10.

[0065] Figure 11D is a top view of the second wiring layer in Figure 10.

[0066] Figure 11E is a top view of the third wiring layer in Figure 10.

[0067] Figure 12A is a schematic cross-sectional view of the structure along the AA' direction in Figure 10;

[0068] Figure 12B is a schematic cross-sectional view of the structure along the BB' direction in Figure 10;

[0069] Figure 12C is a schematic cross-sectional view of the structure along the CC' direction in Figure 10;

[0070] Figure 13 is a top view of another storage array structure in an embodiment of this application;

[0071] Figure 14A is a top view of the semiconductor device layer in Figure 13;

[0072] Figure 14B is a top view of the fourth wiring layer in Figure 13.

[0073] Figure 14C is a top view of the first wiring layer in Figure 13.

[0074] Figure 14D is a top view of the second wiring layer in Figure 13.

[0075] Figure 15A is a schematic cross-sectional view of the structure along the AA' direction in Figure 13;

[0076] Figure 15B is a schematic cross-sectional view of the structure along the BB' direction in Figure 13;

[0077] Figure 15C is a schematic cross-sectional view of the structure along the CC' direction in Figure 13.

[0078] Reference numerals: 100 - memory cell; 111 - first region; 112 - second region; 113 - third region; 10 - substrate; 11 - first dielectric layer; 12 - second dielectric layer; 13 - third dielectric layer; 14 - fourth dielectric layer; 20 - semiconductor device layer; 21 - gate dielectric layer; 30 - first wiring layer; 31 - first electrode interconnect; 32 - second electrode interconnect; 33 - first bit interconnect; 34 - second bit interconnect; 35 - first power interconnect; 36 - second power interconnect; 37 - third power interconnect; 38 - fourth power interconnect Lines; 40 - Second wiring layer; 43 - First power line; 44 - Second power line; 45 - Third power line; 46 - First word line interconnect; 47 - Second word line interconnect; 50 - Third wiring layer; 60 - Fourth wiring layer; 71 - First gate interconnect; 72 - Second gate interconnect; MA1 - First access FET; MA2 - Second access FET; MP1 - First pull-up FET; MP2 - Second pull-up FET; MN1 - First pull-down FET; MN2 - Second pull-down FET; BL1 - First bit line; BL2 - Second bit line; Wf A1 / Wf A2 / Wf P1 / Wf P2 / Wf N1 / Wf N2 - Width; 211 A1 / 211 A2 / 211 P1 / 211 P2 / 211 N1 / 211 N2 - Ditch; 212 A1 / 212 A2 / 212 P1 / 212 P2 / 212 N1 / 212 N2- Gate; CA1- First electrode contact hole; CA2- Second electrode contact hole; CA3- Third electrode contact hole; CA4- Fourth electrode contact hole; CA5- Fifth electrode contact hole; CA6- Sixth electrode contact hole; CB1- First bit line contact hole; CB2- Second bit line contact hole; CB3- Third bit line contact hole; CB4- Fourth bit line contact hole; CC1- First power supply contact hole; CC2- Second power supply contact hole; CC3- Third power supply contact hole; CC4- Fourth power supply contact hole; CC5- Fifth power supply contact hole; CC6- Sixth power supply contact hole; CC7- Seventh power supply contact hole; CC8- Eighth power supply contact hole; CD1- First word line contact hole; CD2- Second word line contact hole; CD3- Third word line contact hole; CD4- Fourth word line contact hole; CD5- Fifth word line contact hole; CD6- Sixth word line contact hole; CE1- First gate contact hole; CE2- Second gate contact hole; 211a P1 / 211a N1 / 211a P2 / 211a N2 / 211a A1 -First section; 211b P1 / 211b P2 / 211b N1 / 211b N2 / 211b A1 / 211a A2 - Second part of the area; F1 - First direction; F2 - Second direction. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0080] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0081] To facilitate understanding of the storage array, static random access memory (SRAM), and electronic device provided in the embodiments of this application, their application scenarios will be introduced first below.

[0082] The storage array provided in this application embodiment can be applied to electronic devices with storage functions, such as SRAM in electronic devices. Electronic devices include, but are not limited to, terminal devices, communication devices, and electronic components. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless networks, fixed networks, servers, and smart broadband. Electronic components include, but are not limited to, memory (e.g., SRAM), processing chips (e.g., central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (AI) processors, digital signal processors (DSPs), and neural network processors), system-on-chips (SoCs), etc., which are not listed here. It is understood that the specific implementation of SRAM can be determined according to the actual application scenario and is not limited here.

[0083] The storage array, SRAM, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0084] Figure 1 is a schematic diagram of an electronic device according to an embodiment of this application. Referring to Figure 1, the electronic device may include a circuit board (not shown in Figure 1) and SRAM, with the SRAM electrically connected to the circuit board. Exemplarily, the SRAM may include a controller and a memory array, with the controller electrically connected to the memory array, thereby enabling the controller to access the memory array. The SRAM may include one or more memory arrays. Furthermore, the electronic device may also include a processor, a cache, and a controller, etc., wherein the SRAM may be integrated into the processor or independently disposed on the circuit board. Exemplarily, the processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, or a neural network processor, etc. The circuit board includes, but is not limited to, a printed circuit board (PCB).

[0085] Figure 2 is a structural block diagram of a storage array provided in an embodiment of this application. Referring to Figure 2, the storage array may include a plurality of storage cells 100, which are arranged in an array of N rows and M columns, where M and N are both integers greater than or equal to 1. Exemplarily, the plurality of storage cells 100 may be arranged along a first direction F1 as a plurality of storage cell rows (e.g., row 1 to row N), and any storage cell row may include a plurality of storage cells 100 arranged along a second direction F2. The plurality of storage cells 100 may also be arranged along the second direction F2 as a plurality of storage cell columns (e.g., column 1 to column M), and any storage cell column may include a plurality of storage cells 100 arranged along the first direction F1. The second direction F2 intersects the first direction F1; for example, the second direction F2 is perpendicular to the first direction F1.

[0086] Figure 3 is a circuit diagram of a memory cell provided in an embodiment of this application. Referring to Figure 3, the memory cell 100 can be configured as a 6T structure. For example, the memory cell 100 may include: a first access FETMA1, a second access FETMA2, a first pull-up FETMP1, a second pull-up FETMP2, a first pull-down FETMN1, and a second pull-down FETMN2. The gates of the first access FETMA1 and the second access FETMA2 are connected to the same WL, and the signal transmitted through the WL drives the first access FETMA1 and the second access FETMA2 to turn on and off. The second terminal of the first access FETMA1 is connected to the first bit line BL1, and data is transmitted through the first bit line BL1. The second terminal of the second access FETMA2 is connected to the second bit line BL2, and data is transmitted through the second bit line BL2. The first terminals of the first access FETMA1, the first terminals of the first pull-up FETMP1 and the first terminal of the first pull-down FETMN1, the gates of the second pull-up FETMP2 and the second pull-down FETMN2 are interconnected to form a memory node QB. The first terminals of the second access FETMA2, the second pull-up FETMP2, and the second pull-down FETMN2, as well as the gates of the first pull-up FETMP1 and the first pull-down FETMN1, are interconnected to form a storage node Q. The second terminals of the first pull-up FETMP1 and the second pull-up FETMP2 are used to receive the first power supply voltage VDD, and the second terminals of the first pull-down FETMN1 and the second pull-down FETMN2 are used to receive the second power supply voltage VSS.

[0087] For example, referring to Figure 3, the first pull-up FETMP1 and the second pull-up FETMP2 are both P-type FETs, and the first pull-down FETMN1 and the second pull-down FETMN2 are both N-type FETs. Therefore, the first pull-up FETMP1 and the first pull-down FETMN1 constitute a first inverter, and the second pull-up FETMP2 and the second pull-down FETMN2 constitute a second inverter. The output terminal of the first inverter is electrically connected to the input terminal of the second inverter, forming a storage node QB. The output terminal of the second inverter is connected to the input terminal of the first inverter, forming a storage node Q. Because the first inverter and the second inverter are cross-coupled, a latching circuit is formed, so that when one storage node is pulled down to a low potential, the other storage node is pulled up to a high potential.

[0088] In semiconductor materials, hole mobility is often greater than or equal to electron mobility. When designing and manufacturing N-type and P-type FETs using these materials, the characteristics of their hole and electron mobility can be fully utilized to ensure good electrical performance for both types of FETs. Furthermore, because the hole and electron mobilities are similar or the hole mobility is higher, the performance of N-type and P-type FETs can be better matched. This is crucial for Complementary Metal Oxide Semiconductor (CMOS) circuit design, as CMOS circuits rely on the symmetry between N-type and P-type FETs. Based on this, in one embodiment of this application, the channels of the first access FET MA1, the second access FET MA2, the first pull-up FET MP1, the second pull-up FET MP2, the first pull-down FET MN1, and the second pull-down FET MN2 are all made of semiconductor material, and the hole mobility of this semiconductor material is greater than or equal to the electron mobility of the semiconductor material. Therefore, by using a semiconductor material with a hole mobility greater than or equal to the electron mobility to form the channels of each FET in the memory cell 100, the performance of the first pull-up FET MP1 and the first pull-down FET MN1 can be better matched, as can the performance of the second pull-up FET MP2 and the second pull-down FET MN2, thereby improving the performance and stability of the memory cell 100 and balancing dynamic power consumption. It is understood that the statement that the hole mobility is equal to the electron mobility described in this application can mean that they are the same within the allowable error range, and will not be elaborated further below.

[0089] Furthermore, for semiconductor materials with hole mobility greater than or equal to electron mobility, both N-type FETs and P-type FETs formed using such semiconductor materials exhibit good electrical performance. In existing memory cells, both the first access FET and the second access FET are configured as N-type FETs. However, given the known gate and source / drain metal contact materials, the process of forming an N-type FET using a semiconductor material with hole mobility greater than or equal to electron mobility is more complex than the process of forming a P-type FET. Moreover, without considering the symmetry between N-type and P-type FETs, the performance of a P-type FET can be further improved. Therefore, continuing to use the existing memory cell structure design while forming the FET in memory cell 100 using a semiconductor material with hole mobility greater than or equal to electron mobility leads to complex processes for the first and second access FETs. To address this, in one embodiment of this application, referring to FIG3, both the first access FET MA1 and the second access FET MA2 are configured as P-type FETs, thereby reducing process complexity and cost. Furthermore, it can fully leverage the advantages of simpler P-type FET technology and stronger driving capability, reduce process complexity, and enable a larger storage window (i.e., a wider range of storage voltages), thereby improving the performance of the storage cell.

[0090] In one embodiment of this application, referring to FIG3, when the memory cell 100 is operating, a low level (e.g., 0V or a second power supply voltage VSS or other numerical voltage) is transmitted on WL, the first access FETMA1 and the second access FETMA2 are turned on, and data in the memory cell 100 is read or written through the first bit line BL1 and the second bit line BL2. Conversely, a high level (e.g., a first power supply voltage VDD or other numerical voltage) is transmitted on WL, the first access FETMA1 and the second access FETMA2 are turned off, and the memory cell 100 stores data. Therefore, for the peripheral circuit connected to WL, it is necessary to invert the level as in the prior art and output it to WL, or a sufficiently powerful inverter needs to be provided between the peripheral circuit and WL so that the peripheral circuit continues to use the level output method of the prior art. Furthermore, when reading data from memory cell 100, the precharge voltage range of the first bit line BL1 and the second bit line BL2 can be 0 to VDD / 2. This reduces the precharge voltage from the original range of VDD / 2 to VDD to 0 to VDD / 2, which not only lowers the precharge voltage and reduces dynamic power consumption but also shortens the charging and discharging time of the precharge voltage, thus improving read and write speeds. The reduced precharge voltage also reduces FET stress, helping to extend the lifespan of memory cell 100. Additionally, the reduced precharge voltage also reduces voltage fluctuations, helping to improve SRAM stability, especially in high-speed or high-density environments. Moreover, as process nodes shrink, the first power supply voltage VDD gradually decreases; adjusting the precharge voltage range to 0 to VDD / 2 better adapts to low-voltage applications while maintaining performance.

[0091] Based on the voltage division requirements after the corresponding FETs in the memory cell 100 are turned on during read and write operations, the driving capability matching relationship of the FETs needs to be met, which in turn requires meeting the on-resistance matching relationship of the P-type FETs and N-type FETs in the memory cell 100. In the prior art, the channel width Wf of the first access FET MA1 is typically... A1 The width Wf of the channel of the second access FETMA2 A2 The width Wf of the channel of the first pull-up FETMP1 P1 The width Wf of the channel of the second pull-up FETMP2 P2 The width Wf of the channel of the first pull-down FETMN1 N1 The width Wf of the channel of the second pull-down FETMN2 N2 The size relationship is set as: Wf N1 and Wf N2 All are greater than Wf A1 and Wf A2 Wf A1 and Wf A2All are greater than Wf P1 and Wf P2 .

[0092] However, in this embodiment, since the first access FETMA1, the second access FETMA2, the first pull-up FETMP1, and the second pull-up FETMP2 are all P-type FETs, and the first pull-down FETMN1 and the second pull-down FETMN2 are N-type FETs, and the hole mobility of the material forming these FET channels is greater than or equal to the electron mobility, if the channel width relationship in the prior art is still used, it will lead to a mismatch in the on-resistance of these P-type FETs and N-type FETs, thereby causing a problem of mismatch in the driving capability of the FETs. However, if the channel width relationship in the prior art is adopted, and the on-resistance matching relationship of the FETs is also required, the area of ​​the corresponding FETs needs to be increased, thereby increasing the area of ​​the memory cell 100, resulting in a large area waste, leading to problems such as increased SRAM area, increased cost, decreased performance, and increased power consumption. Therefore, in this embodiment, the channel width Wf of the first access FETMA1 is... A1 The width Wf of the channel of the second access FETMA2 A2 The width Wf of the channel of the first pull-up FETMP1 P1 The width Wf of the channel of the second pull-up FETMP2 P2 The width Wf of the channel of the first pull-down FETMN1 N1 The width Wf of the channel of the second pull-down FETMN2 N2 The size relationship is set as: Wf P1 and Wf P2 All are greater than Wf A1 and Wf A2 Wf A1 and Wf A2 All are greater than Wf N1 and Wf N2 Therefore, by using semiconductor materials with hole mobility greater than or equal to electron mobility to form the FET channel, and by optimizing the relationship between the width of the channel, the on-resistance of the P-type FET and the N-type FET can be matched, thereby satisfying the matching relationship of the FET's driving capability. As a result, without increasing the area of ​​the memory cell 100, each FET in the memory cell 100 can achieve a higher driving capability, reducing cost, improving performance, and reducing power consumption.

[0093] In this embodiment of the application, the layout of the memory array is redesigned in conjunction with the circuit structure shown in Figure 3. The layout of the memory array in this embodiment of the application is illustrated below with reference to the embodiments and accompanying drawings.

[0094] Example 1

[0095] Figure 4 is a top view of a memory array according to an embodiment of this application. Referring to Figure 4, the memory array includes a substrate (not shown in Figure 4) and memory cells 100 located on the substrate. Each memory cell 100 may include: a first access FETMA1, a second access FETMA2, a first pull-up FETMP1, a second pull-up FETMP2, a first pull-down FETMN1, and a second pull-down FETMN2. The channel 211 of the first access FETMA1... A1 Second access FETMA2 channel 211 A2 The first pull-up FETMP1 channel 211 P1 The second pull-up FETMP2 channel 211 P2 The first pull-down FETMN1 channel 211 N1 Channel 211 of the second pull-down FETMN2 N2 This includes a semiconductor material whose hole mobility is greater than or equal to its electron mobility. Furthermore, the channel 211 of the first access FETMA1... A1 Width Wf A1 Second access FETMA2 channel 211 A2 Width Wf A2 The first pull-up FETMP1 channel 211 P1 Width Wf P1 The second pull-up FETMP2 channel 211 P2 Width Wf P2 The first pull-down FETMN1 channel 211 N1 Width Wf N1 Channel 211 of the second pull-down FETMN2 N2 Width Wf N2 The size relationship is set as: Wf P1 and Wf P2 All are greater than Wf A1 and Wf A2 Wf A1 and Wf A2 All are greater than Wf N1 and Wf N2 In order to achieve the above-mentioned technical effects.

[0096] For example, see Figure 4,212 P1 The gate of the first pull-up FETMP1, channel 211 P1 Width Wf P1 Gate 212 P1 Channel 211 in the coverage area P1Width in the first direction F1. 212 A1 Represents the gate of the first access FETMA1, channel 211 A1 Width Wf A1 Gate 212 A1 Channel 211 in the coverage area A1 Width in the first direction F1. 212 N1 This represents the gate of the first pull-down FET MN1, channel 211. N1 Width Wf N1 Gate 212 N1 Channel 211 in the coverage area N1 Width in the first direction F1. 212 P2 The gate of the second pull-up FETMP2, channel 211 P2 Width Wf P2 Gate 212 P2 Channel 211 in the coverage area P2 Width in the first direction F1. 212 A2 Represents the gate of the second access FETMA2, channel 211 A2 Width Wf A2 Gate 212 A2 Channel 211 in the coverage area A2 Width in the first direction F1. 212 N2 This represents the gate of the first pull-down FET MN1, channel 211. N2 Width Wf N2 Gate 212 N2 Channel 211 in the coverage area N2 The width in the first direction F1. That is, the width direction of the above-mentioned channel is the same as the first direction F1.

[0097] It is understood that, in order to clearly illustrate the structure of the channel width of each FET in the memory cell 100 in the embodiments of this application, FIG4 only shows the channel and gate of each FET in the memory cell 100, and other structures are not shown.

[0098] Carbon nanotubes (CNTs) have a hole mobility approximately equal to their electron mobility. Furthermore, CNTs possess advantages such as high carrier mobility, narrow bandgap, excellent thermal conductivity, and stable chemical properties. CNTFETs, formed by fabricating channels using CNTs, offer advantages such as high mobility and good gate control, achieving sufficient drive current with a relatively small gate capacitance, thus reducing the overall load and providing advantages in SRAM read / write time and noise margin. Based on this, in one embodiment of this application, the semiconductor material includes CNTs, thereby making each FET in the memory cell 100 a CNTFET. For example, referring to FIG5, which is a top view schematic diagram of another memory array structure in an embodiment of this application, the channel 211 of the first access FET MA1... A1 Second access FETMA2 channel 211 A2 The first pull-up FETMP1 channel 211 P1 The second pull-up FETMP2 channel 211 P2 The first pull-down FETMN1 channel 211 N1 Channel 211 of the second pull-down FETMN2 N2 Each is formed by a CNT. For example, the extension direction of the CNT is perpendicular to the width direction of the channel, that is, the extension direction of the CNT is parallel to the second direction F2, and the CNT in the channel of each FET in the memory cell 100 includes semiconductor type CNTs.

[0099] For example, referring to FIG5, the channel 211 of the first pull-up FETMP1 P1 The number of CNTs in the second pull-up FETMP2 channel 211 P2 The number of CNTs in each channel is greater than that of the first access FETMA1 channel 211. A1 The number of CNTs and the second access FETMA2 channel 211 A2 The number of CNTs in the Wf P1 and Wf P2 All are greater than Wf A1 and Wf A2 The relationship. Furthermore, the first access to FETMA1 channel 211 A1 The number of CNTs and the second access FETMA2 channel 211 A2 The number of CNTs in each channel is greater than that of the first pull-down FETMN1 channel 211. N1 The number of CNTs in the second pull-down FETMN2 channel 211 N2 The number of CNTs in the Wf A1 and Wf A2 All are greater than Wf N1 and Wf N2The relationship is as follows. It is understood that Figure 5 only illustrates the CNTs and gates in the channels of each FET in the memory cell 100, and other structures are not shown. Furthermore, tellurium and graphene with open bandgap can exhibit hole mobility greater than or equal to electron mobility. Moreover, under one or more conditions including specific crystal orientation, stress doping, and low temperature, silicon, germanium, or group III-V semiconductor materials can exhibit hole mobility greater than or equal to electron mobility. Based on this, in other embodiments of this application, the semiconductor material may also include, but is not limited to, tellurium, graphene, silicon, germanium, or group III-V semiconductor materials. It is worth mentioning that in the embodiments of this application, CNTs are used as an example for illustration. For embodiments where the semiconductor material is tellurium, graphene, silicon, germanium, or group III-V semiconductor materials, the following embodiments where the semiconductor material is CNTs can be referred to, and repetitions will not be discussed.

[0100] In one embodiment of this application, referring to FIG5, the memory cell 100 may include a first region 111, a second region 112, and a third region 113 arranged along a first direction F1. A first pull-down FET MN1 and a second pull-down FET MN2 are located in the second region 112, so that both the first pull-down FET MN1 and the second pull-down FET MN2 of the N-type FETs are disposed in the middle region of the memory cell 100, which helps to achieve a more compact layout of the memory cell 100 and improve integration. Furthermore, since the first access FET MA1, the second access FET MA2, the first pull-up FET MP1, and the second pull-up FET MP2 are P-type FETs, considering the electrical connection relationship of the FETs in the memory cell 100, two of the first access FET MA1, the second access FET MA2, the first pull-up FET MP1, and the second pull-up FET MP2 can be located in the first region 111, and the other two FETs can be located in the third region 113, so as to reasonably set the position of the P-type FETs, which helps to achieve a more compact layout of the memory cell 100 and improve integration.

[0101] For example, referring to FIG5, the first access FETMA1 and the first pull-up FETMP1 are located in the first region 111, and the first access FETMA1 and the first pull-up FETMP1 are arranged along the second direction F2. Thus, by placing the two P-type FETs, the first access FETMA1 and the first pull-up FETMP1, which require direct electrical connection, in the first region 111, not only can the interconnection length between the two P-type FETs be shortened, parasitic capacitance and resistance be reduced, and signal transmission delay be reduced, but the layout of the memory cell 100 can also be simplified and the wiring complexity reduced.

[0102] For example, referring to FIG5, the second access FETMA2 and the second pull-up FETMP2 are located in the second region 112, and the second access FETMA2 and the second pull-up FETMP2 are also arranged along the second direction F2. Thus, by placing the two P-type FETs, the second access FETMA2 and the second pull-up FETMP2, which require direct electrical connection, in the third region 113, not only can the interconnect length between the two P-type FETs be shortened, parasitic capacitance and resistance be reduced, and signal transmission delay be reduced, but the layout of the memory cell 100 can also be simplified and the wiring complexity reduced.

[0103] For example, referring to FIG5, the channel 211 of the first access FETMA1 A1 At least a portion of the channel 211 of the first pull-up FETMP1 P1 Sharing can save space, reduce parasitic capacitance, reduce power consumption, and optimize signal transmission. For example, the first access FETMA1 channel 211... A1 Channel 211 with the first pull-up FETMP1 P1 When the semiconductor material is CNT, the CNTs in the first access FETMA1 can be shared with a portion of the CNTs in the first pull-up FETMP1, while the CNTs in the first access FETMA1 are not shared with another portion of the CNTs in the first pull-up FETMP1. That is, a portion of the CNTs is not cut off during its extension along the second direction F2 from the region where the first pull-up FETMP1 is located to the region where the first access FETMA1 is located, thus forming the entire channel 211 of the first access FETMA1. A1 It also forms part of the channel 211 in the first pull-up FETMP1. P1 Another portion of the CNTs, extending along the second direction F2 from the region where the first pull-up FETMP1 is located to the region where the first access FETMA1 is located, is truncated, preventing this portion of the CNTs from extending into the region where the first access FETMA1 is located. This results in this portion of the CNTs forming another part of the channel 211 within the first pull-up FETMP1. P1 .

[0104] For example, referring to FIG5, the second access FETMA2 channel 211 A2 At least a portion of the channel 211 of the second pull-up FETMP2 P2 Sharing can save space, reduce parasitic capacitance, reduce power consumption, and optimize signal transmission. For example, the second access FETMA2 channel 211... A2 Channel 211 with the second pull-up FETMP2 P2When the semiconductor material is CNT, the CNTs in the second access FETMA2 can be shared with a portion of the CNTs in the second pull-up FETMP2, while the CNTs in the second access FETMA2 are not shared with another portion of the CNTs in the second pull-up FETMP2. That is, a portion of the CNTs are not cut off as they extend along the second direction F2 from the region where the second pull-up FETMP2 is located to the region where the second access FETMA2 is located, thus forming the entire channel 211 of the second access FETMA2. A2 It also forms part of the channel 211 in the second pull-up FETMP2. P2 Another portion of the CNTs, extending along the second direction F2 from the region where the second pull-up FETMP2 is located to the region where the second access FETMA2 is located, is truncated, preventing this portion of the CNTs from extending into the region where the second access FETMA2 is located. This results in this portion of the CNTs forming another part of the channel 211 within the second pull-up FETMP2. P2 .

[0105] For example, referring to FIG5, the first pull-up FETMP1 and the second access FETMA2 are arranged along the first direction F1, which can save area, optimize signal transmission, and simplify wiring.

[0106] For example, referring to FIG5, the second pull-up FETMP2 and the first access FETMA1 are arranged along the first direction F1, which can save area, optimize signal transmission, and simplify wiring.

[0107] In one embodiment of this application, referring to FIG5, the first pull-down FETMN1 and the second pull-down FETMN2 are staggered in the second direction F2, that is, the first pull-down FETMN1 and the second pull-down FETMN2 are not arranged along the second direction F2. Furthermore, the channel 211 of the first pull-down FETMN1... N1 Channel 211 of the second pull-down FETMN2 N2 Not shared. For example, the first pull-down FET MN1 is located between the second pull-down FET MN2 and the first region 111, that is, the first pull-down FET MN1 is closer to the first region 111 than the second pull-down FET MN2, and the second pull-down FET MN2 is closer to the third region 113 than the first pull-down FET MN1. Thus, the distance between two FETs that require direct gate connection can be brought closer, which can save area, optimize signal transmission, and simplify wiring.

[0108] In one embodiment of this application, referring to FIG5, the gate 212 of the first pull-down FETMN1 N1 The gate 212 of the first pull-up FET MP1 P1 Second access FETMA2 gate 212 A2 Arranging the layout along the first direction F1 can further optimize the map layout.

[0109] In one embodiment of this application, referring to FIG5, the gate 212 of the second pull-down FETMN2 N2 The gate 212 of the second pull-up FETMP2 P2 and the first access FETMA1 gate 212 A1 Arrange the layout along the first direction F1. This further saves space and optimizes the layout.

[0110] As an example, referring to Figure 5, the gate 212 of the first pull-down FET MN1 N1 With the gate 212 of the first pull-up FETMP1 P1 Independent configuration. As another example, referring to Figure 6, which is a top view of another storage array structure in an embodiment of this application, the gate 212 of the first pull-down FETMN1... N1 With the gate 212 of the first pull-up FETMP1 P1 As a single integrated structure, the gate 212 of the first pull-down FET MN1 can be... N1 With the gate 212 of the first pull-up FETMP1 P1 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the first pull-down FET MN1 can be fabricated using the same process. N1 With the gate 212 of the first pull-up FETMP1 P1 This simplifies the manufacturing process.

[0111] As an example, referring to Figure 5, the gate 212 of the second pull-down FET MN2 N2 With the gate 212 of the second pull-up FETMP2 P2 It is also set independently. As another example, referring to Figure 6, the gate 212 of the second pull-down FETMN2 N2 With the gate 212 of the second pull-up FETMP2 P2 It is a single integrated structure. This allows the gate 212 of the second pull-down FET MN2 to be integrated. N2 With the gate 212 of the second pull-up FETMP2 P2 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the second pull-down FET MN2 can be fabricated using the same process. N2 With the gate 212 of the second pull-up FETMP2 P2 This simplifies the manufacturing process.

[0112] To achieve the gate 212 of the first pull-down FETMN1 N1 The connection to the first terminal of the second pull-down FETMN2 is exemplarily shown in FIG6, where the gate 212 of the first pull-down FETMN1 is connected. N1The channel 211 extends along the first direction F1 and is disposed in the second pull-down FETMN2. N2 and the channel 211 of the second pull-down FETMN2 N2 The first part of region 211a N2 Connections can further optimize the map layout. Specifically, the first part, region 211a... N2 The orthogonal projection of the substrate and the gate 212 of the second pull-down FET MN2 N2 The orthographic projections onto the substrate do not overlap, and the first region 211a N2 It can be used as the first terminal of the second pull-down FETMN2 to realize the gate 212 of the first pull-down FETMN1. N1 Signal transmission between the first pole of the second pull-down FETMN2 and the first pole.

[0113] To achieve the gate 212 of the second pull-down FET MN2 N2 The connection to the first terminal of the first pull-down FET MN1 is exemplarily shown in FIG6, with reference to the gate 212 of the second pull-down FET MN2. N2 Channel 211 extending along the first direction F1 and disposed in the first pull-down FETMN1 N1 and the channel 211 of the first pull-down FETMN1 N1 The first part of region 211a N1 Connections can further optimize the map layout. Specifically, the first part, region 211a... N1 The orthogonal projection of the substrate and the gate 212 of the first pull-down FET MN1 N1 The orthographic projections onto the substrate do not overlap, and the first region 211a N1 It can be used as the first terminal of the first pull-down FETMN1 to realize the gate 212 of the second pull-down FETMN2. N2 Signal transmission between the first terminal of the first pull-down FETMN1 and the first terminal of the first pull-down FETMN1.

[0114] In one embodiment of this application, the structure of each FET in the memory cell includes, but is not limited to, Gate All Around (GAA) FET, planar FET, dual-gate FET, fin FET, etc. The following is an example of the structure of each FET in the memory cell being GAAFET.

[0115] Figure 7 is a top view of another memory array in an embodiment of this application. Figure 8A is a top view of the semiconductor device layer in Figure 7. Figure 8B is a top view of the first wiring layer in Figure 7. Figure 8C is a top view of the second wiring layer in Figure 7. Figure 8D is a top view of the third wiring layer in Figure 7. Figure 9A is a cross-sectional view along the AA' direction in Figure 7. Figure 9B is a cross-sectional view along the BB' direction in Figure 7. Figure 9C is a cross-sectional view along the CC' direction in Figure 7. Figure 9D is a cross-sectional view along the DD' direction in Figure 7. Figure 9E is a cross-sectional view along the EE' direction in Figure 7. Referring to Figures 7 to 9E, the memory array includes a semiconductor device layer 20 located on a substrate 10. A first access FET FETMA1, a second access FETMA2, a first pull-up FETMP1, a second pull-up FETMP2, a first pull-down FETMN1, and a second pull-down FETMN2 are disposed on the semiconductor device layer 20. It is understood that, in order to clearly illustrate the structure of each FET in the memory cell 100 in the embodiments of this application, when each FET is illustrated as a Gate All Around (GAA) FET, a gate dielectric layer 21 is also provided between the gate and the CNT in each FET.

[0116] In one embodiment of this application, referring to Figures 7, 8B, and 9A, the first terminals of the first pull-up FETMP1, the first terminals of the first pull-down FETMN1, and the first terminal of the first access FETMA1 are connected via a first electrode interconnect 31, thereby achieving electrical connection between the first terminals of the first pull-up FETMP1, the first terminals of the first pull-down FETMN1, and the first terminal of the first access FETMA1, and realizing signal transmission. For example, the first electrode interconnect 31 is connected to the channel 211 of the first pull-up FETMP1 through the first electrode contact hole CA1. P1 The first part of region 211a P1 The first electrode interconnect 31 is also connected to the channel 211 of the first pull-down FET MN1 through the second electrode contact hole CA2. N1 The first part of region 211a N1 Connection. The first part, region 211a. P1 It can be used as the first terminal of the first pull-up FETMP1. Since the channel of the first access FETMA1 is shared with part of the channel of the first pull-up FETMP1, the first part of region 211a P1 When the channel of the first access FETMA1 is turned on, it is equivalent to the first terminal of the first pull-up FETMP1 being electrically connected to the first terminal of the first access FETMA1. Furthermore, the first portion region 211a... N1 It can be used as the first terminal of the first pull-down FETMN1 to achieve the above-mentioned electrical connection and realize signal transmission.

[0117] In one embodiment of this application, referring to Figures 7, 8B, and 9B, the first terminals of the second access FETMA2, the second pull-up FETMP2, and the second pull-down FETMN2 are connected via a second electrode interconnect 32, thereby achieving an electrical connection between the first terminals of the second access FETMA2, the second pull-up FETMP2, and the second pull-down FETMN2, and enabling signal transmission. For example, the second electrode interconnect 32 is connected to the channel 211 of the second pull-up FETMP2 via a third electrode contact hole CA3. P2 The first part of region 211a P2 The second electrode interconnect 32 is also connected to the channel 211 of the second pull-down FET MN2 through the fourth electrode contact hole CA4. N2 The first part of region 211a N2 Connection. The first part, region 211a. P2 It can be used as the first terminal of the second pull-up FETMP2. Since the channel of the second access FETMA2 is shared with part of the channel of the second pull-up FETMP2, the first part of region 211a P2 When the channel of the second access FETMA2 is turned on, it is equivalent to the first terminal of the second access FETMA2 being electrically connected to the first terminal of the second pull-up FETMP2. Furthermore, the first portion region 211a... N2 It can be used as the first terminal of the second pull-down FETMN2 to achieve the above-mentioned electrical connection and realize signal transmission.

[0118] Referring to Figures 9A and 9B, the memory array further includes a first dielectric layer 11 located on the side of the semiconductor device layer 20 facing away from the substrate 10 and a first wiring layer 30 located on the side of the first dielectric layer 11 facing away from the substrate 10. A first electrode interconnect 31 and a second electrode interconnect 32 can be disposed in the first wiring layer 30. Furthermore, first electrode contact holes CA1 to fourth electrode contact holes CA4 respectively penetrate the first dielectric layer 11. Exemplarily, during fabrication, conductive material can be filled into the first electrode contact holes CA1 to fourth electrode contact holes CA4 to form conductive portions, thereby achieving electrical connection. Exemplarily, the conductive portion can be a single-layer or multi-layer conductive film structure. For example, a single-layer conductive film structure can be a metallic material, and a multi-layer conductive film structure includes a combination structure of metal nitrides and metals, such as TiN / Cu, TaN / Cu, etc. It is understood that the conductive portions described below can be formed similarly, and repeated details will not be elaborated further.

[0119] For example, referring to Figures 7 and 8B, the first electrode interconnect 31 and the second electrode interconnect 32 extend along the first direction F1, respectively. The orthographic projection of the first electrode interconnect 31 onto the substrate 10 and the orthographic projection of the second electrode interconnect 32 onto the substrate 10 are respectively located at the gate 212 of the first pull-down FET MN1. N1 The orthogonal projection of substrate 10 and the gate 212 of the second pull-down FET MN2 N2 Between the orthographic projections of the substrate 10. Furthermore, in order to avoid short-circuiting the first electrode interconnect 31 and the second electrode interconnect 32, the first electrode interconnect 31 and the second electrode interconnect 32 are staggered in the first direction F1, that is, the first electrode interconnect 31 and the second electrode interconnect 32 are not arranged in a straight line along the first direction F1.

[0120] In one embodiment of this application, referring to Figures 7, 8C, 8D, and 9A to 9E, the memory array further includes a first bit line BL1, a second bit line BL2, and WL. The first bit line BL1 is connected to the second terminal of the first access FETMA1 to transmit data. The second bit line BL2 is connected to the second terminal of the second access FETMA2 to transmit data. WL is connected to the gate 212 of the first access FETMA1. A1 Second access FETMA2 gate 212 A2 The connection is used to drive the first access FETMA1 and the second access FETMA2 to turn on and off via signals transmitted through WL.

[0121] For example, the layer containing the first bit line BL1 and the second bit line BL2 is different from the layer containing WL; that is, the first bit line BL1 and the second bit line BL2 are located on the same film layer, while the word line is located on another film layer. Furthermore, WL extends along a first direction F1, and the first bit line BL1 and the second bit line BL2 extend along a second direction F2 and are arranged along the first direction F1. This arrangement, where WL intersects with the first bit line BL1 and the second bit line BL2, simplifies addressing, improves integration density, reduces wiring length, enhances stability, optimizes read / write speed, reduces power consumption, and simplifies the manufacturing process.

[0122] In one embodiment of this application, referring to Figures 7, 8C, 8D, and 9A to 9E, the memory array further includes a second dielectric layer 12 located on the side of the first wiring layer 30 facing away from the substrate 10, a second wiring layer 40 located on the side of the second dielectric layer 12 facing away from the substrate 10, a third dielectric layer 13 located on the side of the second wiring layer 40 facing away from the substrate 10, and a third wiring layer 50 located on the side of the third dielectric layer 13 facing away from the substrate 10. A first bit line BL1 and a second bit line BL2 are disposed on the second wiring layer 40, and WL is disposed on the third wiring layer 50. Therefore, when WL extends along the first direction F1, the layer containing WL is located on the side of the layer containing the first bit line BL1 and the second bit line BL2 facing away from the substrate 10, and the layer containing the first electrode interconnect 31 and the second electrode interconnect 32 is located between the layer containing the first bit line BL1 and the second bit line BL2 and the substrate 10.

[0123] For example, referring to Figures 7 and 8C, the first bit line BL1 and the second bit line BL2 are respectively linear in shape, and the shape of WL is also linear. This simplifies design and manufacturing, reduces parasitic effects, optimizes layout density, improves read and write speed, reduces power consumption, enhances reliability and stability, and facilitates expansion and optimization.

[0124] For example, referring to FIG7, the orthographic projection of the first bit line BL1 on the substrate 10 is located between the orthographic projection of the first region 111 on the substrate 10 and the orthographic projection of the second region 112 on the substrate 10, and the orthographic projection of the second bit line BL2 on the substrate 10 is located between the orthographic projection of the third region 113 on the substrate 10 and the orthographic projection of the second region 112 on the substrate 10, which simplifies wiring, saves storage array area, and improves integration.

[0125] As an example, to electrically connect the first bit line BL1 and the second bit line BL2 to the corresponding FETs respectively, referring to Figures 7, 8A to 8C, 9C and 9D, the first wiring layer 30 also includes a first bit line interconnect 33 and a second bit line interconnect 34. The first bit line BL1 is connected to the first bit line interconnect 33 through the first bit line contact hole CB1, and the first bit line interconnect 33 is connected to the channel 211 of the first access FET MA1 through the second bit line contact hole CB2. A1 The first part of region 211a A1 Connection, first part of region 211a A1 It can serve as the second electrode of the first access FETMA1 to achieve electrical connection between the first bit line BL1 and the second electrode of the first access FETMA1, thereby realizing signal transmission. Furthermore, the second bit line BL2 is connected to the second bit line interconnect 34 through the third bit line contact hole CB3, and the second bit line interconnect 34 is connected to the channel 211 of the second access FETMA2 through the fourth bit line contact hole CB4. A2 The second part of region 211a A2Connection, second part of region 211a A2 It can be used as the second pole of the second access FETMA2 to realize the electrical connection between the second bit line BL2 and the second pole of the second access FETMA2, thereby realizing signal transmission.

[0126] Furthermore, the first line contact hole CB1 and the third line contact hole CB3 penetrate the second dielectric layer 12, and the second line contact hole CB2 and the fourth line contact hole CB4 penetrate the first dielectric layer 11. For example, during the fabrication process, conductive material can be filled into the first line contact hole CB1 to the fourth line contact hole CB4 to form conductive portions, thereby achieving electrical connection.

[0127] For example, referring to Figures 7 and 8B, the first bit interconnect 33 and the second bit interconnect 34 extend along the first direction F1, so that the formation of the first bit interconnect 33 and the second bit interconnect 34 are respectively linear, which simplifies the design and manufacturing and facilitates the expansion and optimization of the layout.

[0128] In one embodiment of this application, to provide a first power supply voltage VDD to a first pull-up FETMP1 and a second power supply voltage VSS to a first pull-down FETMN1 and a second pull-down FETMN2, referring to Figures 7, 8C, 9C to 9E, the memory array further includes a first power line 43, a second power line 44, and a third power line 45. The first power line 43 is connected to the second terminal of the first pull-up FETMP1 to transmit the first power supply voltage VDD to the second terminal of the first pull-up FETMP1. The third power line 45 is connected to the second terminal of the second pull-up FETMP2 to transmit the first power supply voltage VDD to the second terminal of the second pull-up FETMP2. The second power line 44 is connected to the second terminals of the first pull-down FETMN1 and the second pull-down FETMN2 respectively to transmit the second power supply voltage VSS to the second terminals of the first pull-down FETMN1 and the second pull-down FETMN2.

[0129] As an example, referring to Figures 7, 8C, 9C to 9E, the first power line 43, the second power line 44 and the third power line 45 are disposed on the second wiring layer 40, that is, the first power line 43, the second power line 44 and the third power line 45 are disposed on the same layer as the first bit line BL1 and the second bit line BL2, which simplifies the wiring design, improves the integration, and facilitates expansion and optimization.

[0130] For example, referring to Figures 7 and 8C, the orthographic projection of the first bit line BL1 onto the substrate 10 lies between the orthographic projections of the first power line 43 and the second power line 44 onto the substrate 10, and the orthographic projection of the second bit line BL2 onto the substrate 10 lies between the orthographic projections of the second power line 44 and the third power line 45 onto the substrate 10. Therefore, the second power line 44 can be used to reduce the coupling effect of the sum of the first bit line BL1 and the second bit line BL2 connected to the same memory cell 100, thereby reducing signal interference and improving signal read / write accuracy.

[0131] For example, referring to Figures 7 and 8C, the first power line 43, the second power line 44, and the third power line 45 are arranged sequentially along the first direction F1 and extend along the second direction F2 respectively. The orthographic projection of the first power line 43 onto the substrate 10 is located on the side opposite to the orthographic projection of the first region 111 onto the substrate 10, and the orthographic projection of the second power line 44 onto the substrate 10 is located in the channel 211 of the second pull-down FET MN2. N2 The orthogonal projection of substrate 10 and the channel 211 of the first pull-down FET MN1 N1 Between the orthographic projections of the substrate 10, the third power line 45 is located in the third region 113 in the orthographic projection of the substrate 10, facing away from the second region 112 on the side of the orthographic projection of the substrate 10.

[0132] To achieve electrical connection between the first power line 43 and the second terminal of the first pull-up FETMP1, as an example, referring to Figures 7, 8A to 8B, and 9C, the first wiring layer 30 further includes a first power interconnect 35. The first power line 43 is connected to the first power interconnect 35 through a first power contact hole CC1, and the first power interconnect 35 is connected to the channel 211 of the first pull-up FETMP1 through a second power contact hole CC2. P1 The second part, region 211b P1 Connection, Part 2, Area 211b P1 It can be used as the second terminal of the first pull-up FETMP1 to realize the electrical connection between the first power line 43 and the second terminal of the first pull-up FETMP1.

[0133] To achieve electrical connection between the third power line 45 and the second terminal of the second pull-up FET MP2, as an example, referring to Figures 7, 8A to 8C, and 9D, the first wiring layer 30 further includes a second power interconnect 36. The third power line 45 is connected to the second power interconnect 36 through a third power contact hole CC3, and the second power interconnect 36 is connected to the channel 211 of the second pull-up FET MP2 through a fourth power contact hole CC4. P2 The second part, region 211b P2 Connection, Part 2, Area 211bP2 It can be used as the second terminal of the second pull-up FETMP2 to realize the electrical connection between the third power line 45 and the second terminal of the second pull-up FETMP2.

[0134] To achieve electrical connections between the second power line 44 and the second terminal of the first pull-down FET MN1 and the second pull-down FET MN2, as an example, referring to Figures 7, 8A to 8C, and 9E, the first wiring layer 30 further includes a third power interconnect 37 and a fourth power interconnect 38. The second power line 44 is connected to the third power interconnect 37 through a fifth power contact hole CC5, and the third power interconnect 37 is connected to the channel 211 of the first pull-down FET MN1 through a sixth power contact hole CC6. N1 The second part, region 211b N1 Connection. Furthermore, the second power line 44 is connected to the fourth power interconnect 38 via the seventh power contact hole CC7, and the fourth power interconnect 38 is connected to the channel 211 of the second pull-down FET MN2 via the eighth power contact hole CC8. N2 The second part, region 211b N2 Connection. Specifically, the second part, region 211b. N1 It can be used as the second electrode of the first pull-down FETMN1, in the second part of region 211b. N2 It can serve as the second terminal of the second pull-down FET MN2 to achieve electrical connection between the second power line 44 and the second terminal of the first pull-down FET MN1 and the second pull-down FET MN2, respectively. It is understood that the CNT in the corresponding FET and the connection method of the CNT with the third power interconnect 37 and the fourth power interconnect 38 are shown in the semiconductor device layer 20 shown in FIG9E; the remaining structures are not shown.

[0135] Understandably, referring to Figure 8A, the first part, region 211a A1 The orthogonal projection of substrate 10 and the gate 212 of the first access FET MA1 A1 The orthographic projections of substrate 10 do not overlap, the first region 211a P1 Second part of region 211b P1 The orthogonal projection of substrate 10 is respectively aligned with the gate 212 of the first pull-up FET MP1. P1 The orthographic projections of substrate 10 do not overlap, the first region 211a N1 Second part of region 211b N1 The orthogonal projection of substrate 10 is respectively aligned with the gate 212 of the first pull-down FET MN1. N1 The orthographic projections of substrate 10 do not overlap, the first region 211a N2 Second part of region 211b N2The orthogonal projection of substrate 10 is respectively aligned with the gate 212 of the second pull-down FET MN2. N2 The orthographic projections of substrate 10 do not overlap, the second region 211a A2 The orthogonal projection of substrate 10 and the gate 212 of the second access FET MA2 A2 The orthographic projections of substrate 10 do not overlap, the first region 211a P2 Second part of region 211b P2 The orthogonal projection of substrate 10 and the gate 212 of the second pull-up FET MP2 P2 The orthographic projections of substrate 10 do not overlap.

[0136] For example, the first power contact hole CC1, the third power contact hole CC3, the fifth power contact hole CC5, and the seventh power contact hole CC7 penetrate the second dielectric layer 12, and the second power contact hole CC2, the fourth power contact hole CC4, the sixth power contact hole CC6, and the eighth power contact hole CC8 penetrate the first dielectric layer 11. For example, during the fabrication process, conductive material can be filled into the first power contact hole CC1 to the eighth power contact hole CC8 to form conductive portions, thereby achieving electrical connection.

[0137] For example, a memory array has multiple rows of memory cells, multiple first bit lines BL1, multiple second bit lines BL2, multiple first power lines 43, multiple second power lines 44, and multiple third power lines 45. Each row of memory cells corresponds to one first bit line BL1, one second bit line BL2, one first power line 43, one second power line 44, and one third power line 45. Specifically, each first access FETMA1 in a row of memory cells is connected to one first bit line BL1, each second access FETMA2 in a row of memory cells is connected to one second bit line BL2, each first pull-up FETMP1 in a row of memory cells is connected to one first power line 43, each second pull-up FETMP2 in a row of memory cells is connected to one third power line 45, and each second pull-down FETMN2 and first pull-down FETMN1 in a row of memory cells is connected to one second power line 44. This simplifies wiring, saves memory array area, and improves integration.

[0138] In one embodiment of this application, the structures of two adjacent memory cells 100 along the second direction F2 are symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs. Exemplarily, the structures of two adjacent memory cells 100 along the second direction F2 can be mirror-symmetrical about the axis of symmetry along the first direction F1. Further, when the first bit interconnect 33, the second power interconnect 36, and the fourth power interconnect 38 are located between a first portion of adjacent memory cells 100 arranged along the second direction F2, the first portion of adjacent memory cells 100 can share the first bit interconnect 33, the second power interconnect 36, and the fourth power interconnect 38. When the second bit interconnect 34, the first power interconnect 35, and the third power interconnect 37 are located between a second portion of adjacent memory cells 100 arranged along the second direction F2, the second portion of adjacent memory cells 100 can share the second bit interconnect 34, the first power interconnect 35, and the third power interconnect 37. This further simplifies wiring, further saves memory array area, and further improves integration. In other embodiments of this application, the structures of two adjacent memory cells 100 along the second direction F2 can also be the same, that is, the structure of one memory cell 100 is translated along the second direction F2 to form the structure of another memory cell 100. In this case, the first bit interconnect 33, the second bit interconnect 34, and the first power interconnect 35 to the fourth power interconnect 38 can also not be shared between the two memory cells 100. That is, the first bit interconnect 33, the second bit interconnect 34, and the first power interconnect 35 to the fourth power interconnect 38 in different memory cells 100 are independent of each other.

[0139] In one embodiment of this application, the channel 211 in the storage cells 100 arranged along the second direction F2 P1 and 211 A1 The channels 211 in the storage cells 100 arranged along the second direction F2 are shared. P2 and 211 A2 It is also shared, which can save space and optimize the layout. Furthermore, regarding the aforementioned first part of adjacent storage units 100, the channel 211 in the first part of adjacent storage units 100... N2 They are shared, which can save space and optimize the layout. Regarding the second part of the adjacent storage units 100 mentioned above, the channel 211 in the second part of the adjacent storage units 100... N1 They are shared, which can save space and optimize the layout. In other embodiments of this application, the above-mentioned channels may not be shared, and this is not limited here.

[0140] For example, referring to Figures 7 and 8B, the first power interconnect 35, the third power interconnect 37, and the second bit line interconnect 34 of the plurality of memory cells 100 arranged along the first direction F1 are arranged along the first direction F1, and the second power interconnect 36, the fourth power interconnect 38, and the first bit line interconnect 33 of the plurality of memory cells 100 arranged along the first direction F1 are arranged along the first direction F1, further optimizing the layout.

[0141] As an example, in order to connect WL to the gate 212 of the first access FETMA1 respectively A1 Second access FETMA2 gate 212 A2 Electrical connections, referring to Figures 7, 8A, 8B, and 8D, the second wiring layer 40 further includes a first word line interconnect 46 and a second word line interconnect 47. WL is connected to the first word line interconnect 46 through the first word line contact hole CD1, and the first word line interconnect 46 is connected to the gate 212 of the first access FETMA1 through the second word line contact hole CD2. A1 Connection. Furthermore, WL is connected to the second word line interconnect 47 via the third word line contact hole CD3, and the second word line interconnect 47 is connected to the gate 212 of the second access FETMA2 via the fourth word line contact hole CD4. A2 Connection. This allows the gate 212 of the first access FETMA1 to be connected. A1 Second access FETMA2 gate 212 A2 Connected to the same WL, the signal transmitted through the WL drives the first access FETMA1 and the second access FETMA2 to turn on and off.

[0142] For example, the first word line contact hole CD1 and the third word line contact hole CD3 penetrate the third dielectric layer 13, and the second word line contact hole CD2 and the fourth word line contact hole CD4 respectively penetrate the first dielectric layer 11 to the third dielectric layer 13. For example, during the manufacturing process, conductive material can be filled into the first word line contact hole CD1 to the fourth word line contact hole CD4 to form a conductive part to achieve electrical connection.

[0143] For example, the memory array has multiple memory cell columns and multiple WLs, with one memory cell column corresponding to one WL. The first access FETMA1 and the second access FETMA2 in one memory cell column are connected to one WL to simplify wiring, save memory array area, and improve integration.

[0144] In one embodiment of this application, the structures of two adjacent memory cells 100 along the first direction F1 can be made symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs. Exemplarily, the structures of two adjacent memory cells 100 along the first direction F1 can be mirror-symmetrical about the axis of symmetry along the second direction F2. Further, when the first word line interconnect 46 is located between a third portion of adjacent memory cells 100 arranged along the first direction F1, the third portion of adjacent memory cells 100 can share the first word line interconnect 46. When the second word line interconnect 47 is located between a fourth portion of adjacent memory cells 100 arranged along the first direction F1, the fourth portion of adjacent memory cells 100 can share the second word line interconnect 47. Thus, wiring can be further simplified, memory array area can be further saved, and integration density can be further improved. In other embodiments of this application, the structures of two adjacent memory cells 100 along the first direction F1 can also be the same, that is, the structure of one memory cell 100 is translated along the first direction F1 to form the structure of another memory cell 100. In this case, the first word line interconnect 46 and the second word line interconnect 47 may not be shared in the two memory cells 100, that is, the first word line interconnect 46 and the second word line interconnect 47 in different memory cells 100 are independent of each other.

[0145] In one embodiment of this application, the third group of adjacent storage cells 100 can share a first power line. Similarly, the fourth group of adjacent storage cells 100 can share a third power line.

[0146] Example 2

[0147] Figure 10 is a top view of another storage array in an embodiment of this application; Figure 11A is a top view of the semiconductor device layer in Figure 10; Figure 11B is a top view of the fourth wiring layer in Figure 10; Figure 11C is a top view of the first wiring layer in Figure 10; Figure 11D is a top view of the second wiring layer in Figure 10; Figure 11E is a top view of the third wiring layer in Figure 10; Figure 12A is a cross-sectional view along the AA' direction in Figure 10; and Figure 12B is a cross-sectional view along the BB' direction in Figure 10. A structural schematic diagram is shown in Figure 12C, which is a cross-sectional view along the CC' direction in Figure 10. Referring to Figures 10 to 12C, the memory array may include not only the semiconductor device layer 20, the first dielectric layer 11, the first wiring layer 30, the second dielectric layer 12, the second wiring layer 40, the third dielectric layer 13, and the third wiring layer 50, but also a fourth wiring layer 60 located between the semiconductor device layer 20 and the first dielectric layer 11, and a fourth dielectric layer 14 located between the fourth wiring layer 60 and the semiconductor device layer 20. This embodiment is a modification of the implementation in Embodiment 1. The differences between this embodiment and Embodiment 1 described above will only be explained below; the similarities will not be repeated here. It is understood that the semiconductor device layer 20 shown in Figure 12C illustrates the CNTs in the corresponding FETs, as well as the connection methods between the CNTs and the third power interconnect 37 and the fourth power interconnect 38; the remaining structures are not shown.

[0148] In another embodiment of this application, referring to FIG10, WL extends along the second direction F2, and the first bit line BL1 and the second bit line BL2 extend along the first direction F1 and are arranged along the second direction F2, respectively. This arrangement, where WL intersects with the first bit line BL1 and the second bit line BL2, simplifies addressing, improves integration density, reduces wiring length, enhances stability, optimizes read / write speed, reduces power consumption, and simplifies manufacturing processes.

[0149] Furthermore, when using CNTs to form the channels of each FET, the current process for forming semiconductor CNTs limits the purity of the formed semiconductor CNT material, resulting in a small amount of metallic CNTs. This leads to the introduction of a small number of metallic CNTs into the channel. Since metallic CNTs have good conductivity, their presence increases leakage current in the first and second access FETs within the memory cell. Taking a first access FET in a memory cell row as an example, when the first access line extends along the second direction, each first access FET in that row is connected to the first access line. If the CNTs forming the first access FETs in that row are metallic CNTs, the leakage current from each first access FET to the first access line in the off state increases significantly, thereby increasing power consumption, reducing noise margin, slowing down read speed, affecting data stability, and reducing reliability. Referring to Figure 10, in this embodiment, the first line extends along the first direction F1, such that the extension direction of the first line intersects or is perpendicular to the extension direction of the CNT in the first access FET in the memory cell row, thereby connecting the first line to the first access FET in a memory cell column. Based on this, for the same memory cell column, if the CNT in the first access FET of one memory cell row contains a metallic CNT, while the CNTs in the first access FETs of the other memory cell rows do not, the leakage current from only one first access FET to the first line is increased, while the leakage current from the other first access FETs to the first line is less or negligible. This reduces power consumption, increases noise margin, improves read speed, enhances data stability, and improves reliability.

[0150] In one embodiment of this application, referring to Figures 10, 12A to 12C, a first power line 43, a second power line 44, and a third power line 45 are located on a fourth wiring layer 60. Specifically, in the channel 211 between the first power line 43 and the first pull-up FETMP1... P1 The second part, region 211b P1 When connected via the first power interconnect 35, the second power contact CC2 also penetrates the fourth dielectric layer 14. In the channel 211 between the third power line 45 and the second pull-up FET MP2... P2 The second part, region 211b P2 When connected via the second power interconnect 36, the fourth power contact hole CC4 also penetrates the fourth dielectric layer 14. This is in the channel 211 between the second power line 44 and the first pull-down FET MN1. N1 The second part, region 211b N1 When connected via the third power interconnect 37, the sixth power contact hole CC6 also penetrates the fourth dielectric layer 14. This is in the channel 211 between the second power line 44 and the second pull-down FET MN2.N2 The second part, region 211b N2 When connected via the third power interconnect 37, the eighth power contact hole CC8 also penetrates the fourth dielectric layer 14.

[0151] For example, referring to Figures 10, 12A to 12C, when the first wiring layer 30 needs to be connected to a corresponding channel, the interconnects in the first wiring layer 30 also need to penetrate the fourth dielectric layer 14. For example, in the channel 211 of the first pull-up FETMP1 P1 The first part of region 211a P1 Channel 211 with the first pull-down FETMN1 N1 The first part of region 211a N1 When connected via the first electrode interconnect 31, the first electrode contact hole CA1 and the second electrode contact hole CA2 also penetrate the fourth dielectric layer 14. Furthermore, in the channel 211 of the second pull-up FETMP2... P2 The first part of region 211a P2 Channel 211 with the second pull-down FETMN2 N2 The first part of region 211a N2 When connected via the second electrode interconnect 32, the third electrode contact hole CA3 and the fourth electrode contact hole CA4 also penetrate the fourth dielectric layer 14. The rest are similar and will not be elaborated upon here.

[0152] In one embodiment of this application, referring to FIG10, WL connects to the gate 212 of the first access FETMA1 through the fifth word line contact hole CD5. A1 The connection is made, and WL connects to the gate 212 of the second access FETMA2 via the sixth word line contact hole CD6. A2 The connection is achieved by the fifth digit contact hole CD5 and the sixth digit contact hole CD6 sequentially penetrating the third dielectric layer 13, the second dielectric layer 12, the first dielectric layer 11, and the fourth dielectric layer 14, respectively. Furthermore, during fabrication, conductive material can be filled into the fifth digit contact hole CD5 and the sixth digit contact hole CD6 to form conductive portions, thereby achieving electrical connection.

[0153] For example, referring to Figures 10, 11D, and 11E, the first bit line BL1 and the second bit line BL2 are respectively straight lines, and the shape of WL is bent, which simplifies design and manufacturing and facilitates expansion and optimization of the layout. For example, the shape of WL can be rectangular wave-shaped. This application does not limit the shape of WL. For example, it can also be wavy, sawtooth, etc.

[0154] For example, a column of memory cells corresponds to a first bit line BL1 and a second bit line BL2, wherein each first access FETMA1 in a column of memory cells is connected to a first bit line BL1, and each second access FETMA2 in a column of memory cells is connected to a second bit line BL2.

[0155] For example, one row of memory cells corresponds to one word line, wherein the first access FETMA1 and the second access FETMA2 in a row of memory cells are connected to one word line to simplify wiring, save memory array area, and improve integration.

[0156] It is understood that, in this embodiment, other structures in the semiconductor device layer 20, the first dielectric layer 11, the first wiring layer 30, the second dielectric layer 12, the second wiring layer 40, the third dielectric layer 13, and the third wiring layer 50 can refer to the relevant content in Embodiment 1, and will not be elaborated here.

[0157] Example 3

[0158] Figure 13 is a top view of another storage array in an embodiment of this application. Figure 14A is a top view of the semiconductor device layer in Figure 13. Figure 14B is a top view of the fourth wiring layer in Figure 13. Figure 14C is a top view of the first wiring layer in Figure 13. Figure 14D is a top view of the second wiring layer in Figure 13. Figure 15A is a cross-sectional view along the AA' direction in Figure 13. Figure 15B is a cross-sectional view along the BB' direction in Figure 13. Figure 15C is a cross-sectional view along the CC' direction in Figure 13. Referring to Figures 13 to 15C, the storage array may include not only the semiconductor device layer 20, the first dielectric layer 11, the first wiring layer 30, the second dielectric layer 12, and the second wiring layer 40, but also a fourth wiring layer 60 located between the semiconductor device layer 20 and the first dielectric layer 11, and a fourth dielectric layer 14 located between the fourth wiring layer 60 and the semiconductor device layer 20. This embodiment is a modification of the implementation method in Embodiment 2. The following only describes the differences between this embodiment and the above-described embodiment two; the similarities will not be repeated here.

[0159] In another embodiment of this application, referring to FIG13 and FIG14A, the first pull-up FETMP1 and the second pull-up FETMP2 are located in the first region 111, and the first pull-up FETMP1 and the second pull-up FETMP2 are arranged along the second direction F2. Thus, by setting the two P-type FETs, the first pull-up FETMP1 and the second pull-up FETMP2, which realize the pull-up function, in the first region 111, the difference between the first pull-up FETMP1 and the second pull-up FETMP2 can be reduced, the matching of electrical characteristics can be improved, and the stability of the performance of the memory cell 100 can be improved.

[0160] For example, referring to Figures 13 and 14A, in the same memory cell 100, the channel 211 of the first pull-up FETMP1 P1 The channel 211 of the second pull-up FETMP2 P2 Not shared.

[0161] In another embodiment of this application, referring to FIG13 and FIG14A, the first access FETMA1 and the second access FETMA2 are located in the third region 113, and the first access FETMA1 and the second access FETMA2 are arranged along the second direction F2. Thus, by setting the two P-type FETs, the first access FETMA1 and the second access FETMA2, which realize the gating function, in the third region 113, the difference between the first access FETMA1 and the second access FETMA2 can be reduced, the matching of electrical characteristics can be improved, and the stability of the performance of the memory cell 100 can be improved.

[0162] For example, referring to Figures 13 and 14A, in the same memory cell 100, the channel 211 of the first access FETMA1 A1 Second access FETMA2 channel 211 A2 Not shared.

[0163] In another embodiment of this application, referring to Figures 13 and 14A, the first pull-down FET MN1 and the second pull-down FET MN2 are located in the second region 112, and the first pull-down FET MN1 and the second pull-down FET MN2 are arranged along the second direction F2. Thus, by setting the two N-type FETs, the first pull-down FET MN1 and the second pull-down FET MN2, which realize the pull-down function, in the second region 112, the difference between the first pull-down FET MN1 and the second pull-down FET MN2 can be reduced, the matching of electrical characteristics can be improved, and the stability of the performance of the memory cell 100 can be improved.

[0164] For example, referring to Figures 13 and 14A, in the same memory cell 100, the channel 211 of the first pull-down FETMN1 N1 Channel 211 of the second pull-down FETMN2 N2 Not shared.

[0165] In another embodiment of this application, referring to Figures 13 and 14A, the first pull-up FETMP1, the first pull-down FETMN1, and the first access FETMA1 are arranged along the first direction F1, which can save area, optimize signal transmission, and simplify wiring.

[0166] In another embodiment of this application, referring to Figures 13 and 14A, the second pull-up FETMP2, the second pull-down FETMN2, and the second access FETMA2 are arranged along the first direction F1, which can save area, optimize signal transmission, and simplify wiring.

[0167] In another embodiment of this application, referring to Figures 13 and 14A, the gate 212 of the first pull-up FETMP1 P1 Gate 212 of the first pull-down FETMN1 N1 and the first access FETMA1 gate 212 A1 Arranging the layout along the first direction F1 can further optimize the map layout.

[0168] In another embodiment of this application, referring to Figures 13 and 14A, the gate 212 of the second pull-up FETMP2 P2 Gate 212 of the second pull-down FETMN2 N2 Second access FETMA2 gate 212 A2 Arranging the layout along the first direction F1 can further optimize the map layout.

[0169] In another embodiment of this application, referring to Figures 13, 14A, 14C, 15A, and 15B, the first electrode of the first pull-up FETMP1, the first electrode of the first pull-down FETMN1, and the first electrode of the first access FETMA1 are connected via a first electrode interconnect 31. Exemplarily, the first electrode interconnect 31 is connected to the channel 211 of the first pull-up FETMP1 via a first electrode contact hole CA1. P1 The first part of region 211a P1 The first electrode interconnect 31 is also connected to the channel 211 of the first pull-down FET MN1 through the second electrode contact hole CA2. N1 The first part of region 211a N1 The first electrode interconnect 31 is also connected to the channel 211 of the first access FET MA1 via the fifth electrode contact hole CA5. A1 The second part, region 211b A1 Connection. Specifically, the second part, region 211b. A1 It can be used as the first terminal of the first access FETMA1 to achieve the above-mentioned electrical connection and realize signal transmission.

[0170] In another embodiment of this application, referring to Figures 13, 14A, 14C, 15A, and 15B, the first electrode of the second access FETMA2, the first electrode of the second pull-up FETMP2, and the first electrode of the second pull-down FETMN2 are connected via a second electrode interconnect 32. Exemplarily, the second electrode interconnect 32 is connected to the channel 211 of the second pull-up FETMP2 via a third electrode contact hole CA3. P2 The first part of region 211a P2 The second electrode interconnect 32 is also connected to the channel 211 of the second pull-down FET MN2 through the fourth electrode contact hole CA4. N2The first part of region 211a N2 The second electrode interconnect 32 is also connected to the channel 211 of the second access FETMA2 via the sixth electrode contact hole CA6. A2 The second part of region 211a A2 Connection. Specifically, the second part, region 211a. A2 It can be used as the first pole of the second access FETMA2 to achieve the above-mentioned electrical connection and realize signal transmission.

[0171] For example, referring to FIG13, the gate 212 of the first pull-up FETMP1 P1 The gate 212 of the second pull-up FETMP2 is connected to the second electrode interconnect 32. P2 The first electrode interconnect 31 is connected to achieve the aforementioned electrical connection and enable signal transmission. For example, the gate 212 of the first pull-up FETMP1... P1 The gate 212 of the second pull-up FETMP2 can be connected to the second electrode interconnect 32 via the first gate interconnect 71. P2 The first electrode interconnect 31 can be connected via the second gate interconnect 72. As an example, for structures at some process nodes (e.g., earlier than 28nm), the area of ​​the memory cell 100 can be larger; based on this, the first gate interconnect 71 is connected to the gate 212 of the first pull-up FET MP1. P1 As a single structure, the second gate interconnect 72 and the gate 212 of the second pull-up FETMP2 are integrated. P2 As a single integrated structure, the first gate interconnect 71 is connected to the second electrode interconnect 32 through the first gate contact hole CE1, and the second gate interconnect 72 is connected to the first electrode interconnect 31 through the second gate contact hole CE2, simplifying the manufacturing process. Furthermore, the first gate contact hole CE1 and the second gate contact hole CE2 penetrate the first dielectric layer 11 and the fourth dielectric layer 14, respectively. As another example, with the shrinking of process nodes (e.g., later than 28nm), the area of ​​the memory cell 100 is further compressed. Based on this, the first gate interconnect 71 and the second gate interconnect 72 can be disposed on the first wiring layer 30, further optimizing the layout. For example, the first gate interconnect 71 and the second electrode interconnect 32 are a single integrated structure, and the second gate interconnect 72 and the first electrode interconnect 31 are a single integrated structure. The first gate interconnect 71 is connected to the gate of the first pull-up FETMP1 through the third gate contact hole, and the second gate interconnect 72 is connected to the gate of the second pull-up FETMP2 through the fourth gate contact hole, simplifying the manufacturing process. Furthermore, the third gate contact hole and the fourth gate contact hole penetrate the first dielectric layer 11 and the fourth dielectric layer 14, respectively.

[0172] In another embodiment of this application, referring to Figures 13, 14B, 15A, and 15B, the memory array further includes a first power line 43 and a second power line 44. The first power line 43 is connected to the second terminals of a first pull-up FETMP1 and a second pull-up FETMP2, respectively, to transmit a first power supply voltage VDD to the first pull-up FETMP1 and the second pull-up FETMP2 via the first power line 43. Furthermore, the second power line 44 is connected to the second terminals of a first pull-down FETMN1 and a second pull-down FETMN2, respectively, to transmit a second power supply voltage VSS to the second terminals of the first pull-down FETMN1 and the second pull-down FETMN2 via the second power line 44. This further reduces the number of power lines and optimizes the layout.

[0173] In another embodiment of this application, referring to Figures 13, 14B, 15A, and 15B, a first power line 43 and a second power line 44 are disposed on a fourth wiring layer 60. The first power line 43 can be connected to the second terminal of a first pull-up FETMP1 via a first power interconnect 35, and to the second terminal of a second pull-up FETMP2 via a second power interconnect 36. Exemplarily, the first power line 43 is connected to the first power interconnect 35 via a first power contact hole CC1, and the first power interconnect 35 is connected to the channel 211 of the first pull-up FETMP1 via a second power contact hole CC2. P1 The second part, region 211b P1 Connection. Furthermore, the first power line 43 is connected to the second power interconnect 36 via the third power contact hole CC3, and the second power interconnect 36 is connected to the channel 211 of the second pull-up FETMP2 via the fourth power contact hole CC4. P2 The second part, region 211b P2 Connections are made. The second power contact hole CC2 and the fourth power contact hole CC4 also penetrate the fourth dielectric layer 14. Similarly, the sixth power contact hole CC6 and the eighth power contact hole CC8 also penetrate the fourth dielectric layer 14.

[0174] For example, referring to Figures 13, 14A, and 14B, the first power line 43 and the second power line 44 are arranged sequentially along the first direction F1 and extend along the second direction F2 respectively. The orthographic projection of the first power line 43 onto the substrate 10 is located on the side opposite to the orthographic projection of the first region 111 onto the substrate 10, and the orthographic projection of the second power line 44 onto the substrate 10 is located between the orthographic projections of the second region 112 and the third region 113 onto the substrate 10. This optimizes the layout.

[0175] For example, referring to Figures 13, 14A, 14C, and 14D, the WL is disposed on the first wiring layer 30, that is, the WL is disposed on the same layer as the first electrode interconnect 31 and the second electrode interconnect 32, which simplifies wiring design, improves integration, and facilitates expansion and optimization. For example, the orthographic projection of the WL onto the substrate 10 is located on the side opposite to the orthographic projection of the third region 113 onto the substrate 10. For example, the WL is connected to the gate of the first access FETMA1 through the fifth word line contact hole CD5, and the word line is connected to the gate 212 of the second access FETMA2 through the sixth word line contact hole CD6. A2 Connection. In other embodiments of this application, when the storage array further includes a third media layer 13 and a third wiring layer 50, word lines may also be disposed on the third wiring layer 50.

[0176] In one embodiment of this application, the structures of two adjacent memory cells 100 along the second direction F2 are symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs. Exemplarily, the structures of two adjacent memory cells 100 along the second direction F2 can be mirror-symmetrical about the axis of symmetry along the first direction F1. Further, when the second bit line interconnect 34, the second power interconnect 36, and the fourth power interconnect 38 are located between the fifth portion of adjacent memory cells 100 arranged along the second direction F2, the fifth portion of adjacent memory cells 100 can share the second bit line interconnect 34, the second power interconnect 36, and the fourth power interconnect 38. When the first bit line interconnect 33, the first power interconnect 35, and the third power interconnect 37 are located between the sixth portion of adjacent memory cells 100 arranged along the second direction F2, the sixth portion of adjacent memory cells 100 can share the first bit line interconnect 33, the first power interconnect 35, and the third power interconnect 37. Thus, wiring can be further simplified, memory array area can be further saved, and integration density can be further improved. In other embodiments of this application, the structures of two adjacent memory cells 100 along the second direction F2 can also be the same, that is, the structure of one memory cell 100 is translated along the second direction F2 to form the structure of another memory cell 100. In this case, the first bit interconnect 33, the second bit interconnect 34, and the first power interconnect 35 to the fourth power interconnect 38 can also not be shared between the two memory cells 100. That is, the first bit interconnect 33, the second bit interconnect 34, and the first power interconnect 35 to the fourth power interconnect 38 in different memory cells 100 are independent of each other.

[0177] In one embodiment of this application, regarding the fifth adjacent memory cell 100, the channel 211 in the fifth adjacent memory cell 100 is... P2 It is shared, channel 211 N2 It is shared, channel 211 A2They are shared, which can save space and optimize the layout. Regarding the sixth part of the adjacent storage units 100 mentioned above, the channel 211 in the sixth part of the adjacent storage units 100... P1 It is shared, channel 211 N1 It is shared, channel 211 A1 They are shared, which can save space and optimize the layout. In other embodiments of this application, the above-mentioned channels may not be shared, and this is not limited here.

[0178] In one embodiment of this application, the structures of two adjacent memory cells 100 along the first direction F1 can be made symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs. For example, the structures of two adjacent memory cells 100 along the first direction F1 can be mirror-symmetrical about the axis of symmetry along the second direction F2. Further, when the first power line 43 is located between a seventh group of adjacent memory cells 100 arranged along the first direction F1, the seventh group of adjacent memory cells 100 can share a single first power line 43.

[0179] It is understood that, in this embodiment, the other structures in the semiconductor device layer 20, the first dielectric layer 11, the first wiring layer 30, the second dielectric layer 12, the second wiring layer 40, the fourth dielectric layer 14, and the fourth wiring layer 60 can refer to the relevant content in Embodiment 2, and will not be elaborated here.

[0180] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A storage array, characterized in that, The device includes a substrate and a plurality of memory cells located on the substrate. Each memory cell includes: a first access field-effect transistor (FET), a second access FET, a first pull-up FET, a second pull-up FET, a first pull-down FET, and a second pull-down FET, wherein the channel of any one of the first access FET, the second access FET, the first pull-up FET, the second pull-up FET, the first pull-down FET, and the second pull-down FET comprises a semiconductor material, and the hole mobility of the semiconductor material is greater than or equal to the electron mobility of the semiconductor material. The first access FET, the second access FET, the first pull-up FET, and the second pull-up FET are P-type FETs, and the first pull-down FET and the second pull-down FET are N-type FETs. Furthermore, the channel width of the first pull-up FET and the channel width of the second pull-up FET are respectively greater than the channel width of the first access FET and the channel width of the second access FET, and the channel width of the first access FET and the channel width of the second access FET are respectively greater than the channel width of the first pull-down FET and the channel width of the second pull-down FET.

2. The storage array according to claim 1, characterized in that, The semiconductor material includes carbon nanotubes, wherein the number of carbon nanotubes in the channel of the first pull-up FET and the number of carbon nanotubes in the channel of the second pull-up FET are respectively greater than the number of carbon nanotubes in the channel of the first access FET and the channel of the second access FET, and the number of carbon nanotubes in the channel of the first access FET and the channel of the second access FET are respectively greater than the number of carbon nanotubes in the channel of the first pull-down FET and the channel of the second pull-down FET; or, The semiconductor material includes tellurium, graphene, silicon, germanium, or group III-V semiconductor materials.

3. The storage array according to claim 1 or 2, characterized in that, The memory cell includes a first region, a second region, and a third region arranged along a first direction. The first pull-down FET and the second pull-down FET are located in the second region. Two of the first access FET, the second access FET, the first pull-up FET, and the second pull-up FET are located in the first region, and the other two FETs are located in the third region. The first direction is the same as the width direction of the channel.

4. The storage array according to claim 3, characterized in that, The first access FET and the first pull-up FET are located in the first region and arranged along the second direction, and the second access FET and the second pull-up FET are located in the third region and arranged along the second direction, which intersects the first direction.

5. The storage array according to claim 4, characterized in that, The first pull-up FET and the second access FET are arranged along the first direction; and / or, the second pull-up FET and the first access FET are arranged along the first direction.

6. The storage array according to claim 5, characterized in that, The gates of the first pull-down FET, the first pull-up FET, and the second access FET are arranged along the first direction; and / or, The gates of the second pull-down FET, the second pull-up FET, and the first access FET are arranged along the first direction.

7. The storage array according to claim 6, characterized in that, The gate of the first pull-down FET extends along the first direction and is disposed in the channel of the second pull-down FET, and is connected to a first portion region of the channel of the second pull-down FET; and / or, The gate of the second pull-down FET extends along the first direction and is disposed in the channel of the first pull-down FET and is connected to a first portion region of the channel of the first pull-down FET.

8. The storage array according to claim 3, characterized in that, The first pull-up FET and the second pull-up FET are located in the first region and arranged along the second direction, and the first access FET and the second access FET are located in the third region and arranged along the second direction, which intersects the first direction.

9. The storage array according to claim 8, characterized in that, The first pull-up FET, the first pull-down FET, and the first access FET are arranged along the first direction; and / or, The second pull-up FET, the second pull-down FET, and the second access FET are arranged along the first direction.

10. The storage array according to claim 9, characterized in that, The gates of the first pull-up FET, the first pull-down FET, and the first access FET are arranged along the first direction; and / or, The gates of the second pull-up FET, the second pull-down FET, and the second access FET are arranged along the first direction.

11. The storage array according to claim 6, 7 or 10, characterized in that, The gate of the first pull-down FET and the gate of the first pull-up FET are of the same structure; and / or, The gate of the second pull-down FET and the gate of the second pull-up FET are integrated into one structure.

12. The storage array according to any one of claims 1-11, characterized in that, The first terminals of the first pull-up FET, the first terminals of the first pull-down FET, and the first terminals of the first access FET are connected via a first electrode interconnect, and the first terminals of the second access FET, the second pull-up FET, and the second pull-down FET are connected via a second electrode interconnect.

13. The storage array according to any one of claims 1-12, characterized in that, The memory array further includes a first bit line, a second bit line, and a word line. The first bit line is connected to the second terminal of the first access FET, the second bit line is connected to the second terminal of the second access FET, and the word line is connected to the gate of the first access FET and the gate of the second access FET, respectively.

14. The storage array according to claim 13, characterized in that, The first bit line and the second bit line are located on different layers from the word line. Wherein, the character line extends along the first direction, and the first bit line and the second bit line extend along the second direction and are arranged along the first direction; or, the character line extends along the second direction, and the first bit line and the second bit line extend along the first direction and are arranged along the second direction.

15. The storage array according to claim 14, characterized in that, The word line layer is located on the side of the first bit line and the second bit line layer facing away from the substrate, and the first electrode interconnect and the second electrode interconnect layer are located between the first bit line and the second bit line layer and the substrate.

16. The storage array according to claim 14 or 15, characterized in that, The first bit line and the second bit line are both straight lines, and the character line is either bent or straight.

17. The storage array according to any one of claims 4-7, characterized in that, The storage array further includes a first power line, a second power line, and a third power line. The first power line is connected to the second terminal of the first pull-up FET, the third power line is connected to the second terminal of the second pull-up FET, and the second power line is connected to the second terminals of the first pull-down FET and the second pull-down FET, respectively.

18. The storage array according to claim 17, characterized in that, The first power line, the second power line, and the third power line are respectively disposed on the same layer as the first bit line and the second bit line. The orthographic projection of the first bit line on the substrate is located between the orthographic projection of the first power line on the substrate and the orthographic projection of the second power line on the substrate. The orthographic projection of the second bit line on the substrate is located between the orthographic projection of the second power line on the substrate and the orthographic projection of the third power line on the substrate.

19. The storage array according to any one of claims 8-10, characterized in that, The memory array further includes a first power line and a second power line, wherein the first power line is connected to the second terminals of the first pull-up FET and the second pull-up FET, respectively, and the second power line is connected to the second terminals of the first pull-down FET and the second pull-down FET, respectively.

20. The storage array according to claim 19, characterized in that, The first power line and the second power line are arranged sequentially along the first direction and extend along the second direction respectively; The orthographic projection of the first power line on the substrate is located on the side opposite to the orthographic projection of the first region on the substrate, and the orthographic projection of the second power line on the substrate is located between the orthographic projection of the second region on the substrate and the orthographic projection of the third region on the substrate.

21. A static random access memory, characterized in that, include: The controller and at least one storage array as described in any one of claims 1-20, wherein the controller is electrically connected to any one of the storage arrays.

22. An electronic device, characterized in that, include: The circuit board and the static random access memory as described in claim 21, wherein the static random access memory is electrically connected to the circuit board.

Images