Chip stack package and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of chips, and provides a chip stack package and a manufacturing method therefor, and an electronic device, for use in reducing manufacturing costs of package structures. The chip stack package comprises a substrate and at least one chip stack structure arranged on the substrate. The chip stack structure comprises a first chip and a plurality of second chips stacked on the first chip. An active surface of the first chip faces the substrate. Active surfaces of the plurality of second chips all face away from the substrate, and the active surfaces of the plurality of second chips each comprise a wire-bonding region and a non-wire-bonding region. Among two adjacent second chips, the upper chip is farther from the substrate than the lower chip, the lower chip overlaps the upper chip at the non-wire-bonding region, and the wire-bonding region of the upper chip and the wire-bonding region of the lower chip are respectively located on two opposite sides of the chip stack structure and connected to the substrate by means of bonding wires. The multiple layers of chips in the chip stack structure are interconnected by wire bonding, eliminating the need to form TSVs, thereby reducing the manufacturing costs.

Description

Chip stacking packaging and its fabrication methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510387206.2, filed on March 28, 2025, entitled “Chip Stacking Package and Manufacturing Method Thereof, Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a chip stacking package and its manufacturing method, and electronic devices. Background Technology

[0003] The emergence of 3D (dimensional) stacking technology has brought new vitality to the semiconductor industry and has been widely used in mobile devices, the Internet of Things, and high-performance computing. 3D stacking technology integrates multiple chips or components by stacking them vertically (longitudinally), offering advantages such as high integration density, low power consumption, and high bandwidth, but it also has some drawbacks.

[0004] As illustrated in Figure 1, in existing 3D stacked packaging, multiple chips D are stacked vertically. Each chip D contains through-silicon vias (TSVs), and the chips D are interconnected vertically via these TSVs to form a novel chip packaging structure. This packaging structure uses TSVs to achieve vertical interconnection of multiple chips D. However, the fabrication of TSVs within the chips D is complex and has low yield, resulting in high cost for the packaging structure. Summary of the Invention

[0005] This application provides a chip stacking package and its manufacturing method, as well as an electronic device. The multilayer stacked chips are interconnected through a substrate based on wire bonding, which can reduce manufacturing costs.

[0006] This application provides a chip stacking package, the package structure including a substrate and at least one chip stack structure disposed on the substrate. The chip stack structure includes a first chip and a plurality of second chips stacked on the first chip. The active surface of the first chip faces the substrate and is connected to the substrate (i.e., flip-chip first chip). The active surfaces of the plurality of second chips all face the side away from the substrate (i.e., upright second chips), and the active surfaces of the plurality of second chips all include leaded areas and non-leaded areas. Any two adjacent second chips include an upper chip and a lower chip, the upper chip being away from the substrate relative to the lower chip. The lower chip overlaps with the upper chip in the non-leaded area, and the leaded areas of the upper chip and the lower chip are respectively located on a first side and a second side of the chip stack structure and connected to the substrate through bonding wires; the first side and the second side are opposite sides of the chip stack structure along a direction parallel to the substrate (i.e., opposite sides).

[0007] In the chip stacking package provided in this application, a chip stack structure is formed by flip-chipping the bottommost first chip onto a substrate and stacking multiple second chips upright on top of the first chip. The multiple second chips are staggered along opposite sides of the chip stack structure, so that the lead areas of the multiple second chips are distributed from bottom to top on opposite sides of the chip stack structure and connected to the substrate via bonding wires. This allows multiple lead areas on opposite sides of the chip stack structure to form multiple rows of bonding wires, increasing the lead-out capability of the chip stack structure and thus enabling high-density interconnection between the multiple second chips and the first chip. Simultaneously, the connection of the multiple second chips to the substrate via bonding wires avoids the need for through-silicon vias (TSVs) in the chips, thereby avoiding the low yield and high cost problems associated with TSVs. In other words, the chip stacking package provided in this application can improve product yield and reduce product manufacturing costs while achieving high-density interconnection between the multiple second chips and the first chip.

[0008] In some possible implementations, the substrate includes a first bridge chip, a second bridge chip, and multiple through-hole (TMV) vias, all distributed within a molding compound. The first bridge chip protrudes from the edge of the chip stack structure on a first side, and the second bridge chip protrudes from the edge of the chip stack structure on a second side. Multiple lead regions located on the first side of the chip stack structure are connected to the first bridge chip via bonding wires, and multiple lead regions located on the second side of the chip stack structure are connected to the second bridge chip via bonding wires. The first chip, the first bridge chip, and the second bridge chip all have overlapping areas, and are electrically connected to the first and second bridge chips in these overlapping areas. The multiple through-holes are located in the area between the first and second bridge chips, and are electrically connected to the first chip. In this case, the first chip is directly connected to the first and second bridge chips in the overlapping areas; the multiple lead regions located on the first side of the chip stack structure are connected to the protruding area of ​​the first bridge chip on the left side via bonding wires. Multiple lead regions located on the second side of the chip stack structure are connected to the protruding area on the right side of the second bridge chip via bonding wires. In this way, high-density interconnection between multiple second chips and the first chip can be achieved through the first and second bridge chips.

[0009] In some possible implementations, the substrate may further include a first wiring layer, located on the side of the molding compound away from the chip stack structure. The first bridge chip, the second bridge chip, and multiple molded vias are all electrically connected to the first wiring layer. The first wiring layer expands the input / output (I / O) connection points on the back of the substrate, thereby allowing for better matching with external circuitry.

[0010] In some possible implementations, the first bridge chip has at least one first through-silicon via (TSV), which is electrically connected to a first redistribution layer. A lead area located on the first side of the chip stack structure is connected to the first TSV via via bonding wires. The second bridge chip has at least one second TSV, which is electrically connected to the first redistribution layer. A lead area located on the second side of the chip stack structure is connected to the second TSV via via bonding wires. In this configuration, multiple second chips can interact with electronic devices on the back side of the substrate through the first and second TSVs to meet the relevant functional requirements of the second chips.

[0011] In some possible implementations, the substrate further includes a second wiring layer located on the side of the molding compound away from the first wiring layer, and the second wiring layer is electrically connected to the first bridge chip and the second bridge chip. This increases the design flexibility of the substrate.

[0012] In some possible implementations, the substrate includes an interposer (such as a silicon interposer) with through-silicon vias (TSVs) disposed therein. The interposer has a first protrusion region on a first side of the chip stack structure and a second protrusion region on a second side of the chip stack structure. Multiple lead regions located on the first side of the chip stack structure are electrically connected to the interposer via bonding wires in the first protrusion region; multiple lead regions located on the second side of the chip stack structure are electrically connected to the interposer via bonding wires in the second protrusion region. The first chip and the interposer are electrically connected in the overlapping region. In this case, high-density interconnection between multiple second chips and the first chip can be achieved through the interposer.

[0013] In some possible implementations, the substrate may also include a first wiring layer located on the side of the interposer away from the chip stack structure; the interposer is connected to the first wiring layer via a through-silicon via (TSV). The first wiring layer can expand the input / output (I / O) connection points on the back side of the substrate, thereby enabling better matching with external circuitry.

[0014] In some possible implementations, the substrate further includes a second wiring layer located on the side of the interposer away from the first wiring layer, and the second wiring layer is electrically connected to the interposer. This increases the design flexibility of the substrate.

[0015] In some possible implementations, the non-lead regions of multiple second chips project onto the substrate in overlapping manner. This reduces the area occupied by the chip stack structure on the substrate, which is more conducive to product miniaturization.

[0016] In some possible implementations, the projections of two spaced-apart second chips onto the substrate overlap. This reduces the area occupied by the chip stack structure on the substrate, which is more conducive to product miniaturization.

[0017] In some possible implementations, adjacent chips in a chip stack structure are connected by a chip bonding film containing metal. Since metal materials have a high thermal conductivity, the vertical thermal resistance of the chip stack structure can be reduced, thereby improving the heat dissipation performance of the package structure.

[0018] This application also provides a method for fabricating a chip stacked package, which may include: providing a substrate; mounting a first chip on the substrate using a flip-chip method; stacking a plurality of second chips on the first chip to form a chip stack structure on the substrate; wherein the active surfaces of the plurality of second chips face the side away from the substrate (i.e., upright second chips), and the active surfaces of the plurality of second chips all include lead areas and non-lead areas; any two adjacent second chips include an upper chip and a lower chip, the upper chip being away from the substrate relative to the lower chip; the lower chip overlapping the upper chip in the non-lead area, and the lead areas of the upper chip and the lower chip are respectively located on a first side and a second side of the chip stack structure and connected to the substrate by bonding wires; the first side and the second side are opposite sides (i.e., opposite sides) of the chip stack structure along a direction parallel to the substrate.

[0019] This fabrication method involves flip-chip bonding a first chip onto a substrate, and then sequentially bonding multiple second chips along opposite sides of the first chip to form a chip stack structure. The multiple second chips are staggered along opposite sides of the chip stack structure, distributing their lead regions from bottom to top along the opposite sides and connecting them to the substrate via bonding wires. This allows multiple lead regions on opposite sides of the chip stack structure to form multiple rows of bonding wires, increasing the lead-out capability of the chip stack structure and enabling high-density interconnection between the multiple second chips and the first chip. Furthermore, the connection of the multiple second chips to the substrate via bonding wires avoids the need for through-silicon vias (TSVs) within the chips, thus avoiding the low yield and high cost associated with TSVs. In other words, the chip stack packaging provided in this application can improve product yield and reduce manufacturing costs while achieving high-density interconnection between multiple second chips and the first chip.

[0020] In some possible implementations, the aforementioned substrate may include: mounting a first bridge chip and a second bridge chip on a carrier board; molding the first bridge chip and the second bridge chip to a molding layer; and forming a plurality of molded vias in the region of the molding layer between the first bridge chip and the second bridge chip. The carrier board is then removed, and a first redistribution layer is formed on one side of the removed carrier board to form the substrate; wherein the first redistribution layer is electrically connected to the plurality of molded vias. Using this substrate, high-density interconnection between a plurality of second chips and a first chip can be achieved through the first bridge chip and the second bridge chip.

[0021] In some possible implementations, the aforementioned substrate provision may include: fabricating a first redistribution layer on a carrier board; mounting a first bridge chip and a second bridge chip on the first redistribution layer; molding the first bridge chip and the second bridge chip to a molding layer; and forming a plurality of molded vias in the region of the molding layer between the first bridge chip and the second bridge chip to form the substrate; wherein the plurality of molded vias are electrically connected to the first redistribution layer.

[0022] In some possible implementations, the aforementioned substrate may include: providing an interposer layer on a carrier substrate, wherein through-silicon vias (TSVs) are provided in the interposer layer; removing the carrier substrate and fabricating a first redistribution layer on one side of the removed carrier substrate to form the substrate; wherein the interposer layer is electrically connected to the first redistribution layer through the TSVs. Using this substrate, high-density interconnection between multiple second chips and a first chip can be achieved through the interposer layer.

[0023] This application also provides an electronic device that includes a circuit board and a chip stack package as provided in any of the aforementioned possible implementations, wherein the circuit board is connected to the chip stack package. Attached Figure Description

[0024] Figure 1 is a schematic diagram of a 3D stacked packaging structure provided in the prior art;

[0025] Figure 2 is a schematic diagram of an electronic device using a chip stacking packaging structure provided in an embodiment of this application;

[0026] Figure 3 is a schematic diagram of a chip stacking packaging structure provided in an embodiment of this application;

[0027] Figure 4 is a schematic diagram of the structure of the second chip in a chip stacking packaging structure provided in an embodiment of this application;

[0028] Figure 5 is a schematic diagram of a chip stacking packaging structure provided in an embodiment of this application;

[0029] Figure 6 is a schematic diagram of a chip stacking packaging structure provided in an embodiment of this application;

[0030] Figure 7 is a flowchart illustrating the fabrication process of a chip stacked packaging structure provided in an embodiment of this application.

[0031] Figure 8 is a schematic diagram of the chip stacking packaging structure provided in this application during the manufacturing process;

[0032] Figure 9 is a schematic diagram of the chip stacking packaging structure provided in this application during the manufacturing process;

[0033] Figure 10 is a schematic diagram of the chip stacking packaging structure provided in this application during the manufacturing process. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, they can refer to electrical connections or mechanical connections; fixed connections or detachable connections or integral connections; direct connections or indirect connections through an intermediate medium; or internal communication between two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as “up,” “down,” “left,” and “right” are used only in relation to the orientation of the components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and they can change accordingly depending on the orientation of the components in the accompanying drawings.

[0036] This application provides an electronic device that employs a novel chip stacking package. The multi-layer stacked chips in this package structure are interconnected through a substrate based on wire bonding, which can reduce process complexity, improve product yield, and thus reduce product manufacturing costs.

[0037] This application does not limit the configuration of the aforementioned electronic device. The electronic device can be any electronic product with chip stacking and packaging, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0038] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.

[0039] Depending on actual needs, the above-mentioned electronic devices may also include other devices that are electrically connected to the chip stack package, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0040] Schematic, referring to Figure 2, an embodiment of this application provides an electronic device, which includes a PCB and a chip stack package 01 disposed on the PCB and electrically connected to the PCB. The chip stack package 01 adopts the novel structure provided in this application. The multi-layer stacked chips in this structure are interconnected through a substrate based on wire bonding W, which can reduce process complexity, improve yield, and thus reduce product manufacturing costs.

[0041] The following provides a further explanation of the specific settings of the novel chip stacking package provided in this application.

[0042] As illustrated in FIG3, this application provides a chip stacking package 01, which includes a substrate 10 and at least one chip stacking structure 20 disposed on the substrate 10. FIG3 is only illustrated with an example of two chip stacking structures 20 disposed on the substrate 10, but this application is not limited thereto.

[0043] The back side of the substrate 10 (i.e., the side away from the chip stack structure 20) may be provided with integrated passive devices (IPDs) to meet the functional requirements of the chip stack structure 20, as detailed in the following description. Additionally, solder balls may be provided on the back side of the substrate 10 to facilitate interconnection and communication between the chip stack package 01 and external devices.

[0044] Referring again to Figure 3, the chip stacking structure 20 includes a first chip D1 and a plurality of second chips D2 stacked on the first chip D1. That is, the first chip D1 and the plurality of second chips D2 are stacked, with the first chip D1 located at the bottom of the plurality of second chips D2. The active surface of the first chip D1 faces the substrate 10 (i.e., downward) and is electrically connected to the substrate 10. In other words, the first chip D1 is mounted on the substrate 10 using a flip chip (FC) method.

[0045] Referring to Figures 3 and 4, the active surfaces of the multiple second chips D2 face away from the substrate 10 (i.e., upwards), meaning the multiple second chips D2 are stacked on the first chip D1 in a top-mounted manner. The active surfaces A1 of the multiple second chips D2 each include a lead area a1 and a non-lead area a2. The lead area a1 is provided with connection structures (such as pads or bumps) to facilitate interconnection between the second chip and other devices. The non-lead area a2 has no connection structures and is used to facilitate stacking between the upper and lower chips. In two adjacent stacked second chips D2, the non-lead area a2 of the lower chip (i.e., the second chip closer to the substrate) overlaps with the upper chip (i.e., the second chip away from the substrate). The lead areas a2 of the lower chip and the upper chip are located on opposite sides of the chip stacking structure 20 (referred to as opposite sides) and are connected to the substrate 10 via bonding wires W. In this way, multiple lead regions a2 located on opposite sides of the chip stack structure 20 can form multiple rows of bonding lines W to increase the wire output capability of the chip stack structure 20, thereby enabling high-density interconnection between multiple second chips D2 and the first chip D1.

[0046] It should be understood that the active side of a chip refers to the surface on the chip where transistors, circuits, and other functional components are integrated; it is also called the "circuit side," "functional side," or "front side." The chip's input / output (I / O) pads are typically located on the active side and are used for interconnection with external circuitry or packages. Opposite to the active side is the "back side," which is the silicon substrate surface without any circuitry.

[0047] In this application embodiment, "opposite sides" and "opposite sides" refer to opposite sides of the chip stack structure along the direction parallel to the substrate at 20. To facilitate a clearer description of the relevant technical solutions in this application embodiment, "opposite sides" are defined as the first side and the second side, respectively. The following description uses the first side as the left side and the second side as the right side as an example, but it is not limited to this. The first side and the second side can also be the front side and the rear side.

[0048] As illustrated, in the stacked plurality of second chips D2, the lead areas a1 of the spaced second chips D2 are located on the same side of the chip stack structure 20. As shown in Figure 3, from top to bottom, the lead areas a1 of the plurality of second chips D2 located on the odd-numbered layers are located on the right side of the chip stack structure 20 and are connected to the substrate 10 on the right side via bonding wires W; the lead areas a1 of the plurality of second chips D2 located on the even-numbered layers are located on the left side of the chip stack structure 20 and are connected to the substrate 10 on the left side via bonding wires W. In this way, multiple rows of bonding wires W are formed on the left and right sides of the chip stack structure 20, improving the wire output capability of the chip stack structure 20, thereby enhancing the interconnection capability between the plurality of second chips D2 and the first chip D1, and thus meeting the requirements of the packaging structure for high-density interconnection.

[0049] It should be understood that a connection structure (pad, bump) is provided on the surface of the substrate 10 near the chip stack structure 20, and multiple chips (D1, D2) in the chip stack structure 20 are electrically connected to the substrate 10 through the connection structure (pad, bump).

[0050] In summary, in the novel packaging structure provided in this application embodiment, the active surface of the first chip D1 located at the bottom faces downward and is vertically connected to the substrate 10. The active surfaces of the multiple second chips D2 stacked on the first chip D1 face upward, and they are connected to the substrate 10 via bonding wires W along opposite sides (left and right sides) of the chip stack structure 20 in the lead area a1. In this case, the multiple second chips D2 do not need to be connected to the substrate 10 through through-silicon vias (TSVs), but are directly connected to the substrate 10 via bonding wires W, thus avoiding the problems of low yield and high cost caused by TSV fabrication. In this way, while satisfying the high-density interconnection between the multiple second chips D2 and the first chip D1, the yield can be improved and the manufacturing cost reduced.

[0051] Additionally, referring to Figure 3, a dummy chip can be stacked on top of the chip stack structure 20, above a plurality of second chips D2. This dummy chip can be stacked on the non-lead area a2 of the second chips D2. In this case, the stacked first chip D1, the plurality of second chips D2, and the dummy chip as a whole can be encapsulated in molding compound, and the top of the dummy chip is exposed by grinding.

[0052] The aforementioned dummy chip may not contain functional circuitry and serves as a placeholder chip in the package structure. It mainly addresses issues such as mechanical support and thermal management, thereby improving the stability, uniformity, and reliability of the package structure.

[0053] Furthermore, to minimize the area of ​​the chip stack package 01, as shown in Figure 3, the bottommost second chip D2 can completely overlap with the first chip D1, and the projections of the non-lead areas a2 of multiple second chips D2 onto the substrate 10 can overlap. In this case, the area occupied by the chip stack structure 20 on the substrate 10 can be reduced, which is more conducive to product miniaturization.

[0054] Similarly, in order to minimize the area of ​​the chip stack package 01, as shown in FIG3, the projections of multiple lead regions a1 located on the left side (first side) of the chip stack structure 20 onto the substrate 10 can overlap, and the projections of multiple lead regions a1 located on the right side (second side) of the chip stack structure 20 onto the substrate 10 can overlap.

[0055] Of course, in practice, considering process deviations, the projections of the multiple non-lead regions a2 can roughly overlap, and the projections of the multiple lead regions a1 can roughly overlap.

[0056] Furthermore, in the chip stacking structure 20 described above, since no electrical connection is required between any two adjacent chips in the overlapping area, i.e., no leads are needed, two adjacent stacked chips can be bonded together in the overlapping area using a die attach film 201 (DAF). For example, the first chip D1 and the bottommost second chip D2 can be bonded together using the die attach film 201, and two adjacent second chips can be bonded together in the overlapping area using the die attach film 201.

[0057] As illustrated, in some possible implementations, a metallic material may be added to the chip bonding film 201. Since metallic materials have a large thermal conductivity, the vertical thermal resistance of the chip stack structure 20 can be reduced, thereby improving the heat dissipation performance of the package structure.

[0058] This application does not limit the application scenarios of chip stacking package 01; in practice, it can be set as needed.

[0059] As illustrated, in some possible implementations, the chip stacking package 01 can be applied to fields such as SOC (system on chip), DRAM (dynamic random access memory), and UFS (universal flash storage).

[0060] Furthermore, this application does not restrict the types of the first chip D1 and the multiple second chips D2 in the chip stack package 01; in practice, they can be set as needed.

[0061] Indicatively, in some possible implementations, the chip stack package 01 can be applied to high bandwidth memory (HBM). In this case, the first chip D1 can be a logic chip, and the multiple second chips D2 can be DRAM (dynamic random access memory). The multiple DRAMs (D2) are connected to the logic chip (D1) via the substrate 10, thereby achieving high bandwidth interconnect communication.

[0062] Especially with the development of AI (artificial intelligence), high computing power places higher demands on memory bandwidth. Therefore, providing a high-performance, low-cost HBM package has great advantages in current AI application scenarios.

[0063] Furthermore, this application does not impose any restrictions on the arrangement of the substrate 10; in practice, it can be arranged as needed.

[0064] Setup Method 1

[0065] Schematic, referring to Figure 5, in some possible implementations, the substrate 10 may include a first redistribution layer RDL1 and a first bridge chip EB1 (embedded bridge) and a second bridge chip EB2 disposed on the first redistribution layer RDL1. The first bridge chip EB1 and the second bridge chip EB2 are encapsulated in a molding compound, and the molding compound has a plurality of molded vias TMV in the region between the first bridge chip EB1 and the second bridge chip EB2. The first bridge chip EB1, the second bridge chip EB2, and the plurality of molded vias TMV are all electrically connected to the first redistribution layer RDL1. The first redistribution layer RDL1 can expand the input / output (I / O) connection points on the back side of the substrate 10, thereby enabling better matching of external circuits.

[0066] Of course, in some other possible implementations, the first wiring layer RDL1 can also be omitted from the substrate 10.

[0067] Based on this, continuing to refer to Figure 5, the first chip D1 spans across the first bridge chip EB1 and the second bridge chip EB2, meaning that the first chip D1 overlaps with both the first bridge chip EB1 and the second bridge chip EB2, and the first chip D1 is electrically connected to both the first bridge chip EB1 and the second bridge chip EB2 in the overlapping area. Furthermore, the first chip D1 is connected to multiple molded vias (TMVs) located between the first bridge chip EB1 and the second bridge chip EB2, leading the first chip D1 to the back side of the substrate 10 through these TMVs. Additionally, the first bridge chip EB1 protrudes from the left edge of the chip stack structure 20 on its left side (first side) (i.e., the first bridge chip EB1 has a first protruding area on the left side of the chip stack structure 20), and the second bridge chip EB2 protrudes from the right edge of the chip stack structure 20 on its right side (second side) (i.e., the second bridge chip EB2 has a second protruding area on the right side of the chip stack structure 20). In this configuration, multiple lead regions a1 located on the left side of the chip stack structure 20 are connected to the protruding area (first protruding area) on the left side of the first bridge chip EB1 via bonding wires W. Multiple lead regions a1 located on the right side of the chip stack structure 20 are connected to the protruding area (second protruding area) on the right side of the second bridge chip EB2 via bonding wires W.

[0068] Based on this, in order to enable the multiple lead areas a1 located on the left side to interact with the electronic devices on the back side of the substrate 10, referring to Figure 5, in some possible implementations, multiple first through-silicon vias (TSVs) 1 can be provided in the protruding area on the left side of the first bridge chip EB1. The top of the first TSVs 1 is connected to the connection structure (pad, bump) on the surface of the substrate 10, and the bottom is connected to the first redistribution layer RDL1. In this case, multiple second chips D2 are connected to the first TSVs 1 vias 1 vias 2 vias 3 vias 4 vias 5 vias 6 and interconnected with the electronic devices on the back side of the substrate 10 through the first TSVs 1 vias 1 to meet the relevant functional requirements of the second chips, such as power supply requirements.

[0069] Similarly, to enable the multiple lead areas a1 on the right side to interact with the electronic devices on the back side of the substrate 10, referring to Figure 5, in some possible implementations, multiple second through-silicon vias (TSVs) 2 can be provided in the protruding area on the right side of the second bridge chip EB2. The top of each TSV 2 is connected to a connection structure (pad, bump) on the surface of the substrate 10, and the bottom is connected to the first redistribution layer RDL1. In this case, multiple second chips D2 are connected to the multiple TSVs 2 via bonding wires W, and interconnected with the electronic devices on the back side of the substrate 10 through the multiple TSVs 2 to meet the relevant functional requirements of the second chips, such as power supply requirements.

[0070] In other possible implementations, the substrate 10 may also include a second wiring layer located on the side of the first bridge chip EB1 and the second bridge chip EB2 away from the first wiring layer. In this case, multiple chips (D1, D2) in the chip stack structure 20 can be connected to the second wiring layer, and connected to the first bridge chip EB1, the second bridge chip EB2, and the first wiring layer RDL1 through the second wiring layer. This increases the design flexibility of the substrate.

[0071] Setting Method 2

[0072] Schematic, referring to Figure 6, in some possible implementations, the substrate 10 may include a first redistribution layer RDL1 and an interposer 101 disposed on the first redistribution layer RDL1. The interposer 101 has at least one through-silicon via (TSV) electrically connected to the first redistribution layer RDL1. Connection structures (pads, bumps) are provided on the surface of the interposer 101 (the side away from RDL1) to electrically connect to chips in the chip stack structure 20. The first redistribution layer RDL1 can expand the input / output (I / O) connection points on the back side of the substrate 10, thereby allowing for better matching with external circuitry.

[0073] Of course, in some possible implementations, the first overlay layer RDL1 can be omitted from the substrate 10.

[0074] As illustrated, the aforementioned interposer 101 may be a silicon interposer, that is, the interposer 101 includes a silicon substrate and a plurality of wiring layers disposed on the silicon substrate.

[0075] Referring again to Figure 6, the aforementioned interposer 101 protrudes from the left edge of the chip stack structure 20 on the left side (first side) (i.e., the interposer 101 has a first protruding area on the left side of the chip stack structure 20), and from the right edge of the chip stack structure 20 on the right side (second side) (i.e., the interposer 101 has a second protruding area on the right side of the chip stack structure 20). In this case, the first chip D1 is vertically connected to the interposer 101 in the overlapping area. Multiple lead regions a1 located on the left side of the chip stack structure 20 are electrically connected to the protruding area (first protruding area) of the interposer 101 on the left side via bonding wires W. Multiple lead regions a1 located on the right side of the chip stack structure 20 are connected to the protruding area (second protruding area) of the interposer 101 on the right side via bonding wires W. In this way, high-density interconnection between multiple second chips and the first chip can be achieved through the interposer 101.

[0076] To enable interconnection between multiple chips (D1, D2) in the chip stack structure 20 and electronic devices on the back side of the substrate 10, referring to FIG6, in some possible implementations, some or all of the chips in the chip stack structure 20 can be interconnected with electronic devices on the back side of the substrate 10 through multiple through-silicon vias (TSVs). For example, multiple lead regions a1 located on the left side can be electrically connected to TSVs provided in the protruding area (first protruding area) on the left side of the interposer 101 via bonding wires W, thereby achieving interconnection with electronic devices on the back side of the substrate 10. Multiple lead regions a1 located on the right side can be electrically connected to TSVs provided in the protruding area (second protruding area) on the right side of the interposer 101 via bonding wires W, thereby achieving interconnection with electronic devices on the back side of the substrate 10.

[0077] Of course, in some other possible implementations, the substrate 10 may also include a second wiring layer, located on the side of the interposer 101 away from the first wiring layer RDL1. In this case, multiple chips (D1, D2) in the chip stack structure 20 can be connected to the second wiring layer and then connected to the interposer 101 through the second wiring layer. This increases the design flexibility of the substrate.

[0078] The following description, in conjunction with the manufacturing method, further illustrates the chip stacking package provided in the embodiments of this application.

[0079] This application embodiment provides a method for fabricating a chip stacked package, as shown in FIG7. The method may include:

[0080] Step 01: Referring to Figure 8, fabricate substrate 10.

[0081] Schematic, in some possible implementations, referring to Figure 8, step 01 may include: providing a carrier board C1 (such as glass), and mounting a first bridge chip EB1 and a second bridge chip EB2 onto the carrier board C1 using a die-attach film (DAF). Then, the first bridge chip EB1 and the second bridge chip EB2 can be encapsulated, and multiple molded through-holes (TMVs) can be formed in the encapsulation layer. Afterwards, connection structures (pads, bumps) can be formed on the surface to achieve connections with other chips stacked above and with the first bridge chip EB1 and the second bridge chip EB2, thereby forming a substrate 10.

[0082] Of course, referring to Figure 8, according to actual needs, a first through-silicon via (TSV1) can be fabricated in the first bridge chip EB1, a second through-silicon via (TSV2) can be fabricated in the second bridge chip EB2, and a molded through-hole (TMV) can also be fabricated in the area between the first bridge chip EB1 and the second bridge chip EB2 to meet the interconnection between the chips subsequently stacked on the substrate 10 and the electronic devices on the back side of the substrate 10.

[0083] Step 02: Referring to Figure 9, the first chip D1 is mounted on the substrate 10 using a flip-chip (FC) method.

[0084] Schematic, in some possible implementations, referring to Figure 9, step 02 may include: mounting a first chip D1 (such as a logic chip) on the substrate 10 in a flip-chip (FC) manner, corresponding to the area between the first bridge chip EB1 and the second bridge chip EB2, and the first chip D1 is perpendicularly electrically connected to the overlapping area of ​​the first bridge chip EB1 and the second bridge chip EB2. Additionally, the first chip D1 is interconnected with electronic devices on the back side of the substrate 10 through a molded via TMV located between the first bridge chip EB1 and the second bridge chip EB2.

[0085] After the first chip D1 is mounted, it can be underfilled to protect it.

[0086] Step 03: Referring to Figure 10(a), a plurality of second chips D2 are stacked on a first chip D1 to form a chip stack structure 20 on the substrate 10. The active surfaces of the plurality of second chips D2 face away from the substrate 10, and the active surfaces of the plurality of second chips D2 each include a lead area a1 and a non-lead area a2. Any two adjacent second chips D1 include an upper chip and a lower chip. The upper chip is away from the substrate 10 relative to the lower chip. The lower chip overlaps with the upper chip in the non-lead area a2. The lead areas a1 of the upper chip and the lower chip are located on the first side and the second side of the chip stack structure 20, respectively, and are connected to the substrate 10 by bonding wires W. The first side and the second side are opposite sides (i.e., opposite sides) of the chip stack structure 20 along a direction parallel to the substrate 10.

[0087] Schematic, in some possible implementations, referring to Figure 10(a), step 03 may include: using a chip adhesive film (DAF), stacking multiple second chips D2 (such as HBM) sequentially on the back side of the first chip D1 to form a chip stack structure 20 on the substrate 10. The active surfaces (front sides) of the multiple second chips D2 face upwards, and each active surface includes a lead area a1 and a non-lead area a2 (see Figure 4). When stacking the multiple second chips D2 sequentially, the upper and lower second chips D2 are staggered left and right, with the lead areas a1 sequentially distributed on the left and right sides; the upper chip (i.e., the upper second chip) is mounted on the non-lead area a2 of the lower chip (i.e., the lower second chip), exposing the lead area a1 of the lower chip. The multiple lead areas a1 are alternately distributed from bottom to top on the left and right sides of the chip stack structure 20, and bonding wires W are led out from the multiple lead areas a1 to connect to the substrate 10.

[0088] It should be understood that by adjusting the non-lead regions a2 in multiple second chips D2 to overlap as much as possible, the area occupied by the chip stack structure 20 on the substrate 10 can be minimized, thereby reducing area overhead and making the product more suitable for miniaturization.

[0089] In some possible implementations, referring to Figure 10(a), after the mounting of multiple second chips D2 is completed in step 03, a dummy chip can be mounted on top of the multiple second chips D2 to form a chip stack structure 20.

[0090] After step 03 above, other subsequent processes can be carried out according to actual needs.

[0091] As illustrated in Figure 10(b), the chip stack structure 20 can be encapsulated using a molding process and then polished using a back-grinding process. Afterwards, the carrier substrate C1 on the back of the bridge chips (EB1, EB2) is debonded and polished using a back-grinding process to expose the through-silicon vias (TSV1, TSV2) in the first bridge chip EB1 and the second bridge chip EB2. Following this, processes such as ball mounting and dicing are performed to form a monolithic package structure.

[0092] Of course, referring to Figure 10(b), depending on actual needs, in some possible implementations, a first multi-level wiring layer RDL1 can be formed on the back side of the bridge chips (EB1, EB2), and this first multi-level wiring layer RDL1 is connected to the molded through-hole vias (TMVs) and through-silicon vias (TSV1, TSV2). This first multi-level wiring layer RDL1 can be a component of the substrate 10. Of course, in some possible implementations, the first multi-level wiring layer RDL1 may not be fabricated.

[0093] In some other possible implementations, the fabrication process of the substrate 10 may include: providing a carrier board, fabricating a first redistribution layer RDL1 on the carrier board, and then mounting a first bridge chip EB1 and a second bridge chip EB2 on the carrier board C1 using a flip-chip (FC) method; subsequently, the first bridge chip EB1 and the second bridge chip EB2 may be encapsulated, and a plurality of molded vias TMV may be fabricated in the encapsulation layer.

[0094] Additionally, referring to Figure 6, when the substrate 10 uses a silicon interposer:

[0095] In some possible implementations, the fabrication of substrate 10 may include: providing a carrier plate (such as glass), depositing a silicon interposer 101 on the carrier plate, and having through-silicon vias (TSVs) in the silicon interposer 101; and after the subsequent fabrication of the chip stack structure 20, debonding the carrier plate on the back side of the silicon interposer 101 to form a first multilevel wiring layer (RDL1) on the back side of the silicon interposer 101, and electrically connecting the first multilevel wiring layer (RDL1) to the through-silicon vias (TSVs) in the silicon interposer 101 to form substrate 10. Alternatively, the first multilevel wiring layer (RDL1) may not be provided; relevant details can be found above.

[0096] In other possible implementations, the fabrication of substrate 10 may include: providing a carrier plate (such as glass), fabricating a first redistribution layer RDL1 on the carrier plate, and then depositing a silicon interposer 101 on the first redistribution layer RDL1. The silicon interposer 101 contains through-silicon vias (TSVs), and the TSVs are electrically connected to the first redistribution layer RDL1. Related details can be found above.

[0097] It should be understood that, in the embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0098] For other related content in the above manufacturing method, please refer to the corresponding parts in the aforementioned corresponding structural embodiments, which will not be repeated here; for other settings in the aforementioned structural embodiments, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip stacking package, characterized in that, Includes a substrate and at least one chip stack structure disposed on the substrate; The chip stacking structure includes a first chip and a plurality of second chips stacked on the first chip; The active surface of the first chip faces the substrate and is connected to the substrate; The active surfaces of the plurality of second chips all face away from the substrate, and the active surfaces of the plurality of second chips all include lead areas and non-lead areas. Any two adjacent second chips in the plurality of second chips include an upper chip and a lower chip, wherein the upper chip is away from the substrate relative to the lower chip; the lower chip is disposed overlapping the upper chip in the non-lead area, and the lead area of ​​the upper chip and the lead area of ​​the lower chip are respectively located on the first side and the second side of the chip stack structure and connected to the substrate through bonding wires; the first side and the second side are two opposite sides of the chip stack structure along a direction parallel to the substrate.

2. The chip stacking package according to claim 1, characterized in that, The substrate includes a first bridge chip, a second bridge chip, and multiple molded through-holes (TMVs) distributed in a molding layer; The first bridge chip protrudes from the edge of the chip stack structure on the first side, and the second bridge chip protrudes from the edge of the chip stack structure on the second side; The plurality of lead regions located on the first side of the chip stack structure are connected to the first bridge chip via bonding wires, and the plurality of lead regions located on the second side of the chip stack structure are connected to the second bridge chip via bonding wires. The first chip has an overlapping area with both the first bridge chip and the second bridge chip, and is electrically connected to the first bridge chip and the second bridge chip in the overlapping area. The plurality of molded vias (TMVs) are located in the region between the first bridge chip and the second bridge chip, and the plurality of molded vias are electrically connected to the first chip.

3. The chip stacking package according to claim 2, characterized in that, The substrate further includes a first redistribution layer, which is located on the side of the molding layer away from the chip stack structure. The first bridge chip, the second bridge chip, and the plurality of molded vias (TMVs) are all electrically connected to the first redistribution layer.

4. The chip stacking package according to claim 3, characterized in that, The first bridge chip has at least one first through-silicon via (TSV), which is electrically connected to the first redistribution layer; the lead area located on the first side of the chip stack structure is connected to the first TSV via through a bonding wire. The second bridge chip has at least one second through-silicon via (TSV), which is electrically connected to the first redistribution layer; the lead area located on the second side of the chip stack structure is connected to the second TSV via through bonding wires.

5. The chip stacking package according to claim 1, characterized in that, The substrate includes an interposer layer, wherein at least one through-silicon via is provided in the interposer layer; The interposer layer has a first protruding area on a first side of the chip stack structure and a second protruding area on a second side of the chip stack structure; The plurality of lead regions located on the first side of the chip stack structure are electrically connected to the interposer in the first protruding area via the bonding wires; The plurality of lead regions located on the second side of the chip stack structure are electrically connected to the interposer in the second protruding region via the bonding wires; The first chip is electrically connected to the interposer in the overlapping region.

6. The chip stacking package according to claim 5, characterized in that, The substrate further includes a first redistribution layer, which is located on the side of the interposer layer away from the chip stack structure. The interposer layer is connected to the first redistribution layer through the through-silicon via (TSV).

7. The chip stacking package according to any one of claims 1-6, characterized in that, The non-lead areas of the plurality of second chips overlap on the substrate.

8. The chip stacking package according to any one of claims 1-7, characterized in that, The projections of the two second chips, spaced apart, on the substrate overlap.

9. The chip stacking package according to any one of claims 1-8, characterized in that, In the chip stacking structure, two adjacent chips are connected by a chip bonding film; the chip bonding film contains metal.

10. A method for fabricating a chip stacked package, characterized in that, include: Provide substrate; The first chip is mounted on the substrate using a flip-chip method; A plurality of second chips are stacked on the first chip to form a chip stack structure on the substrate; wherein the active surfaces of the plurality of second chips face away from the substrate, and the active surfaces of the plurality of second chips each include a lead area and a non-lead area; any two adjacent second chips include an upper chip and a lower chip, the upper chip being away from the substrate relative to the lower chip; the lower chip is stacked with the upper chip in the non-lead area, and the lead areas of the upper chip and the lower chip are respectively located on a first side and a second side of the chip stack structure and connected to the substrate by bonding wires; the first side and the second side are two opposite sides of the chip stack structure along a direction parallel to the substrate.

11. The method for fabricating a chip stacked package according to claim 10, characterized in that, The substrate provided includes: A first bridge chip and a second bridge chip are mounted on a carrier board, and the first bridge chip and the second bridge chip are encapsulated in a molding layer. Multiple molded vias are formed in the area of ​​the molding layer between the first bridge chip and the second bridge chip. The carrier plate is removed, and a first redistribution layer is formed on the side where the carrier plate was removed to form a substrate; wherein the first redistribution layer is electrically connected to the plurality of molded through holes.

12. The method for fabricating a chip stacked package according to claim 10, characterized in that, The substrate provided includes: Fabricate the first wiring layer on the carrier board; A first bridge chip and a second bridge chip are mounted on the first redistribution layer, and the first bridge chip and the second bridge chip are molded into a molding layer. A plurality of molded vias are formed in the region between the first bridge chip and the second bridge chip in the molding layer to form a substrate; wherein the plurality of molded vias are electrically connected to the first redistribution layer.

13. The method for fabricating a chip stacked package according to claim 10, characterized in that, The substrate provided includes: An interposer layer is disposed on a carrier board, and through-silicon vias are disposed in the interposer layer; The carrier board is removed, and a first redistribution layer is formed on the side where the carrier board was removed to form a substrate; wherein the interposer is electrically connected to the first redistribution layer through the through-silicon via.

14. An electronic device, characterized in that, It includes a circuit board and a chip stack package as described in any one of claims 1-9, wherein the circuit board is connected to the chip stack package.

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