Pulse-width modulation signal adjuster, voltage conversion circuit, and direct-current power supply

Abstract

Provided in the embodiments of the present application is a pulse-width modulation signal adjuster for controlling a voltage converter in a direct-current power supply. The direct-current power supply comprises a multi-phase voltage converter. The pulse-width modulation signal adjuster comprises: a current sensor, which is configured to be electrically connected to the voltage converter to generate a feedback signal corresponding to an output current of the voltage converter; a duty cycle regulation signal generation unit, which is configured to receive the feedback signal and a reference signal, so as to generate a duty cycle regulation signal on the basis of the feedback signal and the reference signal, wherein the reference signal corresponds to a balanced current at which output currents of respective phase voltage converters in the multi-phase voltage converter are balanced; and a pulse-width modulation signal adjustment unit, which is configured to receive an initial pulse-width modulation signal and the duty cycle regulation signal, so as to regulate the duty cycle of the initial pulse-width modulation signal on the basis of the duty cycle regulation signal, thereby obtaining a corrected pulse-width modulation signal for driving the voltage converter.

Description

Pulse width modulation signal conditioner, voltage conversion circuit and DC power supply Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a pulse width modulation signal conditioner for controlling a voltage converter, a voltage conversion circuit including the pulse width modulation signal conditioner, and a DC power supply. Background Technology

[0002] To support high performance and intelligence in electronic devices, these devices typically include highly integrated functional electronic components, often in the form of integrated circuit chips, such as GPUs (Graphics Processing Units). Some functional electronic components in these devices (e.g., processors for image processing or artificial intelligence calculations) require significant operating current, sometimes reaching hundreds or even thousands of amperes, and the current requirements of next-generation processors continue to increase. A single voltage converter typically cannot provide such a large current. To provide a sufficiently large drive current to the load, a feasible solution is to include multiphase voltage converters in the DC power supply supplying the load, and to connect the outputs of these voltage converters in parallel, thereby increasing the output current. Summary of the Invention

[0003] This application provides a pulse width modulation (PWM) signal adjuster for controlling a voltage converter in a DC power supply. The DC power supply includes a multiphase voltage converter. The PWM signal adjuster includes: a current sensor configured to be electrically connected to the voltage converter to generate a feedback signal corresponding to the output current of the voltage converter; a duty cycle adjustment signal generation unit configured to receive the feedback signal and a reference signal to generate a duty cycle adjustment signal based on the feedback signal and the reference signal, wherein the reference signal corresponds to an equalization current in which the output currents of each phase voltage converter in the multiphase voltage converter are balanced; and a PWM signal adjustment unit configured to receive an initial PWM signal and the duty cycle adjustment signal to adjust the duty cycle of the initial PWM signal according to the duty cycle adjustment signal, thereby obtaining a corrected PWM signal for driving the voltage converter.

[0004] According to some embodiments of this application, the feedback signal is a voltage signal corresponding to the output current of the voltage converter. The duty cycle adjustment signal generation unit includes: a comparator having a first input terminal, a second input terminal, and an output terminal electrically connected to the pulse width modulation signal adjustment unit; the first input terminal being electrically connected to the output terminal of the current sensor to receive the feedback signal; and the second input terminal being configured to receive the reference signal; and a buffer circuit having an input terminal electrically connected to the current sensor to receive the feedback signal and output a buffer signal from the output terminal of the buffer circuit; the output terminal of the buffer circuit being electrically connected to the second input terminal of the comparator. The comparator generates the duty cycle adjustment signal based on either the buffer signal or the reference signal and the feedback signal. The pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the feedback signal and the reference signal or the buffer signal.

[0005] According to some embodiments of this application, the buffer circuit includes an operational amplifier and a transistor. The output terminal of the operational amplifier is electrically connected to the control terminal of the transistor. The first input terminal of the operational amplifier is electrically connected to the first input terminal of the comparator. The second input terminal of the operational amplifier is electrically connected to the second input terminal of the comparator. The first terminal of the transistor is used to receive a power supply voltage, and the second terminal of the transistor is electrically connected to the second input terminal of the comparator.

[0006] According to some embodiments of this application, the buffer circuit includes a first diode, the anode of the first diode is electrically connected to the output terminal of the current sensor, and the cathode of the first diode is electrically connected to the second input terminal of the comparator. The duty cycle adjustment signal generation unit further includes a second diode, the anode and cathode of the second diode are electrically connected to the output terminal of the current sensor and the first input terminal of the comparator, respectively, wherein the parameters of the first diode and the second diode are the same.

[0007] According to some embodiments of this application, the feedback signal is a current signal corresponding to the output current of the voltage converter. The duty cycle adjustment signal generation unit includes: a comparator including a first input terminal, a second input terminal, and an output terminal electrically connected to the pulse width modulation signal adjustment unit, the second input terminal of the comparator being configured to receive the reference signal; a mirror current source including a reference current branch and a mirror current branch, the reference current branch being electrically connected to the output terminal of the current sensor and the first input terminal of the comparator, the mirror current branch being electrically connected to the output terminal of the current sensor and the second input terminal of the comparator; and a first resistor electrically connected between the first input terminal and the reference voltage terminal of the comparator to convert the feedback signal into an intermediate voltage signal, wherein the comparator generates the duty cycle adjustment signal based on the reference signal and the intermediate voltage signal, and the pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the reference signal and the intermediate voltage signal.

[0008] According to some embodiments of this application, the duty cycle adjustment signal generation unit further includes a connection resistor electrically connected between the second input terminal and the reference voltage terminal of the comparator.

[0009] According to some embodiments of this application, the corrected pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, wherein the duty cycle of the first pulse width modulation signal is greater than the duty cycle of the initial pulse width modulation signal, and the duty cycle of the second pulse width modulation signal is less than the duty cycle of the initial pulse width modulation signal. The pulse width modulation signal adjustment unit includes: a pulse width modulation signal delay circuit configured to be electrically connected to the output of the comparator and receive the initial pulse width modulation signal, to delay the rising or falling edge of the effective level of the initial pulse width modulation signal under the control of the duty cycle adjustment signal, thereby generating the first pulse width modulation signal or the second pulse width modulation signal; and a selector configured to be electrically connected to the output of the comparator, to select the first pulse width modulation signal or the second pulse width modulation signal as the corrected pulse width modulation signal according to the duty cycle adjustment signal.

[0010] According to some embodiments of this application, the pulse width modulation signal delay circuit includes an RC delay circuit, an AND gate, and an OR gate. The RC delay circuit includes a variable resistor and a capacitor connected in series. The output of the comparator is electrically connected to the variable resistor to adjust the resistance of the variable resistor under the control of the duty cycle adjustment signal. The RC delay circuit generates a delayed signal based on the initial pulse width modulation signal and the duty cycle adjustment signal. The AND gate is configured to receive the delayed signal and the initial pulse width modulation signal to generate the first pulse width modulation signal, and the OR gate is configured to receive the delayed signal and the initial pulse width modulation signal to generate the second pulse width modulation signal.

[0011] According to some embodiments of this application, the selector is configured to: select the first pulse width modulation signal as the correction pulse width modulation signal in response to the amplitude of the duty cycle adjustment signal being greater than a threshold; and select the second pulse width modulation signal as the correction pulse width modulation signal in response to the amplitude of the duty cycle adjustment signal being less than the threshold.

[0012] According to some embodiments of this application, the duty cycle adjustment signal generation unit further includes a filter electrically connected to the output terminal of the comparator, the filter filtering the output signal of the comparator to obtain the duty cycle adjustment signal.

[0013] Another embodiment of this application provides a voltage conversion circuit, the voltage conversion circuit including a voltage converter and a pulse width modulation signal adjuster according to any of the foregoing embodiments, the pulse width modulation signal adjuster being electrically connected to the voltage converter to drive the voltage converter based on the corrected pulse width modulation signal.

[0014] Another embodiment of this application provides a DC power supply comprising: N voltage conversion circuits according to the foregoing embodiments, wherein the output terminals of each voltage converter of the N voltage conversion circuits are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than or equal to 2.

[0015] Another embodiment of this application provides a DC power supply comprising: an N-phase voltage converter and N pulse width modulation signal adjusters according to any of the preceding embodiments, each pulse width modulation signal adjuster being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, the outputs of the N-phase voltage converter being connected in parallel to each other to an output node to provide a DC voltage at the output node, wherein N is an integer greater than or equal to 2, wherein the second inputs of the comparators of the N pulse width modulation signal adjusters are electrically connected to each other to a common node to receive the reference voltage, and the DC power supply further comprising a connection resistor electrically connected between the common node and the reference voltage terminal.

[0016] Another embodiment of this application provides a DC power supply comprising: an N-phase voltage converter and N pulse width modulation signal adjusters according to the foregoing embodiments, each pulse width modulation signal adjuster being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal; the output terminals of the N-phase voltage converter being connected in parallel to each other to an output node to provide a DC voltage at the output node, wherein N is an integer greater than or equal to 2; the second input terminals of the comparators of the N pulse width modulation signal adjusters being electrically connected to each other to a common node to receive the reference voltage; the DC power supply further comprising a connecting resistor electrically connected between the common node and the reference voltage terminal, wherein the resistance value of the first resistor is n times the resistance value of the connecting resistor.

[0017] According to some embodiments of this application, the reference signal corresponds to the average, maximum, or minimum value of each of the feedback signals generated by the N-phase voltage converter.

[0018] According to some embodiments of this application, the DC power supply further includes an initial pulse width modulation signal generator electrically connected to the output node and each pulse width modulation signal adjuster in the N-phase voltage converter, wherein the initial pulse width modulation signal generator is configured to provide a corresponding initial pulse width modulation signal to each pulse width modulation signal adjustment unit in each pulse width modulation signal adjuster according to the DC voltage at the output node.

[0019] The foregoing has outlined some embodiments of this application. Further different embodiments can be obtained based on combinations of these embodiments and combinations of features from different embodiments, and these different embodiments also fall within the protection scope of this application. These and other advantages of this application will become clear from the embodiments described below, and will be further illustrated with reference to the embodiments described below. Attached Figure Description

[0020] Embodiments of this application will now be described in more detail with reference to the accompanying drawings, wherein:

[0021] Figure 1 illustrates a topology of a DC power supply including a multiphase voltage converter;

[0022] Figure 2 illustrates the circuit schematic of a DC-DC voltage converter;

[0023] Figure 3 illustrates a structural block diagram of a pulse width modulation signal conditioner for a voltage converter VC according to an embodiment of this application;

[0024] Figure 4 illustrates a structural block diagram of a pulse width modulation signal conditioner for a voltage converter VC according to another embodiment of this application;

[0025] Figure 5 illustrates a structural block diagram of various pulse width modulation signal adjusters for a multiphase voltage converter according to another embodiment of this application;

[0026] Figure 6 illustrates a structural block diagram of various pulse width modulation signal adjusters for a multiphase voltage converter according to another embodiment of this application;

[0027] Figure 7 illustrates a structural block diagram of various pulse width modulation signal adjusters for a multiphase voltage converter according to another embodiment of this application;

[0028] Figure 8 illustrates a structural block diagram of a pulse width modulation signal conditioner for a voltage converter according to another embodiment of this application;

[0029] Figures 9 and 10 illustrate how the duty cycle of a PWM signal can be changed by delaying the falling or rising edge of the effective level of the PWM signal.

[0030] Figure 11 is an exemplary circuit diagram illustrating a pulse width modulation signal adjustment unit in a pulse width modulation signal adjuster according to another embodiment of this application;

[0031] Figure 12 illustrates the topology of a DC power supply provided according to another embodiment of this application. Detailed Implementation

[0032] The following description provides specific details of various embodiments of this application to enable those skilled in the art to fully understand and implement the various embodiments of this application. In some cases, this application does not show or describe in detail some structures or functions well known in the art to avoid such unnecessary descriptions that would obscure the description of the embodiments of this application. The technical solutions of this application can be embodied in many different forms and for many different purposes, and should not be limited to the embodiments set forth herein. These embodiments are provided to make the technical solutions of this application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0033] Here, some terms used in the embodiments of this application are first explained to facilitate understanding by those skilled in the art. The term "voltage converter" as used herein refers to a circuit that converts one DC voltage to another DC voltage, or converts AC voltage to DC voltage. Examples of voltage converters include rectifiers or DC-DC converters, and a voltage converter may simultaneously include a rectifier and a DC-DC converter electrically connected to the rectifier. The term "DC power supply" as used herein refers to a power supply that provides DC voltage to a load.

[0034] The inventors of this application recognized that, due to limitations in switching transistors and inductor current, the average current that a single voltage converter (e.g., a DC-DC buck converter) can provide is relatively limited, generally not exceeding 30A. However, practical applications often require hundreds or even thousands of amperes of current, especially for loads such as image processors (GPUs) used for artificial intelligence and image processing, whose current demands are constantly increasing. This necessitates the use of DC power supplies comprising multiphase voltage converters connected in parallel to power the loads. Figure 1 illustrates a topology of a DC power supply including multiphase voltage converters. This DC power supply includes N-phase voltage converters, each including a main switching circuit VC1, VC2…or VCn, inductors, capacitors, etc. A pulse width modulation (PWM) signal generator 100 provides corresponding pulse width modulation signals PWM1, PWM2…PWMn to each phase voltage converter in a time-division multiplexing manner. The DC output terminals of each voltage converter are connected to the output terminals of the DC power supply and generate an output voltage Vout. In order to achieve the balance of output current among the phase voltage converters, each voltage converter provides a corresponding feedback current signal I1, I2...In to the pulse width modulation signal generator 100 to adjust the duty cycle of the pulse width modulation signals PWM1, PWM2...PWMn, so that the output current of each phase voltage converter tends to be balanced.

[0035] Figure 2 illustrates an example of the schematic diagram of a voltage converter. As shown in Figure 2, the voltage converter includes an input capacitor C. IN The components are: first transistor K1, second transistor K2, output inductor L, and output capacitor C.OUT The voltage converter shown in Figure 2 is a classic DC-DC buck converter circuit. The first transistor K1 and the second transistor K2 are alternately turned on and off under the control of a PWM signal, converting the DC input voltage V... IN Converted to a lower DC output voltage V OUT When the DC power supply shown in Figure 1 uses the voltage converter shown in Figure 2, the main switching circuits VC1, VC2...VCn of each voltage converter in Figure 1 mainly include the first transistor K1 and the second transistor K2 shown in Figure 2.

[0036] This application provides a pulse width modulation (PWM) signal regulator for controlling a voltage converter in a DC power supply. The DC power supply includes a multiphase voltage converter, as shown in FIG3. The PWM signal regulator includes: a current sensor 310 configured to be electrically connected to the voltage converter VC to generate a feedback signal fi corresponding to the output current Iout of the voltage converter VC; a duty cycle adjustment signal generation unit 320 configured to receive the feedback signal fi and a reference signal Vr to generate a duty cycle adjustment signal di based on the feedback signal fi and the reference signal Vr, wherein the reference signal Vr corresponds to an equalization current in which the output currents of each phase voltage converter in the multiphase voltage converter are balanced; and a PWM signal adjustment unit 330 configured to receive an initial PWM signal PWMi and the duty cycle adjustment signal di to adjust the duty cycle of the initial PWM signal PWMi according to the duty cycle adjustment signal di, thereby obtaining a corrected PWM signal PWMo for driving the voltage converter. The current sensor 310 here can acquire the output current Iout of the voltage converter VC and generate a feedback signal fi. Depending on the type of current sensor, the feedback signal fi can be either a voltage signal or a current signal, but both correspond to the magnitude of the output current Iout. In some embodiments, the feedback signal fi is a voltage signal or a current signal proportional to the output current Iout. For example, the feedback signal fi can be 5mV / A, that is, when the output current Iout is 1A, the feedback signal fi is a voltage signal of 5mV; or, the feedback signal fi can be 5µA / A, that is, when the output current Iout is 1A, the feedback signal fi is a current signal of 5µA.

[0037] The duty cycle adjustment signal generation unit 320 can generate a duty cycle adjustment signal di based on the feedback signal fi output by the current sensor and the reference signal Vr. Based on this, the pulse width modulation signal adjustment unit 330 can increase or decrease the duty cycle of the initial pulse width modulation signal PWMi according to the duty cycle adjustment signal di, thereby obtaining a corrected pulse width modulation signal PWMo for driving the voltage converter VC. The pulse width modulation signal adjuster proposed in this embodiment can be applied to various voltage converters in the DC power supply shown in Figure 1. Specifically, the DC power supply may include an N-phase voltage converter and N pulse width modulation signal regulators for controlling the N-phase voltage converter. Each pulse width modulation signal regulator can readjust the duty cycle of the pulse width modulation signals PWM1, PWM2...PWMn provided to the corresponding voltage converter according to the feedback signal fi output by the current sensor and the reference signal Vr. This can achieve the balance of the output current of each voltage converter without requiring the voltage converter to provide the corresponding feedback current signal to the pulse width modulation signal generator 100. That is, the current transmission lines for transmitting the feedback current signals I1, I2...In shown in Figure 1 can be omitted. This will be further described below in conjunction with the specific application scenarios discussed in different examples.

[0038] In some embodiments, the feedback signal output by the current sensor is a voltage signal corresponding to the output current of the voltage converter, as shown in FIG4. The duty cycle adjustment signal generation unit 320 includes: a comparator CM, which includes a first input terminal a, a second input terminal b, and an output terminal c electrically connected to the pulse width modulation signal adjustment unit 330. The first input terminal a is electrically connected to the output terminal of the current sensor 310 to receive the feedback signal fi, and the second input terminal b is configured to receive the reference signal Vr; a buffer circuit B, the input terminal of which is electrically connected to the output terminal of the current sensor 310 to receive the feedback signal fi and output a buffer signal bi from the output terminal of the buffer circuit. The output terminal of the buffer circuit B is electrically connected to the second input terminal b of the comparator CM. The comparator CM generates a duty cycle adjustment signal di based on either the buffer signal bi or the reference signal Vr and the feedback signal fi. The pulse width modulation signal adjustment unit 330 adjusts the duty cycle of the initial pulse width modulation signal PWMi according to the duty cycle adjustment signal di to reduce the difference between the feedback signal fi and the reference signal Vr or the buffer signal bi. In some embodiments, the buffer signal bi can be a voltage signal slightly lower than the feedback signal fi. The comparator CM can generate a duty cycle adjustment signal di based on the buffer signal bi and the feedback signal fi. When the reference signal Vr exceeds the feedback signal fi, the buffer circuit can be in a disabled state. At this time, the potential of the second input terminal b of the comparator CM is determined by the reference signal Vr, and the comparator CM generates the duty cycle adjustment signal di based on the reference signal and the feedback signal fi.

[0039] Figure 5 illustrates a structural block diagram of a PWM signal regulator for controlling voltage converters VC1 and VC2 in a DC power supply according to an embodiment of this application, showing a specific example of the air-cycle adjustment signal generation unit. The buffer circuit includes an operational amplifier op and a transistor T. The output terminal of operational amplifier op is electrically connected to the control terminal of transistor T. The first input terminal of operational amplifier op is electrically connected to the first input terminal a of comparator CM, and the second input terminal of operational amplifier op is electrically connected to the second input terminal b of comparator CM. The first terminal of transistor T is used to receive the power supply voltage VDD, and the second terminal of transistor T is electrically connected to the second input terminal b of comparator CM. The control terminal of the transistor mentioned here refers to the gate of the transistor used to receive the control signal. The first and second terminals of the transistor refer to electrodes other than the gate, and the first and second terminals of the transistor may respectively include a source or a drain. In this example, transistor T is a P-channel metal-oxide-semiconductor field-effect transistor.

[0040] The following describes in detail the operation of the pulse width modulation signal regulator provided in this application embodiment applied to a DC power supply including a multiphase voltage converter, based on the example shown in Figure 5. As shown in Figure 5, the DC power supply may include multiphase voltage converters VC1…VCn and n pulse width modulation signal regulators for controlling the voltage converters VC1…VCn. Each pulse width modulation signal regulator receives a corresponding initial pulse width modulation signal PWMi1…PWMin. The output terminal of the buffer circuit in each pulse width modulation signal regulator (i.e., the second input terminal of the comparator) is connected to a common node N. The common node N is electrically connected to a reference voltage terminal through a connecting resistor Rc. When the voltage signal at the second input terminal b of the comparator CM in the pulse width modulation signal regulator of a certain phase voltage converter gradually increases and exceeds the feedback signal fi, the operational amplifier op will output a high-level signal, the transistor T will be in the off state, the buffer circuit will be in the ineffective state, and no buffer signal bi will be output. The voltage at the second input terminal b of comparator CM (i.e., the voltage at the common node N) will depend on the maximum value of the buffer signals bi output by the buffer circuits in the pulse width modulation signal regulators used for other phase voltage converters, which are still in normal operation. This maximum value also means that the output current of the corresponding voltage converter is larger than that of the other voltage converters, and has the maximum output current. That is, at this time, the aforementioned reference signal Vr is the buffer signal output by the buffer circuit in the pulse width modulation signal regulator corresponding to the voltage converter with the maximum output current; that is, the reference signal Vr corresponds to the maximum output current. The pulse width modulation signal regulators corresponding to the remaining voltage converters will increase the duty cycle of the initial PWM signal according to the reference signal and the corresponding feedback signal fi, thereby obtaining a correction PWM signal with a larger duty cycle, so that the output current of the remaining voltage converters gradually increases towards the maximum output current. Correspondingly, the feedback signal fi of the current sensor 510 of each phase voltage converter also increases towards the maximum value of the buffer signals bi, and approaches or equals the maximum value. When the voltage signal at the second input terminal b of the comparator CM in the pulse width modulation signal regulator of a certain phase voltage converter is less than the feedback signal fi, the operational amplifier op outputs a low-level signal, the transistor T is turned on, and the voltage signal at the second input terminal b of the comparator CM gradually increases until it equals the feedback signal fi. Each voltage converter's PWM signal regulator can adjust the duty cycle of its initial PWM signal PWMin according to the feedback signal fi and the reference signal Vr, making the feedback signal fi equal to the reference signal. This achieves consistency in the output current of each voltage converter (within the error range), realizing current balancing. The connecting resistor Rc in Figure 5 provides the minimum current required for the buffer circuit during operation.

[0041] Figure 6 illustrates a structural block diagram of a pulse width modulation signal adjuster for controlling voltage converters VC1 and VC2 in a DC power supply according to another embodiment of this application, showing a specific example of a duty cycle adjustment signal generation unit. As shown in Figure 6, the duty cycle adjustment signal generation unit includes a comparator CM and a buffer circuit. The buffer circuit includes a first diode D1, the anode of which is electrically connected to the output terminal of a current sensor 610, and the cathode of the anode of the first diode D1 is electrically connected to the second input terminal b of the comparator CM. The duty cycle adjustment signal generation unit also includes a second diode D2, the anode and cathode of which are electrically connected to the output terminal of the current sensor 610 and the first input terminal a of the comparator CM, respectively. The parameters of the first diode D1 and the second diode D2 are identical. The identical parameters of the first diode and the second diode mean that the temperature characteristics and PN junction voltage drop characteristics of these two diodes are highly consistent. Due to the unidirectional conductivity of diodes, when the feedback signal fi output by the current sensor 610 is less than the voltage at the second input terminal b of the comparator CM, the first diode D1 is in the off state. The voltage at the second input terminal b of the comparator CM (i.e., the voltage at the common node N) will depend on the maximum value of the voltages at the cathodes of the first diodes D1 that are still in the conducting state in the pulse width modulation signal regulators used for other phase voltage converters. This maximum value also means that the output current of the corresponding voltage converter is larger than the output current of other voltage converters, and it has the maximum output current. In other words, at this time, the aforementioned reference signal Vr is the voltage signal at the cathode of the first diode D1 in the pulse width modulation signal regulator corresponding to the voltage converter with the maximum output current, and the reference signal corresponds to the aforementioned maximum output current. The comparator CM in the pulse width modulation signal regulators corresponding to the remaining voltage converters will increase the duty cycle of the initial PWM signal according to the reference signal and the corresponding feedback signal fi, thereby obtaining a correction PWM signal with a larger duty cycle, so that the output current of the remaining voltage converters gradually increases towards the aforementioned maximum output current. Correspondingly, the feedback signal fi of the current sensor 610 of each phase voltage converter also increases towards the maximum value of the voltage at the cathode of each of the first diodes D1, and approaches or equals that maximum value. When the feedback signal fi output by the current sensor 610 is greater than the voltage at the second input terminal b of the comparator CM, the first diode is in the conducting state, and the voltage at the second input terminal b of the comparator CM will also be clamped at a voltage that is the difference between the feedback signal fi and the voltage drop of the first diode.The PWM signal regulator of each voltage converter can adjust the duty cycle of its initial PWM signal PWMin based on the voltage signal at the cathode of the second diode D2 (feedback signal fi minus the voltage drop of the second diode) and the reference signal Vr, so that the voltage at the first input terminal a of the comparator CM (feedback signal fi minus the voltage drop of the second diode D2) is equal to the reference signal Vr. This ensures that the output current of each voltage converter is consistent (within the error range), achieving current balancing. The connecting resistor Rc in Figure 6 provides the minimum required current when the first diode D1 is conducting.

[0042] In some embodiments, the feedback signal output by the current sensor is a current signal corresponding to the output current of the voltage converter. Figure 7 illustrates a structural block diagram of a pulse width modulation signal adjuster for controlling voltage converters VC1 and VC2 in a DC power supply according to another embodiment of this application, wherein a specific example of a duty cycle adjustment signal generation unit is illustrated. As shown in Figure 7, the duty cycle adjustment signal generation unit includes: a comparator CM, which includes a first input terminal a, a second input terminal b, and an output terminal electrically connected to the PWM signal adjustment unit 730, wherein the second input terminal b of the comparator CM is configured to receive a reference signal Vr; a mirror current source, which includes a reference current branch Im1 and a mirror current branch Im2, wherein the reference current branch Im1 is electrically connected to the output terminal of the current sensor 710 and the first input terminal a of the comparator CM, and the mirror current branch Im2 is electrically connected to the output terminal of the current sensor 710 and the second input terminal b of the comparator CM; and a first resistor R1, which is electrically connected between the first input terminal a of the comparator CM and the reference voltage terminal to convert the feedback signal into an intermediate voltage signal. The comparator CM generates a duty cycle adjustment signal based on the reference signal Vr and the intermediate voltage signal. The PWM signal adjustment unit 730 adjusts the duty cycle of the initial PWM signal PWMin according to the duty cycle adjustment signal to reduce the difference between the reference signal Vr and the intermediate voltage signal. In this embodiment, the mirror current source forms the same current signal in the reference current branch Im1 and the mirror current branch Im2 based on the feedback signal of the current sensor 710. The current signal on the reference current branch Im1 forms an intermediate voltage signal through the first resistor R1 and is provided to the first input terminal a of the comparator CM. The current signal on the mirror current branch Im2 flows to the common node N. The second input terminal b of the comparator CM receives the reference signal Vr at the common node N. When the PWM signal regulators of each phase voltage converter are connected to the common node N, the current in the mirror current branch Im2 of each PWM signal regulator is merged into the common node N. At this time, the reference signal Vr at the common node N is (Im21+Im22+……Im2n)*R0, where Im21, Im22, and Im2n are the currents in the mirrored current branches Im2 of the PWM signal regulators in the first-phase power converter, the second-phase voltage converter, and the Nth-phase voltage converter, respectively, and R0 is the resistance value of the connection resistor Rc between the common node N and the reference voltage terminal. Therefore, in this embodiment, the reference signal Vr at the common node N can provide a unified reference signal for the comparator CM of the PWM signal regulator in each phase voltage converter. Thus, the PWM signal adjustment unit 730 can adjust the duty cycle of the initial PWM signal to make the output current of each phase voltage converter tend to be consistent (within the error range). In some embodiments, the resistance value of the first resistor R1 is N times the resistance value R0 of the connection resistor Rc.In this scenario, the reference signal Vr is (Im21+Im22+……Im2n)*R1 / N, meaning that the reference signal Vr is the average value of the intermediate voltage signals in the PWM signal regulators of each phase voltage converter. Therefore, this reference signal Vr can correspond to the average value of the output current of each phase voltage converter. Thus, through this embodiment, the consistency of the output current of each voltage converter (within the error range) can also be achieved, realizing the purpose of current balancing.

[0043] In some embodiments, the duty cycle adjustment signal generation unit further includes a connection resistor electrically connected between the second input terminal and the reference voltage terminal of the comparator. For example, as shown in FIG5, FIG6 or FIG7, in some embodiments, the connection resistor Rc can be used as a component of the PWM signal regulator for one phase voltage converter, while being shared by the PWM signal regulators of the voltage converters of other phases.

[0044] This application does not impose specific limitations on the value of the reference signal Vr. The examples discussed above show that the reference signal Vr corresponds to the average or maximum value of the output current of each phase voltage converter. In other embodiments, the reference signal Vr may correspond to the minimum value of the output current of each phase voltage converter.

[0045] In some embodiments, the corrected PWM signal PWMo includes a first pulse width modulation signal and a second pulse width modulation signal, wherein the duty cycle of the first pulse width modulation signal is greater than the duty cycle of the initial PWM signal, and the duty cycle of the second pulse width modulation signal is less than the duty cycle of the initial PWM signal. As shown in FIG8, the PWM signal adjustment unit 830 includes: a pulse width modulation signal delay circuit DL, configured to be electrically connected to the output of a comparator CM and receive an initial PWM signal PWMi, to delay the rising or falling edge of the effective level of the initial PWM signal under the control of a duty cycle adjustment signal di, thereby generating the first pulse width modulation signal or the second pulse width modulation signal; and a selector SW, configured to be electrically connected to the output of the comparator CM, to select the first pulse width modulation signal or the second pulse width modulation signal as the corrected pulse width modulation signal PWMo according to the duty cycle adjustment signal di. The pulse width modulation signal delay circuit DL can delay the rising or falling edge of the effective level of the initial PWM signal under the control of the duty cycle adjustment signal di, thereby obtaining a corrected PWM signal PWMo with an increased or decreased duty cycle. Figures 9 and 10 illustrate exemplary schematic diagrams of a first pulse width modulation (PWM) signal PWMo1 and a second pulse width modulation (PWM) signal PWMo2 generated from an initial PWM signal PWMi, respectively. The effective level of the initial PWM signal is high. As shown in Figure 9, by delaying the falling edge of the effective level of the initial PWM signal, a first pulse width modulation (PWM) signal PWMo1 with a larger duty cycle can be obtained. As shown in Figure 10, by delaying the rising and falling edges of the effective level of the initial PWM signal, a second pulse width modulation (PWM) signal PWMo2 with a smaller duty cycle can be obtained. In the examples of Figures 9 and 10, the effective level of the initial PWM signal is high. In other embodiments, the effective level of the initial PWM signal can also be low.

[0046] Figure 11 shows an exemplary schematic diagram of the pulse width modulation (PWM) signal delay circuit DL and the selector SW. As shown in Figure 11, the PWM signal delay circuit includes an RC delay circuit, an AND gate A1, and an OR gate O1. The RC delay circuit includes a variable resistor Ra and a capacitor C1 connected in series. The output of the comparator CM is electrically connected to the variable resistor Ra to adjust its resistance under the control of a duty cycle adjustment signal. The RC delay circuit generates a delayed signal based on the initial PWM signal and the duty cycle adjustment signal. The AND gate A1 is configured to receive the delayed signal and the initial PWM signal to generate a first PWM signal, and the OR gate O1 is configured to receive the delayed signal and the initial PWM signal to generate a second PWM signal. The signal at the node between capacitor C1 and the variable resistor Ra in Figure 11 is the aforementioned delayed signal, which is provided to one input of both the AND gate A1 and the OR gate O1. The other input of both the AND gate A1 and the OR gate O1 receives the initial PWM signal PWMi. The selector SW may include a switching switch that can adjust the signal according to the duty cycle. In this embodiment, a second pulse width modulation signal PWMo2 with a reduced duty cycle can be output from AND gate A1, and a first pulse width modulation signal PWMo1 with a increased duty cycle can be output from OR gate O1.

[0047] In some embodiments, as shown in FIG11, the duty cycle adjustment signal generation unit further includes a filter F1 electrically connected to the output of the comparator CM. The filter F1 filters the output signal of the comparator CM to obtain the duty cycle adjustment signal. In some embodiments, the selector SW is configured to: select the first pulse width modulation signal as the correction pulse width modulation signal in response to the amplitude of the duty cycle adjustment signal being greater than a threshold; and select the second pulse width modulation signal as the correction pulse width modulation signal in response to the amplitude of the duty cycle adjustment signal being less than the threshold. The threshold can be set, for example, based on the average or median value of the output signal of the comparator CM. If the amplitude of the power supply voltage received by the comparator CM is VDD, then the amplitude of the output signal of the comparator CM typically does not exceed VDD, and the output signal of the comparator CM can be considered to vary between 0 and VDD, with its average or median value being VDD / 2. If the input signal at the non-inverting input terminal of the comparator (e.g., the second input terminal b) is greater than the input signal at the negative input terminal (e.g., the first input terminal a), meaning the reference signal Vr is greater than the feedback signal fi, it also means that the comparator's output signal (duty cycle adjustment signal) is greater than the threshold VDD / 2. In this case, the switch in the selector SW can connect the output of the PWM signal adjustment unit to the output of the AND gate O1, outputting a first pulse width modulation signal PWMo1 with a larger duty cycle. This increases the PWM signal used to drive the voltage converter, reducing the difference between the reference signal Vr and the feedback signal fi. When the comparator's output signal (duty cycle adjustment signal) is less than the threshold VDD / 2, meaning the feedback signal fi is too large, the selector SW can connect the output of the PWM signal adjustment unit to the output of the AND-OR gate, outputting a second pulse width modulation signal PWMo2 with a smaller duty cycle. This decreases the PWM signal used to drive the voltage converter, reducing the difference between the reference signal Vr and the feedback signal fi.

[0048] In the example of Figure 11, the degree to which the duty cycle of the first pulse width modulation signal PWMo1 or the second pulse width modulation signal PWMo2 increases or decreases relative to the duty cycle of the initial PWM signal PWMi depends on the signal delay of the RC delay circuit, that is, on the resistance value of the variable resistor Ra. The change in the resistance value of the variable resistor Ra can be controlled by the duty cycle adjustment signal output by the comparator CM. In some embodiments, the resistance value of the variable resistor Ra can be designed as K*|di-1 / 2*VDD|, where K is a coefficient, that is, the resistance value of the variable resistor Ra is proportional to the absolute value of the difference between the duty cycle adjustment signal and the aforementioned threshold. When the value of the duty cycle adjustment signal is equal to the aforementioned threshold, the RC delay circuit approximately does not generate an effective delay signal, and the duty cycle of the pulse width modulation signal output from the OR gate O1 or the AND gate A1 is approximately the same as the duty cycle of the initial PWM signal PWMi.

[0049] Figure 11 is merely an example illustrating the structure of the PWM signal adjustment unit and is not intended to limit the specific implementation of the PWM signal adjustment unit. The pulse width modulation signal delay circuit and selector in the PWM signal adjustment unit may have other implementations different from the above example, and this application does not impose any limitations on them.

[0050] The pulse width modulation (PWM) signal regulator proposed in this application can be applied to various voltage converters in a DC power supply. Based on this PWM signal regulator, each voltage converter can readjust the duty cycle of the PWM signal provided to it according to a reference signal and a feedback signal output from a current sensor. This allows for the equalization of the output current of each voltage converter without requiring each voltage converter to provide a corresponding feedback current signal to an external PWM signal generator. Furthermore, this avoids the need for multiple feedback current signal transmission lines between each voltage converter and the external PWM signal generator on the circuit board, simplifying the circuit board routing design of the DC power supply and saving circuit board space.

[0051] Another embodiment of this application provides a voltage conversion circuit including a voltage converter and a pulse width modulation (PWM) signal adjuster according to any of the foregoing embodiments, the PWM signal adjuster being electrically connected to the voltage converter to drive the voltage converter based on the corrected PWM signal.

[0052] Another embodiment of this application provides a DC power supply, which includes N voltage conversion circuits as described in the foregoing embodiments. The output terminals of each voltage converter in the N voltage conversion circuits are connected in parallel to an output node to provide a DC voltage at the output node, where N is an integer greater than or equal to 2.

[0053] Another embodiment of this application provides a DC power supply comprising: an N-phase voltage converter and N pulse width modulation signal regulators according to the foregoing embodiments, each pulse width modulation signal regulator being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal; the outputs of the N-phase voltage converters being connected in parallel to each other to an output node to provide a DC voltage at the output node, wherein N is an integer greater than or equal to 2; the second inputs of the comparators of each of the N pulse width modulation signal regulators being electrically connected to each other to a common node to receive the reference voltage; and the DC power supply further comprising a connection resistor electrically connected between the common node and the reference voltage terminal. Figure 12 illustrates an example of the topology of this DC power supply. The DC power supply comprises: an N-phase voltage converter and N pulse width modulation signal regulators J1, J2...Jn according to the foregoing embodiments, each pulse width modulation signal regulator being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal; each voltage converter comprising a corresponding main switching circuit VC1, VC2... or VCn and an inductor LC1, LC2... or LCn. The outputs of the N-phase voltage converters are connected in parallel to each other to an output node to provide a DC voltage Vout at the output node, where N is an integer greater than or equal to 2. The second inputs of the comparators of the N pulse width modulation signal conditioners are electrically connected to each other to a common node to receive the reference voltage. The DC power supply also includes a connection resistor Rc electrically connected between the common node and the reference voltage terminal.

[0054] In the case where the DC power supply includes a pulse width modulation signal adjuster as shown in Figure 7, that is, the duty cycle adjustment signal generation unit includes a comparator CM, a mirror current source, and a first resistor R1, the resistance value of the first resistor can be n times the resistance value of the connecting resistor Rc.

[0055] In some embodiments, as shown in FIG12, the DC power supply further includes an initial PWM signal generator 100a, which is electrically connected to the output node and each PWM signal regulator J1, J2...Jn in the N-phase voltage converter. The initial PWM signal regulator 100a is configured to provide a corresponding initial PWM signal to each PWM signal adjustment unit in each PWM signal regulator J1, J2...Jn according to the DC voltage at the output node.

[0056] Some embodiments of this application have been described above, but the scope of protection of this application is not limited to the specific forms of the embodiments set forth herein, and the scope of this application is defined by the appended claims. Although the terms first, second, etc., may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms, but only indicate a distinction in name. Furthermore, the term "electrical connection" as used herein includes "direct connection" or "indirect connection".

Claims

1. A pulse width modulation signal adjuster for controlling a voltage converter in a direct current power supply, the direct current power supply comprising a multiphase voltage converter, characterized by, The pulse width modulation signal adjuster includes: A current sensor is configured to be electrically connected to the voltage converter to generate a feedback signal corresponding to the output current of the voltage converter; A duty cycle adjustment signal generation unit is configured to receive the feedback signal and the reference signal to generate a duty cycle adjustment signal based on the feedback signal and the reference signal, wherein the reference signal corresponds to the equalization current in which the output currents of each phase voltage converter in the multiphase voltage converter reach a balance. A pulse width modulation signal adjustment unit is configured to receive an initial pulse width modulation signal and the duty cycle adjustment signal, and adjust the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to obtain a corrected pulse width modulation signal for driving the voltage converter.

2. The pulse width modulated signal adjuster of claim 1, wherein, The feedback signal is a voltage signal corresponding to the output current of the voltage converter, and the duty cycle adjustment signal generation unit includes: The comparator includes a first input terminal, a second input terminal, and an output terminal electrically connected to the pulse width modulation signal adjustment unit. The first input terminal is electrically connected to the output terminal of the current sensor to receive the feedback signal, and the second input terminal is configured to receive the reference signal. A buffer circuit, wherein the input terminal of the buffer circuit is electrically connected to the current sensor to receive the feedback signal and output a buffer signal from the output terminal of the buffer circuit, and the output terminal of the buffer circuit is electrically connected to the second input terminal of the comparator; The comparator generates the duty cycle adjustment signal based on one of the buffer signal or the reference signal and the feedback signal, and the pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the feedback signal and the reference signal or the buffer signal.

3. The pulse width modulated signal adjuster of claim 2, wherein, The buffer circuit includes an operational amplifier and a transistor. The output terminal of the operational amplifier is electrically connected to the control terminal of the transistor. The first input terminal of the operational amplifier is electrically connected to the first input terminal of the comparator. The second input terminal of the operational amplifier is electrically connected to the second input terminal of the comparator. The first terminal of the transistor is used to receive the power supply voltage, and the second terminal of the transistor is electrically connected to the second input terminal of the comparator.

4. The pulse width modulated signal adjuster of claim 2, wherein, The buffer circuit includes a first diode, the anode of which is electrically connected to the output terminal of the current sensor, and the cathode of which is electrically connected to the second input terminal of the comparator. The duty cycle adjustment signal generation unit further includes a second diode, the anode and cathode of which are electrically connected to the output terminal of the current sensor and the first input terminal of the comparator, respectively. The parameters of the first diode and the second diode are the same.

5. The pulse width modulated signal adjuster of claim 1, wherein, The feedback signal is a current signal corresponding to the output current of the voltage converter, and the duty cycle adjustment signal generation unit includes: A comparator includes a first input terminal, a second input terminal, and an output terminal electrically connected to the pulse width modulation signal adjustment unit, wherein the second input terminal of the comparator is configured to receive the reference signal; A mirror current source, comprising a reference current branch and a mirror current branch, wherein the reference current branch is electrically connected to the output terminal of the current sensor and the first input terminal of the comparator, and the mirror current branch is electrically connected to the output terminal of the current sensor and the second input terminal of the comparator; and A first resistor is electrically connected between the first input terminal and the reference voltage terminal of the comparator to convert the feedback signal into an intermediate voltage signal. The comparator generates the duty cycle adjustment signal based on the reference signal and the intermediate voltage signal, and the pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the reference signal and the intermediate voltage signal.

6. The pulse width modulated signal adjuster of any one of claims 2-5, wherein, The duty cycle adjustment signal generation unit further includes a connection resistor electrically connected between the second input terminal and the reference voltage terminal of the comparator.

7. The pulse width modulated signal adjuster of any of claims 2-5, wherein, The corrected pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal. The duty cycle of the first pulse width modulation signal is greater than the duty cycle of the initial pulse width modulation signal, and the duty cycle of the second pulse width modulation signal is less than the duty cycle of the initial pulse width modulation signal. The pulse width modulation signal adjustment unit includes: A pulse width modulation (PWM) signal delay circuit is configured to be electrically connected to the output of the comparator and receive the initial PWM signal, to delay the rising or falling edge of the effective level of the initial PWM signal under the control of the duty cycle adjustment signal, thereby generating the first PWM signal or the second PWM signal; and A selector is configured to be electrically connected to the output of the comparator to select either the first pulse width modulation signal or the second pulse width modulation signal as the correction pulse width modulation signal based on the duty cycle adjustment signal.

8. The pulse width modulated signal adjuster of claim 7, wherein, The pulse width modulation signal delay circuit includes an RC delay circuit, an AND gate, and an OR gate. The RC delay circuit includes a variable resistor and a capacitor connected in series. The output of the comparator is electrically connected to the variable resistor to adjust the resistance of the variable resistor under the control of the duty cycle adjustment signal. The RC delay circuit generates a delayed signal based on the initial pulse width modulation signal and the duty cycle adjustment signal. The AND gate is configured to receive the delayed signal and the initial pulse width modulation signal to generate the first pulse width modulation signal, and the OR gate is configured to receive the delayed signal and the initial pulse width modulation signal to generate the second pulse width modulation signal.

9. The pulse width modulated signal adjuster of claim 7, wherein, The selector is configured to: In response to the amplitude of the duty cycle adjustment signal being greater than a threshold, the first pulse width modulation signal is selected as the correction pulse width modulation signal; and In response to the fact that the amplitude of the duty cycle adjustment signal is less than the threshold, the second pulse width modulation signal is selected as the correction pulse width modulation signal.

10. The pulse width modulated signal adjuster of claim 2, wherein, The duty cycle adjustment signal generation unit further includes a filter electrically connected to the output terminal of the comparator, the filter filtering the output signal of the comparator to obtain the duty cycle adjustment signal.

11. A voltage conversion circuit, characterized by comprising: The voltage conversion circuit includes a voltage converter and a pulse width modulation signal adjuster according to any one of claims 1-10, the pulse width modulation signal adjuster being electrically connected to the voltage converter to drive the voltage converter based on the corrected pulse width modulation signal.

12. A direct current power supply, characterized by, The DC power supply includes: N voltage conversion circuits according to claim 11, wherein the output terminals of each voltage converter in the N voltage conversion circuits are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than or equal to 2.

13. A direct current power supply, characterized by, The DC power supply includes: An N-phase voltage converter and N pulse width modulation signal conditioners according to any one of claims 2-5 and 7-10, each pulse width modulation signal conditioner being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, the outputs of the N-phase voltage converters being connected in parallel to each other to an output node to provide a DC voltage at the output node, wherein N is an integer greater than or equal to 2. The second input terminals of each comparator in the N pulse width modulation signal adjusters are electrically connected to a common node to receive the reference voltage, and the DC power supply also includes a connection resistor electrically connected between the common node and the reference voltage terminal.

14. A direct current power supply, characterized by, The DC power supply includes: An N-phase voltage converter and N pulse width modulation signal conditioners according to claim 5, each pulse width modulation signal conditioner electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, the outputs of the N-phase voltage converters connected in parallel to each other at an output node to provide a DC voltage at the output node, where N is an integer greater than or equal to 2. The second input terminals of each comparator in the N pulse width modulation signal adjusters are electrically connected to a common node to receive the reference voltage. The DC power supply also includes a connection resistor electrically connected between the common node and the reference voltage terminal, wherein the resistance of the first resistor is n times the resistance of the connection resistor.

15. The direct current power supply of claim 13, wherein, The reference signal corresponds to the average, maximum, or minimum value of each of the feedback signals generated by the N-phase voltage converter.

16. The direct current power supply of any of claims 12-15, wherein, The DC power supply also includes an initial pulse width modulation (PWM) signal generator, which is electrically connected to the output node and each PWM signal adjuster in the N-phase voltage converter. The initial pulse width modulation signal generator is configured to provide a corresponding initial pulse width modulation signal to each pulse width modulation signal adjustment unit in each pulse width modulation signal adjuster according to the DC voltage at the output node.

Images