Display panel and display apparatus

Abstract

The present application discloses a display panel and a display apparatus. The display panel comprises: a plurality of pixel circuits arranged in an array. In each pixel circuit, a writing module is electrically connected to a gate of a driving transistor by means of a coupling module; a compensation module is electrically connected between the gate and a drain of the driving transistor; and a light-emitting element is electrically connected to the driving transistor. The display panel further comprises a first driving circuit and a second driving circuit; the first driving circuit comprises a plurality of first shift register units; each first shift register unit is electrically connected to compensation modules of a plurality of rows of pixel circuits in a same pixel group; the second driving circuit comprises a plurality of second shift register units; and each second shift register unit is electrically connected to writing modules of each row of pixel circuits. In the present application, each pixel circuit can independently perform a data writing process and a threshold compensation process, thereby being conducive to increasing the duration of threshold compensation, improving a charging rate in the threshold compensation process, achieving complete compensation for a threshold voltage, and improving the uniformity of display image quality.

Description

A display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202510361178.7, filed with the Chinese Patent Office on March 25, 2025, and Chinese Patent Application No. 202510510886.2, filed with the Chinese Patent Office on April 22, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] With the development of display technology, users have increasingly higher requirements for display quality. Summary of the Invention

[0004] This application provides a display panel and a display device to improve the uniformity of display image quality.

[0005] According to one aspect of this application, a display panel is provided, comprising: a plurality of pixel circuits arranged in an array;

[0006] The pixel circuit includes a driving transistor, a writing module, a coupling module, a compensation module, and a light-emitting element; the writing module is electrically connected to the gate of the driving transistor through the coupling module; the compensation module is electrically connected between the gate and drain of the driving transistor; and the light-emitting element is electrically connected to the driving transistor.

[0007] The pixel circuits described in multiple rows constitute a pixel group;

[0008] The display panel further includes a first driving circuit and a second driving circuit; the first driving circuit is used to sequentially control the compensation modules of multiple rows of pixel circuits in each pixel group to perform threshold compensation on the driving transistor; the second driving circuit is used to sequentially control the writing modules of each row of pixel circuits to write data signals to the gate of the driving transistor.

[0009] The first driving circuit includes a plurality of first shift register units; the first shift register units are electrically connected to the compensation modules of multiple rows of pixel circuits in the same pixel group;

[0010] The second driving circuit includes a plurality of second shift register units; each of the second shift register units is electrically connected to the write module of each row of pixel circuits.

[0011] According to another aspect of this application, a display panel is provided, comprising: a plurality of pixel circuits arranged in an array;

[0012] The pixel circuit includes a driving module, a compensation module, a data writing unit, a coupling module, and a light-emitting element;

[0013] The coupling module is electrically connected between the first node and the second node, and the control terminal of the driving module is electrically connected to the first node; the light-emitting element is electrically connected to the driving module.

[0014] The control terminal of the compensation module is electrically connected to the first shift register unit, and the compensation module is electrically connected between the control terminal of the drive module and the first terminal of the drive module.

[0015] The control terminal of the data writing unit is electrically connected to the second shift register unit, and the data writing unit is electrically connected between the data voltage terminal and the second node.

[0016] According to another aspect of this application, a display device is provided, comprising: the aforementioned display panel. Attached Figure Description

[0017] Figure 1 is a schematic diagram of the circuit structure of a pixel circuit in the related technology;

[0018] Figure 2 is a timing diagram of a pixel circuit in the related technology;

[0019] Figure 3 is a top view of a display panel provided in an embodiment of this application;

[0020] Figure 4 is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application;

[0021] Figure 5 is a timing diagram of a pixel group provided in an embodiment of this application;

[0022] Figure 6 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0023] Figure 7 is a top view of another display panel provided in an embodiment of this application;

[0024] Figure 8 is a timing diagram of another pixel group provided in an embodiment of this application;

[0025] Figure 9 is a timing diagram of another pixel group provided in an embodiment of this application;

[0026] Figure 10 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0027] Figure 11 is a top view of another display panel provided in an embodiment of this application;

[0028] Figure 12 is a timing diagram of another pixel group provided in an embodiment of this application;

[0029] Figure 13 is a partial top view of another display panel provided in an embodiment of this application;

[0030] Figure 14 is a top view of another display panel provided in an embodiment of this application;

[0031] Figure 15 is a timing diagram of another pixel group provided in an embodiment of this application;

[0032] Figure 16 is a partial top view of another display panel provided in an embodiment of this application;

[0033] Figure 17 is a timing diagram of another pixel group provided in an embodiment of this application;

[0034] Figure 18 is a partial top view of another display panel provided in an embodiment of this application;

[0035] Figure 19 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0036] Figure 20 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0037] Figure 21 is a top view of another display panel provided in an embodiment of this application;

[0038] Figure 22 is a timing diagram of another pixel group provided in an embodiment of this application;

[0039] Figure 23 is a partial top view of another display panel provided in an embodiment of this application;

[0040] Figure 24 is a top view of another display panel provided in an embodiment of this application;

[0041] Figure 25 is a timing diagram of another pixel group provided in an embodiment of this application;

[0042] Figure 26 is a partial top view of another display panel provided in an embodiment of this application;

[0043] Figure 27 is a timing diagram of another pixel group provided in an embodiment of this application;

[0044] Figure 28 is a partial top view of another display panel provided in an embodiment of this application;

[0045] Figure 29 is a timing diagram of another pixel group provided in an embodiment of this application;

[0046] Figure 30 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0047] Figure 31 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0048] Figure 32 is a top view of another display panel provided in an embodiment of this application;

[0049] Figure 33 is a top view of another display panel provided in an embodiment of this application;

[0050] Figure 34 is a timing diagram of another pixel group provided in an embodiment of this application;

[0051] Figure 35 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0052] Figure 36 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0053] Figure 37 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0054] Figure 38 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0055] Figure 39 is a timing diagram of another pixel group provided in an embodiment of this application;

[0056] Figure 40 is a timing diagram of another pixel group provided in an embodiment of this application;

[0057] Figure 41 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application;

[0058] Figure 42 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0059] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] Figure 1 is a schematic diagram of the circuit structure of a pixel circuit in the related art. Referring to Figure 1, the pixel circuit PX' includes a driving transistor M3', a light-emitting element LED', an initialization transistor M5', a compensation transistor M4', a writing transistor M2', a first light-emitting control transistor M1', a second light-emitting control transistor M6', a reset transistor M7', and a storage capacitor Cst.

[0061] The first terminal of the initialization transistor M5' receives the reset signal Vref', and the second terminal of the initialization transistor M5' is electrically connected to the gate of the driving transistor M3' at the first node N1'. The gate of the initialization transistor M5' receives the first scan signal Scan1'. The first terminal of the write transistor M2' receives the data signal Data', and the second terminal of the write transistor M2' is electrically connected to the first terminal of the driving transistor M3' at the second node N2'. The gate of the write transistor M2' receives the second scan signal Scan2'. The first terminal of the compensation transistor M4' is electrically connected to the second terminal of the driving transistor M3' at the third node N3', and the second terminal of the compensation transistor M4' is electrically connected to the gate of the driving transistor M3' at the first node N1'. The first terminal of the first light-emitting control transistor M1' receives the first power supply signal PVDD, and the second terminal of the first light-emitting control transistor M1' is electrically connected to the second node N2'. The first terminal of the second light-emitting control transistor M6' is electrically connected to the third node N3', and the second terminal of the second light-emitting control transistor M6' is electrically connected to the anode of the light-emitting element LED' at the fourth node N4'. The cathode of the light-emitting element LED' receives the second power supply signal PVEE. The gates of both the first light-emitting control transistor M1' and the second light-emitting control transistor M6' receive the light-emitting control signal Emit'. The first plate of the storage capacitor Cst receives the first power supply signal PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1'.

[0062] Figure 2 is a timing diagram of a pixel circuit in the related art. The driving timing of Figure 2 corresponds to that of the pixel circuit in Figure 1. Referring to Figures 1 and 2, the pixel circuit PX' includes an initialization phase t1', a compensation phase t2', a writing phase t3', and a light emission phase t4'. When all transistors in the pixel circuit PX' are P-type transistors, a low level is the enable level, and a high level is the disable level.

[0063] During the initialization phase t1', the first scan signal Scan1' jumps to the enable level, the initialization transistor M5' turns on, and the low-level reset signal Vref' is written to the first node N1' through the initialization transistor M5' to initialize the first node N1' and control the drive transistor M3' to turn on.

[0064] The compensation phase t2' and the write phase t3' overlap. During the compensation phase t2' and the write phase t3', the second scan signal Scan2' jumps to the enable level, and the write transistor M2' and the compensation transistor M4' are turned on. The data signal Data' can be transmitted to the first node N1' through the write transistor M2', the drive transistor M3', and the compensation transistor M4'. During this process, the potential of the first node N1' is continuously pulled up until the drive transistor M3' reaches the critical state of being turned off (Vgs of the drive transistor M3' = VN1' - VN2' = Vth). The data signal Data' stops being transmitted to the first node N1', and the compensated data signal Data' is written to the first node N1'. At this time, the potential of the first node N1' is VN1' = Vdata' + Vth.

[0065] During the light-emitting phase t4', the light-emitting control signal Emit' transitions to the enable level, turning on the first light-emitting control transistor M1' and the second light-emitting control transistor M6'. The potential of the second node N2', VN2', is equal to PVDD. The driving transistor M3's voltage, Vgs = VN1' - VN2' = Vdata' + Vth - PVDD < Vth, turns on the driving transistor M3', and the driving current Id' = B' × [Vgs - Vth] 2 =B'×[Vdata'-PVDD] 2 Where B' = (1 / 2) × μ × Cox × (W / L), μ is the electron mobility of the driving transistor M3', Cox is the channel capacitance per unit area in the driving transistor M3', and W / L is the channel width / length ratio of the driving transistor M3'. At this time, the magnitude of the driving current Id' is related to Vdata', but not to Vth.

[0066] However, with the development of high resolution and high refresh rate, the time when the second scan signal Scan2' is at the enable level will be continuously shortened. Taking a resolution of 2800×1260 as an example, at a resolution of 120Hz, the time 1H per line is greater than 2.8us and less than 3.0us, which is barely enough to fully compensate the threshold voltage Vth to the minimum critical time of driving transistor M3'. Taking a resolution of 2800×1260 as an example, at a resolution of 240Hz, the time 1H for each line is greater than 1.4us and less than 1.5us, which is far from sufficient to fully compensate the threshold voltage Vth to the minimum critical time of the driving transistor M3'. Before the driving transistor M3' reaches the critical state of being turned off, the second scan signal Scan2' jumps to the disabled level, causing the threshold voltage Vth of the driving transistor M3' to be unable to fully compensate to the first node N1'. The magnitude of the driving current Id' is affected by Vth. At the same time, the Vth of the driving transistor M3' will shift due to manufacturing process deviations, aging, or temperature changes, resulting in inconsistent driving currents output under the same data signal Data', which will seriously affect the uniformity of the display.

[0067] Moreover, even if the gates of the write transistor M2' and the compensation transistor M4' are configured to receive different scan signals, so that the write transistor M2' and the compensation transistor M4' are turned on in a time-sharing manner, the signal written to the first node N1' later will affect the signal written to the first node N1' earlier, affecting the drive current and thus affecting the uniformity of the display.

[0068] To address the aforementioned technical problems, this application provides a display panel comprising: a plurality of pixel circuits arranged in an array; each pixel circuit includes a driving transistor, a writing module, a coupling module, a compensation module, and a light-emitting element; the writing module is electrically connected to the gate of the driving transistor via the coupling module; the compensation module is electrically connected between the gate and drain of the driving transistor; the light-emitting element is electrically connected to the driving transistor; multiple rows of pixel circuits constitute a pixel group; the display panel further includes a first driving circuit and a second driving circuit; the first driving circuit is used to sequentially control the compensation modules of the multiple rows of pixel circuits in each pixel group to perform threshold compensation on the driving transistor; the second driving circuit is used to sequentially control the writing modules of each row of pixel circuits to write data signals to the gate of the driving transistor; the first driving circuit includes a plurality of first shift register units; the first shift register units are electrically connected to the compensation modules of the multiple rows of pixel circuits in the same pixel group; the second driving circuit includes a plurality of second shift register units; each second shift register unit is electrically connected to the writing module of each row of pixel circuits.

[0069] By adopting the above technical solution, and by setting the writing module to be electrically connected to the driving transistor through the coupling module, the pixel circuit can independently perform the data writing process and the threshold compensation process. The threshold compensation process is no longer affected by the data writing process, nor is it limited by the data writing duration. By setting the first shift register unit of the first driving circuit to be electrically connected to the compensation module of the multi-row pixel circuit in the same pixel group, the multi-row pixel circuit in the same pixel group can perform threshold compensation simultaneously. Thus, during the display time of one frame, the number of times the first driving circuit of the display panel controls the pixel circuit to perform threshold compensation can be different from the number of times the second driving circuit controls the pixel circuit to perform data writing. The duration of the pixel circuit performing threshold compensation is not limited by the frequency of data writing, which is beneficial to increasing the duration of threshold compensation and improving the charging rate during the threshold compensation process. Even under high resolution and high refresh rate conditions, while the pixel circuit achieves fast data writing, it can also achieve complete compensation of the threshold voltage, which is beneficial to improving the uniformity of display quality.

[0070] The above is the core idea of ​​this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0071] Figure 3 is a top view of a display panel according to an embodiment of this application, and Figure 4 is a circuit diagram of a pixel circuit according to an embodiment of this application. Referring to Figures 3 and 4, the display area AA of the display panel 01 includes multiple pixel circuits PX arranged in an array. Each pixel circuit PX includes a driving transistor M3, a writing module 11, a coupling module 12, a compensation module 13, and a light-emitting element LED. The writing module 11 is electrically connected to the gate of the driving transistor M3 at a first node N1 through the coupling module 12, and the writing module 11 and the coupling module 12 are electrically connected to a second node N2. The compensation module 13 is also electrically connected to the gate of the driving transistor M3 at the first node N1, and the compensation module 13 is also electrically connected to the drain of the driving transistor M3 at a third node N3. The light-emitting element LED is electrically connected to the driving transistor M3. Pixel circuits PX located in the same row constitute a pixel row PR, and multiple pixel rows PR can constitute a pixel group, that is, multiple rows of pixel circuits PX can constitute a pixel group.

[0072] The display panel 01 also includes a first driving circuit VSR1 and a second driving circuit VSR2. The first driving circuit VSR1 includes multiple first shift register units 21, each electrically connected to a compensation module 13 of a multi-row pixel circuit PX in the same pixel group. The second driving circuit VSR2 includes multiple second shift register units 22, each electrically connected to a write module 11 of a row pixel circuit PX. The first driving circuit VSR1 sequentially controls the compensation modules 13 of the multi-row pixel circuit PX in each pixel group to perform threshold compensation on the driving transistor M3. The second driving circuit VSR2 sequentially controls the write modules 11 of each row pixel circuit PX to write the data signal Data to the gate of the driving transistor M3.

[0073] Specifically, the first end of the writing module 11 can be electrically connected to the data voltage terminal of the display panel 01 via the data line Data_L, receiving the data signal Data from the data voltage terminal. When the writing module 11 is turned on, the data signal Data can be transmitted to the coupling module 12 via the writing module 11. The coupling module 12 can couple the data signal Data to the first node N1, writing the data signal Data to the gate of the driving transistor M3. The first end of the compensation module 13 can receive the signal from the third node N3. When the compensation module 13 is turned on, the signal from the third node N3 can be transmitted to the first node N1 via the compensation module 13, thereby compensating the threshold voltage Vth of the driving transistor M3 to the first node N1. Thus, when the pixel circuit PX performs data writing, the data signal Data can be superimposed with the signal of the first node N1 without affecting the threshold voltage Vth compensated by the first node N1. When the pixel circuit PX performs threshold compensation, it is not necessary to receive the data signal Data, nor is it limited by the on-time of the writing module 11. That is, when the writing module 11 is turned off, the pixel circuit PX can still perform threshold compensation.

[0074] Referring to Figure 4, the write modules 11 of pixel circuits PX located in the same row can be connected to the same write scan line SP_L and receive the same write scan signal SP; the write modules 11 of pixel circuits PX in different rows can be connected to different write scan lines SP_L and receive different write scan signals SP. A second shift register unit 22 is connected to a write scan line SP_L, providing the same write scan signal SP to the write modules 11 of a row of pixel circuits PX, and controlling the on and off states of the write modules 11 in that row; the write scan signals SP output by multiple second shift register units 22 can be passed sequentially, thereby sequentially controlling each row of pixel circuits PX to write the data signal Data to the gate of the driving transistor M3.

[0075] The compensation modules 13 of pixel circuits PX located in the same row can be connected to the same compensation scan line Scan3_L and receive the same compensation scan signal Scan3. The compensation modules 13 of pixel circuits PX in the same pixel group but different rows can be connected to different compensation scan lines Scan3_L, but can still receive the same compensation scan signal Scan3. The compensation modules 13 of pixel circuits PX in different pixel groups receive different compensation scan signals Scan3. A first shift register unit 21 can be connected to multiple compensation scan lines Scan3_L to provide the same compensation scan signal Scan3 to the compensation modules 13 of multiple rows of pixel circuits PX in the same pixel group, and control the conduction and cutoff of the compensation modules 13 in the pixel group. The compensation scan signals Scan3 output by multiple first shift register units 21 can be passed sequentially, thereby sequentially controlling the compensation modules 13 of multiple rows of pixel circuits PX in each pixel group to perform threshold compensation on the driving transistor M3.

[0076] In this context, the number of rows of pixel circuits PX in the pixel group can be an integer greater than or equal to 2. During the display time of one frame, the number and frequency of the compensation scan signal Scan3 output by the first driving circuit VSR1 are less than the number and frequency of the write scan signal SP output by the second driving circuit VSR2. The pulse width of the effective pulse of the compensation scan signal Scan3 can be greater than the pulse width of the effective pulse of the write scan signal SP, so that the duration of threshold compensation of pixel circuit PX is greater than the duration of data writing of pixel circuit PX.

[0077] In an optional implementation, when the resolution of the display panel 01 increases, the total number of rows of the pixel circuit PX increases. During the display time of one frame, the number and frequency of the write scan signal SP output by the second driving circuit VSR2 both increase, that is, the pulse width of the effective pulse of the write scan signal SP decreases, and the time for the pixel circuit PX to write data is shortened. By increasing the number of rows of the pixel circuit PX in the pixel group, the number and frequency of the compensation scan signal Scan3 output by the first driving circuit VSR1 remain unchanged or change little during the display time of one frame, so that the pulse width of the effective pulse of the write scan signal SP remains unchanged or changes little, thereby reducing the impact of high resolution on the threshold compensation time of the pixel circuit PX.

[0078] In another optional implementation, when the refresh rate of the display panel 01 is increased, the display time of one frame is shortened, the pulse width of the effective pulse of the write scan signal SP is reduced, and the time for the pixel circuit PX to write data is shortened. Alternatively, the number of rows of pixel circuit PX in the pixel group can be increased so that the pulse width of the effective pulse of the compensation scan signal Scan3 remains unchanged or changes little, thereby reducing the impact of the high refresh rate on the threshold compensation time of the pixel circuit PX, so that the threshold compensation time of the pixel circuit PX remains unchanged or changes little.

[0079] Furthermore, the display area AA of the display panel 01 can be provided with multiple first power lines PV1_L and multiple second power lines PV2_L. The display panel 01 can also include a first power terminal and a second power terminal. The first power terminal is used to provide a first power signal PV1 to the first power line PV1_L, and the first power line PV1_L can be electrically connected to the driving transistor M3 of the pixel circuit PX. The second power terminal is used to provide a second power signal PV2 to the second power line PV2_L, and the second power line PV2_L can be electrically connected to the light-emitting element LED.

[0080] It should be noted that the figure only illustrates, by way of example, that the driving transistor M3 is a P-type transistor, in which case the conduction condition of the driving transistor M3 is Vgs < Vth < 0; in other optional embodiments, the driving transistor M3 can also be an N-type transistor, in which case the conduction condition of the driving transistor M3 is Vgs > Vth > 0; the embodiments of this application do not specifically limit the channel type of the driving transistor M3. For ease of description, the embodiments of this application all use a P-type transistor as an example to illustrate the technical solutions of the embodiments of this application.

[0081] It should also be noted that the figure only shows, by way of example, that the plurality of first shift register units 21 of the first driving circuit VSR1 and the plurality of second shift register units 22 of the second driving circuit VSR2 are all located in the non-display areas NA on opposite sides of the display area AA. In other optional embodiments, the plurality of first shift register units 21 of the first driving circuit VSR1 and the plurality of second shift register units 22 of the second driving circuit VSR2 may be located in the non-display areas NA on the same side or different sides of the display area AA. Alternatively, at least some of the plurality of first shift register units 21 of the first driving circuit VSR1 and the plurality of second shift register units 22 of the second driving circuit VSR2 may also be located in the display area AA. The embodiments of this application do not specifically limit the position of the first shift register units 21 and the second shift register units 22.

[0082] The working principle of the pixel circuit provided in the embodiments of this application will be explained below with reference to timing.

[0083] For example, taking a pixel group comprising two pixel rows PR, where the enable levels of the write scan signal SP and the compensation scan signal Scan3 are both low, and the disable levels are both high, this will be explained as an example. Figure 5 is a timing diagram of a pixel group provided in an embodiment of this application. The driving timing of Figure 5 corresponds to the pixel circuit in Figure 4. It should be noted that the enable level referred to here is the potential that controls the conduction between the first and second terminals of each module, and the disable level is the potential that controls the cutoff or disconnection between the first and second terminals of each module.

[0084] Referring to Figures 3 to 5, the compensation module 13 of the 2×j-1 pixel row PR (2×j-1) and the 2×j pixel row PR (2×j) of the j-th pixel group can receive the j-th compensation scan signal Scan3(j) output by the j-th first shift register unit 21(j); the writing module 11 of the 2×j-1 pixel row PR (2×j-1) of the j-th pixel group can receive the 2×j-1 write scan signal SP (2×j-1) output by the 2×j-1 second shift register unit 22 (2×j-1); the writing module 11 of the 2×j pixel row PR (2×j) of the j-th pixel group can receive the 2×j write scan signal SP (2×j) output by the 2×j second shift register unit 22 (2×j).

[0085] During the enable period t01 of the j-th compensation scan signal Scan3(j), the compensation modules 13 of the 2×j-1 row PR and the 2×j row are both turned on, and the pixel circuits PX of the 2×j-1 row and the 2×j row pixel circuits PX both perform threshold compensation. During the enable period t02 of the 2×j-1 write scan signal SP(2×j-1), the write module 11 of the 2×j-1 row is turned on, and the pixel circuit PX of the 2×j-1 row performs data writing; during the enable period t03 of the 2×j write scan signal SP(2×j), the write module 11 of the 2×j row is turned on, and the pixel circuit PX of the 2×j row performs data writing.

[0086] Referring again to Figures 3 to 5, pixel circuits PX in the same column are connected to the same data line Data_L. Different row pixel circuits PX need to write different data signals Data. Therefore, the data writing time periods (t02) and (t03) of the 2×j-1 row pixel circuit PX do not overlap. However, the threshold compensation time periods of the 2×j-1 row pixel circuit PX and the 2×j row pixel circuit PX can overlap and be superimposed, thus extending both the threshold compensation time periods (e.g., t01). In this way, even with high resolution and high refresh rate, it can still be ensured that pixel circuits PX have sufficient time for threshold compensation to fully compensate the threshold voltage Vth of the driving transistor M3 to the gate of the driving transistor M3, preventing the driving current from being affected by Vth and thus affecting the display uniformity of the display panel 01.

[0087] It should be noted that the figure only shows an example of a pixel group including two pixel rows PR. In other embodiments, a pixel group may also include three or four or more pixel rows PR. This application embodiment does not specifically limit the number of pixel rows PR contained in a pixel group.

[0088] The display panel provided in this application embodiment, by setting the writing module to be electrically connected to the driving transistor through the coupling module, allows the pixel circuit to independently perform the data writing process and the threshold compensation process. The threshold compensation process is no longer affected by the data writing process, nor is it limited by the data writing duration. By setting the first shift register unit of the first driving circuit to be electrically connected to the compensation module of the multi-row pixel circuit of the same pixel group, the multi-row pixel circuit of the same pixel group can perform threshold compensation simultaneously. Thus, in the display time of one frame, the number of times the first driving circuit of the display panel controls the pixel circuit to perform threshold compensation can be different from the number of times the second driving circuit controls the pixel circuit to perform data writing. The duration of the pixel circuit performing threshold compensation is not limited by the frequency of data writing, which is beneficial to increasing the duration of threshold compensation and improving the charging rate during the threshold compensation process. Even under high resolution and high refresh rate conditions, while the pixel circuit achieves fast data writing, it can also achieve complete compensation of the threshold voltage, which is beneficial to improving the uniformity of display quality.

[0089] Optionally, referring to Figures 4 and 5, in the same pixel circuit PX, the time period during which the pixel circuit PX performs threshold compensation is located before the time period during which the pixel circuit PX performs data writing, and the two do not overlap.

[0090] Specifically, during the threshold compensation period of the pixel circuit PX, the compensation scan signal Scan3 switches to the enable level, and the compensation module 13 is turned on. The compensation module 13 can transmit the signal of the third node N3 to the first node N1, changing the signal of the first node N1. During the data writing period of the pixel circuit PX, the write scan signal SP switches to the enable level, and the write module 11 is turned on. The write module 11 can couple the data signal Data to the first node N1 and superimpose the data signal Data onto the first node N1. By setting the threshold compensation period of the pixel circuit PX to be before the data writing period of the pixel circuit PX, the threshold voltage of the driving transistor M3 can be compensated to the first node N1 first, and then the data signal Data can be superimposed to the first node N1 through the coupling module 12. This is beneficial for fully compensating the threshold voltage Vth to the first node N1 and for accurately writing the data signal Data to the first node N1. It avoids simultaneous threshold compensation and data writing, which would affect the accurate compensation of the threshold voltage Vth, and also avoids threshold compensation after data writing, which would affect the superimposed data signal Data on the first node N1, resulting in poor display effect.

[0091] Optionally, Figure 6 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application. Referring to Figures 3 and 6, the writing module 11 includes a writing transistor M2. The first terminal of the writing transistor M2 receives the data signal Data. The second terminal of the writing transistor M2 is electrically connected to the first terminal of the coupling module 12 at the second node N2. The gate of the writing transistor M2 can be electrically connected to the second shift register unit 22 through the writing scan line SP_L. The compensation module 13 includes a compensation transistor M4. The first terminal of the compensation transistor M4 is electrically connected to the drain of the driving transistor M3 at the third node N3. The second terminal of the compensation transistor M4 is electrically connected to the gate of the driving transistor M3 at the first node N1. The gate of the compensation transistor M4 can be electrically connected to the first shift register unit 21 through the compensation scan line Scan3_L.

[0092] For example, all transistors in the pixel circuit PX are P-type transistors, and the active layers of all transistors in the pixel circuit PX can be arranged on the same layer, reducing fabrication steps and lowering fabrication costs. Furthermore, the enable level of the gates of all transistors is low, and when the pulse width of the enable level is the same, multiplexing of the gate signals of different transistors is also possible. In an optional embodiment, at least some transistors in the pixel circuit PX can be dual-gate structures, which is beneficial for improving transistor stability and mobility.

[0093] It should be noted that in other optional embodiments, the write transistor M2 and / or the compensation transistor M4 can also be N-type transistors. When the write transistor M2 and / or the compensation transistor M4 are N-type transistors, the active layer of the write transistor M2 and / or the compensation transistor M4 can include a metal oxide material. When preparing the active layer of the write transistor M2 and / or the compensation transistor M4, there is no need to crystallize to form a crystal structure, which makes the defect density of the active layer smaller, and the carrier mobility of the active layer higher and the temperature sensitivity lower. This allows the write transistor M2 and / or the compensation transistor M4 to conduct quickly, improving the charging speed and charging rate under high resolution and high refresh rate conditions, thereby improving the display effect.

[0094] Optionally, the coupling module 12 includes a coupling capacitor C1, which is electrically connected between the first node N1 and the second node N2.

[0095] Specifically, the write transistor M2 is electrically connected to the gate of the drive transistor M3 via the coupling capacitor C1 at the first node N1. On the one hand, the fast charging and discharging characteristics of the coupling capacitor C1 can quickly transmit the changes in the data signal Data at the second terminal of the write transistor M2 to the gate of the drive transistor M3, reducing signal delay and improving the response speed of the pixel circuit PX. On the other hand, the coupling capacitor C1 can isolate the DC signal and superimpose the data signal Data onto the first node N1, avoiding level conflicts or signal overlays caused by direct connection, and ensuring the stable operation of the pixel circuit PX.

[0096] Optionally, Figure 7 is a top view of another display panel provided in an embodiment of this application. Referring to Figures 6 and 7, the pixel circuit PX further includes a light-emitting control module 14, which is electrically connected between the driving transistor M3 and the light-emitting element LED. The display panel 01 also includes a fifth driving circuit VSR5, which is used to sequentially turn on the light-emitting control modules 14 of the multiple rows of pixel circuits PX in each pixel group.

[0097] Specifically, the light-emitting control modules 14 of pixel circuits PX located in the same row can be connected to the same light-emitting control line EM_L and receive the same light-emitting control signal EM; the light-emitting control modules 14 of pixel circuits PX in the same pixel group but different rows can be connected to different light-emitting control lines EM_L, but can still receive the same light-emitting control signal EM; the light-emitting control modules 14 of pixel circuits PX in different pixel groups receive different light-emitting control signals EM. The fifth driving circuit VSR5 includes multiple fifth shift register units 25. Each fifth shift register unit 25 is connected to multiple light-emitting control lines EM_L, providing the same light-emitting control signal EM to the light-emitting control modules 14 of multiple rows of pixel circuits PX in the same pixel group, and controlling the conduction and cutoff of the light-emitting control modules 14 in that pixel group; the light-emitting control signals EM output by the multiple fifth shift register units 25 can be passed sequentially, thereby sequentially controlling the light-emitting elements LED in the multiple rows of pixel circuits PX in each pixel group to display light emission.

[0098] Within the display time of one frame, the number and frequency of the light emission control signals EM output by the fifth driving circuit VSR5 can be the same as the number and frequency of the compensation scan signals Scan3 output by the first driving circuit VSR1, and both are less than the number and frequency of the write scan signals SP output by the second driving circuit VSR2. This helps reduce the number of fifth shift register units 25 in the fifth driving circuit VSR5, simplifies the circuit layout, reduces space occupation, and thus achieves a thinner and lighter display panel 01 with a narrower bezel.

[0099] It is understood that the figure only shows, by way of example, the fifth shift register unit 25 of the fifth driving circuit VSR5 located in the non-display area NA on both sides of the display area AA. In other optional embodiments, the fifth shift register unit 25 may be located in the non-display area NA on the same side of the display area AA, or the fifth shift register unit 25 may also be located in the display area AA. The embodiments of this application do not specifically limit the position of the fifth shift register unit 25.

[0100] For example, the light-emitting control module 14 includes a light-emitting control transistor M6. The first terminal of the light-emitting control transistor M6 is electrically connected to the driving transistor M3 at the third node N3, and the second terminal of the light-emitting control transistor M6 is electrically connected to the light-emitting element LED at the fourth node N4. The gate of the light-emitting control transistor M6 can be electrically connected to the fifth shift register unit 25 through the light-emitting control line EM_L. The light-emitting control transistor M6 can be either a P-type transistor or an N-type transistor. This application embodiment does not limit this; for ease of description, this application embodiment uses the example of P-type transistors in the pixel circuit PX to illustrate the technical solution of this application embodiment.

[0101] Optionally, referring to Figures 6 and 7, the pixel circuit PX also includes a reset module 15, which is electrically connected to the light-emitting element LED. In the same pixel circuit PX, the reset module 15 and the compensation module 13 are connected to the same first shift register unit 21, or the reset module 15 and the write module 11 are connected to the same second shift register unit 22.

[0102] For example, the reset module 15 includes a second reset transistor M7; the first terminal of the second reset transistor M7 can be electrically connected to the second reference voltage terminal via the second reset line Vref2_L to receive the second reset signal Vref2; the second terminal of the second reset transistor M7 is electrically connected to the light-emitting element LED at the fourth node N4. The gate of the second reset transistor M7 can be electrically connected to the first shift register unit 21 via the compensation scan line Scan3_L, and the channel type of the second reset transistor M7 is the same as that of the compensation transistor M4. Alternatively, the gate of the second reset transistor M7 can also be electrically connected to the second shift register unit 22 via the write scan line SP_L, and the channel type of the second reset transistor M7 is the same as that of the write transistor M2. In the same pixel circuit PX, the gate of the second reset transistor M7 can be connected to the same compensation scan line Scan3_L as the gate of the compensation transistor M4, or connected to the same write scan line SP_L as the gate of the write transistor M2. The second reset transistor M7 can be turned on when the light-emitting control transistor M6 is turned off, and transmit the second reset signal Vref2 from the second reference voltage terminal to the fourth node N4 to reset the fourth node N4.

[0103] Continuing with the example of a pixel group comprising two pixel rows PR, where the enable levels of the write scan signal SP, the compensation scan signal Scan3, and the light emission control signal EM are all low, and the disable levels are all high, Figure 8 is a timing diagram of another pixel group provided in this application embodiment. The driving timing in Figure 8 corresponds to the pixel circuit in Figure 6. Referring to Figures 6 to 8, during the display time of one frame, the pixel circuit PX includes a compensation stage T1, a write stage T2, and a light emission stage T3. In the compensation stage T1, the compensation scan signal Scan3 is enabled, the write scan signal SP and the light emission control signal EM are both disabled, the compensation transistor M4 is turned on, and the write transistor M2 and the light emission control transistor M6 are turned off. Furthermore, when light is emitted during the display time of the previous frame, Vgs = VN1 - PV1 < Vth < 0. In the initial stage of the compensation stage T1 during the display time of the current frame, the driving transistor M3 can continue to be turned on, and the first power signal PV1 can be transmitted through the driving transistor M3 and the compensation transistor M4. The signal is transmitted to the first node N1, raising the potential of the first node N1 and continuously increasing the gate-source voltage Vgs of the driving transistor M3 until Vgs = VN1 - PV1 = Vth (Vth < 0). The driving transistor M3 is in the critical state of being turned on and off, and the current in the driving transistor M3 decreases to zero. The first power supply signal PV1 is no longer transmitted to the first node N1, and the potential of the first node N1 is stable. At this time, VN1 = VN3 = PV1 + Vth (Vth < 0), and the threshold voltage Vth is compensated to the first node N1.

[0104] During the write phase T2, the light emission control signal EM remains disabled, the compensation scan signal Scan3 switches to disabled, and the write scan signal SP switches to enabled. The write transistor M2 is turned on, while the compensation transistor M4 and the light emission control transistor M6 are turned off. The data signal Data can be written to the second node N2. The change in the second node N2, ΔVN2, can be coupled to the first node N1 through the coupling capacitor C1, such that ΔVN1 = ΔVN2, VN1 = PV1 + Vth + ΔVN1 = PV1 + Vth + ΔVN2 < PV1 + Vth (ΔVN2 < 0, Vth < 0), and Vgs = VN1 - PV1 = Vth + ΔVN1 = Vth + ΔVN2 < Vth < 0. The driving transistor M3 is fully turned on.

[0105] During the light-emitting phase T3, the compensation scan signal Scan3 remains disabled, the write scan signal SP switches to disabled, the light-emitting control signal EM switches to enabled, the light-emitting control transistor M6 is turned on, and the write transistor M2 and the compensation transistor M4 are turned off. The driving transistor M3 generates a driving current Id based on its gate electrical signal PV1+Vth+ΔVN2 and the first power supply signal PV1. The driving current Id = B × (Vgs - Vth). 2=B×△VN1 2 =B×△VN2 2 The light-emitting element (LED) can display the corresponding brightness according to the driving current Id. The display grayscale of the pixel circuit PX can be controlled by controlling the brightness and light-emitting duration of the LED. Wherein, B = (1 / 2) × μ × Cox × (W / L), μ is the electron mobility of the driving transistor M3, Cox is the channel capacitance per unit area of ​​the driving transistor M3, and W / L is the channel width-to-length ratio of the driving transistor M3.

[0106] Among them, △VN2 is only related to the data signal Data written in the writing stage T2 and the potential of the second node N2 before the writing stage T2, and is not related to the threshold voltage Vth of the driving transistor M3. The device difference of the driving transistor M3 will not affect the magnitude of the driving current Id, nor will it affect the display uniformity.

[0107] In an optional implementation, the potential of the second node N2 before the write phase T2 can be the data signal Data written during the display time of the previous frame, or it can be the data signal Data written by the pixel circuit PX in the same column and the previous row, as shown in Figure 9. During the display time of a frame, before the write phase T2, the write scan signal SP can also switch to the enable level. When the pixel circuit PX in the same column and the previous row (i-2 rows) writes the data signal Data, the pixel circuit PX in the same column and the current row (i row) can write the same data signal Data, which serves as the potential of the second node N2 before the write phase T2. However, the potential of the second node N2 before the write phase T2 is not limited to this.

[0108] Optionally, Figure 10 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application, and Figure 11 is a top view schematic diagram of another display panel provided in an embodiment of this application. Referring to Figures 10 and 11, the writing module 11 further includes a first reset transistor M1. The first terminal of the first reset transistor M1 receives a first reset signal Vref3, and the second terminal of the first reset transistor M1 is electrically connected to the second node N2. The display panel 01 also includes a third driving circuit VSR3. The third driving circuit VSR3 includes a plurality of third shift register units 23. The third shift register units 23 are electrically connected to the gate of the first reset transistor M1. The third driving circuit VSR3 is used to sequentially control the first reset transistor M1 of each row pixel circuit PX to reset the second node N2. In the same pixel circuit PX, the gate of the second reset transistor M7 of the reset module 15 can also be connected to the same third shift register unit 23 as the gate of the first reset transistor M1 of the writing module 11.

[0109] For example, the first terminal of the first reset transistor M1 can be electrically connected to the first reference voltage terminal via the first reset line Vref3_L to receive the first reset signal Vref3; the gate of the first reset transistor M1 can be electrically connected to the third shift register unit 23 via the reset scan line Scan2_L to receive the reset scan signal Scan2. In an optional embodiment, the first reference voltage terminal can be multiplexed with the second reference voltage terminal, and the first reset line Vref3_L can be multiplexed with the second reset line Vref2_L.

[0110] During the display time of one frame, the first reset transistor M1 can be turned on before the write transistor M2 is turned on, resetting the second node N2 and clearing the residual electrical signal of the second node N2 from the display time of the previous frame. Thus, after the pixel circuit PX writes the data signal Data, the change in the second node N2, ΔVN2 = Data - Vref3, is such that when the pixel circuit PX emits light for display, the driving current Id = B × (Vgs - Vth). 2 =B×△VN1 2 =B×△VN2 2 =B×(Data-Vref3) 2 , B=(1 / 2)×μ×Cox×(W / L).

[0111] On the one hand, the potential of the second node N2 before the writing stage T2 of all pixel circuits PX can be uniformly set to Vref3, which is beneficial to simplifying the control of the driving current and also beneficial to the uniformity of the pixel circuits PX in the display panel 01, thereby improving the display uniformity of the display panel 01. On the other hand, the first reset signal Vref3 can be set as a positive electrical signal, and the data signal Data can be an electrical signal with a small absolute value, so that the data signal Data on the data line Data_L changes near 0V, which is beneficial to reduce power consumption, increase charging rate, and achieve high resolution and high refresh rate.

[0112] Based on the above embodiments, in the same pixel circuit PX, the time period during which the pixel circuit PX resets the second node N2 overlaps with the time period during which the pixel circuit PX performs threshold compensation.

[0113] For example, the illustration continues with a pixel group comprising two pixel rows PR, where the enable levels are both low and the disable levels are both high. Figure 12 is a timing diagram of another pixel group provided in an embodiment of this application, and the driving timing of Figure 12 corresponds to the pixel circuit in Figure 10. Referring to Figures 10 to 12, the gate of the first reset transistor M1 in the 2×j-1th row can receive the 2×j-1th reset scan signal Scan2 (2×j-1) output by the 2×j-1th third shift register unit 23 (2×j-1); the gate of the first reset transistor M1 in the 2×jth row can receive the 2×jth reset scan signal Scan2 (2×j) output by the 2×jth third shift register unit 23 (2×j).

[0114] During the enable period t04 of the 2×j-1th reset scan signal Scan2 (2×j-1), the first reset transistor M1 of the 2×j-1th row is turned on, and the potential of the second node N2 of the pixel circuit PX in the 2×j-1th row is reset to Vref3; simultaneously, the compensation transistor M4 of the 2×j-1th row is also turned on, and the potential of the second node N2 of the pixel circuit PX in the 2×j-1th row can be compensated to PV1+Vth. During the enable period t05 of the 2×jth reset scan signal Scan2 (2×j), the first reset transistor M1 of the 2×jth row is turned on, and the potential of the second node N2 of the pixel circuit PX in the 2×jth row is reset to Vref3; simultaneously, the compensation transistor M4 of the 2×jth row is also turned on, and the potential of the second node N2 of the pixel circuit PX in the 2×jth row can be compensated to PV1+Vth.

[0115] In this way, the time period for resetting the second node N2 overlaps with the time period for compensating the first node N1, ensuring that the potential of the first node N1 after threshold compensation is not affected by the potential change of the second node N2, and ensuring that the potential of the second node N2 after reset is not affected by the potential change of the first node N1, which is beneficial to the accurate compensation of the potential of the first node N1 and the accurate reset of the potential of the second node N2.

[0116] In an optional embodiment, each third shift register unit 23 is electrically connected to the gate of the first reset transistor M1 of each row pixel circuit PX; the third shift register unit 23 reuses the second shift register unit 22, and the gate of the first reset transistor M1 of the i-th row pixel circuit PX and the gate of the write transistor M2 of the ie-th row pixel circuit PX are connected to the same second shift register unit 22; wherein i and e are both integers, i > e ≥ 2.

[0117] For example, the illustration continues with a pixel group consisting of two pixel rows PR, where the enable level is low and the disable level is high. Figure 13 is a partial top view of another display panel provided in an embodiment of this application. Referring to Figures 10, 12 and 13, the gate of the first reset transistor M1 in the 2×j-1 row and the gate of the write transistor M2 in the 2×j-3 row can both be electrically connected to the 2×j-3 second shift register unit 22 (2×j-3). The gate of the first reset transistor M1 in the 2×j-1 row can receive the 2×j-3 write scan signal SP (2×j-3) output by the 2×j-3 second shift register unit 22 (2×j-3) as a reset scan signal Scan2 (2×j-1). The gates of the first reset transistor M1 in row 2×j and the write transistor M2 in row 2×j-2 can both be electrically connected to the second shift register unit 22 (2×j-2). The gate of the first reset transistor M1 in row 2×j can receive the second write scan signal SP (2×j-2) output by the second shift register unit 22 (2×j-2) as the reset scan signal Scan2 (2×j). In this way, by multiplexing the shift register units and the signal, the number of driving circuits can be reduced, which is beneficial to achieving a narrow bezel on the display panel 01, and also facilitates circuit layout and simplifies the layout difficulty.

[0118] In another optional embodiment, FIG14 is a top view of another display panel provided in the embodiments of this application. Referring to FIG10 and FIG14, the third shift register unit 23 is electrically connected to the gate of the first reset transistor M1 of the multi-row pixel circuit PX in the same pixel group.

[0119] Specifically, the gates of the first reset transistor M1 in row 2×j-1 and row 2×j can receive the j-th reset scan signal Scan2(j) output by the j-th third shift register unit 23(j). During the display time of one frame, the number and frequency of the reset scan signal Scan2 output by the third driving circuit VSR3 can be the same as the number and frequency of the compensation scan signal Scan3 output by the first driving circuit VSR1, both being less than the number and frequency of the write scan signal SP output by the second driving circuit VSR2. This helps reduce the number of third shift register units 23 in the third driving circuit VSR3, simplifies the circuit layout, reduces space occupation, and thus achieves a thinner and lighter display panel 01 with a narrower bezel.

[0120] Based on the above embodiments, the third shift register unit 23 can reuse the second shift register unit 22; the gate of the first reset transistor M1 of the pixel circuit PX in the j-th pixel group and the gate of the write transistor M2 of the (j-1)×kp row pixel circuit PX are connected to the same second shift register unit 22; where j, k, and p are all integers, j>1, k is the row number of the pixel circuit in the pixel group, and p≥0.

[0121] For example, the following description continues with a pixel group consisting of two pixel rows PR, where the enable level is low and the disable level is high. Figure 15 is a timing diagram of another pixel group provided in an embodiment of this application. The driving timing of Figure 15 corresponds to the pixel circuit in Figure 10. Figure 16 is a partial top view of another display panel provided in an embodiment of this application. Referring to Figures 10, 15, and 16, the gate of the first reset transistor M1 in the 2×j-1 row, the gate of the first reset transistor M1 in the 2×j row, and the gate of the write transistor M2 in the 2×j-2 row can all be electrically connected to the 2×j-2 second shift register units 22 (2×j-2). The gate of the first reset transistor M1 in the 2×j-1 row and the gate of the first reset transistor M1 in the 2×j row can receive the 2×j-2 write scan signal SP (2×j-2) output by the 2×j-2 second shift register units 22 (2×j-2) as a reset scan signal Scan2(j).

[0122] In other optional embodiments, the gate of the first reset transistor M1 in the 2×j-1 row and the gate of the first reset transistor M1 in the 2×j row can also be electrically connected to the second shift register unit 22 (2×j-3) or 22 (2×j-4) in the 2×j-3 or 2×j-4 row, and receive the write scan signal SP (2×j-3) or SP (2×j-4) as the reset scan signal Scan2(j), so that in the display time of a frame, the time period of the pixel circuit PX resetting the second node N2 overlaps with the time period of the pixel circuit PX performing threshold compensation.

[0123] Thus, by multiplexing shift register units and signals, the number of driving circuits can be reduced, which is beneficial for achieving a narrow bezel on the display panel 01 and also facilitates circuit layout, simplifying the layout difficulty. At the same time, in the same pixel circuit PX, the compensation scan signal Scan3 and the reset scan signal Scan2, which have overlapping enable level periods, are connected to different shift register units, which helps to reduce the load on the compensation scan line Scan3_L, reduce the signal delay of the compensation scan signal Scan3, and increase the charging time of the threshold compensation stage. This allows the pixel circuit PX to fully compensate the threshold voltage Vth of the driving transistor M3 to the first node N1, improving the display uniformity of the display panel 01.

[0124] Based on the above embodiments, the third shift register unit 23 can also reuse the first shift register unit 21; in the same pixel circuit PX, the gate of the first reset transistor M1 and the gate of the compensation transistor M4 are connected to the same first shift register unit 21.

[0125] For example, the following description continues with a pixel group consisting of two pixel rows PR, where the enable level is low and the disable level is high. Figure 17 is a timing diagram of another pixel group provided in an embodiment of this application. The driving timing of Figure 17 corresponds to the pixel circuit in Figure 10. Figure 18 is a partial top view of another display panel provided in an embodiment of this application. Referring to Figures 10, 17 and 18, the gates of the first reset transistor M1 in the 2×j-1 row and the first reset transistor M1 in the 2×j row can both be electrically connected to the j-th first shift register unit 21(j). The gates of the first reset transistor M1 in the 2×j-1 row and the first reset transistor M1 in the 2×j row can receive the j-th compensation scan signal Scan3(j) output by the j-th first shift register unit 21(j) as the reset scan signal Scan2(j). The gates of the first reset transistor M1 and the compensation transistor M4, which are located in the same row, can be connected to the same compensation scan line Scan3_L, which helps to reduce the number of bridging signal lines, simplify the circuit layout, and reduce the design difficulty.

[0126] Optionally, Figure 19 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application, and Figure 20 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application. Referring to Figures 19 and 20, the pixel circuit PX further includes a storage module 16, which includes a storage capacitor C2. The first plate of the storage capacitor C2 is electrically connected to the first power supply terminal, and the second plate of the storage capacitor C2 is electrically connected to the first plate of the coupling capacitor C1 at the second node N2, or the second plate of the storage capacitor C2 is electrically connected to the second plate of the coupling capacitor C1 at the first node N1.

[0127] For example, referring to Figure 19, when the second plate of storage capacitor C2 and the first plate of coupling capacitor C1 are electrically connected to the second node N2, storage capacitor C2 can store the potential of the second node N2. During the data writing period of pixel circuit PX, the potential of the second node N2 changes, and storage capacitor C2 can store the changed potential of the second node N2 without affecting the coupling of the potential change ΔVN2 of the second node N2 to the first node N1, where the change in the first node N1 is ΔVN1 = ΔVN2. During the period when pixel circuit PX drives the light-emitting element LED to display light, storage capacitor C2 can maintain the potential stability of the second node N2, thereby maintaining the stability of the first node N1, so that pixel circuit PX provides a stable driving current to the light-emitting element LED, where driving current Id = B × ΔVN1. 2 =B×△VN2 2 =B×(Data-Vref3) 2 , B=(1 / 2)×μ×Cox×(W / L).

[0128] Referring to Figure 20, when the second plate of storage capacitor C2 and the second plate of coupling capacitor C1 are electrically connected to the first node N1, storage capacitor C2 can store the potential of the first node N1. During the data writing period of pixel circuit PX, the potential of the second node N2 changes. Storage capacitor C2 affects the potential change of the second node N2, ΔVN2, which is coupled to the first node N1, making the change of the first node N1, ΔVN1 = ΔVN2 × [C1 / (C1+C2)]. During the period when pixel circuit PX drives the light-emitting element LED to emit light, storage capacitor C2 can maintain the potential stability of the first node N1, so that pixel circuit PX provides a stable driving current to the light-emitting element LED, and the driving current Id = B × ΔVN1. 2 =B×[△VN2×C1 / (C1+C2)] 2 =B×[(Data-Vref3)×C1 / (C1+C2)] 2 , B=(1 / 2)×μ×Cox×(W / L).

[0129] When storage capacitor C2 is connected to the first node N1, the magnitude of the drive current can be adjusted by changing the values ​​of storage capacitor C2 and coupling capacitor C1. Under the same drive current, the data signal Data can be adjusted by changing the values ​​of storage capacitor C2 and coupling capacitor C1. For example, when Id = B × 4, 0V < Data < Vref3 = 4V, as C1 / (C1 + C2) decreases, |Data - Vref3| gradually increases, and Data gradually decreases. This helps to reduce the power consumption on the data line Data_L, improve the charging rate, and achieve high resolution and high refresh rate. When Id = B × 4, Data < Vref3 = 0V, as C1 / (C1 + C2) decreases, |Data - Vref3| gradually increases, and |Data| gradually increases. This also helps to increase the adjustment range of Data on the data line Data_L, achieve precise adjustment of the drive current, and improve display contrast.

[0130] Optionally, Figure 21 is a top view of another display panel provided in an embodiment of this application. Referring to Figures 20 and 21, the pixel circuit PX further includes an initialization module 17, which includes an initialization transistor M5. The first terminal of the initialization transistor M5 receives an initialization signal Vref1, and the second terminal of the initialization transistor M5 is electrically connected to the gate of the driving transistor M3 at the first node N1. The display panel 01 also includes a fourth driving circuit VSR4, which includes a plurality of fourth shift register units 24. The fourth shift register units 24 are electrically connected to the gate of the initialization transistor M5. The fourth driving circuit VSR4 is used to sequentially control the initialization transistors M5 of each row of pixel circuits PX to initialize the first node N1. In the same pixel circuit PX, the gate of the second reset transistor M7 of the reset module 15 can also be connected to the same fourth shift register unit 24 as the gate of the initialization transistor M5 of the initialization module 17.

[0131] For example, the first terminal of the initialization transistor M5 can be electrically connected to the third reference voltage terminal via the third reset line Vref1_L to receive the initialization signal Vref1; the gate of the initialization transistor M5 can be electrically connected to the fourth shift register unit 24 via the initialization scan line Scan1_L to receive the initialization scan signal Scan1. In an optional embodiment, the third reference voltage terminal can be reused from the second reference voltage terminal, and the third reset line Vref1_L can be reused from the second reset line Vref2_L.

[0132] During the display time of one frame, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on, initializing the first node N1, clearing the residual electrical signal of the first node N1 during the display time of the previous frame, and controlling the driving transistor M3 to be fully turned on. Thus, when the pixel circuit PX begins threshold compensation, the first power signal PV1 at the first power supply terminal can be transmitted to the first node N1 through the driving transistor M3 and the compensation transistor M4. The Vgs of the driving transistor M3 can continuously approach the threshold voltage Vth, allowing the driving transistor M3 to reach the critical state of being turned off. At this time, VN1 = PV1 + Vth, and the threshold voltage Vth can be completely compensated to the first node N1. When the pixel circuit PX emits light for display, the driving current Id is not affected by the threshold voltage Vth of the driving transistor M3.

[0133] Based on the above embodiments, during the display time of a frame, in the same pixel circuit PX, the period during which the pixel circuit PX initializes the first node N1 is located before the period during which the pixel circuit PX performs threshold compensation.

[0134] For example, the illustration continues with a pixel group comprising two pixel rows PR, where the enable levels are both low and the disable levels are both high. Figure 22 is a timing diagram of another pixel group provided in an embodiment of this application. The driving timing of Figure 22 corresponds to the pixel circuit in Figure 19 or Figure 20. Referring to Figures 19 to 22, the gate of the initialization transistor M5 in the 2×j-1th row can receive the 2×j-1th initialization scan signal Scan1 (2×j-1) output by the 2×j-1th fourth shift register unit 24 (2×j-1); the gate of the initialization transistor M5 in the 2×jth row can receive the 2×jth initialization scan signal Scan1 (2×j) output by the 2×jth fourth bit register unit 24 (2×j).

[0135] During the display time of one frame, the pixel circuit PX also includes an initialization phase T0, which precedes the compensation phase T1. In the initialization phase T0, the initialization scan signal Scan1 is enabled, while the compensation scan signal Scan3, reset scan signal Scan2, write scan signal SP, and light emission control signal EM are all disabled. The initialization transistor M5 is turned on, and the compensation transistor M4, write transistor M2, and light emission control transistor M6 are turned off. The initialization signal Vref1 of the third reset line Vref1_L can be transmitted to the gate of the driving transistor M3 through the initialization transistor M5, initializing the driving transistor M3 and making it fully turned on.

[0136] In an optional embodiment, each fourth shift register unit 24 is electrically connected to the gate of the initialization transistor M5 of each row pixel circuit PX; the fourth shift register unit 24 reuses the second shift register unit 22, and the gate of the initialization transistor M5 of the i-th row pixel circuit PX and the gate of the write transistor M2 of the ir-th row pixel circuit PX are connected to the same second shift register unit 22; wherein i and r are both integers, i > r ≥ 2.

[0137] For example, the illustration continues with a pixel group consisting of two pixel rows PR, where the enable level is low and the disable level is high. Figure 23 is a partial top view of another display panel provided in the embodiment of this application. Referring to Figures 19, 20, 22 and 23, the gate of the initialization transistor M5 in the 2×j+1 row and the gate of the write transistor M2 in the 2×j-3 row can both be electrically connected to the 2×j-3 second shift register unit 22 (2×j-3). The gate of the initialization transistor M5 in the 2×j+1 row can receive the 2×j-3 write scan signal SP (2×j-3) output by the 2×j-3 second shift register unit 22 (2×j-3) as the initialization scan signal Scan1 (2×j+1).

[0138] The gates of the initialization transistor M5 in row 2×j+2 and the write transistor M2 in row 2×j-2 can both be electrically connected to the second shift register unit 22 (2×j-2). The gate of the initialization transistor M5 in row 2×j+2 can receive the second write scan signal SP (2×j-2) output by the second shift register unit 22 (2×j-2) as the initialization scan signal Scan1 (2×j+2). In this way, by multiplexing the shift register units and the signal, the number of driving circuits can be reduced, which is beneficial to achieving a narrow bezel on the display panel 01, and also facilitates circuit layout and simplifies the layout difficulty.

[0139] In another optional embodiment, FIG24 is a top view of another display panel provided in the embodiments of this application. Referring to FIG19, FIG20 and FIG24, the fourth shift register unit 24 is electrically connected to the gate of the initialization transistor M5 of the multi-row pixel circuit PX in the same pixel group.

[0140] Specifically, the gates of the initialization transistors M5 in the 2×j-1 row and the 2×j row can receive the j-th initialization scan signal Scan1(j) output by the j-th fourth-bit register unit 24(j). During the display time of one frame, the number and frequency of the initialization scan signals Scan1 output by the fourth driving circuit VSR4 can be the same as the number and frequency of the compensation scan signals Scan3 output by the first driving circuit VSR1, both being less than the number and frequency of the write scan signals SP output by the second driving circuit VSR2. This helps reduce the number of fourth shift register units 24 in the fourth driving circuit VSR4, simplifies the circuit layout, reduces space occupation, and thus achieves a thinner and lighter display panel 01 with a narrower bezel.

[0141] Based on the above embodiments, the fourth shift register unit 24 reuses the first shift register unit 21, and the initialization module 17 of the j-th pixel group and the compensation module 13 of the js-th pixel group are connected to the same first shift register unit 21; where j and s are both integers, j > s ≥ 1.

[0142] For example, the following description continues with a pixel group consisting of two pixel rows PR, where the enable level is low and the disable level is high. Figure 25 is a timing diagram of another pixel group provided in an embodiment of this application. The driving timing of Figure 25 corresponds to the pixel circuit of Figure 19 or Figure 20. Figure 26 is a partial top view of another display panel provided in an embodiment of this application. Referring to Figures 19, 20, 25 and 26, the gates of the initialization transistors M5 in the 2×j-1 row and the initialization transistors M5 in the 2×j row can both be electrically connected to the (j-1)th first shift register unit 21 (j-1). The gates of the initialization transistors M5 in the 2×j-1 row and the initialization transistors M5 in the 2×j row can receive the (j-1)th compensation scan signal Scan3 (j-1) output by the (j-1)th first shift register unit 21 (j-1) as the initialization scan signal Scan1 (j). By multiplexing shift register units and signals, the number of driving circuits can be reduced, which is beneficial for achieving a narrow bezel on the display panel 01 and also facilitates circuit layout, simplifying the layout difficulty.

[0143] Based on the above embodiments, the fourth shift register unit 24 can also reuse the second shift register unit 22. The gate of the initialization transistor M5 of the pixel circuit PX in the j-th pixel group and the gate of the write transistor M2 of the (j-1)×kq row pixel circuit PX are connected to the same second shift register unit 22; where j, k, and q are all integers, j>1, k is the row number of the pixel circuit PX in the pixel group, and q≥1.

[0144] For example, let's continue with the illustration using a pixel group consisting of two pixel rows PR, where the enable level is low and the disable level is high. Figure 27 is a timing diagram of another pixel group provided in an embodiment of this application. The driving timing of Figure 27 corresponds to the pixel circuit of Figure 19 or Figure 20. Figure 28 is a partial top view of another display panel provided in an embodiment of this application. Referring to Figures 19, 20, 27 and 28, the gate of the initialization transistor M5 in the 2×j+1 row, the gate of the initialization transistor M5 in the 2×j+2 row and the gate of the write transistor M2 in the 2×j-2 row can all be electrically connected to the 2×j-2 second shift register unit 22 (2×j-2). The gate of the initialization transistor M5 in the 2×j+1 row and the gate of the initialization transistor M5 in the 2×j+2 row can receive the 2×j-2 write scan signal SP (2×j-2) output by the 2×j-2 second shift register unit 22 (2×j-2) as the initialization scan signal Scan1 (j+1).

[0145] In this way, while reducing the number of driving circuits, multiplexing the write scan signal SP as the initialization signal Scan1 helps to shorten the initialization time of the pixel circuit PX, thereby increasing the threshold compensation time of the pixel circuit PX, improving the charging rate of threshold compensation, and thus improving display uniformity.

[0146] In other optional embodiments, the gates of the initialization transistor M5 in the 2×j+1 row and the initialization transistor M5 in the 2×j+2 row can also be electrically connected to the second shift register unit 22 (2×j-3) or 22 (2×j-4) in the 2×j-3 or 2×j-4 row, and receive the write scan signal SP (2×j-3) or SP (2×j-4) as the initialization scan signal Scan1 (j+1), so that in the display time of a frame, in the same pixel circuit PX, the time period during which the pixel circuit PX initializes the first node N1 is located before the time period during which the pixel circuit PX performs threshold compensation.

[0147] Optionally, Figure 29 is a timing diagram of another pixel group provided in the embodiment of this application. The driving timing of Figure 29 corresponds to the pixel circuit of Figure 19 or Figure 20. Referring to Figures 19, 20 and 29, in the display time of a frame, in the same pixel circuit PX, the time period during which the pixel circuit PX initializes the first node N1 alternates with the time period during which the pixel circuit PX performs threshold compensation, and the time period during which the pixel circuit PX performs threshold compensation is the last time period.

[0148] For example, continuing with the illustration, a pixel group includes two pixel rows PR, both with low enable levels and high disable levels, and the gate of the initialization transistor M5 in the same pixel group can receive the same initialization scan signal Scan1. During the display time of one frame, the pixel circuit PX includes an initialization phase T0, a compensation phase T1, a writing phase T2, and a light emission phase T3. During the display time of one frame, the pixel circuit PX may include multiple initialization phases T0 and multiple compensation phases T1. Before writing data, the pixel circuit PX can initialize the first node N1 multiple times, and it can also perform multiple threshold compensations. By repeatedly resetting the first node N1 with alternating high and low potentials, the bias effect of the driving transistor M3 can be eliminated, thereby avoiding the hysteresis problem of the driving transistor M3. When switching from a black screen to a white screen, the brightness of white can be quickly achieved, avoiding ghosting.

[0149] It should be noted that the figure only illustrates the display time of one frame. The pixel circuit PX includes two initialization stages T0 and two compensation stages T1. In other embodiments, the pixel circuit PX may include more than two initialization stages T0 and / or more than two compensation stages T1 during the display time of one frame. This application does not specifically limit the number of initialization stages T0 and compensation stages T1 of the pixel circuit PX during the display time of one frame.

[0150] For example, Figure 30 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application, Figure 31 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application, Figure 32 is a top view of another display panel provided in an embodiment of this application, and Figure 33 is a top view of another display panel provided in an embodiment of this application. Referring to Figures 30 to 33, the pixel circuit PX further includes a reset module 15; the reset module 15 includes a second reset transistor M7; the first electrode of the second reset transistor M7 receives a second reset signal Vref2, and the second electrode of the second reset transistor M7 is electrically connected to the light-emitting element LED at the fourth node N4. The display panel 01 also includes a sixth driving circuit VSR6; the sixth driving circuit VSR6 is used to sequentially control the second reset transistors M7 of each row of pixel circuits PX to reset the fourth node N4; the sixth driving circuit VSR6 includes a plurality of sixth shift register units 26; the sixth shift register units 26 are electrically connected to the gate of the second reset transistor M7.

[0151] For example, the pixel circuit PX further includes a first reset transistor M1; the first terminal of the first reset transistor M1 is electrically connected to a first reference voltage terminal via a first reset line Vref3_L to receive a first reset signal Vref3; the second terminal of the first reset transistor M1 is electrically connected to the second node N2; the gate of the first reset transistor M1 is electrically connected to a third shift register unit 23 via a reset scan line Scan2_L to receive a reset scan signal Scan2. In an optional embodiment, referring to Figures 32 and 33, the third driving circuit VSR3 is used to sequentially control the first reset transistors M1 of the multi-row pixel circuit PX in each pixel group to reset the second node N2, and the third shift register unit 23 is electrically connected to the gate of the first reset transistors M1 of the multi-row pixel circuit PX in the same pixel group. In an optional embodiment, referring to Figure 11, the third driving circuit VSR3 is used to sequentially control the first reset transistors M1 of each row pixel circuit PX to reset the second node N2, and each third shift register unit 23 is electrically connected to the gate of the first reset transistor M1 of each row pixel circuit PX.

[0152] The pixel circuit PX also includes an initialization module 17; the initialization module 17 includes an initialization transistor M5; the first terminal of the initialization transistor M5 is electrically connected to the third reference voltage terminal via the third reset line Vref1_L to receive the initialization signal Vref1; the second terminal of the initialization transistor M5 is electrically connected to the first node N1; the gate of the initialization transistor M5 is electrically connected to the fourth shift register unit 24 via the initialization scan line Scan1_L to receive the initialization scan signal Scan1. In an optional embodiment, referring to FIG33, the fourth driving circuit VSR4 is used to sequentially control the initialization transistors M5 of the multi-row pixel circuits PX in each pixel group to initialize the gate of the driving transistor M3, and the fourth shift register unit 24 is electrically connected to the gate of the initialization transistors M5 of the multi-row pixel circuits PX in the same pixel group. In an optional embodiment, referring to FIG32, the fourth driving circuit VSR4 is used to sequentially control the initialization transistors M5 of each row pixel circuit PX to initialize the gate of the driving transistor M3, and each fourth shift register unit 24 is electrically connected to the gate of the initialization transistor M5 of each row pixel circuit PX.

[0153] The pixel circuit PX also includes a compensation module 13; the compensation module 13 includes a compensation transistor M4; the first terminal of the compensation transistor M4 is electrically connected to the drain of the driving transistor M3 at the third node N3, the second terminal of the compensation transistor M4 is electrically connected to the gate of the driving transistor M3 at the first node N1, and the gate of the compensation transistor M4 can be electrically connected to the first shift register unit 21 through the compensation scan line Scan3_L to receive the compensation scan signal Scan3.

[0154] The reset module 15 includes a second reset transistor M7; the first terminal of the second reset transistor M7 is electrically connected to the second reference voltage terminal via the second reset line Vref2_L, and receives the second reset signal Vref2; the second terminal of the second reset transistor M7 is electrically connected to the light-emitting element LED at the fourth node N4; the gate of the second reset transistor M7 is electrically connected to the sixth shift register unit 26 via the second reset scan line Scan4_L, and receives the second reset scan signal Scan4. In an optional embodiment, the third reference voltage terminal can be reused from the second reference voltage terminal, and the third reset line Vref1_L can be reused from the second reset line Vref2_L.

[0155] In an optional embodiment, referring to Figures 32 and 33, the sixth driving circuit VSR6 is used to sequentially control the second reset transistor M7 of the multi-row pixel circuit PX in each pixel group to reset the fourth node N4. The sixth shift register unit 26 is electrically connected to the gate of the second reset transistor M7 of the multi-row pixel circuit PX in the same pixel group. One sixth shift register unit 26 is connected to multiple second reset scan lines Scan4_L, providing the same second reset scan signal Scan4 to the second reset transistor M7 of the multi-row pixel circuit PX in the same pixel group, and controlling the conduction and cutoff of the second reset transistor M7 in the pixel group. The second reset scan signals Scan4 output by multiple sixth shift register units 26 can be passed sequentially, thereby sequentially controlling the multi-row pixel circuit PX in each pixel group to write the second reset signal Vref2 to the fourth node N4.

[0156] In other alternative embodiments, the sixth driving circuit VSR6 is used to sequentially control the second reset transistor M7 of each row pixel circuit PX to reset the fourth node N4. Each sixth shift register unit 26 is electrically connected to the gate of the second reset transistor M7 of each row pixel circuit PX. One sixth shift register unit 26 is connected to a second reset scan line Scan4_L, providing the same second reset scan signal Scan4 to the second reset transistor M7 of a row pixel circuit PX, and controlling the on and off states of the second reset transistor M7 of that row. The second reset scan signals Scan4 output by multiple sixth shift register units 26 can be cascaded, thereby sequentially controlling each row pixel circuit PX to write the second reset signal Vref2 to the fourth node N4.

[0157] The second reset transistor M7 can be turned on when the light-emitting control transistor M6 is turned off, and transmit the second reset signal Vref2 from the second reference voltage terminal to the fourth node N4 to reset the fourth node N4.

[0158] Optionally, referring to Figures 30 to 33, the sixth shift register unit 26 reuses the first shift register unit 21. In the same pixel circuit PX, the gate of the second reset transistor M7 is connected to the same first shift register unit 21 as the compensation module 13. Specifically, the gate of the second reset transistor M7 is connected to the gate of the compensation transistor M4 in the same first shift register unit 21. Alternatively, the sixth shift register unit 26 reuses the fourth shift register unit 24. In the same pixel circuit PX, the gate of the second reset transistor M7 is connected to the gate of the initialization transistor M5 in the same fourth shift register unit 24.

[0159] For example, the sixth shift register unit 26 multiplexes the first shift register unit 21; the gate of the second reset transistor M7 can be electrically connected to the first shift register unit 21 through the compensation scan line Scan3_L, and the channel type of the second reset transistor M7 is the same as that of the compensation transistor M4; in the same pixel circuit PX, the gate of the second reset transistor M7 can be connected to the same first shift register unit 21 as the gate of the compensation transistor M4 to receive the compensation scan signal Scan3. The gates of the second reset transistor M7 and the compensation transistor M4 located in the same row can be connected to the same compensation scan line Scan3_L, which helps to reduce the number of bridging signal lines, simplify the circuit layout, and reduce the design difficulty.

[0160] In an optional implementation, the sixth shift register unit 26 multiplexes the fourth shift register unit 24; the gate of the second reset transistor M7 can be electrically connected to the fourth shift register unit 24 via the initialization scan line Scan1_L, and the channel type of the second reset transistor M7 is the same as that of the initialization transistor M5; in the same pixel circuit PX, the gate of the second reset transistor M7 can be connected to the same fourth shift register unit 24 as the gate of the initialization transistor M5 to receive the initialization scan signal Scan1. The gates of the second reset transistor M7 and the initialization transistor M5 located in the same row can be connected to the same initialization scan line Scan1_L, which helps to reduce the number of bridging signal lines, simplify the circuit layout, and reduce the design difficulty.

[0161] In other alternative embodiments, the sixth shift register unit 26 reuses the third shift register unit 23. In the same pixel circuit PX, the gate of the second reset transistor M7 and the gate of the first reset transistor M1 are connected to the same third shift register unit 23. For example, the sixth shift register unit 26 reuses the third shift register unit 23; the gate of the second reset transistor M7 can be electrically connected to the third shift register unit 23 via the reset scan line Scan2_L, and the channel type of the second reset transistor M7 is the same as that of the first reset transistor M1; in the same pixel circuit PX, the gate of the second reset transistor M7 and the gate of the first reset transistor M1 can be connected to the same third shift register unit 23. The fact that the gates of the second reset transistor M7 and the first reset transistor M1, located in the same row, can be connected to the same reset scan line Scan2_L helps reduce the number of bridging signal lines, simplifies circuit layout, and reduces design complexity.

[0162] It should be noted that, referring to Figures 30 to 33, the sixth shift register unit 26 and the third shift register unit 23 are not reused. In this case, the reset scan line Scan2_L and the second reset scan line Scan4_L are different scan lines and are not reused.

[0163] The working principle of the pixel circuit provided in the embodiments of this application will be explained below with reference to timing.

[0164] The optional pixel circuit PX operates by at least three sequentially executed stages: a first stage T0, a second stage T1, and a third stage T2. In the first stage T0, initialization transistor M5 is turned on; in the second stage T1, compensation transistor M4 is turned on; and in the third stage T2, write transistor M2 is turned on. The pixel circuit PX also operates by a fourth stage T4, in which the first reset transistor M1 is turned on. Optionally, the fourth stage T4 overlaps with the first stage T0. Optionally, the fourth stage T4 overlaps with the second stage T1. Optionally, the fourth stage T4 does not overlap with the third stage T2. Optionally, the end time of the fourth stage T4 is earlier than the start time of the third stage T2. In one optional embodiment, the fourth stage T4 overlaps with the first stage T0, and the first stage T0 is located within the fourth stage T4. In another optional embodiment, the fourth stage T4 overlaps with the second stage T1, and the second stage T1 is located within the fourth stage T4.

[0165] For example, let's continue with the example where a pixel group includes two pixel rows PR, and the enable levels of the write scan signal SP, reset scan signal Scan2, initialization scan signal Scan1, and compensation scan signal Scan3 are all low, while the disable levels are all high.

[0166] Figure 34 is a timing diagram of another pixel group provided in the embodiment of this application. The driving timing of Figure 34 corresponds to the pixel circuit of Figure 31. In this Figure 34, the gate of the second reset transistor M7 can be connected to the gate of the initialization transistor M5 in the same pixel circuit PX to receive the initialization scan signal Scan1.

[0167] Referring to Figures 31, 33 and 34, the gates of the initialization transistors M5 in the 2×j-1 row and the 2×j row can both be electrically connected to the j-th fourth shift register unit 24(j). The gates of the initialization transistors M5 in the 2×j-1 row and the 2×j row can receive the j-th initialization scan signal Scan1(j) output by the j-th fourth shift register unit 24(j).

[0168] The gates of the compensation transistors M4 in the 2×j-1 row and the 2×j row can both be electrically connected to the j-th first shift register unit 21(j). The gates of the compensation transistors M4 in the 2×j-1 row and the 2×j row can receive the j-th compensation scan signal Scan3(j) output by the j-th first shift register unit 21(j).

[0169] The gates of the first reset transistor M1 in row 2×j-1 and row 2×j can both be electrically connected to the j-th third shift register unit 23(j). The gates of the first reset transistor M1 in row 2×j-1 and row 2×j can receive the j-th reset scan signal Scan2(j) output by the j-th third shift register unit 23(j).

[0170] The gates of the second reset transistor M7 in the 2×j-1 row and the second reset transistor M7 in the 2×j row can both be electrically connected to the j-th fourth shift register unit 24(j). The gates of the second reset transistor M7 in the 2×j-1 row and the second reset transistor M7 in the 2×j row can receive the j-th initialization scan signal Scan1(j) output by the j-th fourth shift register unit 24(j) as the second reset scan signal Scan4(j).

[0171] By multiplexing shift register units and signals, the number of driving circuits can be reduced, which is beneficial for achieving a narrow bezel on the display panel 01 and also facilitates circuit layout, simplifying the layout difficulty.

[0172] During the display time of one frame, the pixel circuit PX includes a first stage T0, a second stage T1, a third stage T2, and a fourth stage T4.

[0173] During the enable period of the j-th reset scan signal Scan2(j), i.e. the fourth stage T4, the first reset transistor M1 of the pixel circuits PX in the 2×j-1 and 2×j rows is turned on. The pixel circuits PX in the 2×j-1 and 2×j rows reset the second node N2. The potential reset of the second node N2 is Vref3.

[0174] The enable period of the j-th reset scan signal Scan2(j) may overlap with the first stage T0, which is also the initialization stage T0 described in the above embodiments. During the overlap period between the fourth stage T4 and the first stage T0, the pixel circuits PX in the 2×j-1 row and PX in the 2×j row both reset the second node N2. At the same time, the initialization transistors M5 in the 2×j-1 row and M5 in the 2×j row are both turned on. The pixel circuits PX in the 2×j-1 row and PX in the 2×j row both initialize the gate of the driving transistor M3, so that the driving transistor M3 is fully turned on. In the first stage T0, i.e., the initialization stage T0, both the pixel circuits PX in the 2×j-1 row and PX in the 2×j row initialize the first node N1. Simultaneously, both the second reset transistors M7 in the 2×j-1 row and M7 in the 2×j row are turned on, and both the pixel circuits PX in the 2×j-1 row and PX in the 2×j row reset the fourth node N4. Further, during the overlapping period between the fourth stage T4 and the first stage T0, both the pixel circuits PX in the 2×j-1 row and PX in the 2×j row reset the second node N2, initialize the first node N1, and simultaneously, both the second reset transistors M7 in the 2×j-1 row and M7 in the 2×j row are turned on, and both the pixel circuits PX in the 2×j-1 row and PX in the 2×j row reset the fourth node N4.

[0175] The enable period of the j-th reset scan signal Scan2(j) may overlap with the second stage T1, which is also the compensation stage T1 described in the above embodiments. During the overlap period of the fourth stage T4 and the second stage T1, the pixel circuit PX of the 2×j-1 row and the pixel circuit PX of the 2×j row both reset the second node N2. At the same time, the compensation transistor M4 of the 2×j-1 row and the compensation transistor M4 of the 2×j row are both turned on, and the pixel circuit PX of the 2×j-1 row and the pixel circuit PX of the 2×j row both perform threshold compensation on the first node N1.

[0176] During the enable period of the 2×j-1 write scan signal SP (2×j-1), which is the third stage T2 of the 2×j-1 row, all write transistors M2 of the 2×j-1 row are turned on, and the pixel circuit PX of the 2×j-1 row performs data writing; during the enable period of the 2×j write scan signal SP (2×j), which is the third stage T2 of the 2×j row, all write transistors M2 of the 2×j row are turned on, and the pixel circuit PX of the 2×j row performs data writing. The third stage T2 is also the write stage T2 described in the above embodiments.

[0177] In other alternative embodiments, in the same pixel circuit PX, the gate of the second reset transistor M7 can be connected to the gate of the compensation transistor M4 in the same first shift register unit 21 to receive the compensation scan signal Scan3. Accordingly, in the second stage T1, i.e., the compensation stage T1, both the 2×j-1 row pixel circuit PX and the 2×j row pixel circuit PX perform threshold compensation on the first node N1. At the same time, both the 2×j-1 row second reset transistor M7 and the 2×j row second reset transistor M7 are turned on, and both the 2×j-1 row pixel circuit PX and the 2×j row pixel circuit PX reset the fourth node N4. Furthermore, during the overlapping period of the fourth stage T4 and the second stage T1, both the pixel circuit PX in the 2×j-1 row and the pixel circuit PX in the 2×j row reset the second node N2, both the pixel circuit PX in the 2×j-1 row and the pixel circuit PX in the 2×j row perform threshold compensation on the first node N1, and at the same time, both the second reset transistor M7 in the 2×j-1 row and the second reset transistor M7 in the 2×j row are turned on, and both the pixel circuit PX in the 2×j-1 row and the pixel circuit PX in the 2×j row reset the fourth node N4.

[0178] In other optional embodiments, the fourth stage T4 may overlap with the first stage T0; specifically, a portion of the time period of the fourth stage T4 may coincide with a portion of the time period of the first stage T0. Alternatively, the fourth stage T4 may overlap with the second stage T1; specifically, a portion of the time period of the fourth stage T4 may coincide with a portion of the time period of the second stage T1.

[0179] Before the pixel circuit PX writes data, the pixel circuit PX can reset the second node N2 multiple times or for a long time.

[0180] Thus, the reset period of the second node N2 overlaps with the initialization period of the first node N1, ensuring that the initialized potential of the first node N1 is not affected by the potential changes of the second node N2, and that the reset potential of the second node N2 is not affected by the potential changes of the first node N1. This facilitates the accurate initialization of the first node N1's potential and the accurate reset of the second node N2's potential. Similarly, the reset period of the second node N2 overlaps with the threshold compensation period of the first node N1, ensuring that the threshold-compensated potential of the first node N1 is not affected by the potential changes of the second node N2, and that the reset potential of the second node N2 is not affected by the potential changes of the first node N1. This facilitates the accurate compensation of the first node N1's potential and the accurate reset of the second node N2's potential.

[0181] As described above, the time periods for resetting the second node N2 of the pixel circuit PX in the 2×j-1 row and the 2×j row can overlap and be superimposed, thus extending both the time periods for resetting the second node N2 of the pixel circuit PX in the 2×j-1 row and the 2×j row (e.g., T4). In this way, even with high resolution and high refresh rate, it can still be ensured that the pixel circuit PX has sufficient time to reset the second node N2 to completely write the first reset signal Vref3 into the second node N2, improving the display uniformity of the display panel 01.

[0182] It should be noted that the figure only shows an example of a pixel group including two pixel rows PR. In other embodiments, a pixel group may also include three or four or more pixel rows PR. This application embodiment does not specifically limit the number of pixel rows PR contained in a pixel group.

[0183] In this embodiment, by setting a third shift register unit 23, a fourth shift register unit 24, and a first shift register unit 21, the pixel circuit PX can independently perform the reset of the second node N2, the initialization of the first node N1, and the threshold compensation process. The third shift register unit 23 is electrically connected to the first reset transistor M1 of the multi-row pixel circuit PX in the same pixel group, which allows the multi-row pixel circuit PX in the same pixel group to simultaneously perform the reset of the second node N2. Thus, during the display time of one frame, the duration or number of times the third shift register unit 23 of the display panel controls the pixel circuit PX to perform the reset of the second node N2 is not limited by the frequency or duration of data writing by the pixel circuit PX. This is beneficial to increase the duration of the reset of the second node N2 and improve the charging rate during the reset process. Even under high resolution and high refresh rate conditions, while the pixel circuit achieves fast data writing, the first reset signal Vref3 can also be fully written, which is beneficial to improve the uniformity of the display quality.

[0184] For example, Figure 35 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application. Referring to Figures 32 and 35, the pixel circuit PX further includes a bias module 18; the bias module 18 is electrically connected between the bias signal terminal and the driving transistor M3; in the same pixel circuit PX, the bias module 18 and the second reset transistor M7 are connected to the same sixth shift register unit VSR6. Optionally, the pixel circuit PX further includes a dimming control module 19; the dimming control module 19 is electrically connected between the first power supply terminal and the driving transistor M3; the display panel further includes a dimming control circuit, which is used to sequentially turn on the dimming control modules 19 of multiple rows of pixel circuits PX in each pixel group; the dimming control circuit includes multiple dimming shift register units; the dimming shift register units are electrically connected to the dimming control module 19. Optionally, the dimming control circuit reuses the fifth driving circuit VSR5.

[0185] The bias module 18 includes a bias transistor M9. The first terminal of the bias transistor M9 is electrically connected to the bias signal terminal through the bias signal line DVH_L to receive the bias signal DVH. The second terminal of the bias transistor M9 is electrically connected to the source of the driving transistor M3 at the fifth node N5. The display panel 01 also includes a sixth driving circuit VSR6, which includes multiple sixth shift register units 26. In the same pixel circuit PX, the gate of the bias transistor M9 of the bias module 18 can also be connected to the gate of the second reset transistor M7 of the reset module 15 through the second reset scan line Scan4_L in the same sixth shift register unit 26. The sixth shift register unit 26 is also used to control the bias transistor M9 of the pixel circuit PX to adjust the bias of the driving transistor M3.

[0186] In an optional embodiment, the gate of the bias transistor M9 and the gate of the second reset transistor M7 are connected to the same sixth shift register unit 26 through the second reset scan line Scan4_L. This helps to reduce the number of bridging signal lines, simplify the circuit layout, and reduce the design difficulty. By multiplexing the shift register unit and the signal, the number of driving circuits can be reduced, which is beneficial to achieving a narrow bezel on the display panel 01. It also helps to simplify the circuit layout and reduce the difficulty of the layout.

[0187] In this embodiment, the bias transistor M9 can be either a P-type transistor or an N-type transistor, and the second reset transistor M7 can also be either a P-type transistor or an N-type transistor. The channel type of the bias transistor M9 and the channel type of the second reset transistor M7 are the same, and this embodiment does not limit this. Optionally, referring to FIG35, the bias transistor M9 and the second reset transistor M7 can both be low-temperature polysilicon transistors, or both can be metal-oxide transistors. At least one of the bias transistor M9 and the second reset transistor M7 can be a dual-gate transistor. It is advantageous that the gates of the bias transistor M9 and the second reset transistor M7, which are located in the same row, are connected to the same sixth shift register unit 26 through the second reset scan line Scan4_L, which helps to reduce the number of bridging signal lines and driving circuits.

[0188] The dimming control module 19 includes a dimming control transistor M8. The first terminal of the dimming control transistor M8 is electrically connected to the first power supply terminal through the first power supply line PV1_L, and receives the first power supply signal PV1. The second terminal of the dimming control transistor M8 is electrically connected to the source of the driving transistor M3 at the fifth node N5. The display panel 01 also includes a fifth driving circuit VSR5, which includes multiple fifth shift register units 25. In the same pixel circuit PX, the gate of the dimming control transistor M8 of the dimming control module 19 can also be connected to the gate of the light-emitting control transistor M6 of the light-emitting control module 14 through the light-emitting control line EM_L in the same fifth shift register unit 25. The fifth shift register unit 25 is used to control the conduction of the dimming control transistor M8 and the light-emitting control transistor M6 during the light-emitting stage T3, driving the light-emitting element LED to emit light.

[0189] In other alternative embodiments, the display panel further includes a dimming control circuit different from the fifth driving circuit VSR5. The dimming control circuit includes multiple dimming shift register units. The dimming control circuit is used to sequentially turn on the dimming control transistors M8 of the multi-row pixel circuits PX in each pixel group. The fifth driving circuit VSR5 is used to sequentially turn on the light-emitting control transistors M6 of the multi-row pixel circuits PX in each pixel group, driving the light-emitting element LED to emit light.

[0190] In an optional embodiment, the gates of the dimming control transistor M8 and the light-emitting control transistor M6, which are located in the same row, are connected to the same fifth shift register unit 25 through the light-emitting control line EM_L. This helps to reduce the number of bridging signal lines, simplify the circuit layout, and reduce the design difficulty. By multiplexing the shift register unit and the signal, the number of driving circuits can be reduced, which is beneficial to achieving a narrow bezel on the display panel 01. It also helps to simplify the circuit layout and reduce the difficulty of the layout.

[0191] In this embodiment, the light-emitting control transistor M6 can be either a P-type transistor or an N-type transistor, and the dimming control transistor M8 can also be either a P-type transistor or an N-type transistor. The channel type of the light-emitting control transistor M6 and the dimming control transistor M8 are the same, and this embodiment does not limit this. Optionally, referring to FIG35, both the light-emitting control transistor M6 and the dimming control transistor M8 can be either low-temperature polysilicon transistors or metal-oxide transistors. At least one of the light-emitting control transistor M6 and the dimming control transistor M8 can be a dual-gate transistor. It is advantageous that the gates of the dimming control transistor M8 and the light-emitting control transistor M6, which are located in the same row, are connected to the same fifth shift register unit 25 through the light-emitting control line EM_L, which helps to reduce the number of bridging signal lines and driving circuits.

[0192] In any embodiment of this application, optionally, any one of the first reset transistor M1, the write transistor M2, and the compensation transistor M4 is a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor. Optionally, at least one of the first reset transistor M1, the write transistor M2, and the compensation transistor M4 is a dual-gate transistor, which can improve the stability of the pixel circuit PX. In any embodiment of this application, optionally, any one of the initialization transistor M5 and the second reset transistor M7 is a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor. Optionally, at least one of the initialization transistor M5 and the second reset transistor M7 is a dual-gate transistor, which can improve the stability of the pixel circuit PX.

[0193] Optionally, referring to Figures 30 to 35, the write module 11 includes a first reset transistor M1; the first terminal of the first reset transistor M1 receives a first reset signal Vref3, and the second terminal of the first reset transistor M1 is electrically connected to the first terminal of the coupling module 12 at the second node N2; the display panel also includes a third driving circuit VSR3; the third driving circuit VSR3 includes multiple third shift register units 23; the third shift register units 23 are electrically connected to the gate of the first reset transistor M1; the display panel includes multiple signal lines, including a first reset line Vref3_L and a third reset line Vref1_L; the first reset line Vref3_L is electrically connected to the first terminal of the first reset transistor M1; the third reset line Vref1_L is electrically connected to the first terminal of the initialization transistor M5. Optionally, the display panel includes multiple signal lines, including a first power line PV1_L and a first reset line Vref3_L; the first power line PV1_L is electrically connected to the driving transistor M3, and the first reset line Vref3_L is electrically connected to the first terminal of the first reset transistor M1. Optionally, the pixel circuit PX also includes a reset module 15; the reset module 15 includes a second reset transistor M7; the first terminal of the second reset transistor M7 receives a second reset signal Vref2, and the second terminal of the second reset transistor M7 is electrically connected to the light-emitting element LED at the fourth node N4; the display panel also includes a sixth driving circuit VSR6; the sixth driving circuit VSR6 includes multiple sixth shift register units 26; the sixth shift register units 26 are electrically connected to the gate of the second reset transistor M7; the display panel includes multiple signal lines, including a third reset line Vref1_L and a second reset line Vref2_L; the third reset line Vref1_L is electrically connected to the first terminal of the initialization transistor M5, and the second reset line Vref2_L is electrically connected to the first terminal of the second reset transistor M7.

[0194] The display panel includes multiple signal lines, which provide scanning signals, control signals, voltage signals, etc., to the pixel circuit PX to drive the pixel circuit PX to work. This example only focuses on the multiple signal lines in the display panel that provide voltage signals to the pixel circuit PX.

[0195] In an optional embodiment, the display panel includes multiple signal lines, including a first reset line Vref3_L. The first reset line Vref3_L is electrically connected to the first terminal of the first reset transistor M1, and a first reference voltage terminal is electrically connected to the first reset line Vref3_L. When the first reset transistor M1 is turned on, the first reference voltage terminal provides a first reset signal Vref3 to the first reset line Vref3_L, which is written to the second node N2 to reset the second node N2.

[0196] The display panel contains multiple signal lines, including a data line Data_L. The data line Data_L is electrically connected to the first terminal of the write transistor M2, and the data voltage terminal is electrically connected to the data line Data_L. When the write transistor M2 is turned on, the data voltage terminal provides the data signal Data to the data line Data_L, which is written to the second node N2 and coupled to the first node N1, so that the first node N1 is written with data.

[0197] The display panel contains multiple signal lines, including a first power line PV1_L. The first power line PV1_L is electrically connected to the driving transistor M3. The first power terminal is electrically connected to the first power line PV1_L. Alternatively, the driving transistor M3 is electrically connected to the first power terminal, which provides a first power signal PV1. When the driving transistor M3 and the compensation transistor M4 are turned on, the first power signal PV1 provided by the first power terminal to the first power line PV1_L is written into the first node N1 to perform threshold compensation on the first node N1.

[0198] The display panel has multiple signal lines, including a third reset line Vref1_L. The third reset line Vref1_L is electrically connected to the first terminal of the initialization transistor M5, and the third reference voltage terminal is electrically connected to the third reset line Vref1_L. When the initialization transistor M5 is turned on, the third reference voltage terminal provides the initialization signal Vref1 provided by the third reset line Vref1_L to the first node N1, thereby resetting the first node N1.

[0199] The display panel has multiple signal lines, including a second reset line Vref2_L. The second reset line Vref2_L is electrically connected to the first terminal of the second reset transistor M7, and the second reference voltage terminal is electrically connected to the second reset line Vref2_L. When the second reset transistor M7 is turned on, the second reset signal Vref2 provided by the second reference voltage terminal to the second reset line Vref2_L is written to the fourth node N4 to reset the fourth node N4.

[0200] In an optional embodiment, the first power supply signal PV1 is less than or equal to the first reset signal Vref3. That is, the first power supply signal PV1 provided by the first power supply line PV1_L to the driving transistor M3 is less than or equal to the first reset signal Vref3 provided by the first reset line Vref3_L to the first terminal of the first reset transistor M1.

[0201] During the display time of one frame, the first reset transistor M1 can be turned on before the write transistor M2 is turned on, resetting the second node N2 and clearing the residual electrical signal of the second node N2 from the display time of the previous frame. Thus, after the pixel circuit PX writes the data signal Data, the change in the second node N2, ΔVN2 = Data - Vref3, is such that when the pixel circuit PX emits light for display, the driving current Id = B × (Vgs - Vth). 2 =B×△VN1 2 =B×△VN2 2 =B×(Data-Vref3) 2 , B=(1 / 2)×μ×Cox×(W / L).

[0202] On the one hand, the potential of the second node N2 before the writing stage T2 of all pixel circuits PX can be uniformly set to Vref3, which is beneficial to simplifying the control of the driving current and also beneficial to the uniformity of the pixel circuits PX in the display panel 01, thereby improving the display uniformity of the display panel 01. On the other hand, the first reset signal Vref3 can be set as a positive electrical signal that is greater than or equal to the first power supply signal PV1. Then the data signal Data can be an electrical signal with a small absolute value, so that the data signal Data on the data line Data_L changes near 0V, which is beneficial to reduce power consumption, increase charging rate, and achieve high resolution and high refresh rate.

[0203] Furthermore, by setting the first reset signal Vref3 to a positive electrical signal that is greater than or equal to the first power supply signal PV1, the reset period of the second node N2 and the compensation period of the first node N1 overlap. This ensures that the potential of the first node N1 after threshold compensation is not affected by the potential change of the second node N2, and also ensures that the potential of the second node N2 after reset is not affected by the potential change of the first node N1. This is beneficial for the accurate compensation of the potential of the first node N1 and the accurate reset of the potential of the second node N2.

[0204] In an optional embodiment, the first power signal PV1 is equal to the first reset signal Vref3, then the first power line PV1_L multiplexes the first reset line Vref3_L. That is, multiplexing the first power line PV1_L providing the first power signal PV1 with the first reset line Vref3_L providing the first reset signal Vref3 helps reduce the number of bridging signal lines, simplifies circuit layout, reduces design complexity, and also facilitates the achievement of a narrow bezel and circuit layout for the display panel 01, simplifying the layout process.

[0205] In an optional embodiment, the initialization signal Vref1 is less than the first reset signal Vref3. The initialization signal Vref1 is less than 0V, while the first reset signal Vref3 and the first power supply signal PV1 are both greater than 0V.

[0206] During the display time of one frame, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on. The initialization signal Vref1 of the third reset line Vref1_L initializes the first node N1, clearing the residual electrical signal of the first node N1 during the display time of the previous frame. The initialization signal Vref1 is less than the first reset signal Vref3, and / or the initialization signal Vref1 is less than 0V. When the initialization transistor M5 is turned on, the initialization signal Vref1 of the third reset line Vref1_L initializes the driving transistor M3, which helps to ensure that the driving transistor M3 is fully turned on. Thus, when the pixel circuit PX begins threshold compensation, the first power signal PV1 at the first power supply terminal can be transmitted to the first node N1 through the driving transistor M3 and the compensation transistor M4. The Vgs of the driving transistor M3 can continuously approach the threshold voltage Vth, so that the driving transistor M3 can reach the critical state of being turned off. The threshold voltage Vth can be completely compensated to the first node N1. When the pixel circuit PX displays light, the driving current Id is not affected by the threshold voltage Vth of the driving transistor M3, thereby improving the display uniformity of the display panel.

[0207] In an optional embodiment, the initialization signal Vref1 is less than or equal to the second reset signal Vref2. Both the initialization signal Vref1 and the second reset signal Vref2 are less than 0V.

[0208] During the display time of one frame, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on. The initialization signal Vref1 of the third reset line Vref1_L initializes the first node N1, clearing the residual electrical signal of the first node N1 during the display time of the previous frame. The initialization signal Vref1 is less than or equal to the second reset signal Vref2, and / or, the initialization signal Vref1 is less than 0V. When the initialization transistor M5 is turned on, the initialization signal Vref1 initializes the driving transistor M3, which helps to ensure that the driving transistor M3 is fully turned on. When the initialization signal Vref1 is less than or equal to the second reset signal Vref2, and / or the second reset signal Vref2 is less than 0V, the second reset signal Vref2 resets the fourth node N4 when the second reset transistor M7 is turned on. This helps to clear the residual electrical signal of the fourth node N4 in the display time of the previous frame, so that when the pixel circuit PX displays light in the light-emitting stage T3, the driving current Id is not affected by the residual electrical signal of the fourth node N4 in the previous frame. The light-emitting element LED can display the corresponding brightness according to the driving current Id, thereby improving the display uniformity of the display panel.

[0209] In an optional embodiment, the initialization signal Vref1 is equal to the second reset signal Vref2, then the third reset line Vref1_L multiplexes the second reset line Vref2_L. That is, the third reset line Vref1_L providing the initialization signal Vref1 multiplexes the second reset line Vref2_L providing the second reset signal Vref2, which helps reduce the number of bridging signal lines, simplifies circuit layout, reduces design complexity, and also facilitates the achievement of a narrow bezel and circuit layout for the display panel 01, simplifying the layout process.

[0210] For example, continuing to refer to Figures 11, 14, 18, 21, 24, 32, and 33, the display panel includes a third driving circuit VSR3 and a fifth driving circuit VSR5. The third driving circuit VSR3 includes a plurality of third shift register units 23, which are electrically connected to the gate of the first reset transistor M1. The fifth driving circuit VSR5 includes a plurality of fifth shift register units 25, which are electrically connected to the light-emitting control module 14. Optionally, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a first side and a second side opposite each other along a row direction, where the row direction is the arrangement direction of multiple pixel circuits PX in a row of pixel circuits PX. The fifth driving circuit VSR5 is located in the non-display area NA and is at least located on the first side of the display area AA. The third driving circuit VSR3 is located in the non-display area NA and is at least located on the second side of the display area AA. Optionally, the fifth driving circuit VSR5 and the third driving circuit VSR3 are located on different sides of the display area AA.

[0211] In an optional embodiment, referring to Figures 11 and 14, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on both sides of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display area NA on one side of the display area AA.

[0212] In an optional embodiment, referring to Figures 18 and 21, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display areas NA on both sides of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display areas NA on both sides of the display area AA.

[0213] In an optional embodiment, referring to FIG24, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on one side of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display areas NA on opposite sides of the display area AA.

[0214] In an optional embodiment, referring to Figures 32 and 33, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on one side of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display area NA on one side of the display area AA. The fifth driving circuit VSR5 and the third driving circuit VSR3 are located on different sides of the display area AA. Specifically, the third driving circuit VSR3 and the fifth driving circuit VSR5 are located in the non-display areas NA on opposite sides of the display area AA.

[0215] The embodiments of this application do not specifically limit the positions of the fifth shift register unit 25 and the third shift register unit 23, and are not limited to the above examples.

[0216] This application provides a display panel. Figure 36 is a schematic diagram of the circuit structure of another pixel circuit provided in this application. Referring to Figures 32 and 36, the display panel includes: multiple pixel circuits PX arranged in an array; each pixel circuit PX includes a driving module 10, a compensation module 13, a data writing unit 11A, a coupling module 12, and a light-emitting element LED; the coupling module 12 is electrically connected between a first node N1 and a second node N2, and the control terminal of the driving module 10 is electrically connected to the first node N1; the light-emitting element LED is electrically connected to the driving module 10; the control terminal of the compensation module 13 is electrically connected to a first shift register unit 21, and the compensation module 13 is electrically connected between the control terminal of the driving module 10 and the first terminal of the driving module 10; the control terminal of the data writing unit 11A is electrically connected to a second shift register unit 22, and the data writing unit 11A is electrically connected between a data voltage terminal and the second node N2.

[0217] In this embodiment, the pixel circuit PX includes a driving module 10. The control terminal of the driving module 10 is electrically connected to the first node N1, the driving module 10 is electrically connected to the light-emitting element LED, and the driving module 10 is electrically connected to the first power supply terminal. Optionally, the driving module 10 includes a driving transistor M3. The control terminal of the driving module 10 is the gate of the driving transistor M3, the gate of the driving transistor M3 is electrically connected to the first node N1, the first terminal of the driving module 10 is the drain of the driving transistor M3, the drain of the driving transistor M3 is electrically connected to the light-emitting element LED, the second terminal of the driving module 10 is the source of the driving transistor M3, and the source of the driving transistor M3 is electrically connected to the first power supply terminal. A high-low level transition at the potential of the first node N1 controls the driving module 10, i.e., the driving transistor M3, to be turned on or off. When the potential of the first node N1 is at an enabled level, the driving transistor M3 is turned on, and the first power supply terminal provides a first power signal PV1 to the driving transistor M3 through the first power line PV1_L; when the potential of the first node N1 is at a disabled level, the driving transistor M3 is turned off. When the driving transistor M3 is a P-type transistor, the enable level of the first node N1 is low and the disable level is high; when the driving transistor M3 is an N-type transistor, the enable level of the first node N1 is high and the disable level is low. It should be noted that the source and drain of the driving transistor M3 are not fixed; they can be interchanged depending on the signal. For example, the source of the driving transistor M3 can be electrically connected to the LED, and the drain of the driving transistor M3 can be electrically connected to the first power supply line PV1_L. The driving transistor M3 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor.

[0218] The pixel circuit PX includes a compensation module 13. The control terminal of the compensation module 13 is electrically connected to the first shift register unit 21 via the compensation scan line Scan3_L, and receives the compensation scan signal Scan3 transmitted by the compensation scan line Scan3_L. The compensation module 13 is electrically connected between the control terminal and the first terminal of the driving module 10. Optionally, the compensation module 13 includes a compensation transistor M4. The control terminal of the compensation module 13 is also the gate of the compensation transistor M4. The gate of the compensation transistor M4 is electrically connected to the compensation scan line Scan3_L. The first terminal of the compensation transistor M4 and the first terminal of the driving module 10 are electrically connected to the third node N3, and the second terminal of the compensation transistor M4 and the control terminal of the driving module 10 are electrically connected to the first node N1. The compensation scan signal Scan3 provided by the compensation scan line Scan3_L undergoes high-low level transitions, thereby controlling the compensation module 13, i.e., the compensation transistor M4, to be turned on or off. When the Scan3 compensation signal is enabled, it turns on the compensation transistor M4 to perform threshold compensation on the gate of the driving transistor M3; when the Scan3 compensation signal is disabled, it turns off the compensation transistor M4. When the compensation transistor M4 is a P-type transistor, the enable level of the Scan3 compensation signal is low; when the compensation transistor M4 is an N-type transistor, the enable level of the Scan3 compensation signal is high. The compensation transistor M4 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor; it can be a single-gate transistor, a dual-gate transistor, or a multi-gate transistor.

[0219] The pixel circuit PX includes a data writing unit 11A. The control terminal of the data writing unit 11A is electrically connected to the second shift register unit 22 via the write scan line SP_L, and receives the write scan signal SP transmitted by the write scan line SP_L. The data writing unit 11A is electrically connected between the data voltage terminal and the second node N2. Optional data writing unit 11A includes a write transistor M2. The control terminal of the data writing unit 11A is also the gate of the write transistor M2. The gate of the write transistor M2 is electrically connected to the write scan line SP_L. The first electrode of the write transistor M2 is electrically connected to the data voltage terminal, which provides the data signal Data to the write transistor M2 via the data line Data_L. The second electrode of the write transistor M2 and the coupling module 12 are electrically connected to the second node N2. The write scan signal SP provided by the write scan line SP_L undergoes a high-low level transition, thereby controlling the data writing unit 11A, i.e., the write transistor M2, to be turned on or off. When the write scan signal SP is at the enable level, it controls the write transistor M2 to turn on, and the data signal Data is written to the second node N2 and coupled to the gate of the driving transistor M3, thus writing data to the pixel circuit PX. When the write scan signal SP is at the disable level, it controls the write transistor M2 to turn off. When the write transistor M2 is a P-type transistor, the enable level of the write scan signal SP is low; when the write transistor M2 is an N-type transistor, the enable level of the write scan signal SP is high. The write transistor M2 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor; the write transistor M2 can be a single-gate transistor, a dual-gate transistor, or a multi-gate transistor.

[0220] The pixel circuit PX includes a coupling module 12, which is electrically connected between a first node N1 and a second node N2. The coupling module 12 includes a coupling capacitor C1, which is electrically connected between the first node N1 and the second node N2.

[0221] When the data writing unit 11A is turned on, the data signal Data can be transmitted to the coupling capacitor C1 through the data writing unit 11A. The coupling capacitor C1 can couple the data signal Data to the first node N1, thereby writing the data signal Data to the gate of the driving transistor M3. When the compensation module 13 is turned on, the signal of the third node N3 can be transmitted to the first node N1 through the compensation module 13, thereby compensating the threshold voltage Vth of the driving transistor M3 to the first node N1. Thus, when the pixel circuit PX performs data writing, the data signal Data can be superimposed with the signal of the first node N1 without affecting the threshold voltage Vth of the first node N1 for threshold compensation. When the pixel circuit PX performs threshold compensation, it does not need to receive the data signal Data, nor is it limited by the on-time of the data writing unit 11A. That is, when the data writing unit 11A is turned off, the pixel circuit PX can still perform threshold compensation.

[0222] In this embodiment, the first driving circuit VSR1 includes multiple first shift register units 21, which are electrically connected to the compensation modules 13 of the multi-row pixel circuits PX in the same pixel group, and are used to control the compensation modules 13 of the multi-row pixel circuits PX in the same pixel group to be turned on or off. The second driving circuit VSR2 includes multiple second shift register units 22, which are electrically connected to the data writing units 11A of the same row pixel circuit PX, and are used to control the data writing units 11A of the same row pixel circuit PX to be turned on or off. That is, in the same pixel circuit PX, the compensation modules 13 and the data writing units 11A are electrically connected to different driving circuits, and the different driving circuits control the compensation modules 13 and the data writing units 11A to work independently.

[0223] In this application, by setting a coupling module, the data writing unit is electrically connected to the control terminal of the driving module through the coupling module, and the compensation module is electrically connected between the control terminal of the driving module and the first terminal. In the same pixel circuit, the control terminal of the compensation module is electrically connected to the first driving circuit, and the control terminal of the data writing unit is electrically connected to the second driving circuit. Therefore, when the pixel circuit performs threshold compensation, the data writing unit is turned off, so it does not need to receive data signals and is not limited by the conduction time of the data writing unit to perform threshold compensation on the control terminal of the driving module. When the pixel circuit performs data writing, the data signal can be coupled to the first node through the coupling module and superimposed on the signal of the first node without affecting the threshold voltage for threshold compensation of the first node. Thus, during the display time of one frame, the number of times the first shift register unit of the display panel controls the pixel circuit to perform threshold compensation can be different from the number of times the second shift register unit controls the pixel circuit to perform data writing. The duration of threshold compensation by the pixel circuit is not limited by the frequency of data writing by the pixel circuit, which is conducive to increasing the duration of threshold compensation and improving the charging rate during the threshold compensation process. Even under high resolution and high refresh rate conditions, while the pixel circuit achieves fast data writing, it can also achieve complete compensation of the threshold voltage, which is conducive to improving the uniformity of display quality.

[0224] Optionally, Figure 37 is a schematic diagram of the circuit structure of another pixel circuit provided in the embodiment of this application. Referring to Figures 32 and 37, the pixel circuit PX further includes a first reset unit 11B; the control terminal of the first reset unit 11B is electrically connected to the third shift register unit 23, and the first reset unit 11B is electrically connected between the first reference voltage terminal and the second node N2.

[0225] The first reset module 11B and the data writing unit 11A constitute the writing module 11 described in other embodiments of this application.

[0226] The pixel circuit PX includes a first reset module 11B. The control terminal of the first reset module 11B is electrically connected to the third shift register unit 23 via the reset scan line Scan2_L, and receives the reset scan signal Scan2 transmitted by the reset scan line Scan2_L. The first reset module 11B is electrically connected between the first reference voltage terminal and the second node N2. Optionally, the first reset module 11B includes a first reset transistor M1. The control terminal of the first reset module 11B is the gate of the first reset transistor M1, and the gate of the first reset transistor M1 is electrically connected to the reset scan line Scan2_L. The first electrode of the first reset transistor M1 is electrically connected to the first reference voltage terminal, and the first reference voltage terminal provides a first reset signal Vref3 to the first reset transistor M1 via the first reset line Vref3_L. The second electrode of the first reset transistor M1 and the coupling module 12 are electrically connected to the second node N2.

[0227] The reset scan signal Scan2 provided by the reset scan line Scan2_L undergoes high-low level transitions to control the first reset module 11B, i.e., the first reset transistor M1, to be turned on or off. When the reset scan signal Scan2 is at an enabled level, it controls the first reset transistor M1 to be turned on, and the first reset signal Vref3 is written to the second node N2 to reset the second node N2. When the reset scan signal Scan2 is at a disabled level, it controls the first reset transistor M1 to be turned off. When the first reset transistor M1 is a P-type transistor, the enabled level of the reset scan signal Scan2 is low; when the first reset transistor M1 is an N-type transistor, the enabled level of the reset scan signal Scan2 is high. The first reset transistor M1 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor; the first reset transistor M1 can be a single-gate transistor, a dual-gate transistor, or a multi-gate transistor.

[0228] During the display time of one frame, the first reset transistor M1 can be turned on before the write transistor M2 is turned on, resetting the second node N2 and clearing the residual electrical signal of the second node N2 from the display time of the previous frame. On the one hand, before the data writing stage of all pixel circuits PX, the potential of the second node N2 can be uniformly unified to Vref3, which helps to simplify the control of the driving current and also helps to improve the uniformity of the pixel circuits PX in the display panel 01, thereby improving the display uniformity of the display panel 01. On the other hand, the first reset signal Vref3 can be set as a positive electrical signal, and the data signal Data can be an electrical signal with a small absolute value, so that the data signal Data on the data line Data_L changes near 0V, which helps to reduce power consumption, increase charging rate, and achieve high resolution and high refresh rate.

[0229] In this embodiment, within the same pixel circuit PX, the first reset module 11B, compensation module 13, and data writing unit 11A are electrically connected to different driving circuits. These different driving circuits control the independent operation of the first reset module 11B, compensation module 13, and data writing unit 11A. When the pixel circuit PX resets the second node N2, the data writing unit 11A is turned off, eliminating the need to receive data signals and the limitation imposed by the on-time of the data writing unit 11A. This increases the reset time of the second node N2, improves the charging rate during the reset process, and allows the first reset signal Vref3 to be completely written into the second node N2. When the pixel circuit PX writes data, the data signal Data can be coupled to the first node N1 through the coupling module 12 and superimposed on the signal of the first node N1 without affecting the threshold voltage for threshold compensation in the first node N1. Thus, even at high resolution and high refresh rate, the pixel circuit PX can achieve rapid data writing while simultaneously achieving a complete reset of the second node N2, which helps improve the uniformity of the display quality.

[0230] Optionally, referring to Figures 32 and 37, the pixel circuit PX also includes an initialization module 17; the control terminal of the initialization module 17 is electrically connected to the fourth shift register unit 24, and the initialization module 17 is electrically connected between the third reference voltage terminal and the first node N1.

[0231] The pixel circuit PX includes an initialization module 17. The control terminal of the initialization module 17 is electrically connected to the fourth shift register unit 24 via the initialization scan line Scan1_L, and receives the initialization scan signal Scan1 transmitted by the initialization scan line Scan1_L. The initialization module 17 is electrically connected between the third reference voltage terminal and the first node N1. Optional initialization module 17 includes an initialization transistor M5. The control terminal of the initialization module 17 is the gate of the initialization transistor M5, and the gate of the initialization transistor M5 is electrically connected to the initialization scan line Scan1_L. The first electrode of the initialization transistor M5 is electrically connected to the third reference voltage terminal, and the third reference voltage terminal provides the initialization signal Vref1 to the initialization transistor M5 via the third reset line Vref1_L. The second electrode of the initialization transistor M5 and the gate of the driving transistor M3 are electrically connected to the first node N1.

[0232] The initialization scan signal Scan1 provided by the initialization scan line Scan1_L undergoes a high-low level transition, thereby controlling the initialization module 17, i.e., the initialization transistor M5, to turn on or off. When the initialization scan signal Scan1 is at an enabled level, it controls the initialization transistor M5 to turn on, and the initialization signal Vref1 is written to the first node N1 to initialize it. When the initialization scan signal Scan1 is at a disabled level, it controls the initialization transistor M5 to turn off. When the initialization transistor M5 is a P-type transistor, the enabled level of the initialization scan signal Scan1 is low; when the initialization transistor M5 is an N-type transistor, the enabled level of the initialization scan signal Scan1 is high. The initialization transistor M5 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor; the initialization transistor M5 can be a single-gate transistor, a dual-gate transistor, or a multi-gate transistor.

[0233] During the display time of one frame, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on, initializing the first node N1, clearing the residual electrical signal of the first node N1 during the display time of the previous frame, and controlling the driving transistor M3 to be fully turned on. Thus, when the pixel circuit PX begins threshold compensation, the first power signal PV1 at the first power supply terminal can be transmitted to the first node N1 through the driving transistor M3 and the compensation transistor M4. The Vgs of the driving transistor M3 can continuously approach the threshold voltage Vth, allowing the driving transistor M3 to reach the critical state of being turned off. At this time, VN1 = PV1 + Vth, and the threshold voltage Vth can be completely compensated to the first node N1. When the pixel circuit PX emits light for display, the driving current Id is not affected by the threshold voltage Vth of the driving transistor M3.

[0234] Optionally, referring to Figures 32 and 37, the pixel circuit PX also includes a light emission control module 14; the control terminal of the light emission control module 14 is electrically connected to the fifth shift register unit 25, and the light emission control module 14 is electrically connected between the driving module 10 and the light emission element LED.

[0235] The pixel circuit PX includes a light-emitting control module 14. The control terminal of the light-emitting control module 14 is electrically connected to the fifth shift register unit 25 via the light-emitting control line EM_L, and receives the light-emitting control signal EM transmitted by the light-emitting control line EM_L. The light-emitting control module 14 and the driving transistor M3 are electrically connected to the third node N3, and the light-emitting element LED is electrically connected to the fourth node N4. Optionally, the light-emitting control module 14 includes a light-emitting control transistor M6. The control terminal of the light-emitting control module 14 is the gate of the light-emitting control transistor M6, and the gate of the light-emitting control transistor M6 is electrically connected to the light-emitting control line EM_L. The first electrode of the light-emitting control transistor M6 is electrically connected to the third node N3, and the second electrode of the light-emitting control transistor M6 and the anode of the light-emitting element LED are electrically connected to the fourth node N4.

[0236] The light-emitting control signal EM provided by the light-emitting control line EM_L undergoes high-low level transitions, thereby controlling the light-emitting control module 14, i.e., the light-emitting control transistor M6, to turn on or off. When the light-emitting control signal EM is at an enabled level, it controls the light-emitting control transistor M6 to turn on, driving the current Id into the LED to emit light; when the light-emitting control signal EM is at a disabled level, it controls the light-emitting control transistor M6 to turn off. When the light-emitting control transistor M6 is a P-type transistor, the enabled level of the light-emitting control signal EM is low; when the light-emitting control transistor M6 is an N-type transistor, the enabled level of the light-emitting control signal EM is high. The light-emitting control transistor M6 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor; the light-emitting control transistor M6 can be a single-gate transistor, a dual-gate transistor, or a multi-gate transistor.

[0237] Optionally, referring to Figures 32 and 37, the pixel circuit PX also includes a reset module 15; the control terminal of the reset module 15 is electrically connected to the sixth shift register unit 26, and the reset module 15 is electrically connected between the second reference voltage terminal and the first electrode of the light-emitting element LED; the first electrode of the light-emitting element LED is also electrically connected to the driving module 10.

[0238] The pixel circuit PX includes a reset module 15. The control terminal of the reset module 15 is electrically connected to the sixth shift register unit 26 via the second reset scan line Scan4_L, and receives the second reset scan signal Scan4 transmitted by the second reset scan line Scan4_L. The reset module 15 is electrically connected between the second reference voltage terminal and the first electrode of the light-emitting element LED, where the first electrode of the light-emitting element LED is the anode of the light-emitting element LED.

[0239] The optional reset module 15 includes a second reset transistor M7. The control terminal of the reset module 15 is the gate of the second reset transistor M7, and the gate of the second reset transistor M7 is electrically connected to the second reset scan line Scan4_L. The first electrode of the second reset transistor M7 is electrically connected to the second reference voltage terminal, and the second reference voltage terminal provides a second reset signal Vref2 to the second reset transistor M7 through the second reset line Vref2_L. The second electrode of the second reset transistor M7 and the anode of the light-emitting element LED are electrically connected to the fourth node N4. An optional third reference voltage terminal multiplexes the second reference voltage terminal, and the third reset line Vref1_L multiplexes the second reset line Vref2_L.

[0240] The second reset scan signal Scan4, provided by the second reset scan line Scan4_L, undergoes high-to-low level transitions to control the second reset transistor M7 to turn on or off. When the second reset scan signal Scan4 is at an enabled level, it turns on the second reset transistor M7, and the second reset signal Vref2 is written to the fourth node N4 to reset the anode of the LED. When the second reset scan signal Scan4 is at a disabled level, it turns off the second reset transistor M7. When the second reset transistor M7 is a P-type transistor, the enabled level of the second reset scan signal Scan4 is low; when the second reset transistor M7 is an N-type transistor, the enabled level of the second reset scan signal Scan4 is high. The second reset transistor M7 can be a low-temperature polysilicon transistor or a metal-oxide-semiconductor transistor; the second reset transistor M7 can be a single-gate transistor, a dual-gate transistor, or a multi-gate transistor.

[0241] During the display time of one frame, in the same pixel circuit PX, the second reset transistor M7 can be turned on when the light-emitting control transistor M6 is turned off, to reset the fourth node N4, clear the residual electrical signal of the fourth node N4 during the display time of the previous frame, and will not affect the magnitude of the drive current Id.

[0242] Optionally, referring to Figures 32 and 37, the coupling module 12 includes a coupling capacitor C1; the pixel circuit PX also includes a storage module 16, which includes a storage capacitor C2; the first plate of the storage capacitor C2 is electrically connected to a first power supply terminal, which is also electrically connected to the driving module 10; the second plate of the storage capacitor C2 is electrically connected to a first node N1, or the second plate of the storage capacitor C2 is electrically connected to a second node N2.

[0243] For example, referring to Figure 37, when the second plate of storage capacitor C2 and the first plate of coupling capacitor C1 are electrically connected to the second node N2, storage capacitor C2 can store the potential of the second node N2. During the data writing period of pixel circuit PX, the potential of the second node N2 changes, and storage capacitor C2 can store the changed potential of the second node N2 without affecting the coupling of the potential change ΔVN2 of the second node N2 to the first node N1, where the change in the first node N1 is ΔVN1 = ΔVN2. During the period when pixel circuit PX drives the light-emitting element LED to display light, storage capacitor C2 can maintain the potential stability of the second node N2, thereby maintaining the stability of the first node N1, so that pixel circuit PX provides a stable driving current to the light-emitting element LED, where driving current Id = B × ΔVN1. 2 =B×△VN2 2 =B×(Data-Vref3) 2 , B=(1 / 2)×μ×Cox×(W / L).

[0244] In other alternative embodiments, the second plate of the storage capacitor C2 is electrically connected to the second plate of the coupling capacitor C1 at the first node N1.

[0245] Optionally, referring to Figures 31, 33, and 37, the sixth shift register unit 26 reuses the fourth shift register unit 24; in the same pixel circuit PX, the control terminal of the reset module 15 and the control terminal of the initialization module 17 are connected to the same fourth shift register unit 24; or, the sixth shift register unit 26 reuses the first shift register unit 21; in the same pixel circuit PX, the control terminal of the reset module 15 and the control terminal of the compensation module 13 are connected to the same first shift register unit 21.

[0246] As described above, the sixth shift register unit 26 reuses the fourth shift register unit 24, so the channel type of the second reset transistor M7 is the same as the channel type of the initialization transistor M5. Alternatively, the sixth shift register unit 26 reuses the first shift register unit 21, so the channel type of the second reset transistor M7 is the same as the channel type of the compensation transistor M4. By multiplexing shift register units and signals, the number of driving circuits can be reduced, which is beneficial for achieving a narrow bezel on the display panel 01, and also facilitates circuit layout, simplifying the layout difficulty.

[0247] It should be noted that, in any embodiment of this application, the transistors in the pixel circuit PX described above can be single-gate transistors, dual-gate transistors, or multi-gate transistors. If a single-gate transistor is defined as a switching device, then a multi-gate transistor can be multiple switching devices electrically connected. Figure 38 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application.

[0248] In an exemplary embodiment, the first reset unit 11B includes at least one first switching device. Referring to FIG. 37, when the first reset unit 11B includes a first switching device M1, the first end of the first switching device M1 is connected to the reset scan line Scan2_L, the second end of the first switching device M1 is connected to the first reset line Vref3_L for outputting the first reset signal Vref3, and the third end of the first switching device M1 is electrically connected to the data writing unit 11A at the second node N2. Referring to FIG. 38, when the first reset unit 11B includes at least two first switching devices (such as M1-1 and M1-2), the first ends of each first switching device M1-1 and M1-2 are respectively connected to the reset scan line Scan2_L, the second ends of each first switching device M1-1 and M1-2 are interconnected with the third ends of adjacent first switching devices, there is a first switching device M1-1 whose second end is connected to the first reset line Vref3_L, and there is a first switching device M1-2 whose third end is electrically connected to the data writing unit 11A at the second node N2.

[0249] In an optional embodiment, the data writing unit 11A includes at least one second switching device. Referring to FIG. 37, when the data writing unit 11A includes a second switching device M2, the first end of the second switching device M2 is connected to the write scan line SP_L, the second end of the second switching device M2 is connected to the data line Data_L for outputting the data signal Data, and the third end of the second switching device M2 is electrically connected to the first reset unit 11B at the second node N2. Referring to FIG. 38, when the data writing unit 11A includes at least two second switching devices (such as M2-1 and M2-2), the first ends of each second switching device M2-1 and M2-2 are respectively connected to the write scan line SP_L, the second ends of each second switching device M2-1 and M2-2 are interconnected with the third ends of adjacent second switching devices, one second switching device M2-1 has its second end connected to the data line Data_L, and one second switching device M2-2 has its third end electrically connected to the first reset unit 11B at the second node N2.

[0250] In an optional embodiment, the compensation module 13 includes at least one fourth switching device. Referring to FIG38, when the compensation module 13 includes one fourth switching device M4, the first end of the fourth switching device M4 is connected to the compensation scan line Scan3_L, the second end of the fourth switching device M4 is electrically connected to the first end of the drive module 10 at the third node N3, and the third end of the fourth switching device M4 is electrically connected to the control terminal of the drive module 10 at the first node N1. Referring to FIG37, when the compensation module 13 includes at least two fourth switching devices (such as M4-1 and M4-2), the first ends of each fourth switching device M4-1 and M4-2 are respectively connected to the compensation scan line Scan3_L, the second ends of each fourth switching device M4-1 and M4-2 are interconnected with the third ends of adjacent fourth switching devices, one fourth switching device M4-2 has its second end connected to the first end of the drive module 10, and one fourth switching device M4-1 has its third end connected to the control terminal of the drive module 10.

[0251] In an optional embodiment, the initialization module 17 includes at least one fifth switching device. Referring to FIG38, when the initialization module 17 includes one fifth switching device M5, the first end of the fifth switching device M5 is connected to the initialization scan line Scan1_L, the second end of the fifth switching device M5 is connected to the third reset line Vref1_L for outputting the initialization signal Vref1, and the third end of the fifth switching device M5 is connected to the control terminal of the drive module 10 at the first node N1. Referring to FIG37, when the initialization module 17 includes at least two fifth switching devices (such as M5-1 and M5-2), the first ends of each fifth switching device M5-1 and M5-2 are respectively connected to the initialization scan line Scan1_L, the second ends of each fifth switching device M5-1 and M5-2 are interconnected with the third ends of adjacent fifth switching devices, there is a fifth switching device M5-1 whose second end is connected to the third reset line Vref1_L, and there is a fifth switching device M5-2 whose third end is connected to the control terminal of the drive module 10.

[0252] In an optional embodiment, the reset module 15 includes at least one seventh switching device. Referring to FIG. 37, when the reset module 15 includes one seventh switching device M7, the first end of the seventh switching device M7 is connected to the second reset scan line Scan4_L, the second end of the seventh switching device M7 is connected to the second reset line Vref2_L for outputting the second reset signal Vref2, and the third end of the seventh switching device M7 is connected to the light emission control module 14 at the fourth node N4. Referring to FIG. 38, when the reset module 15 includes at least two seventh switching devices (such as M7-1 and M7-2), the first ends of each seventh switching device M7-1 and M7-2 are respectively connected to the second reset scan line Scan4_L, the second ends of each seventh switching device M7-1 and M7-2 are interconnected with the third ends of adjacent seventh switching devices, there is a seventh switching device M7-1 whose second end is connected to the second reset line Vref2_L, and there is a seventh switching device M7-2 whose third end is connected to the light emission control module 14 at the fourth node N4.

[0253] The working principle of the pixel circuit provided in the embodiments of this application will be explained below with reference to timing.

[0254] The optional pixel circuit PX operates by at least the following stages executed sequentially: a first stage T0, a second stage T1, a third stage T2, and a light-emitting stage T3. In the first stage T0, the initialization transistor M5 is turned on; in the second stage T1, the compensation transistor M4 is turned on; in the third stage T2, the write transistor M2 is turned on. The pixel circuit PX also operates by a fourth stage T4; in the fourth stage T4, the first reset transistor M1 is turned on. Optionally, the fourth stage T4 overlaps with the first stage T0. Optionally, the fourth stage T4 overlaps with the second stage T1. Optionally, the fourth stage T4 does not overlap with the third stage T2. Optionally, the end time of the fourth stage T4 is earlier than the start time of the third stage T2. In one optional embodiment, the fourth stage T4 overlaps with the first stage T0, and the first stage T0 is located within the fourth stage T4. In another optional embodiment, the fourth stage T4 overlaps with the second stage T1, and the second stage T1 is located within the fourth stage T4.

[0255] Figure 39 is a timing diagram of another pixel group provided in an embodiment of this application, and Figure 40 is a timing diagram of another pixel group provided in an embodiment of this application. The driving timing of Figures 39 and 40 corresponds to the pixel circuit PX in Figure 37.

[0256] Referring to Figures 37 to 40, in the first stage T0, the initialization scan signal Scan1 is at an enable level low, and the initialization transistor M5 is turned on; the reset scan signal Scan2 is at an enable level low, and the first reset transistor M1 is turned on; the compensation scan signal Scan3 is at an enable level high, and the compensation transistor M4 is turned off; the write scan signal SP is at an enable level high, and the write transistor M2 is turned off. Then, in the first stage T0, the initialization signal Vref1 is written to the first node N1, and the potential of the first node N1 is initialized to Vref1; the first reset signal Vref3 is written to the second node N2, and the potential of the second node N2 is reset to Vref3.

[0257] In the second stage T1, the initialization scan signal Scan1 is at a high level (disabled), and the initialization transistor M5 is turned off; the reset scan signal Scan2 is at a low level (enabled), and the first reset transistor M1 is turned on; the compensation scan signal Scan3 is at a low level (enabled), and the compensation transistor M4 is turned on; the write scan signal SP is at a high level (disabled), and the write transistor M2 is turned off. In the second stage T1, the first reset signal Vref3 is continuously written to the second node N2, and the potential of the second node N2 can be completely reset to Vref3; the first power signal PV1 is written to the third node N3, and then continuously written to the first node N1. At this time, the driving transistor M3 performs threshold compensation until the potential of the first node N1 is PV1 + Vth.

[0258] During the enable period of the 2×j-1 write scan signal SP (2×j-1), which is the third stage T2 of the 2×j-1 row, all write transistors M2 of the 2×j-1 row are turned on, and the pixel circuit PX of the 2×j-1 row performs data writing; the potential of the second node N2 of the pixel circuit PX of the 2×j-1 row jumps from Vref3 to the data signal Data, and the change in the second node N2 ΔVN2 is coupled to the first node N1 through the coupling capacitor C1, so that ΔVN1=ΔVN2, VN1=PV1+Vth+ΔVN1=PV1+Vth+ΔVN2<PV1+Vth (ΔVN2<0, Vth<0), Vgs=VN1-PV1=Vth+ΔVN1=Vth+ΔVN2<Vth<0, and the driving transistor M3 is fully turned on. In sequence, during the enable period of the 2×j write scan signal SP (2×j), which is the third stage T2 of the 2×j row, all write transistors M2 of the 2×j row are turned on, and the pixel circuit PX of the 2×j row performs data writing; in the pixel circuit PX of the 2×j row, △VN1=△VN2, VN1=PV1+Vth+△VN1=PV1+Vth+△VN2<PV1+Vth (△VN2<0, Vth<0), Vgs=VN1-PV1=Vth+△VN1=Vth+△VN2<Vth<0, and the driving transistor M3 is fully turned on.

[0259] During the light-emitting stage T3, the light-emitting control signal EM jumps to the enable level, the light-emitting control transistor M6 is turned on, the write transistor M2 and the compensation transistor M4 are turned off, and the driving transistor M3 forms a driving current Id based on its gate electrical signal PV1+Vth+△VN2 and the first power supply signal PV1. The driving current Id = B×(Vgs-Vth). 2 =B×△VN1 2 =B×△VN2 2 The light-emitting element (LED) can display the corresponding brightness according to the driving current Id. The display grayscale of the pixel circuit PX can be controlled by controlling the brightness and light-emitting duration of the LED. Wherein, B = (1 / 2) × μ × Cox × (W / L), μ is the electron mobility of the driving transistor M3, Cox is the channel capacitance per unit area of ​​the driving transistor M3, and W / L is the channel width-to-length ratio of the driving transistor M3.

[0260] For the fourth stage T4, in the same pixel circuit PX, the enable period of the reset scan signal Scan2 overlaps with the first stage T0, which allows the first node N1 and the second node N2 to be reset simultaneously. This effectively avoids the situation where the second node N2 is floating and is pulled low by the coupling of the first node N1. Thus, the high potential Vref3 written to the second node N2 will not be anti-coupled to the first node N1. In other words, the potential of the second node N2 will not affect the potential of the first node N1, ensuring that the driving transistor M3 is fully turned on. This is beneficial for the subsequent T1 stage to perform sufficient threshold compensation on the driving transistor M3 and improve the display effect.

[0261] In this way, the reset period of the second node N2 can be independently controlled. For example, the reset period of the second node N2 can overlap with the initialization period of the first node N1, ensuring that the initialized potential of the first node N1 is not affected by the potential changes of the second node N2, and that the reset potential of the second node N2 is not affected by the potential changes of the first node N1. This is beneficial for the accurate initialization of the potential of the first node N1 and the accurate reset of the potential of the second node N2. Similarly, the reset period of the second node N2 can overlap with the threshold compensation period of the first node N1, ensuring that the threshold compensated potential of the first node N1 is not affected by the potential changes of the second node N2, and that the reset potential of the second node N2 is not affected by the potential changes of the first node N1. This is beneficial for the accurate compensation of the potential of the first node N1 and the accurate reset of the potential of the second node N2.

[0262] In other words, in the first stage T0, the voltage of the first plate of the coupling capacitor C1 is reset to the voltage level corresponding to the first reset signal Vref3 by the first reset unit 11B; in the first stage T0, the voltage of the second plate of the coupling capacitor C1 is reset to the voltage level corresponding to the initialization signal Vref1 by the initialization module 17.

[0263] In the second stage T1, the control terminal of the drive module 10 is compensated by the compensation module 13; in the second stage T1, the voltage of the first plate of the coupling capacitor C1 is reset to the voltage level corresponding to the first reset signal Vref3 by the first reset unit 11B.

[0264] In the third stage T2, the data signal Data is transmitted to the second node N2 through the data writing unit 11A.

[0265] During the light-emitting stage T3, the light-emitting control signal EM is transmitted to the light-emitting control module 14 so that the light-emitting control module 14 works according to the light-emitting control signal EM and drives the light-emitting element LED to work according to the driving current Id generated by the driving module 10.

[0266] Optionally, Figure 41 is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application. Referring to Figures 32 and 41, the pixel circuit further includes a dimming control module 19; the control terminal of the dimming control module 19 is electrically connected to the dimming shift register unit, and the dimming control module 19 is electrically connected between the first power supply terminal and the driving module 10. Optionally, the dimming shift register unit reuses the fifth shift register unit 25.

[0267] The dimming control module 19 includes a dimming control transistor M8. The first terminal of the dimming control transistor M8 is electrically connected to a first power supply terminal via a first power line PV1_L, receiving a first power signal PV1. The second terminal of the dimming control transistor M8 is electrically connected to the source of the driving transistor M3 at a fifth node N5. Optionally, both the dimming control transistor M8 and the light-emitting control transistor M6 may be low-temperature polysilicon transistors (LSPs), or both may be metal-oxide-semiconductor transistors (MOTS). Optionally, at least one of the dimming control transistor M8 and the light-emitting control transistor M6 may be a dual-gate transistor.

[0268] The display panel 01 also includes a fifth driving circuit VSR5, which includes multiple fifth shift register units 25. In the same pixel circuit PX, the dimming shift register unit reuses the fifth shift register unit 25. The gate of the dimming control transistor M8 of the dimming control module 19 can also be connected to the gate of the light-emitting control transistor M6 of the light-emitting control module 14 through the light-emitting control line EM_L in the same fifth shift register unit 25. The fifth shift register unit 25 is used to control the conduction of the dimming control transistor M8 and the light-emitting control transistor M6 during the light-emitting stage T3, driving the light-emitting element LED to emit light. Since the dimming shift register unit reuses the fifth shift register unit 25, the channel type of the dimming control transistor M8 and the channel type of the light-emitting control transistor M6 are the same. By multiplexing the shift register units and the signal, the number of driving circuits can be reduced, which is beneficial for reducing the number of bridging signal lines, for achieving a narrow bezel of the display panel 01, and for circuit layout, simplifying the layout difficulty.

[0269] Optionally, referring to Figures 32 and 41, the pixel circuit PX also includes a bias module 18; the control terminal of the bias module 18 is electrically connected to the sixth shift register unit, and the bias module is electrically connected between the bias signal terminal and the drive transistor M3.

[0270] The bias module 18 includes a bias transistor M9. The first terminal of the bias transistor M9 is electrically connected to the bias signal terminal through the bias signal line DVH_L to receive the bias signal DVH. The second terminal of the bias transistor M9 is electrically connected to the source of the driving transistor M3 at the fifth node N5. The display panel 01 also includes a sixth driving circuit VSR6, which includes multiple sixth shift register units 26. In the same pixel circuit PX, the gate of the bias transistor M9 of the bias module 18 can also be connected to the gate of the second reset transistor M7 of the reset module 15 through the second reset scan line Scan4_L in the same sixth shift register unit 26. The sixth shift register unit 26 is also used to control the bias transistor M9 of the pixel circuit PX to adjust the bias of the driving transistor M3. By multiplexing the shift register units and the signal, the number of driving circuits can be reduced, which is beneficial for reducing the number of bridging signal lines, achieving a narrow bezel for the display panel 01, and simplifying the circuit layout.

[0271] Optionally, referring to Figures 30, 31, 35, 37, and 41, the display panel includes multiple signal lines, including a third reset line Vref1_L and a second reset line Vref2_L. The third reset line Vref1_L is electrically connected to a third reference voltage terminal, which provides an initialization signal Vref1 to the third reset line Vref1_L. The second reset line Vref2_L is electrically connected to a second reference voltage terminal, which provides a second reset signal Vref2 to the second reset line Vref2_L. The optional display panel includes multiple signal lines, including a first power line PV1_L, a third reset line Vref1_L, and a first reset line Vref3_L. The first power line PV1_L is electrically connected to the drive module 10 and provides a first power signal PV1 to the drive module 10. The third reset line Vref1_L is electrically connected to a third reference voltage terminal, which provides an initialization signal Vref1 to the third reset line Vref1_L. The first reset line Vref3_L is electrically connected to a first reference voltage terminal, which provides a first reset signal Vref3 to the first reset line Vref3_L.

[0272] In an optional embodiment, the first power signal PV1 is less than or equal to the first reset signal Vref3. Thus, during the display time of one frame, the first reset transistor M1 can turn on before the write transistor M2 turns on, resetting the second node N2 and clearing the residual electrical signal of the second node N2 from the display time of the previous frame. Before the writing stage T2 of all pixel circuits PX, the potential of the second node N2 can be uniformly unified to Vref3, which simplifies the control of the driving current and also improves the uniformity of the pixel circuits PX in the display panel 01, thereby enhancing the display uniformity of the display panel 01.

[0273] In an optional embodiment, the first power signal PV1 is equal to the first reset signal Vref3, then the first power line PV1_L multiplexes the first reset line Vref3_L. That is, multiplexing the first power line PV1_L providing the first power signal PV1 with the first reset line Vref3_L providing the first reset signal Vref3 helps reduce the number of bridging signal lines, simplifies circuit layout, reduces design complexity, and also facilitates the achievement of a narrow bezel and circuit layout for the display panel 01, simplifying the layout process.

[0274] In an optional embodiment, both the first reset signal Vref3 and the first power signal PV1 are greater than 0V. The first reset signal Vref3 can be set to a positive electrical signal greater than or equal to the first power signal PV1. In this case, the data signal Data can be an electrical signal with a small absolute value, causing the data signal Data on the data line Data_L to vary near 0V. This helps reduce power consumption, improve charging rate, and achieve high resolution and high refresh rate. Furthermore, by setting the first reset signal Vref3 to a positive electrical signal greater than or equal to the first power signal PV1, the reset period of the second node N2 overlaps with the compensation period of the first node N1. This ensures that the potential of the first node N1 after threshold compensation is not affected by the potential changes of the second node N2, and also ensures that the potential of the second node N2 after reset is not affected by the potential changes of the first node N1. This facilitates accurate compensation of the first node N1 potential and accurate reset of the second node N2 potential.

[0275] In an optional embodiment, the initialization signal Vref1 is less than the first reset signal Vref3. The initialization signal Vref1 is less than 0V, while the first reset signal Vref3 and the first power signal PV1 are both greater than 0V. During the display time of one frame, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on. The initialization signal Vref1 of the third reset line Vref1_L initializes the first node N1, clearing the residual electrical signal of the first node N1 during the display time of the previous frame. Since the initialization signal Vref1 is less than the first reset signal Vref3, and / or the initialization signal Vref1 is less than 0V, when the initialization transistor M5 is turned on, the initialization signal Vref1 of the third reset line Vref1_L initializes the driving transistor M3. This facilitates the complete conduction of the driving transistor M3, ensuring that the threshold voltage Vth can be fully compensated to the first node N1 during subsequent threshold compensation. When the pixel circuit PX emits light, the driving current Id is not affected by the threshold voltage Vth of the driving transistor M3, improving the display uniformity of the display panel.

[0276] In an optional embodiment, the initialization signal Vref1 is less than or equal to the second reset signal Vref2. Both the initialization signal Vref1 and the second reset signal Vref2 are less than 0V. During the display time of one frame, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on, and the initialization signal Vref1 of the third reset line Vref1_L initializes the first node N1, clearing the residual electrical signal of the first node N1 during the display time of the previous frame. The initialization signal Vref1 is less than or equal to the second reset signal Vref2, and / or the initialization signal Vref1 is less than 0V; when the initialization transistor M5 is turned on, the initialization signal Vref1 initializes the driving transistor M3, which helps to make the driving transistor M3 fully turn on; when the second reset transistor M7 is turned on, the second reset signal Vref2 resets the fourth node N4, which helps to clear the residual electrical signal of the fourth node N4 in the display time of the previous frame, so that when the pixel circuit PX displays light in the light-emitting stage T3, the driving current Id is not affected by the residual electrical signal of the fourth node N4 in the previous frame, and the light-emitting element LED can display the corresponding brightness according to the driving current Id, thereby improving the display uniformity of the display panel.

[0277] In an optional embodiment, the initialization signal Vref1 is equal to the second reset signal Vref2, then the third reset line Vref1_L multiplexes the second reset line Vref2_L. That is, the third reset line Vref1_L providing the initialization signal Vref1 multiplexes the second reset line Vref2_L providing the second reset signal Vref2, which helps reduce the number of bridging signal lines, simplifies circuit layout, reduces design complexity, and also facilitates the achievement of a narrow bezel and circuit layout for the display panel 01, simplifying the layout process.

[0278] Optionally, referring to Figures 11, 14, 18, 21, 24, 32, and 33, the display panel includes a third driving circuit VSR3 and a fifth driving circuit VSR5. The third driving circuit VSR3 includes multiple third shift register units 23, which are electrically connected to the gate of the first reset transistor M1. The fifth driving circuit VSR5 includes multiple fifth shift register units 25, which are electrically connected to the light-emitting control module 14. Optionally, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a first side and a second side opposite each other along the row direction, where the row direction is the arrangement direction of multiple pixel circuits PX in a row of pixel circuits PX. The fifth driving circuit VSR5 is located in the non-display area NA and is at least located on the first side of the display area AA. The third driving circuit VSR3 is located in the non-display area NA and is at least located on the second side of the display area AA. Optionally, the fifth driving circuit VSR5 and the third driving circuit VSR3 are located on different sides of the display area AA.

[0279] In an optional embodiment, referring to Figures 11 and 14, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on both sides of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display area NA on one side of the display area AA.

[0280] In an optional embodiment, referring to Figures 18 and 21, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display areas NA on both sides of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display areas NA on both sides of the display area AA.

[0281] In an optional embodiment, referring to FIG24, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on one side of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display areas NA on opposite sides of the display area AA.

[0282] In an optional embodiment, referring to Figures 32 and 33, the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on one side of the display area AA, and the third shift register unit 23 of the third driving circuit VSR3 is located in the non-display area NA on one side of the display area AA. The fifth driving circuit VSR5 and the third driving circuit VSR3 are located on different sides of the display area AA. Specifically, the third driving circuit VSR3 and the fifth driving circuit VSR5 are located in the non-display areas NA on opposite sides of the display area AA.

[0283] The embodiments of this application do not specifically limit the positions of the fifth shift register unit 25 and the third shift register unit 23, and are not limited to the above examples.

[0284] Based on the same concept, this application also provides a display device. Figure 42 is a schematic diagram of the structure of a display device provided in this application. As shown in Figure 42, the display device 02 includes a display panel 01 provided in any embodiment of this application. The display device 02 provided in this application can be a mobile phone as shown in Figure 42, or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. This application does not make any special limitations on these categories.

Claims

1. A display panel, comprising: Multiple pixel circuits arranged in an array; The pixel circuit includes a driving transistor, a writing module, a coupling module, a compensation module, and a light-emitting element; The writing module is electrically connected to the gate of the driving transistor through the coupling module; the compensation module is electrically connected between the gate and drain of the driving transistor; the light-emitting element is electrically connected to the driving transistor. The pixel circuits described in multiple rows constitute a pixel group; The display panel further includes a first driving circuit and a second driving circuit; the first driving circuit is used to sequentially control the compensation modules of multiple rows of pixel circuits in each pixel group to perform threshold compensation on the driving transistor; the second driving circuit is used to sequentially control the writing modules of each row of pixel circuits to write data signals to the gate of the driving transistor. The first driving circuit includes a plurality of first shift register units; the first shift register units are electrically connected to the compensation modules of multiple rows of pixel circuits in the same pixel group; The second driving circuit includes a plurality of second shift register units; each of the second shift register units is electrically connected to the write module of each row of pixel circuits.

2. The display panel according to claim 1, wherein, In the same pixel circuit, the time period during which the pixel circuit performs threshold compensation is located before the time period during which the pixel circuit performs data writing, and the two do not overlap.

3. The display panel according to claim 1, wherein, The write module includes a write transistor; The first terminal of the write transistor receives the data signal, and the second terminal of the write transistor is electrically connected to the first terminal of the coupling module at the second node; the gate of the write transistor is electrically connected to the second shift register unit. The compensation module includes a compensation transistor; The first terminal of the compensation transistor is electrically connected to the drain of the driving transistor, and the second terminal of the compensation transistor is electrically connected to the gate of the driving transistor; the gate of the compensation transistor is electrically connected to the first shift register unit.

4. The display panel according to claim 3, wherein, The writing module further includes a first reset transistor; the first terminal of the first reset transistor receives a first reset signal, and the second terminal of the first reset transistor is electrically connected to the second node. The display panel further includes a third driving circuit; the third driving circuit is used to sequentially control the first reset transistor of each row of pixel circuits to reset the second node. The third driving circuit includes multiple third shift register units; the third shift register units are electrically connected to the gate of the first reset transistor.

5. The display panel according to claim 4, wherein, In the same pixel circuit, the time period during which the pixel circuit resets the second node overlaps with the time period during which the pixel circuit performs threshold compensation.

6. The display panel according to claim 4, wherein, Each of the third shift register units is electrically connected to the gate of the first reset transistor of each row of pixel circuits; The third shift register unit reuses the second shift register unit; the gate of the first reset transistor of the pixel circuit in the i-th row and the gate of the write transistor of the pixel circuit in the ie-th row are connected to the same second shift register unit; where i and e are both integers, i > e ≥ 2.

7. The display panel according to claim 4, wherein, The third shift register unit is electrically connected to the gate of the first reset transistor of multiple rows of pixel circuits in the same pixel group.

8. The display panel according to claim 7, wherein, The third shift register unit reuses the second shift register unit; The gate of the first reset transistor of the pixel circuit in the j-th pixel group is connected to the gate of the write transistor of the pixel circuit in the (j-1)×kp-th row in the same second shift register unit. Where j, k, and p are all integers, j > 1, k is the row number of the pixel circuit in the pixel group, and p ≥ 0.

9. The display panel according to claim 7, wherein, The third shift register unit reuses the first shift register unit; In the same pixel circuit, the gate of the first reset transistor and the gate of the compensation transistor are connected to the same first shift register unit.

10. The display panel according to claim 1, wherein, The coupling module includes a coupling capacitor; The pixel circuit also includes a storage module, which includes a storage capacitor. The first plate of the storage capacitor is electrically connected to the first power supply terminal; the second plate of the storage capacitor is electrically connected to the first plate of the coupling capacitor, or the second plate of the storage capacitor is electrically connected to the second plate of the coupling capacitor.

11. The display panel according to claim 1, wherein, The pixel circuit further includes an initialization module; the initialization module includes an initialization transistor; the first terminal of the initialization transistor receives an initialization signal, and the second terminal of the initialization transistor is electrically connected to the gate of the driving transistor at a first node; The display panel further includes a fourth driving circuit; the fourth driving circuit is used to sequentially control the initialization transistors of each row of pixel circuits to initialize the first node; The fourth driving circuit includes a plurality of fourth shift register units; the fourth shift register units are electrically connected to the gate of the initialization transistor.

12. The display panel according to claim 11, wherein, During the display time of a frame, within the same pixel circuit, the period during which the pixel circuit initializes the first node is prior to the period during which the pixel circuit performs threshold compensation.

13. The display panel according to claim 11, wherein, The write module includes a write transistor; The first terminal of the write transistor receives the data signal, and the second terminal of the write transistor is electrically connected to the first terminal of the coupling module at the second node; the gate of the write transistor is electrically connected to the second shift register unit. Each of the fourth shift register units is electrically connected to the gate of the initialization transistor of each row of pixel circuits; The fourth shift register unit reuses the second shift register unit; the gate of the initialization transistor of the pixel circuit in the i-th row and the gate of the write transistor of the pixel circuit in the ir-th row are connected to the same second shift register unit; where i and r are both integers, i > r ≥ 2.

14. The display panel according to claim 11, wherein, The fourth shift register unit is electrically connected to the gate of the initialization transistor of the multiple rows of pixel circuits in the same pixel group.

15. The display panel according to claim 14, wherein, The fourth shift register unit reuses the first shift register unit; The initialization module of the j-th pixel group and the compensation module of the js-th pixel group are connected to the same first shift register unit; where j and s are both integers, j > s ≥ 1.

16. The display panel according to claim 14, wherein, The fourth shift register unit reuses the second shift register unit; The gate of the initialization transistor of the pixel circuit in the j-th pixel group is connected to the gate of the write transistor of the pixel circuit in the (j-1)×kq-th row in the same second shift register unit. Where j, k, and q are all integers, j > 1, k is the number of rows of the pixel circuit in the pixel group, and q ≥ 1.

17. The display panel according to claim 11, wherein, During the display time of a frame, in the same pixel circuit, the period during which the pixel circuit initializes the first node alternates with the period during which the pixel circuit performs threshold compensation, and the period during which the pixel circuit performs threshold compensation is the last period.

18. The display panel according to claim 1, wherein, The pixel circuit also includes a light-emitting control module; the light-emitting control module is electrically connected between the driving transistor and the light-emitting element; The display panel further includes a fifth driving circuit, which is used to sequentially turn on the light emission control modules of multiple rows of pixel circuits in each pixel group.

19. The display panel according to claim 1, wherein, The pixel circuit also includes a reset module; the reset module is electrically connected to the light-emitting element. In the same pixel circuit, the reset module and the compensation module are connected to the same first shift register unit, or the reset module and the write module are connected to the same second shift register unit.

20. The display panel according to claim 4, wherein, The driving transistor is electrically connected to the first power supply terminal, and the first power supply terminal provides a first power signal. The first power signal is less than or equal to the first reset signal.

21. The display panel according to claim 4, wherein, The display panel includes multiple signal lines, including a first power line and a first reset line; The first power line is electrically connected to the driving transistor, and the first reset line is electrically connected to the first terminal of the first reset transistor; The first power line reuses the first reset line.

22. The display panel according to claim 11, wherein, The writing module includes a first reset transistor; the first terminal of the first reset transistor receives a first reset signal, and the second terminal of the first reset transistor is electrically connected to the first terminal of the coupling module at a second node; the display panel further includes a third driving circuit; the third driving circuit includes a plurality of third shift register units; the third shift register units are electrically connected to the gate of the first reset transistor. The display panel includes multiple signal lines, including a first reset line and a third reset line; The first reset line is electrically connected to the first terminal of the first reset transistor; the third reset line is electrically connected to the first terminal of the initialization transistor.

23. The display panel according to claim 22, wherein, The initialization signal is less than the first reset signal.

24. The display panel according to claim 22, wherein, The driving transistor is electrically connected to the first power supply terminal, and the first power supply terminal provides a first power signal. The initialization signal is less than 0V, and both the first reset signal and the first power supply signal are greater than 0V.

25. The display panel according to claim 22, wherein, The pixel circuit further includes a reset module; the reset module includes a second reset transistor; the first terminal of the second reset transistor receives a second reset signal, and the second terminal of the second reset transistor is electrically connected to the light-emitting element at a fourth node; The display panel further includes a sixth driving circuit; the sixth driving circuit is used to sequentially control the second reset transistor of each row of pixel circuits to reset the fourth node; The sixth driving circuit includes multiple sixth shift register units; the sixth shift register units are electrically connected to the gate of the second reset transistor.

26. The display panel according to claim 25, wherein, The sixth shift register unit reuses the first shift register unit. In the same pixel circuit, the gate of the second reset transistor is connected to the compensation module in the same first shift register unit. Alternatively, the sixth shift register unit may reuse the third shift register unit, and in the same pixel circuit, the gate of the second reset transistor and the gate of the first reset transistor may be connected to the same third shift register unit. Alternatively, the sixth shift register unit may reuse the fourth shift register unit, and in the same pixel circuit, the gate of the second reset transistor and the gate of the initialization transistor may be connected to the same fourth shift register unit.

27. The display panel according to claim 11, wherein, The pixel circuit further includes a reset module; the reset module includes a second reset transistor; the first terminal of the second reset transistor receives a second reset signal, and the second terminal of the second reset transistor is electrically connected to the light-emitting element at a fourth node; The display panel further includes a sixth driving circuit; the sixth driving circuit includes a plurality of sixth shift register units; the sixth shift register units are electrically connected to the gate of the second reset transistor; The display panel includes multiple signal lines, including a third reset line and a second reset line; the third reset line is electrically connected to the first terminal of the initialization transistor, and the second reset line is electrically connected to the first terminal of the second reset transistor.

28. The display panel according to claim 27, wherein, The initialization signal is less than or equal to the second reset signal.

29. The display panel according to claim 27, wherein, Both the initialization signal and the second reset signal are less than 0V.

30. The display panel according to claim 27, wherein, The third reset line reuses the second reset line.

31. The display panel according to claim 27, wherein, Either the initialization transistor or the second reset transistor is a low-temperature polysilicon transistor or a metal-oxide transistor.

32. The display panel according to claim 27, wherein, At least one of the initialization transistor and the second reset transistor is a dual-gate transistor.

33. The display panel according to claim 27, wherein, The pixel circuit also includes a bias module; The bias module is electrically connected between the bias signal terminal and the driving transistor; in the same pixel circuit, the bias module and the second reset transistor are connected to the same sixth shift register unit.

34. The display panel according to claim 18, wherein, The pixel circuit also includes a dimming control module; The dimming control module is electrically connected between the first power supply terminal and the driving transistor; the display panel also includes a dimming control circuit, which is used to sequentially turn on the dimming control modules of multiple rows of pixel circuits in each pixel group; The dimming control circuit includes multiple dimming shift registers; the dimming shift registers are electrically connected to the dimming control module.

35. The display panel according to claim 34, wherein, The dimming control circuit reuses the fifth driving circuit.

36. The display panel according to claim 4, wherein, The first reset transistor, the write transistor, and the compensation transistor are either low-temperature polysilicon transistors or metal-oxide transistors.

37. The display panel according to claim 4, wherein, At least one of the first reset transistor, the write transistor, and the compensation transistor is a dual-gate transistor.

38. The display panel according to claim 4, wherein, The pixel circuit further includes an initialization module; the initialization module includes an initialization transistor; the first terminal of the initialization transistor receives an initialization signal, and the second terminal of the initialization transistor is electrically connected to the gate of the driving transistor at a first node; The operation of the pixel circuit includes at least a first stage, a second stage, and a third stage executed sequentially. In the first stage, the initialization transistor is turned on; In the second stage, the compensation transistor is turned on; In the third stage, the write transistor is turned on; The operation of the pixel circuit also includes a fourth stage; In the fourth stage, the first reset transistor is turned on.

39. The display panel according to claim 38, wherein, The fourth stage overlaps with the first stage.

40. The display panel according to claim 38, wherein, The fourth stage overlaps with the second stage.

41. The display panel according to claim 38, wherein, The fourth stage does not overlap with the third stage.

42. The display panel according to claim 38, wherein, The end time of the fourth stage is earlier than the start time of the third stage.

43. The display panel according to claim 18, wherein, The writing module includes a first reset transistor; the first terminal of the first reset transistor receives a first reset signal, and the second terminal of the first reset transistor is electrically connected to the first terminal of the coupling module at the second node. The display panel further includes a third driving circuit; the third driving circuit includes a plurality of third shift register units; the third shift register units are electrically connected to the gate of the first reset transistor; The fifth driving circuit includes multiple fifth shift register units; the fifth shift register units are electrically connected to the light-emitting control module.

44. The display panel according to claim 43, wherein, The display panel includes a display area and a non-display area surrounding the display area. The display area includes a first side and a second side opposite each other along a row direction, where the row direction is the arrangement direction of a plurality of pixel circuits in a row of pixel circuits. The fifth driving circuit is located in the non-display area, and at least on the first side of the display area; The third driving circuit is located in the non-display area, and at least on the second side of the display area.

45. The display panel according to claim 44, wherein, The fifth driving circuit and the third driving circuit are located on different sides of the display area.

46. ​​A display panel, comprising: Multiple pixel circuits arranged in an array; The pixel circuit includes a driving module, a compensation module, a data writing unit, a coupling module, and a light-emitting element; The coupling module is electrically connected between the first node and the second node, and the control terminal of the driving module is electrically connected to the first node; the light-emitting element is electrically connected to the driving module. The control terminal of the compensation module is electrically connected to the first shift register unit, and the compensation module is electrically connected between the control terminal of the drive module and the first terminal of the drive module. The control terminal of the data writing unit is electrically connected to the second shift register unit, and the data writing unit is electrically connected between the data voltage terminal and the second node.

47. The display panel according to claim 46, wherein, The pixel circuit also includes a first reset unit; The control terminal of the first reset unit is electrically connected to the third shift register unit, and the first reset unit is electrically connected between the first reference voltage terminal and the second node.

48. The display panel according to claim 46, wherein, The pixel circuit also includes an initialization module; The control terminal of the initialization module is electrically connected to the fourth shift register unit, and the initialization module is electrically connected between the third reference voltage terminal and the first node.

49. The display panel according to claim 46, wherein, The pixel circuit also includes a light-emitting control module; The control terminal of the light-emitting control module is electrically connected to the fifth shift register unit, and the light-emitting control module is electrically connected between the driving module and the light-emitting element.

50. The display panel according to claim 49, wherein, The pixel circuit also includes a dimming control module; The control terminal of the dimming control module is electrically connected to the dimming shift register unit, and the dimming control module is electrically connected between the first power supply terminal and the drive module.

51. The display panel according to claim 50, wherein, The dimming shift register unit reuses the fifth shift register unit.

52. The display panel according to claim 46, wherein, The pixel circuit also includes a reset module; The control terminal of the reset module is electrically connected to the sixth shift register unit, and the reset module is electrically connected between the second reference voltage terminal and the first electrode of the light-emitting element. The first electrode of the light-emitting element is also electrically connected to the driving module.

53. The display panel according to claim 52, wherein, The pixel circuit also includes a bias module; The control terminal of the bias module is electrically connected to the sixth shift register unit, and the bias module is electrically connected between the bias signal terminal and the drive module.

54. The display panel according to claim 52, wherein, The pixel circuit further includes a first reset unit and an initialization module; the control terminal of the first reset unit is electrically connected to a third shift register unit, and the first reset unit is electrically connected between a first reference voltage terminal and the second node; the control terminal of the initialization module is electrically connected to a fourth shift register unit, and the initialization module is electrically connected between the third reference voltage terminal and the first node; The sixth shift register unit reuses the fourth shift register unit; in the same pixel circuit, the control terminal of the reset module and the control terminal of the initialization module are connected to the same fourth shift register unit; Alternatively, the sixth shift register unit may reuse the third shift register unit; in the same pixel circuit, the control terminal of the reset module and the control terminal of the first reset unit are connected to the same third shift register unit; Alternatively, the sixth shift register unit may reuse the first shift register unit; in the same pixel circuit, the control terminal of the reset module and the control terminal of the compensation module are connected to the same first shift register unit.

55. The display panel according to claim 46, wherein, The coupling module includes a coupling capacitor; The pixel circuit also includes a storage module, which includes a storage capacitor. The first plate of the storage capacitor is electrically connected to the first power supply terminal, and the first power supply terminal is also electrically connected to the driving module. The second plate of the storage capacitor is electrically connected to the first node, or the second plate of the storage capacitor is electrically connected to the second node.

56. The display panel according to claim 48, wherein, The pixel circuit also includes a reset module; the control terminal of the reset module is electrically connected to the sixth shift register unit, and the reset module is electrically connected between the second reference voltage terminal and the light-emitting element; The display panel includes multiple signal lines, including a third reset line and a second reset line. The third reset line is electrically connected to the third reference voltage terminal, and the third reference voltage terminal provides an initialization signal to the third reset line. The second reset line is electrically connected to the second reference voltage terminal, and the second reference voltage terminal provides a second reset signal to the second reset line.

57. The display panel according to claim 56, wherein, The initialization signal is less than or equal to the second reset signal.

58. The display panel according to claim 56, wherein, Both the initialization signal and the second reset signal are less than 0V.

59. The display panel according to claim 56, wherein, The third reset line reuses the second reset line.

60. The display panel according to claim 48, wherein, The pixel circuit further includes a first reset unit; the control terminal of the first reset unit is electrically connected to the third shift register unit, and the first reset unit is electrically connected between the first reference voltage terminal and the second node. The display panel includes multiple signal lines, including a first power line, a third reset line, and a first reset line. The first power line is electrically connected to the drive module and provides a first power signal to the drive module; The third reset line is electrically connected to the third reference voltage terminal, and the third reference voltage terminal provides an initialization signal to the third reset line. The first reset line is electrically connected to the first reference voltage terminal, and the first reference voltage terminal provides a first reset signal to the first reset line.

61. The display panel according to claim 60, wherein, The initialization signal is less than the first reset signal.

62. The display panel according to claim 60, wherein, The first power signal is less than or equal to the first reset signal.

63. The display panel according to claim 60, wherein, The initialization signal is less than 0V, and both the first reset signal and the first power supply signal are greater than 0V.

64. The display panel according to claim 60, wherein, The first power line reuses the first reset line.

65. The display panel according to claim 47, wherein, The compensation module includes a compensation transistor; the data writing unit includes a writing transistor; the first reset unit includes a first reset transistor. The first reset transistor, the write transistor, and the compensation transistor are either low-temperature polysilicon transistors or metal-oxide transistors.

66. The display panel according to claim 47, wherein, The compensation module includes a compensation transistor; the data writing unit includes a writing transistor; the first reset unit includes a first reset transistor. At least one of the first reset transistor, the write transistor, and the compensation transistor is a dual-gate transistor.

67. The display panel according to claim 56, wherein, The initialization module includes an initialization transistor; the reset module includes a second reset transistor. Either the initialization transistor or the second reset transistor is a low-temperature polysilicon transistor or a metal-oxide transistor.

68. The display panel according to claim 56, wherein, The initialization module includes an initialization transistor; the reset module includes a second reset transistor. At least one of the initialization transistor and the second reset transistor is a dual-gate transistor.

69. The display panel according to claim 50, wherein, The light emission control module includes a light emission control transistor; the dimming control module includes a dimming control transistor. Both the light-emitting control transistor and the dimming control transistor are low-temperature polycrystalline silicon transistors.

70. The display panel according to claim 49, wherein, The pixel circuit further includes a first reset unit; the control terminal of the first reset unit is electrically connected to the third shift register unit, and the first reset unit is electrically connected between the first reference voltage terminal and the second node. The display panel includes a third driving circuit; the third driving circuit includes a plurality of the third shift register units; The display panel further includes a fifth driving circuit; the fifth driving circuit includes a plurality of the fifth shift register units.

71. The display panel according to claim 70, wherein, The display panel includes a display area and a non-display area surrounding the display area. The display area includes a first side and a second side opposite each other along a row direction, where the row direction is the arrangement direction of a plurality of pixel circuits in a row of pixel circuits. The fifth driving circuit is located in the non-display area, and at least on the first side of the display area; The third driving circuit is located in the non-display area, and at least on the second side of the display area.

72. The display panel according to claim 71, wherein, The fifth driving circuit and the third driving circuit are located on different sides of the display area.

73. A display device, comprising: The display panel according to any one of claims 1-72.

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