Control method, control apparatus, compute-in-memory system and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a control method, a control apparatus, a compute-in-memory system and an electronic device. The control method is used for controlling the computation of a memory circuit, wherein the memory circuit comprises computing units, the computing units each comprise a plurality of computing sub-units arranged in a first direction, one computing sub-unit comprises a plurality of memory cell arrays, the plurality of memory cell arrays are arranged in a third direction, and one memory cell array comprises memory cells arranged in the first direction and a second direction. The control method comprises: sending address signaling to a memory circuit, the address signaling comprising address information of a plurality of computing units; sending first data to the memory circuit, the first data being used for an input of a first memory cell group; and sending second data to the memory circuit, the second data being used for a second input of the first memory cell group, wherein the first memory cell group belongs to a first computing unit and comprises a plurality of first memory cell arrays, the plurality of computing units include the first computing unit, and the plurality of first memory cell arrays belong to a plurality of computing sub-units of the first computing unit.

Description

Control methods, control devices, computing systems and electronic equipment

[0001] This application claims priority to the following applications, the entire contents of which are incorporated herein by reference:

[0002] This application requests the filing of Chinese patent application No. 202510389650.8 with the invention title "Control Method, Control Device, In-Memory System and Electronic Device" with the China National Intellectual Property Administration on March 28, 2025.

[0003] This application claims to file a Chinese patent application with application number 202510397926.7, entitled "Control Method, Control Device, In-Memory System and Electronic Device", with the date of March 28, 2025, with the date of March 28, 2025, with the date of application to the China National Intellectual Property Administration.

[0004] This application requests the filing of a Chinese patent application with application number 202510421823.X, entitled "Control Method, Control Device, In-Memory System and Electronic Device," to the China National Intellectual Property Administration on April 3, 2025. Technical Field

[0005] This application relates to the field of semiconductor technology, and more specifically, to control methods, control devices, memory computing systems, and electronic devices. Background Technology

[0006] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0007] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their computational performance still needs improvement. Summary of the Invention

[0008] This application provides a control method, control device, in-memory computing system, and electronic device that can improve the computing performance of in-memory computing architecture.

[0009] A first aspect provides a control method for controlling the computation of a storage circuit. The storage circuit includes a computing unit, which includes multiple computing sub-units arranged along a first direction. One of the computing sub-units includes multiple storage cell arrays. The multiple storage cell arrays are arranged along a third direction, and one of the storage cell arrays includes storage cells arranged along the first direction and a second direction. The method includes: sending address signaling to the storage circuit, the address signaling including address information of the multiple computing units; sending first data to the storage circuit, the first data being used as a first input to a first storage cell group; and sending second data to the storage circuit, the second data being used as a second input to the first storage cell group. The first storage cell group belongs to a first computing unit and includes multiple first storage cell arrays. The multiple computing units include the first computing unit, and the multiple first storage cell arrays belong to multiple computing sub-units of the first computing unit.

[0010] The technical solution of this application embodiment enables multiple computing units of a 3D storage circuit to perform in-memory computation in parallel, significantly improving computational efficiency compared to serial operation. This method simultaneously instructs multiple computing units via address signaling, allowing the storage circuit to know the addresses of computing units that can participate in parallel computation, thereby executing computational tasks more efficiently and greatly improving computational efficiency. Furthermore, the control device can synchronously send data (e.g., first data or second data) to multiple computing sub-units of the same computing unit in the storage circuit, thereby controlling multiple storage unit arrays in multiple computing sub-units to participate in the computation. This is applicable to large-scale matrix operations based on the storage circuit, improving its applicability to large-scale model business scenarios. Further, the control device can send multiple data to the same storage unit group without re-specifying the address, thus supporting multiple computations with a single address input, expanding the computational scenario requirements of the storage circuit, and saving the number of address signaling transmissions. For example, this control method allows the storage circuit to be used in scenarios involving multiple data processing of the same model. Therefore, the above control method can improve the computational efficiency of the storage circuit and expand its computational business application scenarios.

[0011] In some implementations of the first aspect, the first data includes input data of a plurality of first memory cell arrays of the first memory cell group.

[0012] In some implementations of the first aspect, the control method further includes: waiting for a first time period in response to the transmission of address signaling; wherein, when the first time period expires, first data is sent to the storage circuit.

[0013] In some implementations of the first aspect, the first time period is not less than the conversion time from receiving signaling to receiving data by the storage circuit. This allows for sufficient preparation time for the storage circuit, further improving the accuracy of data transmission.

[0014] In some implementations of the first aspect, the control method further includes: sending a first start signaling to the storage circuit, the first start signaling being used to indicate the start of computation, wherein the address signaling is used to indicate multiple computation units corresponding to the computation.

[0015] In some implementations of the first aspect, the control method further includes sending a first end signaling to the storage circuit, the first end signaling indicating the end of the initial input for the calculation.

[0016] In some implementations of the first aspect, the control method further includes sending a second start signaling to the storage circuit, the second start signaling being used to indicate the start of input of the second data.

[0017] In some implementations of the first aspect, the control method further includes sending a second end signaling to the storage circuit, the second end signaling indicating the end of the second data input.

[0018] In some implementations of the first aspect, the control method further includes: acquiring a status signal of the storage circuit, wherein a first status value of the status signal is used to indicate an operating state and a second status value is used to indicate a ready state; waiting for a second time period when the status signal changes from the second status value to the first status value; wherein, when the second time period expires, sending second data to the storage circuit.

[0019] In some implementations of the first aspect, the control method further includes: acquiring a status signal of the storage circuit, wherein a first status value of the status signal is used to indicate an operating state and a second status value is used to indicate a ready state; and sending a second termination signal to the storage circuit when the status signal changes from the first status value to the second status value.

[0020] In some implementations of the first aspect, the control method further includes: sending third data to the storage circuit based on the address information of multiple computing units, wherein the third data and the first data are sent synchronously, and the third data is used as the first input of the second storage unit group; sending fourth data to the storage circuit based on the address information of multiple computing units, wherein the fourth data and the second data are sent synchronously, and the fourth data is used as the second input of the second storage unit group; wherein the second storage unit group belongs to the second computing unit and includes multiple second storage unit arrays, the multiple computing units include the second computing unit, and the multiple second storage unit arrays belong to multiple computing sub-units of the second computing unit.

[0021] In a second aspect, a control method is provided for controlling the computation of a storage circuit. The storage circuit includes a computing unit, which includes multiple computing sub-units arranged along a first direction. One of the computing sub-units includes multiple storage cell arrays. The multiple storage cell arrays are arranged along a third direction, and one of the storage cell arrays includes storage cells arranged along the first direction and a second direction. The control method includes: sending address signaling to the storage circuit, the address signaling including address information of the multiple computing units; sending first data to the storage circuit, the first data being used as input to a first storage cell group, the first storage cell group belonging to a first computing unit and including multiple first storage cell arrays, the multiple first storage cell arrays belonging to multiple computing sub-units of the first computing unit; and sending second data to the storage circuit, the second data being used as input to a second storage cell group, the second storage cell group belonging to the first computing unit and including multiple second storage cell arrays, the multiple second storage cell arrays belonging to multiple computing sub-units of the first computing unit.

[0022] The technical solution of this application embodiment enables the parallel execution of in-memory computations by multiple computing units of a three-dimensional storage circuit, significantly improving computational efficiency compared to serial operations. This method simultaneously instructs multiple computing units via address signaling, allowing the storage circuit to know the addresses of computing units that can participate in parallel computations, thereby executing computational tasks more efficiently and greatly improving computational efficiency. Furthermore, the control device can synchronously send data (e.g., first data or second data) to multiple computing sub-units within the same computing unit of the storage circuit, thereby controlling multiple storage unit arrays within these sub-units to participate in the computation. This is applicable to large-scale matrix operations based on the storage circuit, enhancing its applicability to large-scale model business scenarios. Moreover, after sending one address signaling instruction, the control device can control the storage circuit to switch between multiple storage unit groups for multiple data operations, saving the number of address signaling instructions sent and further improving the overall performance of the storage circuit.

[0023] In some implementations of the second aspect, the address signaling further includes first indication information, which is used to indicate the position of the first memory cell group in a third direction, or the first indication information is used to indicate the address of the first control line, which is used to control the opening of the memory cell of the memory circuit at the third direction position where the first memory cell group is located.

[0024] In some implementations of the second aspect, the control method further includes sending a control signal to the storage circuit, the control signal being used to control the activation of the second group of storage cells.

[0025] In some implementations of the second aspect, multiple computing units each include a second memory cell group, and control signaling is used to control the synchronous activation of the second memory cell groups of the multiple computing units. This is beneficial for improving the computational parallelism of the storage circuit.

[0026] In some implementations of the second aspect, the control signaling includes enable signaling, which enables the switching of a third-party up-to-the-moment group of open memory cells.

[0027] In some implementations of the second aspect, the switching step size is 1.

[0028] In some implementations of the second aspect, sending first data to the storage circuit includes: sending multiple sets of first data to the storage circuit based on address information of multiple computing units, wherein the multiple sets of first data are respectively used as input to multiple groups of first storage units; sending second data to the storage circuit includes: sending multiple sets of second data to the storage circuit based on address information of multiple computing units, wherein the multiple sets of second data are respectively used as input to multiple groups of second storage units. This is beneficial for improving the computational parallelism of the storage circuit.

[0029] In some implementations of the second aspect, the control method further includes: sending a start signaling signal to the storage circuit, the start signaling signaling being used to indicate the start of computation, wherein the address signaling is used to indicate multiple computation units corresponding to the computation.

[0030] In some implementations of the second aspect, the control method further includes sending a termination signal to the storage circuit, the termination signal indicating the end of the computation.

[0031] In some implementations of the second aspect, the control method further includes sending a sampling signal to the storage circuit, the sampling signal being used to enable the storage circuit to sample the first data or the second data.

[0032] In some implementations of the second aspect, the first data and the second data are carried in data signaling, and the bit width of the data signaling is not less than 32 bits.

[0033] In some implementations of the second aspect, the control method further includes: acquiring a status signal, wherein a first state of the status signal is used to indicate the output state of the storage circuit; and when the status signal has a first state, reading the calculation result of the storage circuit, wherein the calculation result includes the calculation result of the first storage cell group or the calculation result of the second storage cell group.

[0034] Thirdly, a control device is provided, comprising: an interface circuit and a processing circuit, wherein the interface circuit is signal-connected to the processing circuit, and the processing circuit is used to execute the control method of either the first or second aspect.

[0035] Fourthly, a storage computing system is provided, including: a storage circuit, and a control device as described in the third aspect.

[0036] Fifthly, an electronic device is provided, comprising: the storage and computing system of the fourth aspect.

[0037] In a sixth aspect, a computer program product is provided, the computer program product including instructions that, when executed by a processor, cause the control method of either the first or second aspect above to be executed.

[0038] In a seventh aspect, a computer-readable medium is provided that stores instructions which, when executed by a processor, cause the control method of either the first or second aspect above to be performed. Attached Figure Description

[0039] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0040] Figure 2 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0041] Figure 3 shows a schematic diagram of a three-dimensional memory array in a memory circuit according to an exemplary embodiment of this application.

[0042] Figure 4 shows a schematic diagram of a control method according to an exemplary embodiment of this application.

[0043] Figure 5 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application.

[0044] Figure 6 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0045] Figure 7 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0046] Figure 8 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0047] Figure 9 shows a signaling timing diagram according to an exemplary embodiment of this application.

[0048] Figure 10 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0049] Figure 11 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application.

[0050] Figure 12 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0051] Figure 13 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0052] Figure 14 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0053] Figure 15 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0054] Figure 16 illustrates a signaling timing diagram according to an exemplary embodiment of this application.

[0055] Figure 17 shows a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0056] Figure 18 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation

[0057] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0058] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0059] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0060] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects can be directly connected through a medium (e.g., wires, wiring, etc.), or indirectly connected through other components, or can be an internal connection. "Coupling" includes signal connection between objects, which can be achieved directly through a medium (e.g., wires, wiring, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components. Signaling in the embodiments of this application can also be referred to as a command.

[0061] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0062] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0063] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.

[0064] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0065] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0066] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0067] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0068] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0069] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0070] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0071] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in the example of Figure 2, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0072] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly along columns, and the output terminals can be connected collinearly along rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, a memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0073] In some embodiments, the storage circuit may include a three-dimensional storage array, which may have a greater storage density or storage capacity, enabling the in-memory computing system to support larger model deployments. As an example, Figure 3 shows a schematic diagram of a three-dimensional storage array in a storage circuit according to an exemplary embodiment of this application.

[0074] As shown in Figures 3(a) and (b), the storage circuit 300 includes a plurality of storage cell sets P1-P1 arranged along the X direction. x , where x is a positive integer greater than 1. A set of storage units P u Includes multiple storage cell subsets B arranged along the Y direction u1 -B uy Where u∈[1,x], and y is a positive integer greater than 1. A subset B of storage units uv Includes multiple memory cell arrays A arranged along the Z direction uv1 -A uvzWhere v∈[1,y], and z is a positive integer greater than 1. Storage cell array A uvw The storage cell array A has a two-dimensional structure. uvw This includes storage cells arranged along the X and Y directions, where w∈[1,z]. For example, the storage cell array 210 shown in FIG2 may include one or more storage cell arrays, and when multiple storage cell arrays are included, these multiple storage cell arrays may be located in the same storage cell set P. u Different subsets of storage units.

[0075] For ease of distinction, in some embodiments of this application, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction. The X, Y, and Z directions can be any three distinct directions in three-dimensional space. In some examples, any two of the X, Y, and Z directions are perpendicular to each other.

[0076] In some examples, the storage circuitry includes NAND flash memory, the storage cell set includes a plane or bank, and the storage cell subset includes a block. This application is not limited thereto, and storage circuitry with different three-dimensional structures may have different names.

[0077] This application provides a control method for controlling the in-memory computation operation of a three-dimensional storage circuit (hereinafter referred to as the three-dimensional storage circuit). This method can expand the computing power of the three-dimensional storage circuit and can utilize the three-dimensional storage circuit to meet the computing performance requirements of different business scenarios, such as scenarios with high computing efficiency requirements or high bandwidth requirements. This control method can help expand the application scenarios of the in-memory computation processing of the storage circuit, thereby helping to improve the computing performance of the in-memory computing architecture.

[0078] Figure 4 shows a schematic diagram of a control method according to an exemplary embodiment of this application. This control method can be executed by a control device (e.g., the control circuit in the above embodiments) to control the computation of a storage circuit. The structure of the storage circuit can be found in the relevant description of the embodiment shown in Figure 3. In the embodiments of this application, the set of storage cells in the storage circuit can be used for computation. This set of storage cells is hereinafter also referred to as a computation unit, and a subset of storage cells in the set can also be referred to as a computation subunit.

[0079] As shown in Figure 4, the control method 400 may include the following steps.

[0080] S410, send an address signaling message to the storage circuit, the address signaling message including the address information of the computing unit.

[0081] S420, first data is sent to the storage circuit, the first data being used as the first input of the first storage cell group.

[0082] S430, send second data to the storage circuit, the second data being used as the second input of the first storage cell group.

[0083] The address signaling may include address information of multiple computing units. The first storage unit group may belong to a first computing unit, which may be one of the multiple computing units indicated by the address signaling. The first storage unit group includes multiple first storage unit arrays, which belong to multiple computing sub-units of the first computing unit.

[0084] The technical solution of this application embodiment enables multiple computing units of a 3D storage circuit to perform in-memory computation in parallel, significantly improving computational efficiency compared to serial operation. This method simultaneously instructs multiple computing units via address signaling, allowing the storage circuit to know the addresses of computing units that can participate in parallel computation, thereby executing computational tasks more efficiently and greatly improving computational efficiency. Furthermore, the control device can synchronously send data (e.g., first data or second data) to multiple computing sub-units of the same computing unit in the storage circuit, thereby controlling multiple storage unit arrays in multiple computing sub-units to participate in the computation. This is applicable to large-scale matrix operations based on the storage circuit, improving its applicability to large-scale model business scenarios. Further, the control device can send multiple data to the same storage unit group without re-specifying the address, thus supporting multiple computations with a single address input, expanding the computational scenario requirements of the storage circuit, and saving the number of address signaling transmissions. For example, this control method allows the storage circuit to be used in scenarios involving multiple data processing of the same model. Therefore, the above control method can improve the computational efficiency of the storage circuit and expand its computational business application scenarios.

[0085] For example, referring back to Figure 3, in this embodiment of the application, the address signaling may include calculation units P1 to P2. x The address information of multiple computing units in the signaling is provided. The first computing unit can be one of the multiple computing units indicated by the address signaling. For example, the address signaling includes computing units P1, P3, and P4. x The address information, the first calculation unit can be P1, P3 or P x .

[0086] The first computing unit may include multiple computing sub-units, and each computing sub-unit may include multiple memory cell arrays arranged along the Z-direction. For example, the multiple memory cell arrays in a computing sub-unit are stacked along the Z-direction, with one layer of the computing sub-unit corresponding to one memory cell array. Multiple first memory cell arrays in the first memory cell group may include multiple memory cell arrays located on the same layer in the first computing unit, and these multiple memory cell arrays may belong to different computing sub-units within the first computing unit. The first computing unit includes the computing unit P shown in FIG3. x For example, this computing unit P x Includes multiple computational subunits B x1 To B xy The multiple computational subunits B x1 To B xy At least some of the memory cell arrays located in the same layer within a computational sub-unit can belong to a memory cell group, for example, located in multiple computational sub-units B. x1 To B xy Multiple memory cell arrays in the w-th layer can belong to memory cell group A. xw This array of multiple storage cells includes computing sub-unit B. x1 To B xy An array of all or part of the storage cells in the w-th layer.

[0087] Referring to Figures 3 and 4, in S410, the control device can send address signaling to the storage circuit. This address signaling can include address information of multiple computing units. Based on this address information, the multiple computing units in the storage circuit can independently perform subsequent calculations, enabling them to perform calculations in parallel and improving the computing efficiency of the storage circuit.

[0088] Figure 5 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application. As shown in Figure 5, in some embodiments, the storage circuit 500 may include a three-dimensional storage array 510 and a peripheral circuit 520. The peripheral circuit 520 may control the three-dimensional storage array 510 to perform calculations based on signaling received from a control device. For example, the peripheral circuit may receive address signaling and obtain the computing units to be involved in the calculation based on the address signaling. The computing units to be involved in the calculation may include multiple units, and the multiple computing units may perform calculations in parallel. Taking one computing unit (referred to as the first computing unit) as an example, the peripheral circuit may control the storage units in the first storage unit group of the first computing unit to be turned on in preparation for calculation. Taking layer-by-layer control in the Z direction as an example, the storage units of all or part of the computing sub-units in one layer of the first computing unit may be turned on. In some embodiments, the storage circuit may control the storage units to be turned on in a preset order in the Z direction. In this case, the control device may provide input data in a preset order and may not transmit layer address information to the storage circuit. The layer address information is used to indicate the address of the first storage unit group in the third direction, for example, the layer in which the first storage unit group is located in the third direction. For example, referring to Figure 3, assuming that the storage circuit opens the storage cells layer by layer in the Z direction in a top-to-bottom or bottom-to-top order, the control device provides input data based on this preset, which can reduce the transmission of layer address information and further improve the calculation efficiency.

[0089] In some implementations, the control device can provide layer address information to the storage circuit. This layer address information is used to indicate the address of the first storage cell group in a third-order direction, for example, the layer in which the first storage cell group is located in a third-order direction. Alternatively, the layer address information can be used to indicate the initial address of the storage cell group in a third-order direction for the first calculation, and then the storage circuit can change the enabled storage cell layers based on this initial address in a preset order (e.g., from top to bottom or from bottom to top). This increases the flexibility of the calculation. Here, "top" represents the direction away from the substrate, and "bottom" represents the direction closer to the substrate.

[0090] Referring back to Figure 4, in S420 and S430, the control device can send multiple data to the storage circuit, i.e., provide multiple inputs to the storage circuit. The first data and the second data can be any two of the multiple inputs to the first storage cell group. After receiving the first data or the second data, the storage circuit can buffer the first data or the second data and extract the input from the buffer area to the input terminal of the first storage cell group of the first computing unit. Alternatively, the storage circuit can directly or after converting the first data or the second data can input it to the input terminal of the first storage cell group of the first computing unit, so that the multiple first storage cell arrays in the first storage cell group can perform calculations based on the input first data or the second data and the weight data stored therein. The buffer area can be located in a dedicated buffer area of ​​the peripheral circuit or the three-dimensional storage array.

[0091] Optionally, the control device responds to the transmission of address signaling by waiting for a first time period. Upon the expiration of the first time period, it sends first data to the storage circuit. This implementation allows the storage circuit preparation time, enabling it to transition from receiving signaling to receiving data. Thus, the storage circuit can utilize the first time period to process the address signaling, determine the computing unit to which the subsequent data belongs or is applied, and accurately cache the data in the corresponding cache area or input it into the corresponding computing unit. This facilitates accurate data transmission and reduces the probability of data transmission or caching errors. Optionally, the first time period is not less than the transition time from receiving signaling (e.g., address signaling) to receiving data.

[0092] In some implementations, the first storage cell group includes a storage cell array in which all computing sub-units of the first computing unit are located on the same layer, for example, computing unit P shown in FIG3. x For example, in computing unit P x In this context, a storage unit group includes a computation subunit B. x1 To B xy An array of multiple storage cells located on the same layer. Accordingly, the first or second data includes computation sub-cell B. x1 To B xy Input data of the storage cell array located on the same layer.

[0093] Optionally, the first data or the second data may include valid data, or the first data may include both valid and invalid data. Invalid data can be used to "mask" some storage cells in the first storage cell group, such as storage cells within some computational sub-units. This application does not limit the form of invalid data. Taking binary data as an example, it can be represented as 0, and when it is reflected as an input signal, it can be a high voltage (e.g., VDD) or a low voltage (e.g., VSS). The result calculated by the storage cell based on invalid data is an invalid result and will not affect the overall calculation result of the storage cell group. Through this implementation, data input can be performed on all computational sub-units in the first computational unit without distinguishing between multiple computational sub-units, thus simplifying the complexity of the control instructions from the control device to the storage circuit.

[0094] In other embodiments, the first storage unit group includes a storage unit array in which some computing sub-units of the first computing unit are located on the same layer, for example, computing unit P shown in FIG3. x For example, in computing unit P x In the first storage unit group, computing subunit B is included. x1 To B xy The first computing unit has some computing sub-units located in the same layer of the storage cell array. Correspondingly, the first data includes the input data of the storage cell array in the same layer as some computing sub-units of the first computing unit.

[0095] In this embodiment, the control device can send a control command to the storage circuit to turn off or disable the computing sub-units in the first computing unit that do not participate in the calculation (for example, control the transistors of the storage cells in the computing sub-units that do not participate in the calculation to be in the off state). The storage circuit will exclude the computing sub-units that do not participate in the calculation and allocate the first data to the storage cell array of the computing sub-units in the first computing unit that participate in the calculation.

[0096] Optionally, the layer address of the first storage unit group can be a preset layer address, and the control device may not need to indicate the layer address of the first storage unit group in the first computing unit. After the storage circuit receives the first data sent by the control device, the storage circuit can input the first data to the input terminal of the first storage unit group according to the address of the first computing unit indicated by the address signaling and the preset layer address.

[0097] Alternatively, the address signaling sent by the control device to the storage circuit may include not only the address information of the first computing unit but also layer address information. After receiving the first data sent by the control device, the storage circuit can input the first data to the input terminal of the first storage unit group based on the address information of the computing unit and the layer address information in the address signaling.

[0098] In some implementations, the layer address information described above can be used to indicate the address or location of a first memory cell group in the first computing unit along the Z direction. The first computing unit may include multiple memory cell groups along the Z direction, and the layer address information can be used to indicate one of these multiple memory cell groups.

[0099] In some implementations, memory cell arrays located on the same layer in the Z-direction of memory circuits or computing units can be connected via a common control line. Signals on this control line are used to control the activation (e.g., transistor conduction) or deactivation (e.g., transistor cutoff) of memory cells. As an example, a memory cell may include a transistor, and the control line may be connected to the gate of the transistor. The aforementioned layer address information may include address information for the control line, which is used to control the activation of memory cells in the first memory cell group in the Z-direction. Optionally, in the first computing unit, multiple memory cells in a memory cell group may be connected to the same control line.

[0100] In some embodiments of this application, the data (first data or second data) input by the control device to the storage circuit may include digital signals, and the storage circuit may not be equipped with a DAC to perform digital-to-analog conversion on the input data.

[0101] Referring to Figure 4, the first storage unit group can perform a first calculation based on first data and a second calculation based on second data. The first and second calculations can be any two calculations in a series of calculations. In some embodiments of this application, the input for the second calculation can be performed during the first calculation, thus further improving the computational efficiency of the in-memory computing system. For example, the first and second calculations are two adjacent calculations. The first data is cached in a cache area after input and then input to the first storage unit group for calculation. During the calculation process of the first storage unit group, the second data can be input to the storage circuit, which can cache the second data in a cache area. A cache area can be set for the first calculation unit. The first data and the second data can be stored in the same cache area or in different cache sub-areas. These different cache sub-areas are all set for the first calculation unit and are used to alternately store input data.

[0102] In some embodiments of this application, the storage circuit can provide a status signal or status information to the control device. This status signal or information indicates the status of the storage circuit, which may be a first state or a second state. In the first state, the storage circuit is in an operating state, a busy state, or a non-ready state; in other words, the computing unit participating in the calculation is in an operating state, a busy state, or a non-ready state. In the second state, the storage circuit is in a non-operating state, a ready state, or an idle state; in other words, the computing unit participating in the calculation is in a non-operating state, a ready state, or an idle state. The control device can control data input based on this status signal or status information.

[0103] Taking the first and second data as input data for two consecutive calculations as an example. Optionally, the control device can wait for a certain period of time after sending the first data before sending the second data, allowing the storage circuit time to prepare for receiving the second data. During this preparation time, the storage circuit can prepare a buffer area (or buffer sub-area) for storing the second data, so that the second data is stored in the corresponding buffer area (or buffer sub-area). This allows the control device to use the time of the current calculation to input data for the next calculation, further improving the calculation efficiency of the storage circuit. Moreover, this waiting time can reduce the possibility of the second data erroneously overwriting the input data of the previous calculation, thus preventing calculation errors.

[0104] In some implementations, the storage circuit can provide a status signal, which the control device actively detects to determine the status of the storage circuit for input control. This approach simplifies the signal interaction process between the control device and the storage circuit. For example, the control device can acquire the status signal of the storage circuit. When the status signal changes from a second status value to a first status value, the control device waits for a second time period. Upon the expiration of the second time period, second data is sent to the storage circuit. The first status value can indicate the first status, such as indicating that the storage circuit (or multiple computing units involved in the calculation) is in a working state, a busy state, or a non-ready state. The second status value can indicate the second status, such as indicating that the storage circuit (or multiple computing units involved in the calculation) is in a non-working state, a ready state, or an idle state.

[0105] This application does not limit the size of the first or second time period. The storage circuit can be tested, and the first or second time period can be set based on the test results. This allows the storage circuit preparation time between different inputs (e.g., two data inputs, or between signaling and data inputs), ensuring accurate reception of data or signaling. In some embodiments, the storage circuit may be configured with terminals whose voltage levels reflect the state of the storage circuit. The state signal (also called a preparation signal) of the storage circuit may include the voltage level of these terminals. For example, a low voltage level may indicate a first state, and a high voltage level may indicate a second state; or conversely, a low voltage level may indicate a second state, and a high voltage level may indicate a first state. A control device can be connected to these terminals of the storage circuit and obtain the state of the storage circuit by detecting the voltage level of these terminals. Alternatively, in other embodiments, the control device can obtain the state of the storage circuit through other means, such as by sending state information to the control device via signaling.

[0106] In other embodiments, the storage circuit may send an instruction message to the control device, which may indicate that the control device is inputting data into the storage circuit, or indicate that the storage circuit can receive data. The control device may, in response to the instruction message, input data into the storage circuit. Alternatively, the control device may input data into the storage circuit in response to the instruction message without performing a second waiting period.

[0107] The control device can input data to the storage circuit according to the state of the storage circuit. This implementation method is conducive to better cooperation between the control device and the storage circuit, and improves the reliability of the storage system.

[0108] In some other implementations, the control device may not input data based on the state of the storage circuit, but instead wait for a preset time period between two data inputs, assuming the storage circuit has completed its preparation. For example, after sending the first data, wait for a third time period, and when the third time period expires, send the second data to the storage circuit.

[0109] Similar to steps S420 or S430 above, the control device can send data to the storage circuit multiple times for the same group of storage cells to control the group of storage cells in the storage circuit to perform multiple calculations. Each calculation does not require repeated input of address signaling, which can greatly simplify the complexity of control commands and greatly improve the calculation efficiency of the storage circuit.

[0110] In some implementations, for a computing unit of a memory circuit, memory cells having the same (X, Y) location are located within a memory cell string (or memory cell stream). The memory cell string includes cascaded memory cells, and at least one selection cell may be provided within the memory cell string. The selection cell may be located at at least one end of the memory string. The memory cell may include, for example, a transistor. The selection cell may include transistors of the same or different types as the memory cell, and the selection cell may be cascaded with adjacent memory cells. Cascading, for example, includes connecting the source and drain of the transistor.

[0111] In some implementations, data (e.g., first data or second data) sent by the control device to the storage circuit can be input to the corresponding storage cell through a selection unit, so that the group of storage cells can perform calculations based on the input data.

[0112] Optionally, the selection unit may include a transistor, and the data sent by the control device to the storage circuit may be input to the gate of the selection unit, or it may be input to the source or drain of the selection unit.

[0113] In some examples, the select cell can be located at the top of the memory cell string. Data can be input through the gate of the select cell; this input data can be called top select gate (TSG) data, or simply TSG data. In other words, the data sent by the control device to the memory circuit (such as the first and second data mentioned above) can include TSG data. Similarly, the data sent by the control device to the memory circuit can be called bottom select gate (BSG) data. Here, "top" represents the direction away from the substrate, and "bottom" represents the direction closer to the substrate.

[0114] In the embodiment shown in Figure 4, the same group of storage cells in the storage circuit can perform multiple calculations. For example, a first calculation can be performed based on first data, and a second calculation can be performed based on second data. Furthermore, different calculation units in the storage circuit can perform calculations independently. For instance, address signaling includes address information for multiple calculation units. The storage circuit can determine a calculation area based on this address information, allowing different calculation units within that area to perform calculations independently. For each group of storage cells in a calculation unit, one or more calculations can be performed, and the number of calculations performed by different groups of storage cells can be the same or different. Therefore, this control method can improve the computational efficiency of the storage circuit and enhance the computational flexibility within the calculation area, enabling the storage circuit to be flexibly adapted to models in different business scenarios.

[0115] In some embodiments of this application, the control device optimizes the data input and control computation data and signaling flow, thereby simultaneously improving computational efficiency and reliability. The following description uses the example of first data being used for the first input of the storage unit group and second data being used for the second input of the storage unit group; the process for subsequent inputs is similar to the second data input.

[0116] For example, Figure 6 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0117] As shown in Figure 6, the control method 600 executed by the control device may include the following steps.

[0118] S610, a first start signaling message is sent to the storage circuit. This first start signaling message is used to indicate the start of the calculation. This first start signaling message can also be called a storage start command.

[0119] S620, send an address signaling to the storage circuit. The address signaling is used to indicate multiple computing units corresponding to the calculation. For example, the address signaling includes the address information of the multiple computing units corresponding to the calculation.

[0120] S630, first data is sent to the storage circuit. The first data is used for the first input of the first storage unit group in the first computing unit. The first computing unit is any one of the multiple computing units indicated by the address signaling.

[0121] S640, a first end signal is sent to the storage circuit. This first end signal is used to indicate the end of the initial input for the calculation. This first end signal can also be called the storage input end command.

[0122] S650 sends a second start signaling to the storage circuit, which indicates the start of the input of second data. The second start signaling can also be called a data input command.

[0123] S660, send second data to the storage circuit, the second data being used as the second input to the first storage cell group.

[0124] S670, a second end signal is sent to the storage circuit. This second end signal is used to indicate the end of the second data input. The second end command can also be called a data input end command.

[0125] The above calculation and control process can utilize the timing combination of signaling and data transmission to achieve calculation and control of the storage circuit, simplifying control signaling and improving the calculation efficiency of the storage circuit.

[0126] In this embodiment, the descriptions of S620, S630, and S660 can be found in the descriptions of S410, S420, and S430 in the embodiment shown in Figure 4 above. In S610, the control device sends a first start signaling to the storage circuit. This first start signaling instructs the storage circuit to use subsequent signaling and data for computation (or storage). Based on this first start signaling, the storage circuit can determine that the storage area indicated by the address information in subsequent address signaling is used for computation, for example, multiple computation units indicated by the address signaling are used for computation. Furthermore, based on the first start signaling, the storage circuit can determine that subsequent data input is used for data input to these multiple computation units. Thus, the first start signaling can be used to indicate the start of computation and simultaneously distinguish the storage circuit from signaling for other functions, such as erase, program, write, or read signals.

[0127] In S620, the address signaling sent by the control device to the storage circuit can be used to indicate the addresses of multiple computing units participating in the computation. These multiple computing units can perform computations in parallel to improve computational efficiency. When a computing unit performs multiple computations, it is not necessary to resend the address information of that computing unit, reducing the complexity of control signaling and further improving computational efficiency. This results in a significant efficiency improvement for scenarios involving rapid, multiple computations, meeting the high-speed computation requirements of such scenarios.

[0128] In S630, the control device sends first data to the storage circuit. This first data is, for example, the data input for the first calculation, and the storage circuit can cache the first data in a cache area (or cache sub-area) corresponding to the first calculation unit.

[0129] In S640, the control device can send a first end signaling to the storage circuit, thereby indicating to the storage circuit the end of the initial input for the calculation. The storage circuit can understand the end of the initial input for the current calculation based on this first end signaling and can begin the calculation. In the above embodiments, the initial input may include data input, thus allowing the storage circuit to start the first calculation more quickly, further improving calculation efficiency; in this case, the first end signaling can be used to end the first data input. In some other embodiments, the initial input may not include data input. After the address signaling input is completed, the first end signaling is sent, followed by the sending of a second start signaling, the first input data (e.g., first data), and the second end signaling to achieve the first data input.

[0130] In S650, the control device can send a second start signaling to the storage circuit, thereby indicating the start of the second data input. Based on this second start signaling, the storage circuit continues to receive data and performs more calculations using the same group of storage cells. The second start signaling is used to indicate the start of the k-th data input in the subsequent calculation process, where k is a positive integer.

[0131] Based on the second start signaling, the storage circuit can determine that the subsequent transmitted second data is also input data for the first storage cell group that participated in the previous calculation. This simplifies the complexity of the signaling sent by the control device to the storage circuit, improves the communication efficiency and speed between the control device and the storage circuit, and further enhances computational efficiency. The second start signaling can be simply designed, representing its type only through a format or code, without carrying specific information such as address information, thus simplifying the signaling complexity.

[0132] In S660, the control device can send second data to the storage circuit. The control device can input the second data into the storage circuit during the calculation of the first data, and the storage circuit can cache the second data in a cache area (or cache sub-area, which may be different from the cache sub-area that caches the first data) in the first calculation unit; the storage circuit can provide the second data to the same group of storage units for calculation based on the second start signaling.

[0133] In S670, the control device can send a second end signaling to the storage circuit, thereby indicating the end of the second data input. Optionally, the second end signaling can be the same as or different from the first end signaling described above. The first or second end signaling is used to indicate the end of a data input in the current calculation process. For example, the second end signaling can be different from the first end signaling to distinguish between the first input and subsequent inputs; alternatively, the second end command can be the same as the second start command, indicating the start and end of a data input by repeatedly sending the same command, thus saving the number of signaling types and further simplifying the signaling design. Furthermore, the second end command can be the same as the first end command, which also saves the number of signaling types and further simplifies the signaling design.

[0134] In some implementations, the control device can also acquire the status signal of the storage circuit. When the status signal changes from a first state to a second state, a second end signaling is sent. The meaning of the status signal is the same as described above and will not be repeated here. This implementation method allows for the combination of the storage circuit's status and signaling to trigger multiple calculation processes, improving computational efficiency. Furthermore, it helps reduce the idle time ratio of the storage circuit, improving overall utilization of the storage circuit. Referring to S650 to S670 above, the control device can send multiple data transmissions to the storage circuit. Before each data transmission, a second start signaling can be sent to the storage circuit, and after the data transmission, a second end signaling can be sent. Optionally, the second start signaling corresponding to multiple data transmissions can be the same or different, and the second end signaling corresponding to multiple data transmissions can be the same or different. When the second start signaling and / or the second end signaling corresponding to multiple data transmissions are the same, the complexity of the signaling sent by the control device to the storage circuit can be simplified, improving the communication efficiency and speed between the control device and the storage circuit. When the second start signaling and / or the second end signaling corresponding to multiple data transmissions are different, it is beneficial to manage multiple data inputs and calculations in the storage circuit.

[0135] Optionally, the method shown in FIG6 is merely an illustration of an embodiment and not a limitation. In some alternative embodiments, any one or more of S610, S640, S650, and S670 shown in FIG6 may be omitted. In other alternative embodiments, based on the embodiment shown in FIG6, other signaling may be added. For example, after S620, the control device may send an end signaling to the storage circuit to indicate the end of address signaling input.

[0136] Through the technical solutions of this application embodiment, during the process of the control device controlling the storage circuit to perform in-memory computation, a signal indicating the start of computation can be sent before the initial input to the storage circuit. This initial input may include address signaling, or it may include address signaling and initial input data, thereby improving computational efficiency. Alternatively, a signal indicating the end of the initial input can be sent after the initial input to the storage circuit is completed, and a signal indicating the end of the data input can be sent after subsequent data input is completed; or, a signal indicating the end of the data input can be sent before each subsequent round of data input. This approach is beneficial for improving the orderliness of the interaction between the control device and the storage circuit, and also for improving the integrity of the signaling and / or data received by the storage circuit, thereby improving the in-memory computational performance of the storage circuit.

[0137] In the above embodiments, when performing multiple calculations, the control device can control multiple calculations without address indication, but only through signaling (e.g., first start signaling, first end signaling, second start signaling, and second end signaling) and the timing of data input, which greatly improves the calculation efficiency.

[0138] In some embodiments of this application, the data input process can be further optimized: a waiting delay time can be used for the storage circuit to convert between signaling and data reception. The next round of input, including sending a second start signaling and the data for the next round of input, is initiated only after the storage circuit is ready. Furthermore, a signaling indication of the end of the initial input can be set to complete the initial input. This process design makes data input more orderly, simplifies signaling control, improves computational efficiency, and enhances the stability and reliability of the in-memory computing system.

[0139] For example, Figure 7 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0140] As shown in Figure 7, the control method 700 executed by the control device may include the following steps.

[0141] S710 sends an address signaling message to the storage circuit, which includes address information of multiple computing units.

[0142] The S720, in response to the transmission of address signaling, waits for the first time period.

[0143] S730, when the first time period expires, first data is sent to the storage circuit. The first data is used for the first input of the first storage unit group in the first computing unit. The first computing unit is the computing unit among the above-mentioned multiple computing units.

[0144] S740, a first end signal is sent to the storage circuit, which indicates the end of the calculation of the initial input.

[0145] S750: Obtain the status signal of the storage circuit. For a description of the status signal, please refer to the above embodiment.

[0146] S760 waits for a second time period when the status signal changes from the second status value to the first status value.

[0147] S770, when the second time period expires, sends second data to the storage circuit, which is used for the second input of the first storage cell group.

[0148] S780 acquires the status signal of the storage circuit.

[0149] S790, when the status signal changes from the first status value to the second status value, a second end signaling is sent to indicate the end of the second data input.

[0150] The above embodiments realize the feedback of the storage circuit through status signals. The operation is optimized through this feedback mechanism. When the status signal of the storage circuit is in the second state, the next round of data input continues. When the status signal of the storage circuit changes to the first state, the second end signaling is sent, which improves the efficiency of sending signaling, reduces the idle time ratio of the storage circuit, and improves the overall utilization of the storage circuit.

[0151] In this application embodiment, the technical solutions of S710, S730, and S770 can be found in the relevant descriptions of S410, S420, and S430 in the embodiment shown in Figure 4 above. The technical solutions of S740 and S790 can be found in the relevant descriptions of S640 and S670 in the embodiment shown in Figure 6 above.

[0152] In S720 and S730, the control device responds to the transmission of address signaling by waiting for a first time period. When the first time period expires, the control device sends the first data to the storage circuit. This first time period provides the storage circuit with preparation time from receiving signaling to receiving data, which is beneficial for the storage circuit to accurately receive data and perform effective calculations, thereby improving the computing performance of the storage circuit.

[0153] In some implementations, the first time period may include a predetermined time period. This predetermined time period may be determined based on the transition time from receiving signaling to receiving data by the storage circuit. As an example, the first time period is not less than the transition time from receiving signaling to receiving data by the storage circuit. This implementation allows the storage circuit to accurately receive data sent by the control device when it is ready, thereby improving the computing performance of the storage circuit.

[0154] In S750, the control device can acquire a status signal from the storage circuit, which is used to provide feedback on the state of the storage circuit, such as the state of the computing unit participating in the calculation. When the computing unit participating in the calculation is in a first state, the storage circuit can generate a status signal with a first state value; when the computing unit participating in the calculation is in a second state, the storage circuit can generate a status signal with a second state value. Optionally, when at least one of the multiple computing units performs a calculation operation, a reading operation of the calculation result, or other types of operation, the multiple computing units are in the first state, and the storage circuit generates a status signal with a corresponding first state value. When the multiple computing units are not performing a calculation operation, a reading operation of the calculation result, or other types of operation, the multiple computing units are in the second state, and the storage circuit generates a status signal with a corresponding second state value.

[0155] In S760 and S770, when the status signal changes from the second state to the first state, a second time period is waited for. When the second time period expires, the control device sends the second data to the storage circuit. Optionally, the control device may also send a second start signaling before sending the second data. In this case, the control device can send the second start signaling and the second data to the storage circuit when the second time period expires.

[0156] After the storage circuit receives the first data sent by the control device, it can perform calculation operations based on the first data, and the status signal of the storage circuit changes from the second status value to the first status value. After the storage circuit enters the first state, the control device can wait for a period of time before sending the second data to the storage circuit, so that the transmission of the second data is completed during the storage circuit's calculation operation on the first data, further increasing the calculation efficiency and preparing the input data for the next round of calculation in advance.

[0157] Optionally, after the control device finishes sending the first data, it sends a first end signal to the storage circuit to indicate the end of the first data input. The storage circuit can perform calculation operations on the received first data based on the first end signal, and the status signal of the storage circuit changes from the second state to the first state.

[0158] For S760 and S770, as some alternative implementations, the control device may, in response to the transmission of the first end signaling, wait for a fourth time period, and when the fourth time period expires, the control device may send second data to the storage circuit.

[0159] The aforementioned second and fourth time periods can provide preparation time for the storage circuit to receive data (second data) from the receiving signaling (first end signaling), which is beneficial for the storage circuit to effectively receive and calculate data, thereby further improving the computing performance of the storage circuit.

[0160] This application does not limit the size of the fourth time period, which may include a set time period. This set time period can be determined based on the transition time from receiving the end signaling to receiving data by the storage circuit. As an example, if the set time period is not less than the transition time from receiving the end signaling to receiving data by the storage circuit, this implementation allows the storage circuit to effectively receive data sent by the control device when ready, thereby further improving the computing performance of the storage circuit.

[0161] This application does not limit the size of the first to fourth time periods, nor does it limit whether these time periods are equal; they can be all the same, all different, or partially the same. For example, the transition time of the storage circuit from receiving the end signaling to receiving data can be the same as or different from the transition time from receiving the address signaling to receiving data.

[0162] In S780 and S790, the control device can again acquire the status signal of the storage circuit, the process of which can be referred to the relevant description above. When the status signal of the storage circuit changes from the first state value to the second state value, the control device sends a second end signaling to the storage circuit to indicate the end of the second data input. The storage circuit in the ready state can perform calculations on the received second data based on the second end signaling. This method is beneficial to improving the efficiency of the signaling and data sent by the control device to the storage circuit, and also beneficial to improving the completeness of the data received by the storage circuit, thereby further improving the computing performance of the storage circuit.

[0163] Through the technical solution of the embodiments of this application, the control device takes into account the conversion time of the storage circuit from receiving signaling to receiving data, as well as the operating state of the storage circuit, during the process of sending signaling and data to the storage circuit. This provides a control method with high signaling and data transmission efficiency, which is conducive to the storage circuit accurately receiving data, improving the integrity and effectiveness of the data received by the storage circuit, and further improving the computing performance of the storage circuit.

[0164] Referring to S750 to S790 above, the control device can send data to the storage circuit multiple times. For any data transmission, it can obtain the status signal of the storage circuit and, in conjunction with the change of the status signal, send data and an end signal to the storage circuit.

[0165] Optionally, the method shown in FIG7 is only an illustration of an embodiment and not a limitation. In some alternative embodiments, the method shown in FIG7 can be combined with the method shown in FIG6 above. For example, in the embodiment shown in FIG7, the relevant schemes of the start signaling and / or input signaling shown in FIG6 can be added.

[0166] In this embodiment, the address signaling may include the addresses of multiple computing units, which can be used to control multiple computing units in the storage circuit to perform operations in parallel, further improving computing efficiency. The above embodiments describe the calculation process of one computing unit as an example. During data input, the control device can input data from multiple computing units, such as inputting a first data group including the first data of the multiple computing units participating in the calculation; or inputting a second data group including the second data of the multiple computing units participating in the calculation. The calculations of each computing unit can be independent of each other and performed in parallel, and all can refer to the description in the above embodiments.

[0167] For example, FIG8 shows a schematic diagram of another control method according to an exemplary embodiment of the present application.

[0168] As shown in Figure 8, the control method 800 executed by the control device may include the following steps.

[0169] S810, send address signaling to the storage circuit. The address signaling includes address information of multiple computing units, including a first computing unit and a second computing unit.

[0170] S820, based on the address information of the first computing unit and the second computing unit, sends first data and third data to the storage circuit. The first data is used as the first input of the first storage unit group in the first computing unit, and the third data is used as the first input of the second storage unit group in the second computing unit.

[0171] S830, based on the address information of the first computing unit and the second computing unit, sends second data and fourth data to the storage circuit. The second data is used as the second input of the first storage unit group, and the fourth data is used as the second input of the second storage unit group.

[0172] The first storage unit group includes multiple first storage unit arrays, which belong to multiple computing sub-units of the first computing unit. The second storage unit group includes multiple second storage unit arrays, which belong to multiple computing sub-units of the second computing unit.

[0173] In this embodiment, the first computing unit and the second computing unit can be any two computing units from a plurality of computing units indicated by address signaling. The plurality of first storage unit arrays in the first storage unit group can include a plurality of storage unit arrays where a plurality of computing sub-units in the first computing unit are located on the same layer. The plurality of second storage unit arrays in the second storage unit group can include a plurality of storage unit arrays where a plurality of computing sub-units in the second computing unit are located on the same layer. Optionally, the plurality of second storage unit arrays in the second storage unit group can be located on the same layer as the plurality of first storage unit arrays in the first storage unit group, or they can be located on different layers.

[0174] The first computing unit includes the computing unit P shown in Figure 3. x The second calculation unit includes, for example, the calculation unit P1 shown in Figure 3. This calculation unit P... x Includes multiple computational subunits B x1 To B xy The multiple computational subunits B x1 To B xy A memory cell array in which at least some computational sub-units are located in the same layer can belong to a memory cell group, for example, located in multiple computational sub-units B. x1 To B xy Multiple memory cell arrays in the w-th layer can belong to memory cell group A. xw The computing unit P1 includes multiple computing subunits B. 11 To B 1y The multiple computational subunits B11 To B 1y In a storage cell array where at least some computational sub-units are located in the same layer, they can belong to a storage cell group. For example, as shown in Figure 3(b), multiple computational sub-units B are located in the same storage cell group. 11 To B 1y Multiple memory cell arrays in layer w' can belong to memory cell group A. 1w’ , where w' can be equal to or not equal to w.

[0175] Referring to Figures 3 and 8, in S810, the control device can send address signaling to the storage circuit. This address signaling can include address information of multiple computing units, including address information of the first computing unit and the second computing unit. Based on this address information, the first and second computing units in the storage circuit can perform calculations on subsequent input data.

[0176] In S820, based on the address information of the first and second computing units in the address signaling, the control device can send first data and third data to the storage circuit.

[0177] In S830, based on the address information of the first and second computing units in the address signaling, the control device can send second and fourth data to the storage circuit.

[0178] Optionally, the first and third data can be sent synchronously, as can the second and fourth data, which can further improve computational efficiency. In some embodiments, the storage circuit sets up an independent data channel for each computing unit for data transmission within that unit. This allows input data from different computing units to be transmitted synchronously, further improving computational efficiency. Input data from multiple computing units indicated in the address signaling can be input synchronously. For example, the first and third data can be transmitted through the first and second data channels, respectively, where the first and second data channels correspond to the first and second computing units, respectively. Similarly, the second and fourth data can be transmitted through the first and second data channels, respectively.

[0179] In other implementations, input data from different computing units can be sent serially, for example, at different times. Optionally, the data of the computing units can be sent serially based on the order of address information in the address signaling, which can save information used to associate data and computing units and reduce signaling complexity. For example, the first data and the third data are sent based on the order of the address information of the first and second computing units in the address signaling. Similarly, the second data and the fourth data are sent based on the order of the address information of the first and second computing units in the address signaling.

[0180] After receiving the first data and the third data, the storage circuit can input the first data to the input terminals of multiple first storage cell arrays (first storage cell groups) located on the same layer in the first computing unit, so that the multiple first storage cell arrays perform a first calculation based on the input first data and the weight data stored therein. The third data can be input to the input terminals of multiple second storage cell arrays (second storage cell groups) located on the same layer in the second computing unit, so that the multiple second storage cell arrays perform a first calculation based on the input third data and the weight data stored therein. Optionally, the first computing unit and the second computing unit can execute the first calculation synchronously.

[0181] Optionally, the layer address of the first storage unit group can be a predetermined layer address 1, which, combined with the address of the first computing unit, can serve as the first storage unit group. Similarly, the layer address of the second storage unit group can be a predetermined layer address 2, which, combined with the address of the second computing unit, can determine the second storage unit group. The address signaling sent by the control device to the storage circuit does not need to indicate the layer address information of the first storage unit group in the first computing unit and the second storage unit group in the second computing unit. After the storage circuit receives the first data and the third data sent by the control device, the first data is input to the input terminal of the first storage unit group determined by the predetermined layer address, and the third data can be input to the input terminal of the second storage unit group determined by the predetermined layer address.

[0182] Alternatively, the address signaling sent by the control device to the storage circuit may include, in addition to the address information of the first computing unit and the second computing unit, the layer address information of the first storage unit group in the first computing unit and the second storage unit group in the second computing unit. After the storage circuit receives the first data and the third data sent by the control device, it can input the first data to the input terminal of the first storage unit group and the third data to the second storage unit group based on the layer address information of the first storage unit group and the second storage unit group.

[0183] Similarly, after receiving the second and fourth data, the storage circuit can input the second data to the input terminals of multiple first storage cell arrays (first storage cell groups) located on the same layer in the first computing unit, so that the multiple first storage cell arrays perform a second calculation based on the input second data and the weight data stored therein. The fourth data can be input to the input terminals of multiple second storage cell arrays (second storage cell groups) located on the same layer in the second computing unit, so that the multiple second storage cell arrays perform a second calculation based on the input fourth data and the weight data stored therein. Optionally, the first computing unit and the second computing unit can execute the second calculation synchronously.

[0184] Similar to the S830, the control device can send data to the storage circuit multiple times to control the first and second storage cell groups in the storage circuit to perform multiple calculations in parallel. Each calculation does not require repeated input of address information, which can greatly simplify the complexity of control commands and improve the calculation efficiency of the storage circuit.

[0185] Through the technical solution of the embodiments of this application, the control device can control multiple computing units in the storage circuit to perform parallel computing, which greatly improves the computing efficiency of the storage circuit.

[0186] Figure 9 shows a signaling timing diagram according to an exemplary embodiment of this application.

[0187] As shown in Figure 9, the signaling timing sent by the control device to the storage circuit may include the following process.

[0188] (1) The control device sends a first start signal to the storage circuit. For example, the first start signal may include a storage start command as shown in Figure 9, and the storage circuit starts the calculation process.

[0189] (2) The control device sends address information of multiple computing units participating in parallel computing to the storage circuit. As shown in Figure 9, the address signaling includes the address information of computing units 0 to X, so computing units 0 to X can be computed in parallel during subsequent computing processes. Optionally, the address signaling may also include the initial layer address information of multiple computing units. In one example, multiple computing units may share the same layer address, and the groups of storage units participating in the computation within the multiple computing units may be located in the same layer.

[0190] (3) The control device waits for a first time period. For example, the first time period is not less than the conversion delay time from receiving signaling to receiving data in the storage circuit, which can be called the signaling-to-data conversion delay time.

[0191] (4) The control device sends data from multiple computing units participating in the calculation to the storage circuit to begin data input. Optionally, the data from the multiple computing units can be input in parallel. Optionally, a computing unit includes multiple computing sub-units, and a group of storage units in the computing unit participates in the calculation of the input data. The group of storage units includes multiple storage unit arrays belonging to different computing sub-units, and the data input to the computing unit may include data from multiple storage unit arrays.

[0192] (5) The control device sends a first end signal to the storage circuit. For example, the first end signal may include, for example, the storage input end command shown in FIG9, to complete the first round of data input.

[0193] (6) In response to the first round of data input, the storage circuit can start to perform the first round of calculation based on the first round of data. The status signal fed back by the storage circuit can change. For example, the status signal shown in the figure can include a level signal, which can be changed from a high level to a low level. The low level can be used to indicate that the storage circuit is in a busy state, and the high level can be used to indicate that the storage circuit is in a ready state.

[0194] (7) The control device waits for a second time period, exemplarily, the second time period being no less than the transition delay time from receiving the memory input end command to receiving data from the storage circuit, in preparation for the next round of data input. Optionally, the control device may wait for this second time period in response to sending the memory input end command. Alternatively, the control device may also wait for this second time period when the status signal fed back by the storage circuit changes from a high level to a low level. This second time period may be referred to as the signaling transition signaling delay time.

[0195] (8) The control device sends a second start signaling to the storage circuit, which includes, for example, a data input command and inputs data to multiple computing units participating in the computation. Optionally, the control device may input data to different computing units in parallel.

[0196] (9) The control device waits for the status signal of the storage circuit to change again. For example, the status signal can change from low level to high level, indicating that the storage circuit is ready to perform the next round of calculation.

[0197] (10) The control device sends a second end signal to the storage circuit, which includes, for example, a data input end command, to complete the operation of this stage.

[0198] Repeat steps (7) to (10) above to cycle through the storage circuit for subsequent calculations.

[0199] For ease of understanding, T0, T1, and T2 in Figure 9 represent different times. For example, T0 represents the start of the second time period before the second data input, or the time when the first round of data input is completed, or the start of the storage circuit's status signal becoming busy, i.e., the start of the first calculation. Similarly, T1 represents the start of the first round of input after the initial input, or the time when the initial input is completed, or the start of the storage circuit's status signal becoming busy, i.e., the start of the first calculation (which could be the second or first calculation) after the first round of input. And so on, T2 represents the start of the second round of input after the initial input, or the time when the previous round of input is completed, or the start of the storage circuit's status signal becoming busy, i.e., the start of the second calculation (which could be the third or second calculation) after the first round of input.

[0200] As an example, the storage circuit provided in any of the above embodiments may include NAND flash memory. The computing unit in the storage circuit includes a plane (or bank) in the NAND flash memory, and the multiple computing sub-units in the computing unit may include multiple blocks in the plane or bank. The multiple storage cell arrays in the multiple computing sub-units may include multiple storage cell arrays located on the same layer in multiple blocks. The multiple storage cell arrays on the same layer may be connected to the same control line, for example, connected to the same word line (WL). Optionally, the storage cell arrays located on the same layer in a computing unit may be connected to the same WL, or the storage cell arrays located on the same layer in multiple computing units may be connected to the same WL. Figure 10 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0201] As shown in Figure 10, the control method 1000 may include the following steps.

[0202] S1010, send an address signaling message to the storage circuit, the address signaling message including the address information of the computing unit.

[0203] S1020, First data is sent to the storage circuit, which is used as input to the first storage cell group.

[0204] S1030, send second data to the storage circuit, the second data being used as input to the second storage cell group.

[0205] The address signaling may include address information of multiple computing units. A first storage unit group belongs to a first computing unit, which may be one of the multiple computing units indicated by the address signaling. The first storage unit group includes multiple first storage unit arrays, which are multiple computing sub-units of the first computing unit. A second storage unit group also belongs to the first computing unit, and this second storage unit group includes multiple second storage unit arrays, which are also multiple computing sub-units of the first computing unit.

[0206] Through the technical solution of this application embodiment, the control device instructs multiple computing units in the address signaling, enabling the storage circuit to know the addresses of the computing units that can participate in the calculation in parallel. This enhances the parallelism of in-memory computing operations and simplifies the signaling for the control device to control multiple computing units of the three-dimensional storage circuit to perform in-memory calculations in parallel. Compared with serial operations, the above technical solution can significantly improve computing efficiency. Furthermore, after the control device sends an address signaling message, the storage unit groups participating in the calculation can be quickly switched. The control device simplifies the control logic through the coordination of data transmission and storage unit group switching, enabling rapid calculation of multiple storage unit groups within a computing unit. This saves the number of address signaling transmissions and parsings and accelerates the switching efficiency of storage unit groups within the computing unit, greatly improving the computing efficiency and performance of the in-memory computing system.

[0207] For example, referring back to Figure 3, in this embodiment of the application, the address signaling may include calculation units P1 to P2. x The address information of multiple computing units is provided, and the first computing unit can be one of the multiple computing units indicated by the address signaling. For example, the address signaling includes computing units P1, P3, and P4. x The address information, the first calculation unit can be P1, P3 or P x The computational unit in the process.

[0208] The first computing unit may include multiple computing sub-units, and each computing sub-unit may include multiple storage cell arrays arranged along the Z-direction. For example, the multiple storage cell arrays in a computing sub-unit are stacked along the Z-direction, with one storage cell array corresponding to one layer in the computing sub-unit. Multiple first storage cell arrays in a first storage cell group may include multiple storage cell arrays located on the same layer in the first computing unit, and multiple second storage cell arrays in a second storage cell group may include multiple storage cell arrays located on another layer in the first computing unit. The storage cell arrays in the first and second storage cell groups may belong to the same computing sub-unit of the first computing unit, or they may belong to different computing sub-units within the first computing unit. When the storage cell arrays in the first and second storage cell groups belong to the same computing sub-unit of the first computing unit, the control logic can be simplified. Switching of the storage cell groups participating in the computation can be achieved through simple switching control along a third direction, which is beneficial for further improving the computational efficiency of the in-memory computing system.

[0209] Optionally, the first computing unit includes the computing unit P shown in FIG3. x For example, this computing unit P x Includes multiple computational subunits B x1 To B xy The multiple computational subunits Bx1 To B xy In a storage cell array located at the same layer, multiple computing sub-units B can belong to a storage cell group. x1 To B xy A storage cell array located in another layer can belong to another storage cell group. For example, it may be located in multiple computing sub-units B. x1 To B xy Multiple memory cell arrays in the w-th layer can belong to memory cell group A. xw The array of multiple storage cells includes computing sub-unit B. x1 To B xy A storage cell array of all or part of the w-th layer. Located in multiple computational sub-units B. x1 To B xy Multiple memory cell arrays in layer w' can belong to memory cell group A. xw’ The array of multiple storage cells includes computing sub-unit B. x1 To B xy The storage cell array is a combination of all or part of the w'th layer. In this embodiment, control is performed at the granularity of storage cell groups, enabling rapid selection of multiple storage cell arrays. This is particularly suitable for large-scale in-memory computing's demands for computing power and speed, and is beneficial for improving the computing performance of in-memory computing systems.

[0210] In one example, the storage circuit may include a set layer address, which may indicate the layer address at which the first calculation corresponding to the address signaling begins. That is, after receiving the address signaling, the storage circuit uses the layer address of the storage unit group to perform the first calculation within the first calculation unit indicated by the address signaling. For example, the layer address may include the position of the first storage unit group in the third direction (Z direction). After receiving the address signaling, the storage circuit can control the first storage unit group based on the address of the first calculation unit in the address signaling and the position of the first storage unit group in the third direction. In this case, the control device may not send the layer address information to the storage circuit. That is, after receiving the address signaling, the storage circuit, based on the set layer address, opens the storage units of the layer indicated by the layer address of the multiple calculation units indicated in the address signaling. For example, if the first storage unit group is the storage unit group for the first calculation of the first calculation unit, the storage circuit opens the storage units within the layer indicated by the set layer address. The first storage unit group includes these storage units to prepare for subsequent calculations.

[0211] In some implementations, memory cell arrays located on the same layer in the Z-direction of memory circuits or computing units can be connected via a common control line. Signals on this control line are used to control the activation (e.g., transistor conduction) or deactivation (e.g., transistor cutoff) of memory cells. As an example, a memory cell may include a transistor, and the control line may be connected to the gate of the transistor. The aforementioned layer address information may include address information for the control line, which is used to control the activation of memory cells in the first memory cell group in the Z-direction. Optionally, in the first computing unit, multiple memory cells in a memory cell group may be connected to the same control line.

[0212] For example, the set layer address may include the address of a first control line, which can control the activation of the memory cells in the storage circuit at a third-direction location where the first memory cell group is located. For instance, a computing unit includes multiple computing sub-units, each including a memory cell array stacked along the Z-direction. Each layer of the memory cell array can be activated by a corresponding control line. Different layers of memory cell arrays are controlled by different control lines, which can be distinguished by their corresponding control line addresses. The storage circuit may include the address of the set first control line, which can control the activation of the memory cells in the layer where the first memory cell group is located in the first computing unit. Therefore, after receiving address signaling, the storage circuit can control the first memory cell group based on the address of the first computing unit and the address of the first control line in the address signaling.

[0213] In another example, the control device can also dynamically control the layer address of the first memory cell group. Exemplarily, the address signaling may further include first indication information, which may indicate the third-party upward position of the first memory cell group; or, the first indication information may indicate the address of a first control line, which is used to control the activation of memory cells in the memory circuit at the third-party upward position of the first memory cell group. The memory circuit can control the first memory cell group based on the address of the first computing unit in the address signaling and the third-party upward position of the first memory cell group indicated by the first indication information. Alternatively, the memory circuit can control the first memory cell group based on the address of the first computing unit in the address signaling and the address of the first control line indicated by the first indication information. Further details will not be elaborated further.

[0214] Optionally, the address signaling includes address information of multiple computing units, such as computing units P1 to P2 shown in FIG3. x For example, the computing units P1 to P x Includes multiple computational subunits B 11 To B xyEach computing unit may include a first storage unit group. For example, the first storage unit group in computing unit P1 may include computing subunit B. 11 To B 1y In a multi-layer array of first storage cells located on the same level, the first storage cell group in computing unit P2 may include computing unit B. 21 To B 2y Multiple first storage cell arrays located on the same layer, ..., computing unit P x The first group of storage units may include computing unit B. x1 To B xy Multiple first storage cell arrays located on the same layer.

[0215] In one example, computational units P1 to P2 are used. x The first group of memory cells can be located on the same layer in the Z direction. For example, the memory circuit includes a defined layer address, and calculation units P1 to P2... x The first memory cell group in the system can all be located in the same layer indicated by the set layer address. For example, the first indication information can indicate a layer address, such as the location of a first memory cell group in a third-order direction or the address of a first control line. This layer address can be applied to multiple computing units indicated by the address signaling. That is, the layer address of the first memory cell group in multiple computing units is the layer address indicated by the first indication information.

[0216] In this embodiment, multiple computing units each include a first storage unit group, and the storage units in these first storage unit groups can all participate in subsequent calculations, which is beneficial to improving the computational parallelism of the storage circuit. This embodiment can be applied to scenarios where a layer of storage units in the control storage circuit is controlled by a single control line. Therefore, this embodiment also helps to reduce the number of control lines in the storage circuit and reduce the control complexity of the control device on the storage circuit.

[0217] In another example, computational units P1 to P... x The first group of storage cells can be located in the same or different layers in the Z direction. For example, the storage circuit may include X identical or different set layer addresses, which are associated with the computing units P1 to P2. x Each layer address corresponds one-to-one with the corresponding layer address. The layer address for each computing unit can indicate the Z-direction location of the first memory cell group within that computing unit or the address of the first control line. For example, the first indication information can indicate multiple identical or different layer addresses, each corresponding one-to-one with the multiple computing units indicated by the address information. For instance, the address signaling might include computing units P1 to P2. xGiven the address information, the first indication information can indicate X identical or different layer addresses, which are related to the calculation units P1 to P2. x Each corresponds to the other one-to-one.

[0218] In this implementation, the addresses (layer addresses) of the first memory cell groups in different computing units do not need to be completely consistent in the Z direction, thus providing greater flexibility and making it applicable to various architecture types of memory circuits.

[0219] Referring to Figures 3 and 10, in S1010, the control device can send address signaling to the storage circuit. This address signaling can include address information of multiple computing units. Based on this address information, the multiple computing units in the storage circuit can independently perform subsequent calculations, enabling them to perform calculations in parallel and improving the computing efficiency of the storage circuit.

[0220] Figure 11 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application. As shown in Figure 11, in some embodiments, the storage circuit 1100 may include a three-dimensional storage array 1110 and a peripheral circuit 1120. The peripheral circuit 1120 may control the three-dimensional storage array 1110 to perform calculations based on signaling received from a control device. For example, the peripheral circuit 1120 may receive address signaling and obtain the computing units to be involved in the calculation based on the address signaling. The computing units to be involved in the calculation may include multiple units, and the multiple computing units may perform calculations in parallel. Taking one computing unit (referred to as a first computing unit) as an example, the peripheral circuit may control the storage units in the first storage unit's first storage unit group to be turned on, in preparation for calculation. Taking Z-direction layer-by-layer control as an example, the peripheral circuit may control the storage units of all or part of the computing sub-units in one layer of the first computing unit to be turned on. In some implementations, the storage circuit can control the activation of storage cells in a preset order along the Z-axis. In this case, the control device can provide input data in the preset order, without transmitting layer address information to the storage circuit. This layer address information indicates the address of the first storage cell group in the third direction, for example, the layer in which the first storage cell group is located in the third direction. For example, referring to Figure 3, assuming the storage circuit activates storage cells layer by layer in the Z-axis in a top-to-bottom or bottom-to-top order, the control device can provide input data based on this preset order, reducing the transmission of layer address information and further improving computational efficiency.

[0221] In some implementations, the control device can provide layer address information to the storage circuit. This layer address information is used to indicate the address of the first storage cell group in a third-order direction, for example, the layer in which the first storage cell group is located in a third-order direction. Alternatively, the layer address information can be used to indicate the initial address of the storage cell group in a third-order direction for the first calculation, and then the storage circuit can change the enabled storage cell layers based on this initial address in a preset order (e.g., from top to bottom or from bottom to top). This increases the flexibility of the calculation. Here, "top" represents the direction away from the substrate, and "bottom" represents the direction closer to the substrate.

[0222] In some implementations, the control device sends control signals to the storage circuit, which control the switching of activated storage cell groups in a preset order (e.g., from top to bottom or from bottom to top). The storage circuit can activate the storage cell group participating in the calculation for the first time based on a set layer address or an initial address sent by the control device, and then switch the activated storage cell groups based on the control signals. Referring back to Figure 10, in S1020, the control device can send first data to the storage circuit, which can be used as input to the first storage cell group. Since the address signaling has indicated the address of the first computing unit where the first storage cell group is located, the storage circuit can input the first data to the input terminal of the first storage cell group of the first computing unit according to the address of the first computing unit, so that multiple first storage cells in the first storage cell group can perform calculations based on the input first data and the weight data stored therein.

[0223] Optionally, the first data may include multiple first sub-data, which can serve as multiple inputs to the first storage unit group, thereby enabling the first storage unit group to perform multiple calculations. This implementation is better suited for certain business scenarios where there are numerous calculations based on the same weight. Switching the activated storage unit group after multiple calculations via control signaling improves computational efficiency, simplifies control logic, and allows for more efficient control of storage unit group switching, while also satisfying flexible control over the number of calculations within a group. Therefore, this application allows for one or more calculations to be performed in the first storage unit group. This implementation eliminates the need to repeatedly send address signaling and layer address information, saving signaling transmission content, simplifying control logic, improving computational efficiency, and further enhancing the computational performance of the in-memory computing system.

[0224] As mentioned above, the address signaling can indicate the address information of multiple computing units, including the computing units used for subsequent calculations. Optionally, the control device can sequentially send multiple first data to the storage circuit according to the order of the addresses of the multiple computing units included in the address signaling. Each of these multiple first data corresponds one-to-one with the multiple computing units indicated by the address signaling, serving as input to the first storage unit group within the corresponding computing unit. Alternatively, the control device can send multiple first data to multiple computing units in parallel based on the addresses of the multiple computing units included in the address signaling. In some embodiments, the aforementioned synchronous transmission includes the parallel transmission of multiple first data, which can further improve computational efficiency. The storage circuit can set up an independent data channel for each computing unit for data transmission within that computing unit. This allows for synchronous transmission of input data from different computing units, further improving computational efficiency. Input data for the multiple computing units indicated in the address signaling can be input synchronously. For example, the first data for the first computing unit and the first data for the second computing unit can be transmitted through a first data channel and a second data channel, respectively, where the first data channel and the second data channel correspond to the first computing unit and the second computing unit, respectively. This application uses first data and second data to distinguish data in different storage unit groups, but it is not used to distinguish data in different computing units. Data synchronously transmitted to different computing units can be collectively referred to as first data or second data, but it is not required that these first data or second data are the same. Multiple first data can be the same, different or partially the same. Similarly, multiple second data can be the same, different or partially the same.

[0225] The control device and the storage circuit can be interconnected via a data bus, which may include multiple data signal paths. Each computing unit in the storage circuit has one or more corresponding data signal paths. Multiple first data items sent by the control device to the storage circuit can be transmitted in parallel through different data signal lines on the data bus. For example, the first data item of computing unit P1 can be transmitted to computing unit P1 through the data signal path corresponding to computing unit P1, and the first data item of computing unit P2 can be transmitted to computing unit P2 through the data signal path corresponding to computing unit P1. The control device can send multiple first data items corresponding to multiple computing units to the storage circuit in parallel via this data bus.

[0226] In other embodiments, the aforementioned plurality of first data can be sent sequentially. In some embodiments, the control device can send the plurality of first data to the storage circuit sequentially based on the address information of the plurality of computing units. For example, if the address information of computing unit P1 in the address signaling is located before that of computing unit P2, the control device can send the first data of computing unit P1 first, and then send the first data of computing unit P2.

[0227] Optionally, the storage circuit can receive first data sent by the control device through its interface circuit, and the management circuit can be used to control the input of the first data to the first storage unit group in the first computing unit. In the embodiments below, the storage circuit can receive other data (e.g., second data) and signaling through the interface circuit, and the management circuit can be used to control the computing units in the three-dimensional storage array according to the data and signaling. For the sake of brevity, unless otherwise specified, the following description uses the storage circuit as the object to illustrate the relevant processes, and does not elaborate on the interface circuit and management circuit.

[0228] In S1030, the control device can send second data to the storage circuit. After receiving the second data, the storage circuit can input the second data to the input terminal of a plurality of second storage cell arrays (second storage cell groups) located on the same layer in the first computing unit, so that the plurality of second storage cell arrays can perform calculations based on the input second data and the weight data stored therein.

[0229] In one example, within the first computing unit, a first storage unit group and a second storage unit group can be switched according to a set order and a set time, wherein the second storage unit group is located after the first storage unit group in the set order. For example, the storage circuit starts a timer after activating the first storage unit group; when the timer exceeds the set time, the first storage unit group is deactivated and the second storage unit group is activated. Correspondingly, the control device can determine the amount of first data based on the amount of computation performed by the first storage unit group within the set time, and send the first data to the storage circuit based on this amount of data, so that the first storage unit group can complete the computation of the first data within the set time. The second data is processed similarly, and will not be described in detail here.

[0230] In another example, within the first calculation unit, the first and second storage unit groups can be switched according to a set order and a set number of calculations, wherein the second storage unit group is located after the first storage unit group in the set order. For example, the storage circuit starts counting after activating the first storage unit group, and the count increments by one each time the first storage unit group performs a calculation. When the count reaches the set number of calculations, the storage circuit deactivates the first storage unit group and activates the second storage unit group. Accordingly, the control device can determine the amount of first data based on the amount of calculation performed by the first storage unit group within the set number of calculations, and send the first data to the storage circuit based on this amount of data, so that the first storage unit group can complete the calculation of the first data within the set number of calculations. The second data is calculated similarly, and will not be described in detail here.

[0231] Using the schemes in the two examples above, the control device does not need to send instructions to the storage circuit, and the storage circuit can automatically switch from the first storage cell group to the second storage cell group. Therefore, it is beneficial to save signaling overhead and further improve computing performance.

[0232] In another example, the storage circuit can also send a control signal to the storage circuit before sending the second data. Under the control of this control signal, the storage circuit can open the second storage cell group and, optionally, close the first storage cell group. After sending the control signal, the control device can then send the second data, thereby helping to ensure that the storage circuit correctly calculates the second data and improving the reliability of the calculation results.

[0233] For example, the control signaling may include the layer address information of the second memory cell group in the third direction (Z direction). The storage circuit can then, based on the layer address information indicated by the control signaling, enable multiple memory cell arrays on the corresponding layer of the first computing unit as the second memory cell group. Using this implementation, the control device can select the second memory cell group relatively flexibly through control signaling, thus offering greater flexibility.

[0234] For example, the control signaling may include an enable signaling signal, which enables the switching of enabled memory cell groups in the third direction. The storage circuit includes a set sequence; upon receiving the enable signaling signal, it switches to the next memory cell group after the first memory cell group, i.e., the second memory cell group, according to the set sequence. For example, this set sequence may be a position incremented by 1 in the third direction (Z direction). For example, the switching step size in the third direction is 1. The second memory cell group and the first memory cell group can be two adjacent memory cell groups in the Z direction. Through this implementation, the switching of multiple memory cell groups in the storage circuit is achieved through enable signaling, which facilitates rapid switching between multiple memory cell groups, accelerates the operation and calculation speed of the storage circuit, meets the needs of rapid processing in in-memory computing systems, and further improves the efficiency of in-memory computing operations. Furthermore, the command format of the enable signaling can be set relatively simply, which helps reduce the complexity of signaling interaction and further improves the efficiency and performance of in-memory computing operations.

[0235] Optionally, the multiple computing units indicated by the address signaling each include a second storage unit group, and the multiple computing units can simultaneously activate the second storage unit group. For example, the multiple computing units have the same setting order and setting time; or, for another example, the multiple computing units have the same setting order and setting number of calculations; or, for yet another example, the multiple computing units synchronously activate the second storage unit group in response to the control of the same control signaling.

[0236] Optionally, the second data may include multiple second sub-data, which can serve as multiple inputs to the second storage unit group, thereby enabling the second storage unit group to perform multiple calculations. This implementation is better suited for certain business scenarios where there are numerous calculations based on the same weight. Switching the activated storage unit group after multiple calculations via control signaling improves computational efficiency, simplifies control logic, and allows for more efficient control of storage unit group switching, while also allowing for flexible control of the number of calculations within a group. Therefore, in this application, one or more calculations can be performed in the first storage unit group. This implementation eliminates the need to repeatedly send address signaling and layer address information, saving signaling transmission content, simplifying control logic, improving computational efficiency, and further enhancing the computational performance of the in-memory computing system.

[0237] As mentioned above, the address signaling can indicate the address information of multiple computing units, including the computing units used for subsequent calculations. Optionally, the control device can sequentially send multiple second data or synchronously send multiple second data to the storage circuit according to the addresses of the multiple computing units included in the address signaling. These multiple second data correspond one-to-one with the multiple computing units indicated by the address signaling and serve as inputs to the second storage unit group in the corresponding computing unit.

[0238] Optionally, the above-described methods of sequentially or synchronously sending multiple second data can refer to the relevant descriptions of multiple first data, which will not be repeated here.

[0239] In some implementations, for a computing unit of a memory circuit, memory cells having the same (X, Y) location are located within a memory cell string (or memory cell stream). The memory cell string includes cascaded memory cells, and at least one selection cell may be provided within the memory cell string. The selection cell may be located at at least one end of the memory cell string. The memory cells may include, for example, transistors, and the selection cell may include transistors of the same or different types as the memory cells. The selection cell may be cascaded with adjacent memory cells. Cascading, for example, involves connecting the source and drain of the transistors.

[0240] In some implementations, data (e.g., first data or second data) sent by the control device to the storage circuit can be input to the corresponding storage cell through a selection unit, so that the group of storage cells can perform calculations based on the input data.

[0241] Optionally, the selection unit may include a transistor, and the data sent by the control device to the storage circuit may be input to the gate of the selection unit, or it may be input to the source or drain of the selection unit.

[0242] In some examples, the select cell can be located at the top of the memory cell string. Data can be input through the gate of the select cell; this input data can be called top select gate (TSG) data, or simply TSG data. Similarly, data sent by the control device to the memory circuit can be called bottom select gate (BSG) data. Here, "top" represents the direction away from the substrate, and "bottom" represents the direction closer to the substrate.

[0243] In the embodiment shown in Figure 10, the first and second storage unit groups within the first computing unit can perform calculations based on the first and second data, respectively. Furthermore, different computing units within the storage circuit can perform calculations independently. For example, address signaling includes address information for multiple computing units, and the storage circuit can determine a computing region based on this address information. Thus, different computing units within this region can perform calculations independently, and for each computing unit's storage unit group, one or more calculations can be performed. The number of calculations performed by different computing unit storage unit groups can be the same or different. Therefore, this control method can improve the computing efficiency of the storage circuit and enhance the computing flexibility within the computing region, enabling the storage circuit to be flexibly adapted to models in different business scenarios.

[0244] Figure 12 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0245] As shown in Figure 12, the control method 1200 executed by the control device may include the following steps.

[0246] S1210, send address signaling to the storage circuit, the address signaling including address information of multiple computing units and first indication information.

[0247] S1220, First data is sent to the storage circuit, which is used as input to the first storage cell group.

[0248] S1230, send a control signal to the storage circuit, the control signal being used to control the opening of the second storage cell group.

[0249] S1240, send second data to the storage circuit, the second data being used as input to the second storage cell group.

[0250] In the embodiments of this application, the technical solutions of S1210, S1220 and S1240 can be found in the relevant descriptions of S1010, S1020 and S1030 in the embodiment shown in Figure 10 above.

[0251] In S1210, the address signaling sent by the control device to the storage circuit may include not only address information of multiple computing units, but also first indication information, which indicates the layer address of the first storage cell group in the Z direction. Optionally, the layer address may be the initial layer address of the storage cell group performing the first calculation within the computing unit.

[0252] In some examples, the first indication information is used to indicate the position of the first memory cell group in the Z direction. The first computing unit includes multiple memory cell groups along the Z direction, and the first indication information can be used to indicate the position of the first memory cell group in the third direction (Z direction). The storage circuit can operate on the first memory cell group according to the address information of the first computing unit and the position in the third direction.

[0253] In other examples, the first indication information can be used to indicate the address of a first control line used to control the activation of memory cells at a Z-direction location where the first memory cell group is located. Optionally, multiple memory cells in a memory cell group can be connected to the same control line, which can be used to control the multiple memory cells to be turned on (enabled) or off (disabled). As an example, when the memory cells include transistors, the same control line can be connected to the gates of multiple memory cells in a memory cell group.

[0254] In the above two implementation methods, the address signaling sent by the control device to the storage circuit includes address information and indication information of multiple computing units. Based on the address information and indication information, the storage circuit can accurately and quickly open the storage units in the first storage unit group, thereby improving the computing performance and efficiency of the storage circuit.

[0255] In S1230, the control device can send a control signal to the storage circuit, which can be used to control the opening of the second storage cell group.

[0256] Optionally, the second storage cell group may include a storage cell array located on the same layer within a computing unit. A storage cell group is located on one layer within a computing unit. The control signaling can control the activation of a storage cell group within a computing unit on a layer-by-layer basis.

[0257] In some implementations, the control signaling includes an enable signaling signal for enabling the switching of active memory cell groups in the Z direction. The switching of memory cell groups can have a set switching step size, and based on this enable signaling, the storage circuitry can implement switching between multiple memory cell groups in the Z direction. In some examples, the switching step size can be 1. The second memory cell group and the first memory cell group can be two adjacent memory cell groups in the storage circuitry. In other implementations, the switching step size can be greater than 1.

[0258] The technical solution of this implementation uses enable signaling to switch and activate multiple memory cell groups in the memory circuit. This facilitates rapid switching between memory cell groups, accelerates the operation and calculation speed of the memory circuit, meets the high-speed processing requirements of in-memory computing systems, and further improves the efficiency of in-memory computing operations. Furthermore, the command format of the enable signaling can be set relatively simply, which helps reduce the complexity of signaling interaction and further improves the efficiency and performance of in-memory computing operations.

[0259] Optionally, in the embodiments of this application, the order of S1230 and S1240 is not limited. S1230 can be executed before or after S1240, or they can be executed simultaneously.

[0260] Referring to S1230 to S1240 above, the control device can send multiple control commands to the storage circuit to control the storage circuit to switch between multiple storage cell groups. Before each switch, data can also be sent to the storage circuit multiple times, causing the currently active storage cell group in the storage circuit to perform multiple calculations. Each calculation and switch does not require repeatedly inputting the addresses and other information of multiple calculation units, which can greatly simplify the complexity of control commands and improve the calculation efficiency of the storage circuit.

[0261] Figure 13 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0262] As shown in Figure 13, the control method 1300 executed by the control device may include the following steps.

[0263] S1310, send address signaling to the storage circuit, the address signaling including address information of multiple computing units.

[0264] S1320, send first sub-data to the storage circuit, the first sub-data being used for the first input of the first storage cell group in the first computing unit.

[0265] S1330, send the second sub-data to the storage circuit, which is used for the second input of the first storage cell group.

[0266] The first storage unit group includes multiple first storage unit arrays, which belong to multiple computing sub-units of the first computing unit.

[0267] In the embodiments of this application, the technical solutions of S1310 and S1320 can be found in the relevant descriptions of S1010 and S1020 in the embodiment shown in Figure 10 above.

[0268] In some implementations, the first computing unit can be any one of multiple computing units, and the first storage unit group can belong to that first computing unit. This application's embodiments illustrate this by assuming the first storage unit group belongs to a single computing unit (the first computing unit).

[0269] After the control device sends an address signaling instruction to the storage circuit to indicate the address of the first computing unit, it can send first data to the storage circuit. The first data may include first sub-data and second sub-data. The above description uses the first and second sub-data as examples. The control device can send data to the same storage unit group (e.g., the first storage unit group) multiple times for calculation. For example, it can send first sub-data, second sub-data, ..., Lth sub-data, where L represents the number of calculations performed on the storage unit group, or the number of times data is input for one round of calculation on the same storage unit group. In this way, the control device can control the first storage unit group in the first computing unit to perform multiple calculations, expanding the computing power of the storage circuit and making it better suited for certain business scenarios where there are many calculations based on the same weight. Furthermore, each calculation does not require repeated input of address information, which greatly simplifies the complexity of control commands and further improves the computing efficiency of the storage circuit.

[0270] Figure 14 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0271] As shown in Figure 14, the control method 1400 executed by the control device may include the following steps.

[0272] S1401, a first start signaling is sent to the storage circuit, which is used to indicate the start of the calculation.

[0273] S1402, send an address signaling to the storage circuit. The address signaling is used to indicate the multiple computing units corresponding to the calculation, and the address signaling includes the address information of the multiple computing units.

[0274] S1403, send first sub-data to the storage circuit. The first sub-data is used for the first input of the first storage cell group in the first computing unit. The first computing unit is included in the plurality of computing units indicated by the address signaling. The first data includes the first sub-data.

[0275] S1404, a first end signal is sent to the storage circuit, which is used to indicate the end of the first sub-data input.

[0276] S1405, a second start signaling is sent to the storage circuit, which is used to indicate the start of the next sub-data input.

[0277] S1406, send the second sub-data to the storage circuit. The second sub-data is used for the second input of the first storage cell group. The first data includes the second sub-data.

[0278] S1407, a second end signal is sent to the storage circuit, which is used to indicate the end of this sub-data input.

[0279] S1408, a control signal is sent to the storage circuit, which is used to control the second storage cell group in the first computing unit to be turned on.

[0280] S1409, send the second start signaling to the storage circuit.

[0281] S1410, send third sub-data to the storage circuit. This third sub-data is used for the first input of the second storage cell group. The second data includes the third sub-data.

[0282] S1411, send the second end signaling to the storage circuit.

[0283] S1412, send the second start signaling to the storage circuit.

[0284] S1413, send the fourth sub-data to the storage circuit. The fourth sub-data is used for the second input of the second storage cell group. The second data includes the fourth sub-data.

[0285] S1414, send the second end signaling to the storage circuit.

[0286] In S1401, the control device can send a first start signaling to the storage circuit, which instructs the storage circuit to begin data calculation. This implementation allows the storage circuit to switch to address receiving mode upon receiving the first start signaling, waiting for the control device to send address signaling, thus ensuring the storage circuit's reception of address signaling.

[0287] In S1402, the address signaling sent by the control device to the storage circuit can be used to indicate the addresses of multiple computing units participating in the computation. Optionally, before the storage circuit receives a new first start signaling and a new address signaling, the storage circuit can operate based on the address information of multiple computing units in the most recently received address signaling.

[0288] In S1403, the control device sends the first sub-data to the storage circuit. Optionally, after the first sub-data is received through the interface circuit of the storage circuit, it can be buffered in the cache circuit of the storage circuit.

[0289] In S1404, the control device may send a first end signaling to the storage circuit, thereby indicating to the storage circuit the end of the first sub-data input. Optionally, the storage circuit may, based on the first end signaling, retrieve the first sub-data from the cache circuit and input the first sub-data into the first storage cell group in the first computing unit, so as to control the first storage cell group to perform the first calculation based on the input first sub-data.

[0290] In S1405, the control device may send a second start signaling to the storage circuit, which may indicate the start of the next sub-data input. This second start signaling is different from the first start signaling in S1401, which is used to indicate the start of the overall calculation process. This overall calculation process is relative to the multiple calculation units indicated by the address signaling. That is to say, the multiple calculations performed in the above-mentioned multiple calculation units belong to the above-mentioned overall calculation process.

[0291] The second start signaling is used to indicate the start of the k-th sub-data input in the overall calculation process, excluding the first sub-data input, where k is a positive integer. Optionally, the second start signaling does not need to include complex information such as addresses. The storage circuit can determine, based on the second start signaling, that the subsequently transmitted sub-data is also input data for the first storage cell group that participated in the previous calculation, thereby simplifying the complexity of the signaling sent by the control device to the storage circuit and improving the communication efficiency and speed between the control device and the storage circuit.

[0292] In S1406, the control device can send the second sub-data to the storage circuit. Both the second sub-data and the first sub-data are part of the first data. Optionally, after the second sub-data is received through the interface circuit of the storage circuit, it can be buffered in the cache circuit of the storage circuit.

[0293] In S1407, the control device may send a second end signaling to the storage circuit, thereby indicating to the storage circuit the end of this sub-data input. Optionally, the storage circuit may, based on the second end signaling, retrieve the second sub-data from the cache circuit and input the second sub-data into the first storage unit group in the first computing unit, so as to control the first storage unit group to perform a second calculation based on the input second sub-data.

[0294] Optionally, the second termination signaling can be similar to the first termination signaling described above, and both can be referred to as termination signaling. This termination signaling is used to indicate the end of one sub-data input in the current calculation process. This termination signaling is not used to indicate the number of sub-data inputs. Alternatively, the second termination signaling can also be different from the first termination signaling described above. For example, the second termination signaling can be used to indicate the end of the k-th sub-data input in the current calculation process, and the first termination signaling can be used to indicate the end of the first sub-data input in the current calculation process.

[0295] Referring to S1405 to S1407 above, the first data includes multiple sub-data. The control device can send multiple sub-data to the storage circuit. Before and after each sub-data transmission, a second start signaling and a second end signaling can be sent to the storage circuit. Optionally, the second start signaling corresponding to multiple sub-data transmissions can be the same or different, and the second end signaling corresponding to multiple sub-data transmissions can be the same or different. When the second start signaling and / or the second end signaling corresponding to multiple sub-data transmissions are the same, the complexity of the signaling sent by the control device to the storage circuit can be simplified, improving the communication efficiency and speed between the control device and the storage circuit. When the second start signaling and / or the second end signaling corresponding to multiple sub-data transmissions are different, it is beneficial for managing the input and calculation of multiple sub-data in the storage circuit.

[0296] Optionally, the method shown in FIG14 is merely an illustration of an embodiment and not a limitation. In some alternative embodiments, any one or more of S1401, S1404, S1405, and S1407 shown in FIG14 may be omitted. In other alternative embodiments, additional signaling may be added based on the embodiment shown in FIG14.

[0297] Through the technical solution of the embodiments of this application, during the process of the control device controlling the storage circuit to perform in-memory calculation, a signal indicating the start of sending address signaling and / or sub-data can be sent before sending address signaling and / or sub-data to the storage circuit. Alternatively, a signal indicating the end of sending address signaling and / or sub-data can be sent before sending address signaling and / or sub-data to the storage circuit. This method is beneficial to improving the orderliness of the interaction between the control device and the storage circuit, and also beneficial to improving the integrity of the signaling and / or sub-data received by the storage circuit, thereby improving the storage performance of the storage circuit.

[0298] Taking the first data as including a first sub-data and a second sub-data as an example, the input of the first data is completed after the first sub-data and the second sub-data are input into the first storage unit group in two separate steps. As shown in S1408, after the first data input is completed, the control device can also send a control command to the storage circuit to control the storage circuit to open the second storage unit group in the first computing unit. However, this is only an example. In other embodiments, the first data may include more or fewer sub-data. Before step S1408, the control device may send more or fewer sub-data to the storage circuit, and the specific number of times is not limited, depending on the business performed by the storage computing system.

[0299] In the following steps S1410 to S1414, the control device can send the second data to the storage circuit in a similar manner to the first data transmission. The first transmission sends the third sub-data for the first input of the second storage cell group, and the second transmission sends the fourth sub-data for the second input of the second storage cell group. The specific process will not be elaborated further. Similarly, the second data can include more or fewer sub-data, and after the second data transmission is complete, the control device can further send control signals to control the activation of other storage cell groups in the first computing unit, such as the activation of the third storage cell group.

[0300] In the above embodiments, when performing calculations on multiple storage unit groups, the control device can switch storage unit groups without address indication, but only through control signaling. Furthermore, the number of calculations within a storage unit group is controlled by the timing of data input, such as the first start signaling, the first end signaling, the second start signaling, and the second end signaling, thereby improving the flexibility of calculation and bringing benefits to the application of in-memory computing systems in multiple scenarios.

[0301] In this embodiment, sending an address signaling message once can enable computation in multiple memory cell groups of computing units, and the computation in these memory cell groups can be performed synchronously. Optionally, multiple computations can be performed in a single memory cell group, greatly improving the efficiency of address signaling and thus enhancing the computational performance of the storage circuit. Furthermore, the above process design makes data input more orderly, simplifies signaling control, and improves computational efficiency while enhancing the stability and reliability of the in-memory computing system.

[0302] Figure 15 shows a schematic diagram of another control method according to an exemplary embodiment of this application.

[0303] As shown in Figure 15, the control method 1500 executed by the control device may include the following steps.

[0304] S1510, send address signaling to the storage circuit, the address signaling including address information of multiple computing units.

[0305] S1520, in response to the transmission of address signaling, waits for the first time period.

[0306] S1530, when the first time period expires, the control device sends first sub-data to the storage circuit, which is used for the first input of the first storage unit group in the first computing unit.

[0307] S1540, a first end signaling is sent to the storage circuit, which is used to indicate the end of the first sub-data input.

[0308] S1550, obtain the indication signal of the storage circuit, wherein state 1 of the indication signal is used to indicate that multiple computing units are in working state, and state 2 is used to indicate that multiple computing units are in ready state.

[0309] S1560, when the indication signal changes from state 2 to state 1, wait for the second time period.

[0310] S1570, when the second time period expires, sends the second sub-data to the storage circuit, which is used for the second input of the first storage cell group.

[0311] S1580, obtains the indication signal from the storage circuit.

[0312] S1590, when the indication signal changes from state 1 to state 2, a second end signaling is sent to indicate the end of the second sub-data input.

[0313] Subsequently, the system switches to the second storage unit group, and the control device continues to send the second data, which includes the third sub-data and the fourth sub-data. The specific sending process can be referred to the description of the embodiment shown in Figure 14, and will not be repeated here.

[0314] In the embodiments of this application, the technical solutions of S1510, S1530, S1540, S1570 and S1590 can be found in the relevant descriptions of S1420, S1430, S1440, S1460 and S1470 in the embodiments shown in Figure 14 above.

[0315] In S1520 and S1530, the control device responds to the transmission of address signaling by waiting for a first time period. When the first time period expires, the control device sends the first data to the storage circuit. This first time period provides the storage circuit with preparation time from receiving the address signaling to receiving the data, which is beneficial for the storage circuit to effectively receive and calculate the data, thereby improving the computing performance of the storage circuit.

[0316] In some implementations, the first time period can be determined based on the transition time from receiving address signaling to receiving data by the storage circuit. As an example, this first time period is not less than the transition time from receiving address signaling to receiving data by the storage circuit. This implementation helps to ensure that the storage circuit can effectively receive data sent by the control device when ready, thereby guaranteeing the computing performance of the storage circuit.

[0317] In S1550, the control device can acquire an indication signal from the storage circuit, which is used to provide feedback on the status of multiple computing units within the storage circuit. When the multiple computing units are in an active or busy state, the indication signal of the storage circuit has state 1; when the multiple computing units are in a ready or available state, the indication signal of the storage circuit has state 2.

[0318] Optionally, when multiple computing units are in operation, the multiple computing units perform computation operations, read-out operations after computation, or other types of operations.

[0319] Optionally, when multiple computing units are in a ready state, no computing operations, read operations, or other types of operations are performed on the multiple computing units.

[0320] Optionally, if multiple computing units are busy, they cannot immediately respond to new signaling until the currently executed operation is completed.

[0321] Optionally, when multiple computing units are in an available state, the multiple computing units can immediately respond to new signaling and execute new operations.

[0322] In some embodiments, the interface circuit of the storage circuit may be configured with terminals, and the level signal on these terminals can provide feedback on the status of multiple computing units. The indication signal of the storage circuit may include the level signal on these terminals. For example, a low level signal may indicate that multiple computing units are in an active state, and a high level signal may indicate that multiple computing units are in a ready state. Similarly, a high level signal may indicate that multiple computing units are in an active state, and a low level signal may indicate that multiple computing units are in a ready state. A control device may be connected to the terminals of the storage circuit and obtain the indication signal of the storage circuit by detecting the level signal on these terminals. Alternatively, in other embodiments, the control device may also obtain the status of the storage circuit in other ways, such as by the storage circuit sending status information to the control device via signaling.

[0323] In S1560 and S1570, when the indicator signal changes from state 2 to state 1, a second time period is waited for. When the second time period expires, the control device sends the second sub-data to the storage circuit. Optionally, the control device may also send a second start command before sending the second sub-data. In this case, the control device can send the second start command and the second sub-data to the storage circuit when the second time period expires.

[0324] After the storage circuit receives the first sub-data sent by the control device, it can perform a calculation operation based on the first sub-data, and the indication signal of the storage circuit changes from state 2 (ready state or available state) to state 1 (working state or busy state). Additionally, the control device sends a first end signaling to the storage circuit to indicate the end of the first sub-data input. The storage circuit can then perform a calculation operation on the received first sub-data based on this first end signaling, and the indication signal of the storage circuit changes from state 2 to state 1. For S1560 and S1570, as some alternative embodiments, the control device can respond to the sending of the first end signaling by waiting for a third time period. When the third time period expires, the control device sends the second sub-data to the storage circuit.

[0325] The aforementioned second and third time periods can provide preparation time for the storage circuit from receiving signaling (first end signaling) to receiving data (third data), which is beneficial for the storage circuit to effectively receive and calculate data, thereby improving the computing performance of the storage circuit.

[0326] In some implementations, the second and third time periods can be determined based on the transition time from receiving the end signaling to receiving data by the storage circuit. As an example, the second and third time periods are not less than the transition time from receiving the end signaling to receiving data by the storage circuit. This implementation helps to ensure that the storage circuit can effectively receive data sent by the control device when ready, thereby guaranteeing the computing performance of the storage circuit.

[0327] In S1580 and S1590, the control device can again acquire the indication signal from the storage circuit; the process of acquiring this indication signal can be found in the relevant description of S1550 above. When the indication signal of the storage circuit changes from state 1 (operating state) to state 2 (ready state), the control device sends a second end signaling to the storage circuit to indicate the end of the second sub-data input. The storage circuit in the ready state can perform calculations on the received complete second sub-data based on this second end signaling. This method improves the efficiency of the signaling and sub-data sent by the control device to the storage circuit and enhances the completeness of the data received by the storage circuit, thereby further improving the computational performance of the storage circuit.

[0328] Through the technical solution of the embodiments of this application, the control device takes into account the conversion time of the storage circuit from receiving signaling to receiving sub-data, as well as the operating state of the storage circuit, during the process of sending signaling and sub-data to the storage circuit. This provides a control method with high efficiency in sending signaling and sub-data, which helps to ensure that the storage circuit receives sub-data in a better state (e.g., a ready state), improves the integrity and effectiveness of the sub-data received by the storage circuit, and further enhances the computing performance of the storage circuit.

[0329] Referring to S1550 to S1590 above, the control device can send multiple sub-data to the storage circuit. For any sub-data transmission, it can obtain the indication signal of the storage circuit and, in conjunction with the change of the indication signal, send sub-data and end signaling to the storage circuit.

[0330] Optionally, the method shown in FIG15 is only an illustration of an embodiment and not a limitation. In some alternative embodiments, the method shown in FIG15 can be combined with the method shown in FIG14 above. For example, in the embodiment shown in FIG15, the relevant schemes of the first start signaling and / or the second start signaling shown in FIG14 can be added.

[0331] In the embodiments shown in Figures 13 to 15 above, in order to distinguish the sub-data that is input multiple times to the first storage cell group in the storage circuit, the data input to the first storage cell group for the first time is called the first sub-data, and the data input to the first storage cell group for the second time is called the second sub-data.

[0332] Furthermore, in the embodiments shown in Figures 13 to 15 above, the example is that the control device inputs multiple sub-data into the first storage cell group in the storage circuit. The control device can also input multiple sub-data into other storage cell groups in the storage circuit, such as the second storage cell group. The way the control device inputs multiple sub-data into other storage cell groups can be referred to the relevant description of any of the embodiments in Figures 13 to 15 above.

[0333] In some embodiments of this application, the control device can wait for a certain period of time (e.g., a second time period) after inputting data once (e.g., inputting a sub-data of the first data or the second data) before inputting the next data, thus reserving time for the storage circuit to prepare for receiving the next data. During this preparation time, the storage circuit can prepare a buffer area (or a buffer sub-area) for storing the next data, so that the next data is stored in the corresponding buffer area (or buffer sub-area). This allows the control device to use the time of the current calculation to input the data for the next calculation, further improving the calculation efficiency of the storage circuit. Moreover, this waiting time can reduce the possibility of the next data incorrectly overwriting the input data of the previous calculation, thus preventing calculation errors.

[0334] Optionally, in any of the above embodiments, after the control device inputs data to the last group of storage units participating in the calculation in the first computing unit through the control method of the above embodiments, the control device may also send a termination signal to the storage circuit. This termination signal is used to indicate the end of the entire calculation process. This approach helps to improve the orderliness of the interaction between the control device and the storage circuit, thereby improving the storage and computing performance of the storage circuit.

[0335] Based on any of the embodiments described above, the control method may further include: the control device sending a sampling signal to the storage circuit, which may also be referred to as a data valid signal, to enable the storage circuit to sample the received data. In this embodiment, the control device can send a sampling signal to the storage circuit simultaneously with the data it sends, so that the storage circuit samples the received data according to the sampling signal. This is beneficial for improving the accuracy and reliability of data transmission, thereby improving the computing performance of the in-memory computing system. In some examples, the trigger edge of the sampling signal (e.g., a rising edge or a falling edge) is used to trigger data sampling.

[0336] In some embodiments, the data sent by the control device to the storage circuit is carried in data signaling, and the bit width of the data signaling is not less than 32 bits. In some embodiments of this application, the storage unit groups within multiple computing units can be operated in parallel, thus the amount of data processed in one operation is relatively large. By increasing the bit width of the data signaling, it is beneficial to improve the parallel transmission of data, reduce the number of data signaling and transmission time, improve data transmission efficiency to match the data processing efficiency of this application, and thereby improve system performance.

[0337] Based on any of the embodiments described above, the control method may further include: a control device acquiring a status signal of the storage circuit, the status signal including a first state indicating the output state of the storage circuit. When the status signal of the storage circuit has the first state, the control device reads the calculation result of the storage circuit, the calculation result including the calculation result of a first storage cell group or a second storage cell group. Optionally, the first state of the status signal can be used to indicate that the storage circuit is ready to output, or to indicate that the storage circuit has established a stable output signal of calculation result. In this embodiment, the storage circuit can feed back its output state to the control device through the status signal, which helps the control device to read the calculation result of the storage circuit more accurately based on the status signal, thereby improving the overall performance of the in-memory computing system.

[0338] In some examples, the control device can read the calculation result after one group of storage cells has been calculated, or after multiple groups of storage cells in one calculation unit have been calculated, or after multiple groups of storage cells in multiple calculation units have been calculated, based on the status signal. This application does not specifically limit this.

[0339] In some implementations, the status signal of the storage circuit can be output through at least one terminal of the storage circuit instead of being transmitted via signaling. This implementation can reduce the number of signaling transmissions between the control device and the storage circuit, speed up data transmission between the two, improve data transmission efficiency, meet the real-time requirements of the storage process, and thus improve system performance.

[0340] Figure 16 illustrates a signaling timing diagram according to an exemplary embodiment of this application.

[0341] As shown in Figure 16, the signaling timing sent by the control device to the storage circuit may include the following process.

[0342] (1) The control device sends a first start signal to the storage circuit, such as the first start signal, which may include the storage start command shown in Figure 16, to indicate the start of the calculation.

[0343] (2) The control device sends an address signal to the storage circuit. For example, the address signal may include the address input command shown in Figure 16. The address signal may include the address information of multiple computing units participating in the calculation.

[0344] (3) The control device sends a data input command to the storage circuit. The data input command may include at least one input data from multiple computing units. Optionally, the data input command may include input data from multiple storage cell groups (belonging to multiple computing units respectively), and the input data of the multiple storage cell groups may be input in parallel. For a storage cell group (belonging to a computing unit), the data input command may optionally include multiple input data, and the multiple input data may be input serially. The data input command may also include at least one second start signaling and a second end signaling, located at the beginning and end positions of each input, to control a storage cell group in the storage circuit to perform multiple calculations. As an example, Figure 16 illustrates multiple data input commands and multiple calculations of a storage cell group. The address input command is used to indicate the addresses of multiple computing units. The first storage cell group belongs to the first computing unit, and the first computing unit may be any one of the multiple computing units indicated by the address input command. The first storage cell group includes multiple storage cell arrays located on the same layer in the Z direction of the first computing unit. Optionally, in addition to including the address information of multiple computing units, the address input command may also include first indication information, which may indicate the layer address of the first storage unit group.

[0345] (4) The control device sends control signals to the storage circuit, such as the storage enable command shown in Figure 16, to enable the switching of the storage cell group in the Z direction. Based on the storage enable command, the storage circuit can activate the second storage cell group in the first computing unit. The control device can also send at least one data input command to the storage circuit to control the second storage cell group to perform at least one calculation.

[0346] (5) The control device can send multiple control signals to the storage circuit, such as storage enable commands, to enable the switching of multiple storage cell groups in the Z direction. Any storage cell group can perform at least one calculation based on at least one data input command.

[0347] (6) The control device sends a storage end command to the storage circuit to indicate the end of the entire calculation process.

[0348] Figure 16 is for illustrative purposes only and shows a portion of the signaling timing provided in the embodiments of this application. During the calculation process of any group of memory cells in the control storage circuit, in addition to the signaling shown in Figure 16, which may include address input commands, enable input commands, or data input commands, other types of signaling may also be included, such as the end signaling and / or start signaling shown in Figure 14.

[0349] As an example, the storage circuit provided in any of the above embodiments may include NAND flash memory. The computing unit in the storage circuit includes a plane (or bank) in the NAND flash memory, and the multiple computing sub-units in the computing unit may include multiple blocks in the plane. The multiple storage cell arrays in the multiple computing sub-units may include multiple storage cell arrays located on the same layer in multiple blocks. The multiple storage cell arrays on the same layer may be connected to the same control line, for example, connected to the same word line (WL). Optionally, the storage cell arrays located on the same layer in a computing unit may be connected to the same WL, or the storage cell arrays located on the same layer in multiple computing units may be connected to the same WL.

[0350] This application also provides a control device, which may be located within or include the above-described control circuit. The control device may be located within the control circuit 120 / 220 shown in FIG. 1 or FIG. 2, or may be independent of the control circuit 120 / 220. This control device can be used to execute any of the above-described control methods.

[0351] This application embodiment also provides a control device, which may include a processor connected to a memory. The memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above control methods. The memory may be a memory within the control device or a memory outside the control device.

[0352] This application also provides a control device, as shown in FIG17. FIG17 shows a schematic diagram of another control device according to an exemplary embodiment of this application. As shown in FIG17, the control device 1700 includes: at least one processing circuit 1710 and an interface circuit 1720, the interface circuit 1720 being used for signal connection with a storage circuit, and at least one processing circuit 1710 being used for executing any of the control methods provided in the above embodiments.

[0353] For example, in some embodiments, the processing circuit may include an application-specific integrated circuit (ASIC), which implements some or all of the functions of the control device by designing the logical relationships between the devices within the circuit; as another example, in some embodiments, the processing circuit may be implemented by a programmable logic device (PLD) circuit, which may include a large number of logic devices, and the logical relationships between the logic devices are configured through a configuration file, thereby implementing some or all of the functions of the control device.

[0354] Optionally, the control device provided in the embodiments of this application can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0355] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, including, for example, a central processing unit (CPU), a microcontroller unit (MCU), a graphics processing unit (GPU), or a digital signal processor (DSP). Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0356] This application also provides a memory computing system, which includes a storage circuit and a control device, the control device being used to execute any of the control methods proposed in this application.

[0357] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0358] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0359] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0360] This application also provides an electronic device, as shown in FIG18. FIG18 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG18, the electronic device 1800 may include any of the above-described in-memory computing systems 1810 for processing data of the electronic device. The electronic device may also include an input / output device 1820 for receiving user input or outputting processing results. This application does not limit the input type and output type. For example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 1830, which may process data provided to the in-memory computing system 1810 or process the output data of the in-memory computing system 1810. The output of the input / output device 1820 may be based on the output of the processor 1830 or the output of the in-memory computing system 1810.

[0361] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0362] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method for controlling computation in a storage circuit, the storage circuit including a computation unit, the computation unit including a plurality of computation sub-units arranged along a first direction, one of the computation sub-units including a plurality of storage cell arrays arranged along a third direction, one of the storage cell arrays including storage cells arranged along the first direction and a second direction, the control method comprising: Send address signaling to the storage circuit, the address signaling including address information of multiple computing units; Send first data to the storage circuit, the first data being used as a first input to the first storage cell group; Send second data to the storage circuit, the second data being used as a second input to the first storage cell group; The first storage unit group belongs to the first computing unit and includes multiple first storage unit arrays. The multiple computing units include the first computing unit, and the multiple first storage unit arrays belong to multiple computing sub-units of the first computing unit.

2. The control method according to claim 1, wherein, The first data includes the input data of the plurality of first storage cell arrays of the first storage cell group.

3. The control method according to claim 1 or 2 further includes: In response to the transmission of the address signaling, wait for a first time period; Specifically, when the first time period expires, the first data is sent to the storage circuit.

4. The control method according to claim 3, wherein, The first time period is not less than the conversion time from receiving signaling to receiving data in the storage circuit.

5. The control method according to any one of claims 1 to 4, further comprising: A first start signaling is sent to the storage circuit, the first start signaling being used to indicate the start of computation, wherein the address signaling is used to indicate the plurality of computation units corresponding to the computation.

6. The control method according to claim 5 further includes: A first termination signal is sent to the storage circuit, the first termination signal indicating the end of the initial input for the calculation.

7. The control method according to claim 6 further includes: Acquire the status signal of the storage circuit, wherein a first status value of the status signal is used to indicate the working state and a second status value is used to indicate the ready state. When the status signal changes from the second status value to the first status value, wait for a second time period; Specifically, when the second time period expires, second data is sent to the storage circuit.

8. The control method according to any one of claims 1 to 7, further comprising: A second end signal is sent to the storage circuit, the second end signal indicating the end of the second data input.

9. The control method according to claim 8, further comprising: Acquire the status signal of the storage circuit, wherein a first status value of the status signal is used to indicate the working state and a second status value is used to indicate the preparation state; When the status signal changes from the first status value to the second status value, the second termination signal is sent to the storage circuit.

10. The control method according to any one of claims 1 to 9, further comprising: A second start signaling is sent to the storage circuit, the second start signaling being used to indicate the start of input of the second data.

11. The control method according to any one of claims 1 to 10, further comprising: Based on the address information of the plurality of computing units, third data is sent to the storage circuit. The third data is sent synchronously with the first data and is used as the first input of the second storage unit group. Based on the address information of the plurality of computing units, fourth data is sent to the storage circuit. The fourth data is sent synchronously with the second data, and the fourth data is used as the second input of the second storage unit group. The second storage unit group belongs to the second computing unit and includes multiple second storage unit arrays. The multiple computing units include the second computing unit, and the multiple second storage unit arrays belong to multiple computing sub-units of the second computing unit.

12. A control method for controlling computation in a storage circuit, the storage circuit including a computation unit, the computation unit including a plurality of computation sub-units arranged along a first direction, one of the computation sub-units including a plurality of storage cell arrays arranged along a third direction, one of the storage cell arrays including storage cells arranged along the first direction and a second direction, the control method comprising: Send address signaling to the storage circuit, the address signaling including address information of multiple computing units; Send first data to the storage circuit. The first data is used as input to the first storage unit group. The first storage unit group belongs to the first computing unit and includes multiple first storage unit arrays. The multiple first storage unit arrays belong to multiple computing sub-units of the first computing unit. The storage circuit sends second data, which is used as input to a second storage unit group. The second storage unit group belongs to the first computing unit and includes multiple second storage unit arrays, which belong to multiple computing sub-units of the first computing unit.

13. The control method according to claim 12, wherein, The address signaling further includes first indication information, which is used to indicate the position of the first storage cell group in the third direction, or the first indication information is used to indicate the address of the first control line, which is used to control the opening of the storage cells of the storage circuit at the third direction position where the first storage cell group is located.

14. The control method according to claim 12 or 13, further comprising: A control signal is sent to the storage circuit, the control signal being used to control the activation of the second storage cell group.

15. The control method according to claim 14, wherein, Each of the plurality of computing units includes a second storage unit group, and the control signaling is used to control the second storage unit groups of the plurality of computing units to be turned on synchronously.

16. The control method according to claim 14 or 15, wherein, The control signaling includes enable signaling, which enables the switching of the third-party up-enabled storage cell group.

17. The control method according to claim 16, wherein, The switching step size is 1.

18. The control method according to any one of claims 12 to 17, wherein, Sending the first data to the storage circuit includes: Based on the address information of the plurality of computing units, a plurality of first data are sent to the storage circuit, and the plurality of first data are respectively used as inputs to a plurality of first storage unit groups; Sending the second data to the storage circuit includes: Based on the address information of the plurality of computing units, a plurality of second data are sent to the storage circuit, and the plurality of second data are respectively used as inputs to a plurality of second storage unit groups.

19. The control method according to any one of claims 12 to 18, further comprising: A start signaling is sent to the storage circuit, the start signaling being used to indicate the start of computation, wherein the address signaling is used to indicate the plurality of computation units corresponding to the computation.

20. The control method according to claim 19, further comprising: A termination signal is sent to the storage circuit, the termination signal indicating the end of the computation.

21. The control method according to any one of claims 12 to 20, further comprising: A sampling signal is sent to the storage circuit, the sampling signal being used to enable the storage circuit to sample the first data or the second data.

22. The control method according to any one of claims 12 to 21, wherein, The first data and the second data are carried in data signaling, and the bit width of the data signaling is not less than 32 bits.

23. The control method according to any one of claims 12 to 22, further comprising: Acquire a status signal, wherein a first state of the status signal is used to indicate the output state of the storage circuit; When the status signal has the first state, the calculation result of the storage circuit is read, and the calculation result includes the calculation result of the first storage cell group or the calculation result of the second storage cell group.

24. A control device, comprising: An interface circuit and a processing circuit, wherein the interface circuit is used to signal connect with the processing circuit, and the processing circuit is used to execute the control method as described in any one of claims 1 to 23.

25. An in-memory computing system, comprising: The storage circuit, and the control device as described in claim 24.

26. An electronic device comprising: The in-memory computing system as described in claim 25.

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