Power semiconductor device and method of producing a power semiconductor device
Patent Information
- Application Number
- PCT/EP2025/057970
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2026-10-01
Smart Images
Figure EP2025057970_01102026_PF_FP_ABST
Abstract
Description
[0001] P2024, 1162 WO E / P240154WO01 March 24, 2025
[0002] 1
[0003] Description
[0004] POWER SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A POWER SEMICONDUCTOR DEVICE
[0005] The present disclosure relates to a power semiconductor device with an insulated trench gate electrode, for instance to an insulated gate bipolar transistor (IGBT), and to a method for producing a power semiconductor device.
[0006] It is well known that the switching characteristics of an IGBT or any MOS -based device in general are largely governed by its parasitic gate - capacitances namely gate-emitter capacitance, Cge, and gate - collector capacitance, Cgc, also known as reverse feedback or Miller capacitance. Gatecapacitances govern device switching characteristics i. e. switching losses and switching speed.
[0007] An obj ect to be solved is to provide a power semiconductor device with improved switching characteristics.
[0008] Exemplary embodiments of the disclosure address the above shortcomings, inter alia, for example a power semiconductor device according to claim 1. Further configurations and developments are the subj ect-matter of the dependent claims.
[0009] Firstly, the semiconductor device is specified.
[0010] According to an embodiment, the power semiconductor device has a semiconductor body extending along a center axis between an emitter side with a gate electrode and a collector side with a collector electrode. The collector side is arranged opposite the emitter side. The power semiconductorP2024, 1162 WO E / P240154WO01 March 24, 2025
[0011] device comprises a drift layer of a first conductivity type. The drift layer is arranged between the emitter side and the collector side. The power semiconductor device further comprises a base layer of a second conductivity type. The second conductivity type is different than the first conductivity type. The base layer extends between the drift layer and the emitter side. The power semiconductor device further comprises a source region of the first conductivity type. The source region is arranged on a side of the base layer that faces away from the drift layer.
[0012] In the subsequent description of the exemplary embodiments the first conductivity type is n- type and the second conductivity type is p- type so that the base layer 28 is a p-type layer. However, the layers may also be inverted with respect to their conductivity type. A region, layer or section being of electron conduction is n- type, or n-doped and a region, layer or section being of hole conduction is p-type, or p- doped.
[0013] The power semiconductor device further comprises a first trench and a second trench. The first trench and the second trench extend from the emitter side into the drift layer. The second trench is being spaced apart from the first trench at a first distance along a radial direction. For example, the first distance between the first trench and the second trench is between 0.1 µm and 20 µm inclusive, for example between 1 µm and 20 µm inclusive, for example between 0.1 µm and 10 µm inclusive, for example between 1 µm and 10 µm inclusive. The second trench encloses at least partially the first trench annularly.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0014] 3
[0015] An insulated trench gate electrode with a gate dielectric layer extends into the first trench. The trench gate electrode is electrically conductive and electrically insulated from the semiconductor body. The first trench is filled with an electrically conductive material, like highly doped polysilicon and forms the trench gate electrode. For instance, the electrically conductive material in the first trench is electrically connected to the gate electrode.
[0016] During operation of the power semiconductor device the first trench represents an active trench at the potential level of the gate voltage.
[0017] An electrically conductive layer extends into the second trench. The second trench is filled with an electrically conductive material, like highly doped polysilicon and forms the electrically conductive layer. For instance, the electrically conductive material in the second trench is electrically connected to the gate electrode.
[0018] The electrically conductive layer is electrically insulated from the drift layer and the base layer by an electrically insulating layer. The electrically conductive material of the electrically insulating layer is, for example, electrically isolated from the semiconductor body by isolating material. The first trench and the second trench may have the same depth, so that they can be formed in a common process step. The first trench and the second trench may have dif ferent depths. The gate dielectric layer and the electrically conductive layer may comprise the same material or different materials.
[0019] Trenches with a gate-biased electrode therein are called first trench, also known as active trenches. Trenches withP2024, 1162 WO E / P240154WO01 March 24, 2025
[0020] emi tter -biased electrode therein are called second trench, also known as dummy trenches. The first trench is connected to the gate and the second trench is connected to an emitter electrode.
[0021] The base layer comprises a first base region, a second base region and a third base region. The first base region, also known as p base, is arranged between the drift layer and the source region along the center axis. The base first region is arranged on the side of the first trench facing away from the second trench along the radial direction.
[0022] The second base region is arranged between the first trench and the second trench along the radial direction. The second base region separates the first trench and the second trench by the first distance along the radial direction.
[0023] The third base region is arranged on the side of the second trench facing away from the first trench along the radial direction. The third base region is also known as deep p-well.
[0024] A first contact region is embedded in the first base region. The first contact region, also called p contact, is of the second conductivity type, i. e. p- doped, and adj oins the first base region as well as the emitter side. The source region is also embedded in the first base region. The source region is of the first conductivity type, i. e. n-doped, and adj oins the first base region as well as the emitter side. At the emitter side, the source region is in direct mechanical and electrical contact with the gate electrode. Also, the first contact region is in direct mechanical and electrical contact with the gate electrode at the emitter side.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0025] Optimizing the device parasitic capacitance could significantly improve device switching performance. In this direction, several approaches have been reported in the literature to optimize and reduce gate - capacitances. Such techniques include split-gate (SG) design, side-gate concept, use of different combinations of gate and emi tter -biased trenches etc.
[0026] The use of an emi tter -biased trench to shield the
[0027] gate - trench in 2D improves coupling and thereby reduces Miller capacitance Cgc. This arrangement of cell -based trenches instead of ID stripes where the gate- trench is surrounded by emitter trench in 2D such that the perimeter of emitter trench is greater than the gate trench for improved emitter-gate coupling.
[0028] According to an embodiment, the first trench encloses at least partially the source region annularly, such that the first trench is arranged between the source region and the second trench.
[0029] According to a further embodiment, the second trench encloses at least partially the source region annularly, such that the source region is arranged between the first trench and the second trench.
[0030] According to a further embodiment, the first trench is a closed circular ring arranged around the central axis.
[0031] The first trench is a closed ring when viewed along the central axis.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0032] According to a further embodiment, the second trench is a closed circular ring arranged around the central axis.
[0033] The second trench is a closed ring when viewed along the central axis.
[0034] According to a further embodiment, the power semiconductor device comprises comprising at least one second contact region on the emitter side arranged along the radial direction.
[0035] The second contact region is embedded in the second base region. The second contact region is of the second conductivity type, i. e. p- doped, and adj oins the second base region as well as the emitter side. At the emitter side, the second contact region is in direct mechanical and electrical contact with the gate electrode. The gate electrode is not in direct mechanical or electrical contact with the second base region so that an exchange of charge carriers between the gate electrode and the second base region always has to happen through the second contact region.
[0036] For example, the second base region and the second contact region are arranged between the first trench and the second trench in the radial direction. The second base region may adj oin the first trench and the second trench in the radial direction.
[0037] According to a further embodiment, the at least one second contact region is arranged along the radial direction within the first trench.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0038] 7
[0039] According to a further embodiment, the at least one second contact region is arranged along the radial direction within the second trench.
[0040] According to a further embodiment, the first trench has a first central portion and a first peripheral portion extending away from the first central portion along the radial direction.
[0041] The first central portion is circularly arranged around the central axis C.
[0042] According to a further embodiment, the second trench has a second central portion and a second peripheral portion extending away from the second central portion along the radial direction.
[0043] The second central portion 42 is circularly arranged around the central axis C.
[0044] This continuous trench stripe configuration of the trenches facilitates to maintain continuity in the poly-distribution in the trench gate electrode and the electrically conductive layer.
[0045] According to a further embodiment, the power semiconductor device comprises a plurality of cell units.
[0046] According to a further embodiment the geometry of the cell unis may have any shape such as square, hexagonal, octagonal or spiral designs. The cell units are not limited to a circular shape when viewed along the center axis.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0047] According to a further embodiment the second trench is interrupted at two opposing sides along the radial direction, such that the first trench of one cell unit is interconnected with the first trench of at least one adj acent cell unit.
[0048] According to a further embodiment, the plurality of cell units is arranged in a line along the radial direction.
[0049] According to a further embodiment, the plurality of cell units is arranged in a grid along the radial direction.
[0050] The cell units are, for example, arranged in a line along the radial direction. Alternatively, the cell units are arranged in a grid- like structure, for example in a 3 by 3 matrix along the radial direction. The grid- like structure is not necessarily a symmetric structure and can deviate f rom this structure. For example, the cell units are arranged in a 4 by 2 grid.
[0051] According to a further embodiment, an insulating layer is arranged between the emitter side and the gate dielectric layer.
[0052] The power semiconductor device comprises on top of the emitter side an insulating layer. The insulating layer is for example a gate oxide or a field oxide layer. The insulating layer is also on the inside of the first and / or second trenches. Basically, the gate dielectric layer is in-between the insulated trench gate electrode and the insulating layer along the radial direction. Basically, the electrically insulating layer is in-between the electrically conductive layer and the insulating layer along the radial direction.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0053] 9
[0054] Using this arrangement of the power semiconductor device facilitates maintaining the continuity of gate-poly from one cell unit to another cell unit by creating small openings in the second trench to allow passing the gate-poly to the next cell unit on top of the insulating layer. The size of the openings in the second trench are between 1 µm and 5 µm.
[0055] According to a further embodiment, an interlayer dielectric is arranged on top of the emitter side.
[0056] The power semiconductor device comprises on top of the emitter side an interlayer dielectric. The interlayer dielectric is for example an undoped silicate gate (USG). Using this arrangement of the power semiconductor device facilitates maintaining the continuity of gate-poly from one cell unit to another cell unit by using two levels of Polygate depositions separated by the interlayer dielectric, which acts as an insulating layer.
[0057] According to a further embodiment, the first trench comprises a split-gate.
[0058] The split-gate regions with insulated trench gate electrodes and the electrically conductive layers extending in the radial direction. The insulated trench gate electrode and the electrically conductive layer are arranged side by side around the source region. Between the insulated trench gate electrode and the electrically conductive layer may be a gap or an insulation. The insulated trench gate electrode of the first trench is biased to the gate electrode. The electrically conductive layer of the second trench is biased to the emitter electrode.P2024, 1162 WO E / P240154WO01 March 24, 2025
[0059] 10
[0060] According to a further embodiment, the power semiconductor device is an insulated gate bipolar transistor, a MOSFET or a reverse conducting IGBT, wherein the semiconductor material comprises silicon and / or silicon carbide and / or gallium nitride.
[0061] Further aspects of the disclosure will become apparent from the following description of the exemplary embodiments and figures. In the exemplary embodiments and figures similar or similarly acting constituent parts are provided with the same reference signs. Generally, only the differences with respect to the individual embodiments are described. Unless specified otherwise, the description of a part or aspect in one embodiment applies to a corresponding part or aspect in another embodiment as well.
[0062] The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and / or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
[0063] Figure 1 is a schematic sectional view of a power semiconductor device according to an embodiment,
[0064] Figure 2 to 5 are schematic cross-sectional views of the power semiconductor device according to embodiments,
[0065] Figures 6 and 7 are schematic sectional views of the power semiconductor device according to further embodiments,
[0066] Figures 8 and 9 are further schematic cross-sectional views of the power semiconductor device according to embodiments.P2024, 1162 WO E / P240154W001 March 24, 2025
[0067] - 11 -
[0068] Figure 1 shows a power semiconductor device 100. The power semiconductor device 100 comprises a semiconductor body 2. The semiconductor body 2 extends between an emitter side 21 and a collector side 22 along a center axis C. The emitter side 21 and the collector side 22 extend mainly in a radial direction R. The radial direction R is perpendicular to the center axis C. The radial direction R points away from the center axis C. The collector side 22 is opposite the emitter side 21 along the center axis C. A gate electrode 51 is applied on the emitter side 21. A collector electrode 52 is applied on the collector side 22. The semiconductor body 2 is made of, for example, Si or SiC or GaN. The semiconductor device 100 has a structure which is similar to concentric circles when viewed from the direction along the center axis C. In particular, the semiconductor device 100 is arranged rotationally symmetrically around the center axis C.
[0069] The power semiconductor device 100 further comprises a drift layer 26 of a first conductivity type. The drift layer 26 is arranged between the emitter side 21 and the collector side 22. A base layer 28 of a second conductivity type different than the first conductivity type extends between the drift layer 26 and the emitter side 21. A source region 29 of the first conductivity type is arranged on a side of the base layer 28 that faces away from the drift layer 26.
[0070] In the subsequent description of the exemplary embodiments the first conductivity type is n- type and the second conductivity type is p- type so that the base layer 28 is a p-type layer. However, the layers may also be inverted with respect to their conductivity type. A region, layer or section being of electron conduction is n- type, or n-dopedP2024, 1162 WO E / P240154W001 March 24, 2025
[0071] - 12 -
[0072] and a region, layer or section being of hole conduction is p-type, or p- doped.
[0073] The power semiconductor device 100 further comprises a first trench 3 and a second trench 4. The first trench 3 and the second trench 4 extend from the emitter side 21 into the drift layer 26. An insulated trench gate electrode 30 with a gate dielectric layer 31 extends into the first trench 3. The trench gate electrode 30 is electrically conductive and electrically insulated from the semiconductor body 2. The first trench 3 is filled with an electrically conductive material, like highly doped polysilicon and forms the gate electrode 30. For instance, the electrically conductive material in the first trench 3 is electrically connected to the gate electrode 51. During operation of the power semiconductor device 100 the first trench 3 represents an active trench at the potential level of the gate voltage.
[0074] The base layer 28 comprises a first base region 281, a second base region 282 and a third base region 283. The first base region 281, also known as p base, is arranged between the drift layer 26 and the source region 29 along the center axis C. The base first region 281 is arranged on the side of the first trench 3 facing away from the second trench 4 along the radial direction R.
[0075] The second base region 282 is arranged between the first trench 3 and the second trench 4 along the radial direction R. The second base region 282 separates the first trench 3 and the second trench 4 by a first distance dl along the radial direction R.P2024, 1162 WO E / P240154W001 March 24, 2025
[0076] - 13 -
[0077] The third base region 283 is arranged on the side of the second trench 4 facing away from the first trench 3 along the radial direction R. The third base region 283 is also known as deep p-well.
[0078] A first contact region 284 is embedded in the first base region 281. The first contact region 284, also called p contact, is of the second conductivity type, i. e. p-doped, and adjoins the first base region 281 as well as the emitter side 21. The source region 29 is also embedded in the first base region 281. The source region 29 is of the first conductivity type, i.e. n-doped, and adjoins the first base region 281 as well as the emitter side 21. At the emitter side 21, the source region 29 is in direct mechanical and electrical contact with the gate electrode 51. Also, the first contact region 284 is in direct mechanical and electrical contact with the gate electrode 51 at the emitter side 21.
[0079] A second contact region 60 is embedded in the second base region 282. The second contact region 60 is of the second conductivity type, i.e. p-doped, and adjoins the second base region 282 as well as the emitter side 21. At the emitter side 21, the second contact region 60 is in direct mechanical and electrical contact with the gate electrode 51. The gate electrode 51 is not in direct mechanical or electrical contact with the second base region 282 so that an exchange of charge carriers between the gate electrode 51 and the second base region 282 always has to happen through the second contact region 60.
[0080] In figure 1 the second trench 4 is arranged on a side of the first trench 3 facing away from the source region 29 and doesP2024, 1162 WO E / P240154W001 March 24, 2025
[0081] 14
[0082] not represent an active trench. An electrically conductive layer 40 extends into the second trench 4. The second trench 4 is filled with an electrically conductive material, like highly doped polysilicon and forms the electrically conductive layer 40. For instance, the electrically conductive material in the second trench 4 is electrically connected to the gate electrode 51.
[0083] The electrically conductive layer 40 is electrically insulated from the drift layer 26 and the base layer 28 by an electrically insulating layer 41. The electrically conductive material of the electrically insulating layer 41 is, for example, electrically isolated form the semiconductor body 2 by isolating material. The first trench 3 and the second trench 4 may have the same depth, so that they can be formed in a common process step.
[0084] Trenches with a gate-biased electrode therein are called first trench 3, also known as active trenches. Trenches with emitter-biased electrode therein are called second trench 4, also known as dummy trenches. For example, the second base region 282 and the second contact region 60 are arranged between the first trench 3 and the second trench 4 in the radial direction R. The second base region 282 may adj oin the first trench 3 and the second trench 4 in the radial direction R.
[0085] The second base regions 282 each lie between two trenches 3, 4 and adj oin them. The trench closer to the first base region 281 is an active trench 3. The respective other second trench 4 is a dummy trench. The second trenches 4 are filled with electrically conductive material which is, for example, electrically connected to the gate electrode 51 and,P2024, 1162 WO E / P240154W001 March 24, 2025
[0086] - 15 -
[0087] therefore, lies on the same electrical potential as the gate electrode 51. The second trenches 4 help to reduce the capacitance between the gate electrodes 30 and the collector electrode 52, also called Miller capacitance or gate-collector capacitance, Cgc.
[0088] However, the electrically conductive layer 40 may also be electrically separated from the gate electrode 51. For example, the electrically conductive layer 40 is at the same voltage as the gate electrode 51 or at a positive voltage with respect to the gate electrode 51 during operation of the power semiconductor device 1. For example, the electrically conductive layer 40 is at the voltage applied to the gate electrode 51 or at the voltage applied to the insulated trench gate electrode 30. However, the applied voltage may also differ from both the voltage at the insulated trench gate electrode 30 and the voltage at the gate electrode 51. A positive voltage applied to the electrically conductive layer 40 may provide an improved electrostatic shielding of the second base region 282.
[0089] The trenches 3, 4 of the semiconductor device 100, independently of whether they are active or dummy trenches, may all have the same dimensions within the limits of the manufacturing tolerances. Alternatively, the second trenches 4 may be deeper or less deep than the first trenches 3.
[0090] Figure 1, as well as the other figures, may only show a section of a semiconductor device 100. The structures shown in these figures comprising the base layer 281, 282, 283 and the contact regions 284, 60 and the source region 29, and the electrodes 51 may be repeated several times in the radial direction R.P2024, 1162 WO E / P240154W001 March 24, 2025
[0091] - 16 -
[0092] Figures 2 to 5 show cross-sectional views of different embodiments of the power semiconductor device 100 along the sectional axis A-A.
[0093] Figure 2 shows the power semiconductor device 100 along the center axis C. The semiconductor device 100 has a structure which is similar to concentric circles when viewed from the direction along the center axis C. In particular, the semiconductor device 100 is arranged rotationally symmetrically around the center axis C. The power semiconductor device 100 extends along the radial direction R.
[0094] In the center of the power semiconductor device 100, the first contact region 284 is arranged. The first contact region 284 is surrounded by the source region 29. The source region 29 is surrounded by the first trench 3. The insulated trench gate electrode 30 is framed on its inner side facing the center axis C and its outer side facing away from the center axis C by the gate dielectric layer 31 of the first trench 3. The first trench 3 is surrounded by the second base region 282. The second base region 282 is surrounded by the second trench 4. The electrically conductive layer 40 is framed on its inner side facing the center axis C and its outer side facing away from the center axis C by the electrically insulating layer 41 of the second trench 4.
[0095] The second trench 4 is surrounded by the third base region 283. The second base region 282 is arranged between the first trench 3 and the second trench 4 along the radial direction R. More precisely, the second base region 282 is arranged between the insulated trench gate electrode 30 and its gateP2024, 1162 WO E / P240154W001 March 24, 2025
[0096] dielectric layer 31 and the electrically conductive layer 40 and its electrically insulating layer 41. The first trench 3 and the second trench 4 are spaced apart by the first distance dl.
[0097] Four of the second contact regions 60 are embedded in the second base region 282. The disclosed number of the second contact regions 60 is not limited to four contacts and can have any number of second contact regions 60. The second contact regions 60 are arranged in an equidistant manner, such that the angular distance between two second contact regions 60 is approximately 90°. The angular distance can deviate from 90°, and an asymmetric arrangement of the second contact regions 60 is also possible. For, example three second contact regions 60 can be arranged around the center axis C with an angular distance of 120°. Alternatively, 2, 5, 6 or more second contact regions 60 are arranged around the center axis C.
[0098] Figure 3 shows the power semiconductor device 100 along the center axis C in a different configuration.
[0099] The semiconductor device 100 has a structure which is similar to concentric circles when viewed from the direction along the center axis C. The power semiconductor device 100 extends along the radial direction R.
[0100] In the center of the power semiconductor device 100, the second base region 282 is arranged. The second contact region 60 is embedded in the second base region 282 at the center of the semiconductor device 100. The second base region 282 is surrounded by the first trench 3. The insulated trench gate electrode 30 is framed on its inner side facing the centerP2024, 1162 WO E / P240154W001 March 24, 2025
[0101] axis C and its outer side facing away from the center axis C by the gate dielectric layer 31 of the first trench 3. The first trench 3 is surrounded by the source region 29.
[0102] The source region 29 is surrounded by the first contact region 284. The first contact region 284 is surrounded by the second trench 4. The electrically conductive layer 40 is framed on its inner side facing the center axis C and its outer side facing away from the center axis C by the electrically insulating layer 41 of the second trench 4. The second trench 4 is again surrounded by the third base region 283. The first trench 3 and the second trench 4 are spaced apart by the first distance dl.
[0103] Figure 4 shows the power semiconductor device 100 along the center axis C in a different configuration. The configuration of the semiconductor device 100 is similar to the configuration of the semiconductor device 100 from fig. 2. The difference is that the source region 29 is surrounded by the first trench 3. More precisely, the source region 29 is arranged by the insulated trench gate electrode 30 and the electrically conductive layer 40. The arrangement of the insulated trench gate electrode 30 and the electrically conductive layer 40 is also called a split-gate. The insulated trench gate electrode 30 and the electrically conductive layer 40 are arranged side by side around the source region 29. Between the insulated trench gate electrode 30 and the electrically conductive layer 40 may be a gap or an insulation (not shown). The insulated trench gate electrode 30 of the first trench 3 is biased to the gate electrode 51. The electrically conductive layer 40 of the second trench 4 is biased to the emitter electrode.P2024, 1162 WO E / P240154W001 March 24, 2025
[0104] - 19 -
[0105] Figure 5 shows the power semiconductor device 100 along the center axis C in a different configuration. The semiconductor device 100 has a structure which is a combination of concentric circles and continuous trench stripes along the radial direction R when viewed from the direction along the center axis C. The power semiconductor device 100 extends mainly along the radial direction R.
[0106] In the center of the power semiconductor device 100, the first contact region 284 is arranged. The first contact region 284 is concentrically surrounded by the source region 29. The source region 29 is surrounded by the first trench 3. The insulated trench gate electrode 30 is framed on its inner side facing the center axis C and its outer side facing away from the center axis C by the gate dielectric layer 31 of the first trench 3. While the inner side of the gate dielectric layer 31 concentrically surrounds the source region 29, the outer side of the gate dielectric layer 31 facing away from the center axis C surrounds the source region 29 mainly concentrically, but also extends along the radial direction R away from the center axis C. The first trench 3 has a striplike structure along the radial direction R. The first trench 3 is surrounded by the second base region 282. The second base region 282 is similarly shaped like the first trench 3 and has a continuous strip-like shape along the radial direction R.
[0107] The second base region 282 is surrounded by the second trench 4. The electrically conductive layer 40 is framed on its inner side facing the center axis C and its outer side facing away from the center axis C by the electrically insulating layer 41 of the second trench 4. The second trench 4 isP2024, 1162 WO E / P240154W001 March 24, 2025
[0108] similarly shaped like the first trench 3 and has a continuous strip- like shape along the radial direction R.
[0109] The first trench has a first central portion 32 and a first peripheral portion 33 extending away from the first central portion 32 along the radial direction R. The first central portion 32 is circularly arranged around the central axis C.
[0110] The second trench 4 has a second central portion 42 and a second peripheral portion 43 extending away from the second central portion 42 along the radial direction R. The second central portion 42 is circularly arranged around the central axis C.
[0111] This continuous trench stripe configuration of the trenches 3, 4 facilitates to maintain continuity in the poly-distribution in the trench gate electrode 30 and the electrically conductive layer 40.
[0112] The second base region 282 is arranged between the first trench 3 and the second trench 4 along the radial direction R. More precisely, the second base region 282 is arranged between the insulated trench gate electrode 30 and its gate dielectric layer 31 and the electrically conductive layer 40 and its electrically insulating layer 41.
[0113] Figures 6 and 7 show schematic sectional views of the power semiconductor device 100 in different arrangements of cell units 1.
[0114] Figure 6 shows the power semiconductor device 100 with a plurality of cell units 1. The cell units 1 are arranged in a line along the radial direction R. Alternatively, the cellP2024, 1162 WO E / P240154W001 March 24, 2025
[0115] 21
[0116] units 1 are arranged in a grid-like structure, for example in a 3 by 3 matrix along the radial direction R. The grid-like structure is not necessarily a symmetric structure and can deviate from this structure. For example, the cell units 1 are arranged in a 4 by 2 grid.
[0117] In figure 6 the dashed line B-B indicates a cross-sectional view of the power semiconductor device 100. The power semiconductor device 100 comprises on top of the emitter side 21 an interlayer dielectric 35. The interlayer dielectric 35 is for example an undoped silicate gate (USG). Using this arrangement of the power semiconductor device 100 facilitates maintaining the continuity of gate-poly from one cell unit 1 to another cell unit 1 by using two levels of Poly- gate depositions separated by the interlayer dielectric 35, which acts as an insulating layer.
[0118] Figure 7 shows the power semiconductor device 100 with the plurality of cell units 1 in a different configuration. The cell units 1 are arranged in a line along the radial direction R. Alternatively, the cell units 1 are arranged in a grid-like structure, for example in a 3 by 3 matrix along the radial direction R. The grid-like structure is not necessarily a symmetric structure and can deviate from this structure. For example, the cell units 1 are arranged in a 4 by 2 grid.
[0119] In figure 7 the dashed line C-C indicates a cross-sectional view of the power semiconductor device 100. The power semiconductor device 100 comprises on top of the emitter side 21 a gate oxide layer 70. The gate oxide layer 70 is also on the trenches 3, 4 (not shown).P2024, 1162 WO E / P240154W001 March 24, 2025
[0120] - 22 -
[0121] Using this arrangement of the power semiconductor device 100 facilitates maintaining the continuity of gate-poly from one cell unit 1 to another cell unit 1 by creating small openings in the second trench 4 to allow passing the gate poly to the next cell unit 1 on top of the insulating layer, more precisely on top of the gate oxide layer 70. The size of the openings in the second trench 4 are between 1 µm and 5 µm.
[0122] Figures 8 and 9 show further schematic cross-sectional views of the power semiconductor device 100.
[0123] Figure 8 shows the power semiconductor device 100 along the center axis C in a different configuration. The configuration of the semiconductor device 100 is similar to the semiconductor device 100 of figure 1 and differs by the geometry of the first trench 3. In this configuration the first trench 3 has a similar arrangement and geometry as the first contact region 284 of figure 2 when viewed from the direction along the center axis C. In particular, the semiconductor device 100 is arranged rotationally symmetrically around the center axis C. The power semiconductor device 100 extends along the radial direction R. The radial direction R extends away from the center axis C. In the center of the power semiconductor device 100, the first trench 3 is arranged. The first trench 3 is surrounded by the source region and the first contact region 284. The source region 29 is surrounded by the second trench 4.
[0124] The center axis C extends through the insulated trench gate electrode 30. The insulated trench gate electrode 30 is framed on its sides facing away from the center axis C by the gate dielectric layer 31. The first trench 3 is further surrounded by the second base region 282. The second baseP2024, 1162 WO E / P240154W001 March 24, 2025
[0125] - 23 -
[0126] region 282 is surrounded by the second trench 4. The electrically conductive layer 40 is framed on its inner side facing the center axis C and its outer side facing away from the center axis C by the electrically insulating layer 41 of the second trench 4.
[0127] The second trench 4 is surrounded by the third base region 283. The second base region 282 is arranged between the first trench 3 and the second trench 4 along the radial direction R. More precisely, the second base region 282 is arranged between the insulated trench gate electrode 30 and its gate dielectric layer 31 and the electrically conductive layer 40 and its electrically insulating layer 41. The first trench 3 and the second trench 4 are spaced apart by the first distance dl.
[0128] The shape of the first trench 3 is not limited to a circular shape when viewed from the direction of the center axis C. The first trench 3 may also have an elongated shape when viewed from the direction of the center axis C. For example, the shape of the first trench is elliptical and correspondingly the second trench has also an elliptical shape when viewed from the direction of the center axis C. Alternatively, the shape of the first trench 3 and the second trench 4 is square, hexagonal, octagonal or has a spiral design.
[0129] Figure 9 shows the power semiconductor device 100 along the center axis C in a different configuration. The configuration of the semiconductor device 100 is similar to the semiconductor device 100 of figure 8 and differs by the amount of first trenches 3 and second trenches 4.P2024, 1162 WO E / P240154W001 March 24, 2025
[0130] - 24 -
[0131] Multiple pairs of first trenches 3 surrounded by second trenches 4 are arranged next to each other along the radial direction R. Again, the first trenches are similar to the first contact region 284 shown in figure 2. Alternatively, all the trenches 3, 4 have the shape of concentric circles when viewed from the direction along the center axis C.
[0132] Alternatively, the shape of the first trench 3 and / or the second trench is elliptical, square, hexagonal, octagonal or has a spiral design when viewed from the direction along the center axis C.
[0133] The disclosure described herein is not restricted by the description given with reference to the exemplary embodiments. Rather, the disclosure encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.P2024, 1162 WO E / P240154W001 March 24, 2025
[0134] - 25 -
[0135] Reference Signs
[0136] 100 power semiconductor device
[0137] 1 cell unit
[0138] 2 semiconductor body
[0139] 21 emitter side
[0140] 22 collector side
[0141] 25 collector layer
[0142] 26 drift layer
[0143] 28 base layer
[0144] 281 first base region
[0145] 282 second base region
[0146] 283 third base region
[0147] 284 first contact region
[0148] 29 source region
[0149] 3 first trench
[0150] 30 insulated trench gate electrode 31 gate dielectric layer
[0151] 35 interlayer dielectric
[0152] 4 second trench
[0153] 40 electrically conductive layer 41 electrically insulating layer 51 gate electrode
[0154] 52 collector electrode
[0155] 60 second contact region
[0156] 70 insulating layer
[0157] C center axis
[0158] R radial direction
[0159] dl first distance
Claims
P2024, 1162 WO E / P240154W001 March 24, 2025Claims1. A power semiconductor device (100) with a semiconductor body (2) extending along a center axis (C) between an emitter side (21) with a gate electrode (51) and a collector side (22) with a collector electrode (52) opposite the emitter side (21), the power semiconductor device (100) comprising:a drift layer (26) of a first conductivity type;a base layer (28) of a second conductivity type different than the first conductivity type extending between the drift layer (26) and the emitter side (21);a source region (29 ) of the first conductivity type arranged on a side of the base layer (28) facing away from the drift layer (26);a first trench (3 ) extending from the emitter side (21) into the drift layer (26);an insulated trench gate electrode (30) extending into the first trench (3 );a second trench (4) extending from the emitter side (21) into the drift layer (26), and being spaced from the first trench (3 ) at a first distance (dl) along a radial direction (R), wherein- the second trench (4) encloses at least partially the first trench (3 ) annularly, andan electrically conductive layer (40) extending into the second trench (4), the electrically conductive layer (40) being electrically insulated from the base layer (28) and the drift layer (26) by an electrically insulating layer (41).
2. Power semiconductor device (100) according to claim 1, wherein the first trench (3 ) encloses at least partially the source region (29 ) annularly, such that the first trench (3 )P2024, 1162 WO E / P240154W001 March 24, 202527is arranged between the source region (29 ) and the second trench (4 ).
3. Power semiconductor device (100) according to claim 1, wherein the second trench (4) encloses at least partially the source region (29 ) annularly, such that the source region (29 ) is arranged between the first trench (3 ) and the second trench (4 ).
4. Power semiconductor device (100) according to any of the preceding claims, wherein the first trench (3 ) is a closed circular ring arranged around the central axis (C).
5. Power semiconductor device (100) according to any of the preceding claims, wherein the second trench (4) is a closed circular ring arranged around the central axis (C).
6. Power semiconductor device (100) according to any of the preceding claims, wherein the first distance (dl) between the first trench (3 ) and the second trench (4) is between 0.1 pm and 20 pm inclusive.
7. Power semiconductor device (100) according to any of the preceding claims, comprising at least one second contact region (60) on the emitter side (21) arranged along the radial direction (R).
8. Power semiconductor device (100) according to claim 7, wherein the at least one second contact region (60) is arranged along the radial direction (R) within the first trench ( 3 ).P2024, 1162 WO E / P240154W001 March 24, 20259. Power semiconductor device (100) according to claim 7 or 8, wherein the at least one second contact region ( 60) is arranged along the radial direction (R) within the second trench ( 3 ).
10. Power semiconductor device (100) according to any of the preceding claims, wherein the first trench (3 ) has a first central portion (32) and a first peripheral portion (33 ) extending away from the first central portion (32) along the radial direction (R).
11. Power semiconductor device (100) according to any of the preceding claims, wherein the second trench (4) has a second central portion (42) and a second peripheral portion (43 ) extending away from the second central portion (42) along the radial direction (R).
12. Power semiconductor device (100) according to any of the preceding claims, comprising a plurality of cell units (1).
13. Power semiconductor device (100) according to claim 12, wherein the shape of the geometry of the cell unit (1) is square, hexagonal, octagonal or has a spiral design.
14. Power semiconductor device (100) according to claim 12 or 13, wherein the second trench (4) is interrupted at two opposing sides along the radial direction (R), such that the first trench (3 ) of one cell unit (1) is interconnected with the first trench (3 ) of at least one adj acent cell unit (1).
15. Power semiconductor device (100) according to any of claims 12 to 14, wherein the plurality of cell units (1) is arranged in a line along the radial direction (R).P2024, 1162 WO E / P240154W001 March 24, 2025- 29 -16. Power semiconductor device (100) according to any of claims 12 to 15, wherein the plurality of cell units (1) is arranged in a grid along the radial direction (R).
17. Power semiconductor device (100) according to any of the preceding claims, wherein an insulating layer (70) is arranged between the emitter side (21) and the gate dielectric layer (31).
18. Power semiconductor device (100) according to any of the preceding claims, comprising an interlayer dielectric (35) arranged on top of the emitter side (21).
19. Power semiconductor device (100) according to any of the preceding claims, wherein the first trench (3 ) comprises a split - gate.
20. Power semiconductor device (100) according to any of the preceding claims, wherein the power semiconductor device (100) is an insulated gate bipolar transistor, a MOSFET or a reverse conducting IGBT, wherein the semiconductor material comprises silicon and / or silicon carbide and / or gallium nitride.