Amplifier with improved power supply rejection ratio

Abstract

An operational amplifier circuit includes a first transistor coupled to an output node, configured to generate an output signal based on an input signal applied to its gate and a combined bias current provided to the output node. The circuit further includes a current redistribution circuit having a first current path with a second transistor providing a first bias current to a first injection point at the output node and a second current path with a third transistor providing a second bias current to a second injection point coupled to a terminal of the first transistor. A potential-setting component is coupled between the first and second injection points, establishing a higher electrical potential at the second injection point than at the first injection point. The second and third transistors are coupled to a shared supply voltage source, and their respective bias currents collectively form the combined bias current.

Description

[0001] 2024P01135 P98425

[0002] - 1 -

[0003] AMPLIFIER WITH IMPROVED POWER SUPPLY REJECTION RATIO

[0004] Description

[0005] FIELD

[0006] This disclosure generally relates to operational amplifier circuits with enhanced power supply rej ection ratio (PSRR) .

[0007] BACKGROUND

[0008] Various applications require operational amplifiers that maintain high signal integrity in environments with power supply noise and fluctuations . This is important in power management systems, sensor interfaces, and high-precision analog signal processing circuits, where fluctuations in supply voltage can degrade performance . Specific applications include medical instrumentation, low-noise amplifiers, ADC front-end circuits, and power regulation systems in DC-DC converter-based architectures, e . g. in high noise environments, e . g. in automotive applications .

[0009] It is an obj ective of the invention to provide an operational amplifier circuit having improved operational characteristics .

[0010] The invention is set out in the appended set of claims .

[0011] In one aspect, an operational amplifier circuit is provided including: a first transistor coupled to an output node and configured to provide an output signal to the output node based on an input signal provided to a gate of the first transistor and based on a combined bias current provided to the output node . The operational amplifier circuit further includes a current redistribution circuit . The current redistribution circuit includes a first current path including a second transistor configured to provide a first bias current to a2024P01135 P98425

[0012] first inj ection point, the first inj ection point coupled to the output node . The current redistribution circuit further includes a second current path including a third transistor configured to provide a second bias current to a second inj ection point, the second inj ection point coupled to a terminal of the first transistor . The operational amplifier circuit further includes a potential setting component coupled between the first inj ection point and the second inj ection point and configured that in operation the drain-source voltage of the third transistor is larger than the drain-source voltage of the second transistor . The second transistor and the third transistor are coupled to a shared supply voltage source . The first bias current and the second bias current form the combined bias current .

[0013] In another aspect, a method for manufacturing an operational amplifier circuit is provided. The method includes forming a first transistor coupled to an output node and configured to provide an output signal to the output node based on an input signal provided to a gate of the first transistor and based on a combined bias current provided to the output node . The method further includes forming a current redistribution circuit . The current redistribution circuit includes a first current path including a second transistor configured to provide a first bias current to a first inj ection point, the first inj ection point being coupled to the output node . The current redistribution circuit further includes a second current path including a third transistor configured to provide a second bias current to a second inj ection point, the second inj ection point being coupled to a terminal of the first transistor . The method further includes forming a potentialsetting component coupled between the first inj ection point and the second inj ection point . The potential-setting component is configured that in operation the drain-source voltage of the third transistor is larger than the drain-source voltage of the second transistor . The second transistor and the third transistor are coupled to a shared supply voltage2024P01135 P98425

[0014] 3

[0015] source . The first bias current and the second bias current form the combined bias current .

[0016] By redistributing the bias current between the inj ection points, the disclosed amplifier circuit mitigates power supply variations that would otherwise couple into the output signal, particularly at higher frequencies . This configuration attenuates supply-induced disturbances, improving the power supply rej ection ratio (PSRR) in frequency ranges where conventional amplifiers exhibit degradation. As a result, the operational amplifier circuit may maintain a lower noise floor, enhancing the signal-to-noise ratio (SNR) in environments subj ect to supply fluctuations, electromagnetic interference, or switching noise . These improvements are particularly advantageous in precision analog front-end circuits, communication systems, and sensor applications, for example .

[0017] In the drawings, like reference characters generally refer to the same parts throughout the different views . The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which :

[0018] FIG.1A shows a circuit diagram of an amplifier stage of a comparative example;

[0019] FIG. IB shows an IV diagram and an uV diagram of an amplifier stage;

[0020] FIG. 2 shows a circuit diagram of an amplifier stage according to various embodiments;2024P01135 P98425

[0021] FIG. 3 shows a circuit diagram of an amplifier stage according to various embodiments; and

[0022] FIG. 4 shows graph illustrating the power supply rej ection ratio for the circuits illustrated in FIG. l to FIG. 3.

[0023] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the disclosure may be practiced. One or more aspects are described in sufficient detail to enable those skilled in the art to practice the disclosure . Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the disclosure . The various aspects described herein are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects . Various aspects are described in connection with methods and various aspects are described in connection with devices . However, it may be understood that aspects described in connection with methods may similarly apply to the devices, and vice versa . Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures . Throughout the drawings, it should be noted that proportions are not necessary to scale and that the size of features may be emphasized for ease of illustration.

[0024] Operational amplifiers are fundamental components in analog circuit design, widely used in applications requiring high precision, stability, and dynamic performance . Among the available amplifier architectures, the two-stage topology is commonly employed due to its ability to provide high gain, low noise characteristics, and the capability to efficiently drive capacitive loads . The first stage of such an amplifier is typically designed with a minimal number of components to reduce primary noise and offset sources, thereby improving2024P01135 P98425

[0025] 5

[0026] accuracy. The second stage, in turn, may be configured to provide additional drive strength and bandwidth while utilizing the Miller effect for compensation. This compensation mechanism inherently results in pole-splitting, shifting the dominant pole to a higher frequency, which can contribute to achieving a large gain-bandwidth product (GBW) while maintaining stability. However, a two-stage configuration is not necessarily required, as similar considerations may apply to a single-stage amplifier where the same trade-offs between PSRR, gain, and output drive capability arise .

[0027] In applications where power supply rej ection ratio (PSRR) performance is relevant, achieving a large GBW may be desirable, as it can facilitate suppression of high-frequency disturbances originating from cascaded amplifier stages or fluctuations in the power supply. To achieve this, the amplifier' s biasing may be adjusted to push the output pole to a higher frequency, thereby improving stability under varying load conditions . However, this approach introduces additional considerations related to supply-induced disturbances that propagate through the amplifier and impact overall performance .

[0028] In conventional amplifier architectures, such as that illustrated in FIG.1A, the output stage remains susceptible to noise coupling from the supply rail due to the finite output impedance of the biasing current generator, typically implemented as a transistor . The drain-source resistance rds and drain capacitance Cd of this transistor Mpout 9 create a conductive and capacitive path through which fluctuations in the supply voltage Vdd can reach the amplifier output (e . g. between Mpout and Mnout) . This issue may become particularly critical when the output voltage is near the supply rail, as the transistor may enter the triode region, significantly reducing its output impedance and leading to degradation in PSRR performance .2024P01135 P98425

[0029] 6

[0030] The extent to which supply disturbances affect an operational amplifier depends on the gain distribution across its stages . The first-stage amplifier may play a role in rej ecting supply variations, but as frequency increases beyond the GBW, its ability to suppress disturbances diminishes . This may render the second stage increasingly significant in determining the overall PSRR of the system. In power management circuits, where the supply voltage is often derived from DC-DC converters, the issue may become more pronounced. DC-DC converters introduce ripple components into the supply voltage, with a fundamental frequency in the megahertz range and additional harmonics that may bypass conventional rej ection mechanisms and interfere with amplifier operation. If not adequately suppressed, these high-frequency noise components may degrade signal integrity and overall system performance .

[0031] The operational amplifier circuit in various embodiments effectively mitigates supply disturbances while avoiding unnecessary complexity or trade-offs in other amplifier parameters .

[0032] In the context of the present disclosure, an amplifier stage refers to a circuit configuration designed to receive an input signal and generate an amplified output signal . The amplifier stage may be implemented in various forms, including a single-stage amplifier or a multi-stage amplifier, where a multistage configuration may include a first-stage differential amplifier followed by a second-stage gain stage . The amplifier stage may incorporate active and passive components to set gain characteristics, frequency response, and output impedance, depending on the specific implementation.

[0033] In the context of the present disclosure, a cascode transistor refers to a transistor including a source, a drain, and a gate, where the gate may receive a bias voltage, and the drain may be coupled to an output node of an amplifier stage . The2024P01135 P98425

[0034] 7

[0035] cascode transistor may operate in saturation mode, where the drain-source voltage (V_DS) remains sufficiently high to prevent the device from entering the linear (triode) region. Under these conditions, the cascode transistor may act as an intermediate current steering element, directing any current inj ected at its source towards its drain, which may coincide with the amplifier output . Once the gate is controlled via a stable biasing circuit and the source terminal receives a current redistributed from the bias current supply, the circuit may improve the amplifier' s ability to mitigate noise and unwanted supply-induced disturbances at the output node in case the current inj ected into the source by the redistribution section exhibits reduced sensitivity to supply variations . However, the redistribution of bias current may be achieved by other means, and the cascode transistor itself is not necessarily required.

[0036] In the context of the present disclosure, a biasing circuit refers to a circuit arrangement that provides a voltage or current to establish an operating point of an active component, such as a transistor . In the case of a cascode transistor, the biasing circuit may be configured to apply a bias voltage to the gate to maintain operation in a desired region, such as saturation mode . The biasing circuit may include one or more voltage reference generators, resistor-divider networks, current mirrors, or feedback-controlled bias sources, depending on the implementation. In some configurations, the biasing circuit may be designed to maintain stable transistor operation despite variations in supply voltage, temperature, or process conditions .

[0037] In the context of the present disclosure, a current redistribution circuit refers to a circuit arrangement that divides a bias current into at least two paths and directs portions of the bias current to different circuit nodes or provides different bias currents . In some configurations, the current redistribution circuit may include a first current2024P01135 P98425

[0038] 8

[0039] path that directs a first portion of the bias current to the output node and a second current path that directs a second portion of the bias current to an internal node of the amplifier circuit, such as the source of a cascode transistor . The second current path may establish a conductive connection between the source of the cascode transistor and a bias current source . By redistributing the bias current in this manner, the overall current that biases Mnout may originate from current sources operating under different conditions, which may influence how supply variations propagate through the amplifier circuit . The redistribution of bias current may be achieved through multiple circuit configurations, including those without a cascode structure .

[0040] In the context of the present disclosure, a current mirror refers to a circuit configuration that replicates or scales a reference current, such as Ibiasl or Ibias2, using one or more reference transistors, such as 124, 124-1, or 124-2 (see FIG. 2 and FIG. 3) . A current mirror may be included in the current redistribution circuit to regulate the second portion of the bias current, for example, the current directed to the source of a cascode transistor or another internal amplifier node . The current mirror may be configured to ensure that the bias current division remains proportional to a predetermined reference level, thereby maintaining consistent operating conditions across variations in process, voltage, or temperature .

[0041] In the context of the present disclosure, a power supply rej ection ratio (PSRR) refers to the ability of an electrical circuit, particularly an amplifier, to attenuate variations in its power supply voltage and reduce their influence on the output signal . PSRR may be a measurable parameter characterizing the extent to which an amplifier mitigates supply noise or fluctuations . The redistribution of bias current, as disclosed herein, may influence PSRR by modifying2024P01135 P98425

[0042] 9

[0043] how supply variations propagate through the amplifier' s biasing elements and output stage .

[0044] PSRR is typically expressed in decibels (dB) and is mathematically defined as :

[0045]

[0046] where AVsuppiyrepresents a variation in the supply voltage, and AVout represents the corresponding variation at the amplifier output .

[0047] PSRR is particularly relevant in low-noise analog applications, including precision sensor interfaces, medical instrumentation, and analog-to-digital converter (ADC) frontend circuits . In power management systems, particularly those utilizing DC-DC converters, PSRR mitigates supply ripple components that typically occur at frequencies between 1 MHz and 100 MHz .

[0048] Typical PSRR values range from 60 dB in low-end operational amplifiers to over 100 dB in high-precision designs . In linear voltage regulators (LDOs) , PSRR is generally high at low frequencies but decreases at higher frequencies . PSRR optimization in circuit design may include dynamic bias modulation, feedback control mechanisms, and selective filtering techniques to improve noise rej ection over a broad frequency spectrum while maintaining other performance parameters, such as gain-bandwidth product (GBW) and output drive capability.

[0049] FIG.1A shows a circuit diagram of an amplifier stage of a comparative example employed in applications requiring high signal amplification, such as automotive environments subj ect to significant electrical noise . The circuit comprises an amplifier circuit 1, which includes a first amplifier stage 2 that provides initial gain and a second amplifier stage 3 that is coupled in series to further amplify the signal . The second2024P01135 P98425

[0050] 10

[0051] amplifier stage 3 includes a transistor Mnout 4, having a gate coupled to the input of the second stage, a drain providing the output, and a source coupled to a power supply circuit . A resistive-capacitive (RC) circuit is connected in parallel between the drain and gate of Mnout 4, influencing the frequency response of the stage .

[0052] The VDD circuit includes a bias source 6 ( Ibias) , which is coupled to the gate of a transistor Mpout 8 and to the drain and gate of another transistor 7, forming a reference circuit for biasing. The drain of Mpout 8 is connected to the drain of Mnout 4, establishing a direct current path between the amplifier output and the supply rail . A parasitic AC path, illustrated by rds 9 and Cd 10, forms between the source and drain of Mpout 8.

[0053] In some amplifier topologies, such as the example shown in FIG.1A, a two-stage architecture is employed to achieve a high gain-bandwidth product (GBW) while ensuring robust signal amplification. In such cases, the first amplifier stage 2 is designed to introduce minimal noise while amplifying the input signal, while the second amplifier stage 3 provides additional gain and output drive capability. The circuit exploits Miller compensation, which inherently pushes the output pole to a higher frequency, extending bandwidth and improving gain.

[0054] As illustrated in FIG.1A, a limitation of this approach arises from the biasing scheme of the second stage . The biasing transistor Mpout 8, which serves as a current source, exhibits a finite drain-source resistance (rds 9) and drain capacitance (Cd 10) . These parasitic elements form an unintended low-impedance AC path between the supply rail Vdd and the output node, allowing supply variations to couple into the amplified signal . This effect becomes particularly critical in high-noise environments, such as automotive systems, where fluctuations in the power supply— resulting from switching2024P01135 P98425

[0055] - 11 -

[0056] regulators, load variations, or electromagnetic interference-are prevalent .

[0057] A drawback of this configuration is the dependence of Mpout 8 on its operating region, as also illustrated in FIG.1A. When Mpout 8 operates in saturation mode, its output impedance remains high, limiting the extent of supply noise coupling. However, as the output voltage approaches the voltage of the supply rail Vdd, Mpout 8 may enter the triode region, where its rds collapses, drastically reducing its impedance and increasing susceptibility to power supply fluctuations . As a result, the power supply rej ection ratio (PSRR) degrades, particularly at higher frequency ranges, where Cd 10 dominates the impedance response, further exacerbating the problem.

[0058] Attempts to mitigate these effects by increasing the aspect ratio (W / L) of Mpout 8 may improve rds 9 but introduce additional trade-offs, including increased device area and higher parasitic capacitance Cd. Alternatively, employing external RC filtering could theoretically reduce the impact of supply variations . However, this approach is often impractical, particularly in power-sensitive applications, where even a small DC bias shift may cause undesirable variations in output voltage . Another option, inserting a low-dropout regulator (LDO) between the DC-DC converter and the amplifier stage, may present cost and complexity challenges, making it unsuitable for certain applications .

[0059] FIG. IB illustrates an IV diagram (top) and an uV diagram (bottom) of an amplifier stage . FIG. IB illustrates the operating characteristics of a transistor in the biasing network, highlighting the relationship between drain-source voltage (Vds) , drain current ( Id) , and impedance behavior . The figure includes an IV diagram (top graph) and a uV diagram (bottom graph) , which together illustrate the effects of biasing conditions on output impedance and PSRR performance .2024P01135 P98425

[0060] - 12 -

[0061] In the top graph, the IV curve 30 represents drain current I 20 as a function of drain-source voltage V 24. The curve 30 demonstrates the expected transition between operating regions in a MOSFET, showing three distinct voltage levels marked by vertical dashed lines 32, 34, and 36. At low drain-source voltage Vds lower than dashed line 32, the transistor operates in the triode region, where drain current increases steeply with voltage . At intermediate voltage (between dashed lines 32 and 34, the transistor enters the transition region where the relationship between Id and Vds begins to linearize . At higher drain-source voltage, e . g. between dashed lines 34 and 36, the transistor operates deep in saturation, where current is primarily controlled by gate-source voltage Vgs, and further increases in Vds have minimal impact on Id.

[0062] In the bottom graph, the curve 28 represents the impedance parameter "u" 22 as a function of V 24, illustrating how transistor characteristics evolve with increasing drain-source voltage . Note, "u" is obtained as the derivative of the IV curve 30 so that it represent the reciprocal of rds in FIG. IB . The trend exhibits a decaying relationship, showing that at Vds below dashed line 32, u is relatively high, at Vds between dashed lines 32 and 34 "u" decreases, and at Vds between dashed lines 34 and 36, "u" becomes linear . This behavior is consistent with the effects of channel length modulation and impedance degradation, where low Vds corresponds to lower rds (higher Cd and weaker PSRR) , while higher Vds corresponds to higher rds (lower Cd and stronger PSRR) .

[0063] FIG. IB illustrates the PSRR-limiting behavior of Mpoutl versus Mpout2 in the bias current splitting architecture in FIG. 2 and FIG. 3. Mpoutl may operate at about the first voltage level -dashed line 32 - placing it in the triode region, where rds is low, making it more susceptible to supply noise inj ection. Additionally, Cd is larger at this voltage, further increasing supply noise coupling. In contrast, Mpout2 may operate at a higher voltage - dashed line 36 - ensuring it remains in2024P01135 P98425

[0064] saturation, where rds is significantly larger . Thus, Mpout2 may have a reduced sensitivity to supply fluctuations and minimized Cd.

[0065] Thus, the bias current redistribution approach (discussed in further detail below) directs the majority of bias current through Mpout2 and, this way, improves PSRR by leveraging its impedance characteristics at higher drain-source voltages . FIG.1A also highlights that increasing the size of Mpoutl inherently increases Cd, which counteracts any potential PSRR benefits gained from increased impedance . By redistributing the bias current in a way that prioritizes Mpout2 as the dominant conduction path, the operational amplifier circuit reduces the impact of supply fluctuations on amplifier performance, particularly in frequency ranges where PSRR is most critical for maintaining signal integrity.

[0066] FIG. 2 shows a circuit diagram of an operational amplifier circuit 100 according to various embodiments . The circuit redistributes bias current to improve power supply rej ection ratio (PSRR) , reducing the impact of supply Vdd variations on the output of the operational amplifier circuit 100. The introduction of a potential setting component 112, e . g. a cascode transistor 112 (illustrated) or a diode, provides bias current inj ection points with different voltage potential . When considering the same type (e . g. same channel characteristics) of the transistors Mpoutl 120 and Mpout2 122, the different voltage potentials determine the bias current ratio, and thus the current flow ratio through Mpoutl 120 (also denoted as second transistor) and Mpout2 122 (also denoted as third transistor) - that are both connected to the same share supply voltage Vdd source (also denoted as rail) . In a more general term, the ratio between the currents from the transistors Mpoutl 120 and Mpoutl 122 originates from their sizes (e . g. the channel characteristics) , and thus the different bias potentials determine the output impedance of2024P01135 P98425

[0067] - 14 -

[0068] the first and second bias current paths by setting their aspect ratios .

[0069] As illustrated, the operational amplifier circuit 100 may include a first amplifier stage 102 and a second amplifier stage 110, e . g. a first transistor 110. The first amplifier stage 102, if present, amplifies an input signal before providing it to the second amplifier stage 110 at an input node 118. The second amplifier stage 110 amplifies the input signal . Alternatively, the operational amplifier circuit 100 may be implemented as a single-stage amplifier without departing from the principles disclosed.

[0070] For example, the second amplifier stage 110 includes a commonsource transistor Mnout 110 (e . g. first transistor) . The gate of Mnout 110 is coupled to input node 118, while its drain is coupled to an output node 150 of the operational amplifier circuit . The drain of Mnout 110 is coupled to a node 114 (coupled or denoted as second inj ection point) . The second amplifier stage 110 may also include a cascode transistor 112 as potential setting component 112. As illustrated, the cascode transistor 112 may have its gate biased by a reference voltage Vbias, its source coupled to node 114, and its drain coupled to the drain of transistor Mpoutl 120 and the output node 150.

[0071] A resistive-capacitive (RC) circuit includes a resistor 106 and a capacitor 108 connected in series . The RC circuit is coupled between the input of the second amplifier stage (or output of the first amplifier stage 102 ) and the drain of Mpoutl 120. The RC circuit 106-108 provides Miller compensation, contributing to amplifier stability. In case of a single stage operational amplifier circuit, the coupling is between Mpoutl 120 and a low impedance source 116 which is referred to GND. Thus, any GND variation can be tracked, monitored or compensated.2024P01135 P98425

[0072] 15

[0073] In some implementations, the output node 150 of the operational amplifier circuit 100 may coincide with the drain of transistor Mpoutl 120, the first inj ection point or with the drain of cascode transistor 112, depending on circuit configuration.

[0074] The operational amplifier circuit 100 includes a biasing network 104. As illustrated in FIG. 2, a bias source 126 ( Ibias) provides a reference current . The bias source 126 is coupled to the gates of Mpoutl 120, Mpout2 122, and a reference transistor 124. The source terminals of Mpoutl 120, Mpout2 122, and reference transistor 124 are coupled together at supply rail VDD. The drain of Mpout2 122 is coupled to node 114, so that Mpout2 inj ects current into the source of cascode transistor 112. Mpoutl 120 directs a portion of the bias current to the drain of cascode transistor 112 ( first inj ection point) , while Mpout2 122 directs another portion of the bias current to node 114 (second inj ection point) .

[0075] The introduction of Mpoutl 120 and Mpout2 122 as separate current paths may provide a PSRR improvement by altering how bias current is distributed. The splitting of Mpout (see FIG. l ) into two distinct transistors Mpoutl, Mpout2 allows for an increase in output impedance rds, which helps to mitigate the coupling of supply Vdd variations into the operational amplifier circuit ' s output 150. The redistribution of bias current ensures that Mpout2 122 operates in a region that improves PSRR, e . g. in a saturation mode, e . g. particularly by avoiding operation near triode mode (see FIG. IB) .

[0076] In some configurations, a cascode transistor 112 may be present to separate the drain connections of Mpoutl 120 and Mpout2 122, e . g. the first and second inj ection points . If the drainsource voltage (Vds) of cascode transistor 112 is sufficiently high, Mpout2 122 operates at a larger Vds than Mpoutl 120. This increases the output impedance of Mpout2 (see Fig. IB) , further improving PSRR. Additionally, inj ection from Mpoutl2024P01135 P98425

[0077] 16

[0078] is reduced, as its bias current is lower due to the split with Mpout2 .

[0079] The operational amplifier circuit 100 benefits from bias current redistribution even in the absence of a cascode transistor 112. For example, a diode or alternative current inj ection structure for generating a DC voltage drop, e . g. a resistor, a resistor network or any combination thereof, could be employed as reference voltage component 122 to achieve similar effects in certain configurations .

[0080] The operational amplifier circuit 100 redistributes bias current to reduce direct supply Vdd noise coupling using a first bias current path 132 and a second bias current path 130. In conventional amplifier designs, high output voltages result in a reduced drain-source resistance (rds) and increased parasitic capacitance, which can degrade PSRR. By redistributing bias current between Mpoutl and Mpout2 , these effects can be mitigated. For example, the drain-source voltage (Vds) of Mpout2 remains independent of the output voltage, which may help stabilize impedance and reduce supply noise coupling.

[0081] The sizing of Mpoutl 120 and Mpout2 122, as well as the division of bias current between them, may be determined based on a balance between PSRR performance and amplifier load pull-up capability. In some implementations, Mpout2 122 may operate under a DC biasing condition optimized for PSRR enhancement . It may be preferable to configure Mpout2 to conduct a larger portion of the bias current, thereby reducing the impact of supply fluctuations at the amplifier output .

[0082] A possible approach to bias current distribution involves first determining the maximum load current that the operational amplifier circuit 100 is expected to drive . This load current may be assigned to Mpoutl, ensuring that the amplifier maintains sufficient pull-up capability across operating2024P01135 P98425

[0083] - 17 -

[0084] conditions . The remaining bias current may be directed to Mpout2, defining a current ratio between Mpoutl and Mpout2 . This ratio may be adjusted to balance load drive strength with PSRR enhancement .

[0085] The width-to-length (W / L) ratio of Mpoutl 120 may be selected to ensure that it remains in saturation mode across the full output voltage range, including maximum expected output levels . Ensuring saturation in this manner may prevent undesirable variations in drain impedance, which could otherwise degrade amplifier performance . Once the W / L ratio of Mpoutl is determined, the W / L ratio of Mpout2 122 may be proportionally adjusted based on the assigned current ratio, ensuring that Mpout2 remains properly biased while maximizing its contribution to PSRR enhancement . Illustratively, the W / L ratio of Mpoutl 120 may be configured, designed or selected that Mpoutl 120 operates outside a triode region. Then, Mpout2 may be sized accordingly with the same L and W, and thus forming a desired current ratio .

[0086] Depending on design constraints, additional factors such as power dissipation, layout area, and transistor matching may influence the final selection of W / L ratios . In some implementations, further optimization techniques, including feedback-controlled current regulation or dynamic biasing, may be used to refine bias current distribution and transistor sizing for enhanced PSRR performance across varying conditions .

[0087] The bias voltage Vbias applied to the gate of cascode transistor 112 does not necessarily require dynamic adjustment based on circuit conditions . A fixed reference voltage may be sufficient to establish a stable operating point for the cascode transistor 112. A suitable choice for Vbias may position the source of cascode transistor 112 slightly above the saturation voltage of Mnout 110, ensuring that Mnout 110 remains in saturation mode across operating conditions . By2024P01135 P98425

[0088] 18

[0089] selecting Vbias appropriately, cascode transistor 112 may maintain a high drain-source voltage (Vds) across Mpout2 122, which may increase the output impedance of Mpout2 and reduce its susceptibility to supply variations . Since Mpout2 contributes to PSRR performance, the proper selection of Vbias may directly impact PSRR enhancement, e . g. in the applicationspecific frequency range, and particularly at higher frequencies thereof . The choice of Vbias may be influenced by available headroom, output swing constraints, and process variations . However, dynamic regulation is not necessarily required, as a well-selected fixed voltage reference may ensure stable operation across different circuit conditions .

[0090] FIG. 3 illustrates a circuit diagram of an operational amplifier circuit 100 providing an alternative embodiment of the amplifier stage illustrated in FIG. 2. This embodiment enhances PSRR performance by modifying the bias current distribution circuit 104 through the introduction of two independent bias sources . The separate bias branches may allow optimized sizing for Mpout2, reducing supply noise coupling while maintaining stability across process and temperature variations .

[0091] The operational amplifier circuit 100 may include a first amplifier stage 102 and a second amplifier stage 110, although implementations with a single amplifier stage are also possible . The first amplifier stage 102, if present, is configured to amplify an input signal and provide it to the second amplifier stage 110. The second amplifier stage 110 may be coupled in series with the first amplifier stage 102, with its input node 118 receiving the output signal from the first amplifier stage 102.

[0092] The second amplifier stage 110 includes a common-source transistor Mnout 110. The gate of Mnout 110 is coupled to input node 118, and its drain is coupled to node 114. The second amplifier stage 110 may further include a cascode transistor 112. In some configurations, the source of cascode2024P01135 P98425

[0093] transistor 112 may be coupled to a negative supply rail 116, such as GND. The gate of cascode transistor 112 is biased at a fixed voltage Vbias . The source of cascode transistor 112 is coupled to node 114, while its drain is coupled to the drain of transistor Mpoutl 120.

[0094] A resistive-capacitive (RC) circuit, similar to that in FIG. 2, may include a resistor 106 and a capacitor 108.

[0095] The operational amplifier circuit 100 includes a biasing network 104, which comprises a first current path 132 having a first bias source 126-1 ( Ibiasl ) and a second current path 130 having a second bias source 126-2 ( Ibias2 ) . These bias sources generate independent bias currents Ibiasl and Ibias2, e . g. dynamically or statically. The second transistor Mpoutl 120 is coupled to first bias source 126-1, and the third transistor Mpout2 122 is coupled to second bias source 126-2. The drain of Mpoutl 120 remains coupled to the drain of cascode transistor 112 and the RC circuit 106-108 ( first inj ection point) , as described in FIG. 2. The drain of Mpout2 122 remains coupled to node 114 (second inj ection point) . The source terminals of Mpoutl 120, Mpout2 122, first reference transistor 124-1, and second reference transistor 124-2 are all coupled to the supply Vdd rail .

[0096] The gate of Mpoutl 120 is coupled to the drain and gate of second reference transistor 124-2, which is biased by first bias source 126-1. The gate of Mpout2 122 is coupled to the drain and gate of first reference transistor 124-1, which is biased by second bias source 126-2. The reference transistors 124-1 and 124-2 generate reference currents for their respective biasing current paths 130, 132, thereby splitting the original single-biasing network (FIG. 2 ) into two separate branches (FIG. 3) .

[0097] The introduction of two independent bias sources 126-1, 126-2 allows for greater control over bias current distribution.2024P01135 P98425

[0098] The third transistor Mpout2 122, which supplies second bias current to node 114 (the second inj ection point) , may be separately biased from Mpoutl 120, which provides current inj ection to the amplifier output 150 (the first inj ection point) . This separation allows Mpoutl and Mpout2 to be independently optimized, particularly in terms of their width (W) and length (L) ratios . The width of Mpout2 122 may be reduced, while its length may be increased. Increasing Mpout2' s channel length enhances its output impedance, and reducing its width lowers its parasitic capacitance (Cd) , thereby further improving PSRR.

[0099] By modifying the biasing scheme, the operational amplifier circuit may further reduce supply Vdd fluctuations coupling into the output signal . The cascode transistor 112 may contribute to stabilizing the voltage at node 114, while the redistribution of bias current ensures that variations in supply voltage have a minimized impact on the operational amplifier circuit ' s output . The introduction of independent biasing may improve the circuit' s resilience to supply voltage disturbances . The use of separate reference transistors for each biasing branch allows more precise control of bias current ratios, which may contribute to enhanced stability over variations in process conditions and temperature .

[0100] The revised biasing scheme provides a refined current distribution, which may help to minimize supply noise inj ection into the output signal . This biasing scheme may allow for improved area efficiency, particularly when the reduction in width (W) is larger than the increase in length (L) . The overall circuit may maintain high PSRR performance while enabling transistor sizing that balances noise rej ection and drive capability.

[0101] The values of Ibiasl ( 126-1 ) and Ibias2 ( 126-2 ) may be selected to ensure that the currents through Mpoutl 120 and Mpout2 122 remain consistent with those in FIG. 2. Since the current2024P01135 P98425

[0102] 21

[0103] requirements of Mnout 110 and the connected load may remain the same, the sum of Mpoutl and Mpout2 currents may remain unchanged compared to prior configurations (FIG. l ) .

[0104] Both Mpoutl and Mpout2 may function as current mirror outputs . Accordingly, Ibiasl and Ibias2 may be determined by the gain of their respective current mirrors . The specific gain values of these mirrors may not be essential and may generally be selected based on one or more factors, including optimization of current accuracy, matching constraints (if applicable) , circuit area considerations, and power dissipation. In various implementations, Ibiasl and Ibias2 may be derived from a common reference current through mirroring, ensuring consistent biasing conditions across the amplifier . However, it may not be essential to generate these currents from a single source, and alternative configurations may be implemented if required by specific design constraints .

[0105] The separation of the current mirrors into two independent branches (current path 130, 132 ) may allow the circuit to exploit a larger drain-source voltage (Vds) across Mpout2 relative to Mpoutl . By allowing Mpout2 to operate with a higher Vds, it may be possible to reduce its W / L ratio, thereby minimizing supply noise inj ection into the output . Since Mpout2 is less constrained by output drive requirements, reducing Mpout2' s size may further improve PSRR without significantly impacting overall amplifier performance .

[0106] Decoupling the aspect ratios of Mpoutl and Mpout2 may involve the use of separate reference transistors (diodes) to generate their respective gate voltages . This may allow greater flexibility in sizing Mpout2 independently of Mpoutl, thereby optimizing its contribution to supply noise rej ection.

[0107] The introduction of independent bias sources ( Ibiasl and Ibias2 ) may not significantly impact temperature stability relative to the single-bias configuration in FIG. 2. When2024P01135 P98425

[0108] Ibiasl and Ibias2 are derived from the same reference current, the DC operating conditions of the amplifier stage circuit may remain unchanged when transitioning from the biasing scheme in FIG. 2 to that of FIG. 3. This configuration may facilitate a smaller Mpout2, thereby reducing circuit area and minimizing the inj ection of supply noise . Since the underlying current relationships remain the same as in FIG. 2, no additional compensation techniques may be required to maintain stable operation across temperature variations .

[0109] FIG. 4 illustrates a graphical representation of the power supply rej ection ratio (PSRR) performance for the amplifier circuits shown in FIG.1A through FIG. 3. The figure provides a comparative evaluation of the disclosed amplifier circuits, demonstrating the effects of bias current redistribution and independent biasing branches on PSRR performance . The data suggest that these configurations may facilitate improved PSRR across a wide frequency range, making them potentially beneficial for applications requiring high signal integrity in noise-sensitive environments .

[0110] To ensure a consistent comparison, the voltage reference in all implementations is set to 4.5V under a supply voltage of 5V. The first amplifier stage is assumed to receive a clean supply voltage, isolating the observed PSRR effects to the modifications in the second-stage amplifier . In FIG. 2, the bias current redistribution scheme directs 25% of the total current through Mpoutl and 75% through Mpout2, while maintaining the total device width as in the prior art configuration. The modifications in FIG. 3 further refine this design by adjusting transistor sizing, particularly by increasing the channel length of Mpout2 while reducing its width, which may contribute to an improved PSRR across all frequency ranges .

[0111] The graph presents the transfer function 404 from the supply to the amplifier output (i . e . , the drain of Mpoutl ) , which is2024P01135 P98425

[0112] 23

[0113] the reciprocal of PSRR, measured in decibels (dB) as a function of frequency 402 in Hertz (Hz) . Three distinct curves are shown, each corresponding to a different amplifier configuration: curve 408 represents the conventional design of FIG.1A, curve 410 corresponds to the embodiment of FIG. 2, and curve 412 represents the embodiment of FIG. 3. Additionally, a predefined operational threshold frequency 406 is indicated as a reference point for evaluating high-frequency PSRR performance .

[0114] The PSRR curve 408, corresponding to the amplifier circuit of FIG.1A, represents a conventional configuration in which no bias current redistribution is applied. This circuit exhibits the lowest PSRR performance across the frequency spectrum, with a notable decline at higher frequencies . As frequency increases, the impedance of the biasing transistor decreases, exacerbating the susceptibility of the amplifier output to power supply fluctuations . The graph illustrates that, under high-frequency operating conditions, supply-induced variations are more likely to propagate into the output signal .

[0115] The PSRR curve 410, corresponding to the amplifier circuit of FIG. 2, represents a configuration incorporating bias current redistribution. This implementation demonstrates an increase in PSRR, particularly at low-to-medium frequencies, compared to FIG.1A. The introduction of Mpout2 as a separate bias current source modifies the drain-source voltage (Vds) across Mpout2, which in turn increases its drain-source resistance (rds) . The increased rds may reduce the amount of supply voltage fluctuations inj ected into the output node, contributing to better PSRR performance in the low-to-medium frequency range .

[0116] The PSRR curve 412, corresponding to the amplifier circuit of FIG. 3, represents an implementation with independent biasing branches for the current mirror transistors . This modification introduces two independent bias current sources, allowing for2024P01135 P98425

[0117] 24

[0118] further optimization of transistor sizing, particularly in the W / L ratio of Mpout2 . By increasing the channel length of Mpout2 while reducing its width, the parasitic capacitances associated with Mpout2 decrease, which may lead to a reduction in the amount of power supply disturbance inj ection across them. The reduced Cd of Mpout2 can provide an improvement in high-frequency PSRR performance, making this configuration particularly advantageous for applications operating at higher switching frequencies .

[0119] The improvements illustrated in FIG. 4 indicate that bias current redistribution and independent biasing branches may provide an effective means for reducing supply noise coupling in amplifier circuits . The embodiment represented by curve 412 suggests the most favorable PSRR performance, exceeding the desired operational threshold 406 across the entire frequency range . This configuration may be suited for applications that require high-precision signal processing and strong immunity to power supply fluctuations, including automotive and industrial electronics, communication systems, and precision sensor interfaces .

[0120] The circuit configuration may be further modified by introducing a cascode transistor in the bias current path of Mpout2, which may serve to further refine PSRR characteristics by reducing supply-induced variations in Mpout2 . In some implementations, this additional cascode transistor may be placed between the drain of Mpout2 and the voltage setting component, e . g. the cascode 112 source or node 114, forming an alternative current inj ection path distinct from the direct connection in prior configurations .

[0121] When included, the additional cascode transistor may help stabilize the drain-source impedance of Mpout2 by isolating it from direct supply fluctuations, thereby reducing the extent to which supply noise propagates through the biasing network. Since Mpout2 carries the majority of the bias current, any2024P01135 P98425

[0122] 25

[0123] variations in its impedance may otherwise influence the amplifier' s rej ection of supply disturbances . By introducing a cascode element at this location, the bias current through Mpout2 may be better shielded from external variations, contributing to further PSRR refinement .

[0124] This modification may be applied to both the FIG. 2 and FIG. 3 configurations, where Mpout2 already serves as the dominant bias current path. In FIG. 2, the cascode transistor in the Mpout2 branch may further reduce PSRR degradation at lower frequencies, while in FIG. 3, where Mpout2 is independently biased, the addition of the cascode transistor may help extend PSRR enhancements across a broader frequency spectrum, particularly by limiting high-frequency noise inj ection.

[0125] The cascode transistor in the Mpout2 bias path may be biased by a fixed reference voltage, similar to the existing cascode transistor in the second amplifier stage . Alternatively, in some implementations, it may be dynamically biased based on the voltage conditions at the source of Mpout2, optimizing its contribution to impedance stability while maintaining flexibility in current distribution.

[0126] In cases where process variations or environmental factors influence biasing conditions, the cascode transistor in the Mpout2 branch may further mitigate the impact of temperaturedependent fluctuations, ensuring a more consistent PSRR response under varying operating conditions .

[0127] By refining the current redistribution architecture through the introduction of an additional cascode transistor, certain implementations may achieve further stability in PSRR, particularly in scenarios where power supply variations are expected across a wide frequency range .

[0128] The dimensions and layout of the transistors influence both power consumption and performance . A shorter channel length2024P01135 P98425

[0129] for transistors in the current redistribution circuit 104 may reduce overall area requirements, but it can also increase sensitivity to process variations . A longer channel length may provide more stable PSRR performance, as it increases transistor output impedance and reduces supply noise inj ection. The width-to-length ratio of transistors can be optimized to achieve a trade-off between gain, drive capability, and power efficiency depending on the specific system constraints .

[0130] Different fabrication technologies offer additional flexibility for implementing these configurations . A silicon-on-insulator (SOI ) process may reduce parasitic capacitances, improving high-frequency PSRR performance . A bulk CMOS process provides a cost-effective alternative while still offering enhanced noise rej ection properties . FinFET or fully depleted SOI (FD-SOI ) processes may further reduce leakage currents and power consumption, making them suitable for ultra-low-power applications . The selection of fabrication technology may depend on specific design constraints and performance requirements .

[0131] Operational amplifiers incorporating these PSRR enhancement techniques may be particularly useful in environments where power supply variations impact circuit performance . Power management circuits utilizing DC-DC converters may benefit from improved supply noise rej ection, particularly in systems operating at switching frequencies between 1 MHz and 10 MHz . Analog signal processing applications, including precision sensor interfaces and data acquisition circuits, may also benefit from minimized power-induced noise, ensuring higher signal integrity for low-amplitude signals .

[0132] Medical instrumentation, including bio-signal processing and imaging systems, may benefit from stable analog amplification in the presence of fluctuating supply conditions . Power supply rej ection ratio (PSRR) characteristics influence how well low-2024P01135 P98425

[0133] 27

[0134] level physiological signals remain unaffected by variations in system power . In communication systems, noise-sensitive circuits such as low-noise amplifiers (LNAs) may rely on stable supply rej ection to preserve signal integrity, particularly in radio-frequency applications where power fluctuations could introduce unwanted interference .

[0135] Automotive and industrial electronics often operate under conditions where supply voltage fluctuates due to load transients and temperature variations . PSRR characteristics may influence amplifier performance across a broad range of operating conditions, helping to maintain stability in control and sensing circuits . High-speed data conversion applications, including ADC front-end circuits, may require effective power supply noise filtering to prevent dynamic range limitations and maintain an optimal signal-to-noise ratio (SNR) .

[0136] Noise suppression in mixed-signal systems, where analog and digital circuits coexist, may help prevent digital switching noise from interfering with sensitive analog signals . Integrated circuits designed for environments with supply variations, including aerospace and defense applications, may benefit from PSRR characteristics that provide resilience against power disturbances . Whether implemented in consumer electronics, industrial automation, or precision measurement systems, controlling supply noise rej ection may influence circuit stability and predictable operation.

[0137] Bias current distribution within the amplifier may influence power supply noise coupling and PSRR characteristics . In some implementations, modifications to the biasing circuit may redistribute current paths to mitigate supply fluctuations while maintaining overall circuit performance . For example, increasing the channel length of certain transistors may improve isolation from supply noise without significantly affecting the gain-bandwidth product . A longer channel length2024P01135 P98425

[0138] 28

[0139] could stabilize drain-source impedance variations, limiting the effect of supply fluctuations on the output node .

[0140] The circuit architecture may be implemented using various semiconductor technologies, each offering different design trade-offs . A silicon-on-insulator (SOI ) substrate may reduce parasitic capacitances, potentially improving high-frequency PSRR, while a bulk CMOS process may provide an alternative approach with comparable rej ection of supply noise . FinFET or FD-SOI technologies may further influence circuit performance in applications requiring low leakage currents and controlled power consumption.

[0141] As disclosed in FIG. 3, an alternative configuration modifies not only the PMOS current generator but also the current mirror structure to refine bias current distribution. The pull-up transistor inj ecting current into the cascode transistor source (Mpout2 ) may be configured with a reduced width and increased channel length. This configuration may decrease parasitic capacitance and limit direct supply noise inj ection. A dedicated reference diode may regulate the current mirror, resulting in improved PSRR characteristics at higher frequencies . In some cases, improvements of up to 10 dB in the high-frequency range may be observed, while maintaining bias current deviations within ±5% . These adjustments may influence noise immunity while preserving dynamic performance .

[0142] The amplifier circuit may be suited for applications requiring stable analog performance in the presence of power supply variations . In power management systems incorporating DC-DC converters, improved rej ection of supply ripple may contribute to stability in precision voltage regulation and feedback loops . In analog signal processing, controlling supply-induced fluctuations may help maintain accuracy in sensor interfaces and instrumentation amplifiers .2024P01135 P98425

[0143] 29

[0144] Medical instrumentation, including bio-signal acquisition and diagnostic imaging, may benefit from PSRR characteristics that maintain amplifier performance under variable power conditions . In high-resolution data conversion, such as ADC front-end circuits, managing PSRR across a broad frequency range may help prevent supply noise from affecting signal-to-noise ratio and dynamic range .

[0145] In communication systems, particularly in low-noise amplifiers (LNAs) , fluctuations in supply voltage may influence phase noise and degrade signal integrity. The bias current distribution approach may help minimize power supply interference, making it applicable to radio-frequency and mixed-signal environments . In industrial and automotive electronics, where power supply stability varies due to load transients and temperature fluctuations, PSRR characteristics may influence reliable operation in control and monitoring systems .

[0146] The amplifier circuit may include an amplifier stage configured to receive an input signal and generate an amplified output signal at an output node . The amplifier stage may be implemented in various configurations, including a single-stage amplifier or a multi-stage amplifier . In some cases, the amplifier stage may include a first-stage differential amplifier followed by a second-stage gain stage . A cascode transistor may be included, having a source, a drain, and a gate, where the drain of the cascode transistor may be coupled to the output node of the amplifier stage . A biasing circuit may be arranged to apply a bias voltage to the gate of the cascode transistor, allowing both the cascode transistor and the second stage input to operate in saturation mode .

[0147] A bias current redistribution circuit may be coupled to the amplifier stage . The redistribution circuit may include a first current path directing a first portion of a bias current to the output node and a second current path directing a second2024P01135 P98425

[0148] 30

[0149] portion of the bias current to an alternative inj ection point, which may include the source of the cascode transistor . The second current path may provide a conductive connection between the source of the cascode transistor and a bias current source .

[0150] In certain implementations, the second current path may include a current mirror configured to regulate the second portion of the bias current based on a reference current . The current mirror may help ensure that the fraction of bias current directed to the alternative inj ection point remains proportional to a reference level, which may influence stability across process variations and temperature changes . In some cases, the distribution of bias current between the first and second current paths may be asymmetric, such that the second portion exceeds the first portion. The ratio of bias current division may be selected based on design considerations, including PSRR optimization, load current, and frequency response characteristics .

[0151] The biasing circuit configured to set the gate voltage of the cascode transistor may be implemented in different ways . In some configurations, the biasing circuit may include a voltage reference generator providing a fixed bias voltage . In other cases, a feedback-controlled biasing stage may be used, where the bias voltage is adjusted based on variations in the output signal to compensate for changing operating conditions .

[0152] The amplifier stage may be fabricated using various semiconductor processes, including but not limited to bulk CMOS or silicon-on-insulator (SOI ) technology. In some cases, an SOI process may reduce parasitic capacitance, which may influence PSRR and frequency response by limiting leakage paths and improving overall isolation. The circuit may be configured to operate over a frequency range that includes 1 MHz to 100 MHz, where variations in impedance at the drain of the cascode transistor may be managed to stabilize gain and output characteristics in high-frequency applications .2024P01135 P98425

[0153] 31

[0154] By implementing a bias current redistribution circuit that selectively diverts a portion of the bias current to an alternative inj ection point, some amplifier configurations may achieve PSRR performance characteristics that differ from architectures where the entire bias current is inj ected into the output node . The circuit may be applicable in various systems where PSRR characteristics are a design consideration, including analog front-end circuits, sensor interfaces, and power management circuits, where supply noise behavior may influence overall performance .

[0155] In the following some examples are described, which relate to what is described herein and shown in the figures .

[0156] Example 1 is an operational amplifier circuit including a first transistor coupled to an output node and configured to provide an output signal to the output node based on an input signal provided to a gate of the first transistor and based on a combined bias current provided to the output node . The operational amplifier circuit further includes a current redistribution circuit . The current redistribution circuit includes a first current path including a second transistor configured to provide a first bias current to a first inj ection point, the first inj ection point coupled to the output node, The current redistribution circuit further includes a second current path including a third transistor configured to provide a second bias current to a second inj ection point, the second inj ection point coupled to a terminal of the first transistor . The operational amplifier circuit further includes a potential setting component coupled between the first inj ection point and the second inj ection point and configured that in operation the drain-source voltage of the third transistor is larger than the drain-source voltage of the second transistor . The second transistor and the third transistor are coupled to a shared supply voltage source . The first bias current and the second bias current form the combined bias current .2024P01135 P98425

[0157] 32

[0158] The potential setting component coupled between the first inj ection point and the second inj ection point may configured or cause that in operation the electrical potential at the second inj ection point is larger than the electrical potential at the first inj ection point .

[0159] In Example 2 the subj ect matter of Example 1 can optionally include that the current redistribution circuit includes a bias current source configured to provide the bias current . The bias current source is coupled to the first current path and the second current path. The first bias current is a first portion of the bias current, and the second bias current is a second portion of the bias current, both portions being provided from the bias current source .

[0160] In Example 3 the subj ect matter of Example 1 can optionally include that the current redistribution circuit includes a first bias current source configured to provide the first bias current and a second bias current source configured to provide the second bias current .

[0161] In Example 4, the subj ect matter of any one of Examples 1 to 3 can optionally include that the potential-setting component includes a cascode transistor or a diode .

[0162] In Example 5, the subj ect matter of any one of Examples 1 to 4 can optionally include that the potential-setting component is configured such that the second bias current is larger than the first bias current .

[0163] In Example 6, the subj ect matter of any one of Examples 1 to 5 can optionally include that the second current path includes a current mirror . The current mirror is electrically coupled to the second inj ection point and is configured to set the second bias current in proportion to a reference current .2024P01135 P98425

[0164] 33

[0165] In Example 7, the subj ect matter of any one of Examples 1 to 5 can optionally include that the first current path includes a current mirror . The current mirror is electrically coupled to the first inj ection point and is configured to set the first bias current in proportion to a reference current .

[0166] In Example 8, the subj ect matter of any one of Examples 1 to 7 can optionally include that the operational amplifier circuit is a two-stage amplifier, wherein the output of a first amplifier stage is electrically coupled to the gate of the first transistor .

[0167] In Example 9, the subj ect matter of any one of Examples 1 to 8 can optionally include that the second current path includes a cascode transistor arranged between the third transistor and the second inj ection point .

[0168] In Example 10, the subj ect matter of any one of Examples 2 to 9 can optionally include that the second transistor and the third transistor have identical channel geometry such that their width-to-length (W / L) ratio is about the same .

[0169] In Example 11, the subj ect matter of any one of Examples 3 to 9 can optionally include that the second transistor has a width-to-length (W / L) ratio different from that of the third transistor .

[0170] In Example 12, the subj ect matter of any one of Examples 3 to 9 can optionally include that the third transistor has a smaller width and a larger length compared to the second transistor .

[0171] Example 13 is a method for manufacturing an operational amplifier circuit . The method includes forming a first transistor coupled to an output node and configured to provide an output signal to the output node based on an input signal provided to a gate of the first transistor and based on a2024P01135 P98425

[0172] - 34 -

[0173] combined bias current provided to the output node . The method further includes forming a current redistribution circuit . The current redistribution circuit includes a first current path including a second transistor configured to provide a first bias current to a first inj ection point, the first inj ection point being coupled to the output node . The current redistribution circuit further includes a second current path including a third transistor configured to provide a second bias current to a second inj ection point, the second inj ection point being coupled to a terminal of the first transistor . The method further includes forming a potential-setting component coupled between the first inj ection point and the second inj ection point . The potential-setting component is configured that in operation the drain-source voltage of the third transistor is larger than the drain-source voltage of the second transistor . The second transistor and the third transistor are coupled to a shared supply voltage source . The first bias current and the second bias current form the combined bias current .

[0174] In Example 14, the subj ect matter of any one of Examples 1 to 11 can optionally be included in an integrated circuit or system-level implementation, including any of the following: a power management system, wherein the circuit is configured to influence power supply noise characteristics; an analog front-end module, wherein the module is configured to interface with an analog-to-digital converter (ADC) in a signal processing system; a power regulation system, wherein the power regulation system includes a voltage reference generator; a medical imaging device, wherein the medical imaging device is configured to process analog signals from a sensor array; a wireless communication device, wherein the wireless communication device includes a low-noise amplification stage arranged to process radio-frequency signals; a sensor system, wherein the sensor system is configured to generate an electrical output corresponding to an input stimulus .2024P01135 P98425

[0175] The term "drain-source voltage" as used herein encompasses the terminal voltage across the main current path of a transistor, including collector-emitter voltage in bipolar junction transistors and drain-source voltage in field-effect transistors .

[0176] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any example or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other examples or designs .

[0177] The words "plurality" and "multiple" in the description or the claims expressly refer to a quantity greater than one . The terms "group (of ) ", "set [of ] ", "collection (of ) ", "series (of ) ", "sequence (of ) ", "grouping (of ) ", etc . , and the like in the description or in the claims refer to a quantity equal to or greater than one, i . e . one or more . Any term expressed in plural form that does not expressly state "plurality" or "multiple" likewise refers to a quantity equal to or greater than one .

[0178] The term "connected" can be understood in the sense of a (e . g. mechanical, optical and / or electrical) , e . g. direct or indirect, connection and / or interaction. For example, several elements can be connected together mechanically such that they are physically retained (e . g. , a plug connected to a socket) and electrically such that they have an electrically conductive path (e . g. , signal paths exist along a communicative chain) .

[0179] While the above descriptions and connected figures may depict optical device components as separate elements, skilled persons will appreciate the various possibilities to combine or integrate discrete optical functions into a single element . Such may include combining two or more components from a single component . Conversely, skilled persons will recognize the possibility to separate a single element into two or more2024P01135 P98425

[0180] 36

[0181] discrete elements, such as splitting a single component into two or more separate component .

[0182] It is appreciated that implementations of methods detailed herein are exemplary in nature, and are thus understood as capable of being implemented in a corresponding device . Likewise, it is appreciated that implementations of devices detailed herein are understood as capable of being implemented as a corresponding method. It is thus understood that a device corresponding to a method detailed herein may include one or more components configured to perform each aspect of the related method.

[0183] All acronyms defined in the above description additionally hold in all claims included herein.

[0184] While the disclosure has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims . The scope of the disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced .2024P01135 P98425

[0185] Reference Numeral List

[0186] 1 Amplifier circuit

[0187] 2 First amplifier stage

[0188] 3 Second amplifier stage

[0189] 4 Mnout transistor

[0190] 5 RC-circuit

[0191] 6 Bias source

[0192] 7 Reference transistor

[0193] 8 Mpout transistor with its drain as output

[0194] 9 rds

[0195] 10 Cd

[0196] 20 Current I

[0197] 22 u

[0198] 24 Voltage

[0199] 28 uV- curve

[0200] 30 IV-curve

[0201] 32, 34, 36 threshold values

[0202] 100 Operational amplifier stage

[0203] 102 First amplifier stage

[0204] 104 current redistribution circuit, biasing network 106 Resistor

[0205] 108 Capacitor

[0206] 118 Input node

[0207] 110 Second amplifier stage, Mnout transistor

[0208] 112 Mease

[0209] 114 First Node

[0210] 116 second supply node, e . g. negative supply

[0211] 120 Mpoutl transistor

[0212] 122 Mpout2 transistor

[0213] 124 Reference transistor for biasing Mpoutl and Mpout2 124-1 First reference transistor (biasing Mpout2 ) 124-2 Second reference transistor (biasing Mpoutl ) 126 Bias source ( Ibias)

[0214] 126-1 First bias source ( Ibiasl, biasing Mpoutl ) 126-2 Second bias source ( Ibias2, biasing Mpout2 ) 130, 132 Current paths2024P01135 P98425

[0215] - 38 -

[0216] 150 output node

[0217] 152, 152-1, 152-2 second node

[0218] 402 Frequency

[0219] 406 Operational threshold frequency 408, 410, 412 PSRR curves

[0220] Vdd supply voltage

Claims

2024P01135 P98425CLAIMS1. An operational amplifier circuit ( 100) comprising:a first transistor (Mnout, 110) coupled to an output node ( 150) and configured to provide an output signal to the output node ( 150) based on an input signal provided to a gate of the first transistor and based on a combined bias current ( Ibias) provided to the output node ( 150) ;a current redistribution circuit ( 104 ) comprising:a first current path ( 132 ) comprising a second transistor configured to provide a first bias current to a first inj ection point, the first inj ection point coupled to the output node, a second current path ( 130) comprising a third transistor configured to provide a second bias current to a second inj ection point, the second inj ection point coupled to a terminal of the first transistor; anda potential setting component ( 112 ) coupled between the first inj ection point and the second inj ection point and configured that in operation the drainsource voltage of the third transistor is larger than the drain-source voltage of the second transistor;wherein the second transistor and the third transistor are coupled to a shared supply voltage source (VDD / GND) , andwherein the first bias current and the second bias current form the combined bias current .2 . The operational amplifier circuit of claim 1, the current redistribution circuit ( 104 ) comprising a bias current source configured to provide the bias current, and coupled to the first current path ( 132 ) and the second current path ( 130) , wherein the first bias current is a first portion and the second bias current is a second portion of the bias current provided from the bias current source .2024P01135 P984253. The operational amplifier circuit of claim 1, the current redistribution circuit ( 104 ) comprising a first bias current source configured to provide the first bias current, and a second bias current source configured to provide the second bias current .

4. The operational amplifier circuit of any one of claims 1 to 3, wherein the potential setting ( 112 ) comprises a cascode transistor or a diode .

5. The operational amplifier circuit of any one of claims 1 to 4, wherein the voltage reference component is configured such that the second bias current is larger than the first bias current .

6. The operational amplifier circuit of any one of claims 1 to 5, wherein the second current path comprises a current mirror ( 124, 124-2 ) coupled to second inj ection point, the current mirror configured to set the second bias current in proportion to a reference current .

7. The operational amplifier circuit of any one of claims 1 to 5, wherein the first current path comprises a current mirror ( 124-1 ) coupled to first inj ection point, the current mirror configured to set the first bias current in proportion to a reference current .

8. The operational amplifier circuit of any one of claims 1 to 7, wherein the operational amplifier circuit is a two- stage amplifier, wherein an output of a first stage ( 102 ) is provided as gate input signal for the first transistor .

9. The operational amplifier circuit of any one of claims 1 to 8, wherein the second current path comprises a cascode transistor between the third transistor and the second inj ection point .2024P01135 P9842510. The operational amplifier circuit of any one of claims 2 to 9, wherein the second transistor and the third transistor have identical channel geometry, such that their width-to-length (W / L) ratio is the same .

11. The operational amplifier circuit of any one of claims 3 to 9, wherein the second transistor has a width-to-length (W / L) ratio different from that of the third transistor .

12. The operational amplifier circuit of any one of claims 3 to 9, wherein the third transistor has a smaller width (W) and a larger length (L) compared to the second transistor .

13. A method of fabricating an operational amplifier circuit, the method comprising:forming a first transistor (Mnout, 110) coupled to an output node ( 150) and configured to provide an output signal to the output node ( 150 ) based on an input signal provided to a gate of the first transistor and based on a combined bias current ( Ibias) provided to the output node ( 150 ) ;forming a current redistribution circuit ( 104 ) comprising :a first current path ( 132 ) comprising a second transistor configured to provide a first bias current to a first inj ection point, the first inj ection point coupled to the output node,a second current path ( 130) comprising a third transistor configured to provide a second bias current to a second inj ection point, the second inj ection point coupled to a terminal of the first transistor; andforming a potential setting component ( 112 ) coupled between the first inj ection point and the second inj ection point and configured that in operation the drain-source voltage of the third transistor is larger than the drainsource voltage of the second transistor;2024P01135 P9842542wherein the second transistor and the third transistor are coupled to a shared supply voltage source (VDD / GND) , andwherein the first bias current and the second bias current form the combined bias current .

14. An integrated circuit comprising the operational amplifier circuit of any one of claims 1 to 12, wherein the integrated circuit is configured for use in power management systems .

15. An analog front-end module comprising the operational amplifier circuit of any one of claims 1 to 12, wherein the analog front-end module is configured to interface with an analog-to-digital converter (ADC) in a signal processing system.

16. A power regulation system comprising the operational amplifier circuit of any one of claims 1 to 12, wherein the power regulation system comprises a voltage reference generator .

17. A medical imaging device comprising the operational amplifier circuit of any one of claims 1 to 12, wherein the medical imaging device is configured to process analog signals from a sensor array.

18. A wireless communication device comprising the operational amplifier circuit of any one of claims 1 to 12, wherein the wireless communication device comprises a low-noise amplification stage arranged to process radio-frequency signals .

19. A sensor system comprising the operational amplifier circuit of any one of claims 1 to 12, wherein the sensor system is configured to generate an electrical output corresponding to an input stimulus .

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