Method for forming a structure adapted for further processing for forming a semiconductor device and structure for a semiconductor device

Abstract

According to the invention, a method for forming a structure adapted for further processing for forming a semiconductor device, comprising the steps of:  providing a filter layer (2) comprising  a permanent handling layer (6),  a bulk oxide layer (8) on top of the permanent handling layer (6),  a hybrid filter layer (10) arranged on top of the bulk oxide layer (8), and  a passivation layer (12) arranged on top of the hybrid filter layer (10),  providing a CMOS (Complementary Metal-Oxide- Semiconductor) layer, comprising another passivation layer (14) arranged on top of the CMOS layer (4),  arranging the filter layer (2) on top of the CMOS layer (4), so that the passivation layer (12) of the filter layer (2) is contacting the passivation layer (14) of the CMOS layer (4),  bonding the filter layer (2) and the CMOS layer (4),  forming at least one TSV in the structure (1),  applying electrical connections onto the structure (1), wherein the steps of  arranging the filter layer (2) on top of the CMOS layer (4), so that the passivation layer (12) of the filter layer (2) is contacting the CMOS layer (4), and  bonding the filter layer (2) and the CMOS layer (4) are performed before the step of 2024PF00753 - 29 -  forming the at least one TSV in the structure (1), is disclosed. Furthermore, a corresponding structure adapted for further processing in the forming of a semiconductor device being formed by such a method and a structure for a semiconductor device is disclosed.

Description

[0001] 2024PF00753

[0002] METHOD FOR FORMING A STRUCTURE ADAPTED FOR FURTHER PROCESSING FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE FOR A SEMICONDUCTOR DEVICE

[0003] DESCRIPTION

[0004] TECHNICAL FIELD

[0005] The present invention relates to a method for forming a structure adapted for further processing for forming a semiconductor device, a structure adapted for further processing in the forming of a semiconductor device being formed by such a method, a structure for a semiconductor device, a sensor comprising the structure for a semiconductor device, a handheld comprising the structure for a semiconductor device and a wearable comprising the structure for a semiconductor device .

[0006] BACKGROUND

[0007] In semiconductor manufacturing, the production of hybrid filters and through-silicon vias (TSVs) generally follows a structured process .

[0008] Initially, the CMOS layer is deposited onto a temporary carrier wafer / layer, which serves as the base for the subsequent steps . Once the CMOS layer is applied, TSVs are created by etching deep, narrow holes into the wafer / layer, followed by filling them with conductive materials like copper or tungsten. These allow vertical electrical connections through the wafer / layer .

[0009] After the TSVs are formed, a passivation oxide layer is applied to protect the layer and its components from contamination and electrical interference . This layer provides both physical protection and electrical isolation.2024PF00753

[0010] 2

[0011] Subsequently, hybrid filters are deposited onto the CMOS layer . These filters, which may include both active and passive components, are integrated using techniques such as sputtering. The hybrid filter enables signal processing and conditioning for the final product .

[0012] To provide mechanical support during further processing, a second handling wafer / layer is applied to the top of the hybrid filters . This layer ensures the structure remains stable during further processing steps, including the additional bonding and integration processes .

[0013] In some cases, waf er-to-waf er (W2W) bonding is employed to form a bond between the semiconductor wafer / layer and the handling wafer / layer, enhancing mechanical stability and providing alignment during the multi-step processes .

[0014] At the end of the process, both the first and the second temporary carrier layers are removed, exposing the hybrid filters and completing the final semiconductor structure .

[0015] However, this removal can introduce defects or cracks, necessitating additional cleaning and inspection steps to ensure the integrity and performance of the semiconductor device .

[0016] Furthermore, there is the risk of scrapping the CMOS layers, which can be costly when filter process excursions occur .

[0017] Additionally, defects induced by temporary bonding voids can lead to significant electrical and mechanical issues, as perfect bonding is often difficult to achieve .

[0018] These challenges highlight the need for a method for forming a structure adapted for further processing for forming a semiconductor device, a structure adapted for further processing in the forming of a semiconductor device being formed by such a method and a structure for a semiconductor2024PF00753

[0019] 3

[0020] device, which overcome these disadvantages by improving the process reliability and ensuring higher quality outcomes .

[0021] SUMMARY

[0022] The obj ect or the present invention is therefore to provide a method for forming a structure adapted for further processing for forming a semiconductor device, a structure adapted for further processing in the forming of a semiconductor device being formed by such a method and a structure for a semiconductor device, which overcome these disadvantages by improving the process reliability and ensuring higher quality outcomes .

[0023] According to the invention, the obj ect is met by a method with the steps specified in claim 1 and by a structure specified in claims 10 and 11.

[0024] Therefore, a method for forming a structure adapted for further processing for forming a semiconductor device, comprising the steps of :

[0025] - providing a filter layer comprising

[0026] - a permanent handling layer,

[0027] - a bulk oxide layer on top of the permanent handling layer,

[0028] - a hybrid filter layer arranged on top of the bulk oxide layer, and

[0029] - a passivation layer arranged on top of the hybrid filter layer,

[0030] - providing a CMOS (Complementary Metal-Oxide-Semiconductor ) layer, comprising another passivation layer arranged on top of the CMOS layer,

[0031] - arranging the filter layer on top of the CMOS layer,

[0032] so that the passivation layer of the filter layer is contacting the passivation layer of the CMOS layer, - bonding the filter layer and the CMOS layer,

[0033] - forming at least one TSV in the structure,

[0034] - applying electrical connections onto the structure,2024PF00753

[0035] 4

[0036] wherein the steps of

[0037] - arranging the filter layer on top of the CMOS layer, so that the passivation layer of the filter layer is contacting the CMOS layer,

[0038] and

[0039] - bonding the filter layer and the CMOS layer

[0040] are performed before the step of

[0041] - forming the at least one TSV in the structure,

[0042] is proposed by the invention.

[0043] A permanent handling layer in semiconductor manufacturing refers to a layer that provides mechanical stability and protection to a structure or a part of a structure or a plurality of layers or a layer throughout the processing stages . Unlike temporary layers, which are removed after certain steps, the permanent handling layer is designed to remain .

[0044] This layer is typically used to offer support during operations like bonding, etching, grinding, or thinning, where additional mechanical stability is needed to prevent damage to delicate structures or components on the layer .

[0045] The permanent handling layer is often made from materials such as adhesive films or polymers, or e . g. glass chosen for their durability and strength to withstand various manufacturing processes . It serves to prevent the structure or the part of a structure or the plurality of layers or a layer from warping, cracking, or experiencing mechanical stress during critical steps, ensuring the integrity of the semiconductor device .

[0046] By providing mechanical support, the permanent handling layer ensures that the structure or the part of a structure or the plurality of layers or a layer does not undergo warping or damage during complex processing steps . It also acts as a protective shield, safeguarding the layer from contamination, mechanical stress, and physical damage . This protection2024PF00753

[0047] 5

[0048] enhances the overall yield and quality of the semiconductor device . Moreover, the layer helps streamline the manufacturing process by offering precise handling and minimizing defects .

[0049] A hybrid filter in the context of semiconductor technology refers to a filtering structure that integrates both active and passive components . These filters are designed to process signals, often in high-frequency applications, by selectively allowing certain frequencies to pass through while blocking others .

[0050] They are called "hybrid" because they combine different types of components— active components like transistors or amplifiers, and passive components like resistors, capacitors, and inductors or even barrier film layers .

[0051] The active components in a hybrid filter typically perform amplification or signal processing functions . For example, transistors might be used to amplify weak signals or to control the flow of current . The passive components, on the other hand, are used for energy storage, resistance, or inductance, helping to shape and filter the signal ' s characteristics .

[0052] In semiconductors, the integration of both active and passive components into a single filter offers several advantages, including reduced component count, better signal integrity, and more efficient space utilization. By combining these components in a single package, hybrid filters can deliver improved performance while reducing the overall footprint of the system.

[0053] A passivation oxide layer is a thin layer of oxide material, typically silicon dioxide (SiO2) , that is applied to the surface of a semiconductor layer during the manufacturing process . Its primary purpose is to protect the underlying semiconductor material from contamination, oxidation, and other environmental factors that could degrade its performance .2024PF00753

[0054] The passivation oxide layer acts as a barrier, preventing impurities and defects from affecting the device .

[0055] Additionally, it helps to stabilize the electrical characteristics of the semiconductor by reducing surface states and minimizing leakage currents . This protective layer is crucial for ensuring the reliability, stability, and longevity of semiconductor devices .

[0056] A CMOS (Complementary Metal-Oxide-Semiconductor ) is a technology used in integrated circuits ( ICs) that combines both p-type and n-type semiconductor materials to create circuits with low power consumption.

[0057] The bonding of the filter layer and the CMOS layer may be done with a W2W (waf er-to-waf er , here it is referred to layer-to-layer) bond interface, which is a technique used in semiconductor manufacturing to directly bond two layers together .

[0058] The bonding can be achieved using various methods such as direct bonding, adhesive bonding, or thermal compression bonding. The W2W bond interface ensures alignment and enhances the mechanical stability of the combined layers .

[0059] This bonding method improves the mechanical stability and alignment precision of the layers, ensuring a strong and dependable connection.

[0060] The W2W bond interface also enhances thermal conductivity, aiding in heat dissipation during high-temperature processes and thereby reducing the risk of thermal damage .

[0061] Moreover, this technique minimizes the introduction of contaminants and defects, resulting in higher quality and performance of the final semiconductor devices .

[0062] The at least one TSV can be formed e . g. by Deep Reactive Ion Etching (DRIE) , which is an etching technique used in2024PF00753

[0063] 7

[0064] semiconductor manufacturing to create deep and narrow features in silicon layers . DRIE is known for its ability to achieve high aspect ratio structures, meaning it can etch deep holes or trenches with minimal widening at the top .

[0065] The process involves alternating steps of etching and passivation in a high-vacuum environment . During the etching step, reactive ions are directed towards the layer surface to remove material . In the passivation step, a protective layer is deposited on the sidewalls of the etched features to prevent lateral etching. This cycle is repeated to achieve the desired depth and profile .

[0066] TSVs can be created not only through the DRIE (Deep Reactive Ion Etching) process but also using alternative methods such as laser drilling, plasma etching, or mechanical drilling.

[0067] Applying electrical connections onto a semiconductor structure can be accomplished using several methods . One common technique is soldering, which uses a fusible metal alloy to join electrical connections to the semiconductor structure . This can be done using a soldering iron or reflow soldering techniques for more complex assemblies . Another method is wire bonding, which uses fine wires, typically made of gold or aluminum, to connect the semiconductor device to external circuitry. Wire bonding can be performed using thermosonic bonding, ultrasonic bonding, or thermocompression bonding techniques .

[0068] Flip-chip bonding is another technique where the semiconductor device is "flipped" so that its active surface faces downward and is connected directly to the substrate or another chip using solder bumps or conductive adhesives . Conductive adhesives, which contain conductive particles, can also be used to attach electrical connections to the semiconductor structure, particularly useful for flexible or temperaturesensitive applications .2024PF00753

[0069] 8

[0070] Electrical connections in semiconductor structures can take various forms . Solder bumps, used in flip-chip bonding, provide robust connections . Wire bonds, utilizing fine wires such as gold or aluminum, connect the device to external circuitry. Conductive adhesives, containing particles like silver, are ideal for creating connections in flexible or temperature-sensitive applications . Through-silicon vias (TSVs) enable vertical connections through the silicon layer, facilitating 3D stacking of devices . Ball Grid Array (BGA) connections use solder balls to attach the device to a printed circuit board, ensuring good thermal and electrical performance .

[0071] In this approach, the bonding of the filter layer and the CMOS layer is carried out before forming the TSVs (Through-Silicon Vias) in the structure .

[0072] This method effectively eliminates defects caused by temporary bonding voids and reduces the risk of cracking thin layers during the debonding process .

[0073] Compared to traditional methods, this new approach separates the filter and CMOS TSV processes, reducing risk and shortening the manufacturing cycle time . Additionally, it simplifies the workflow by eliminating the need for temporary bonding and debonding steps .

[0074] With processing the filter and TSV components of the CMOS layer separately, the necessity for temporary bonding and debonding in the filter processing stage is removed.

[0075] As used herein, the term ' layer ' refers to any structural or functional element forming part of the described structure, including, but not limited to, oxide layers, filter layers, substrate layers, handling layers, and wafers . The use of the term ' layer ' is not intended to limit the elements to thin film-like structures; it encompasses elements of varying thicknesses, compositions, and functionalities .2024PF00753

[0076] 9

[0077] In an embodiment of the invention, the CMOS layer may comprise a CMOS Image Sensor (CIS) .

[0078] A CMOS layer refers to a structure in semiconductor devices that utilizes Complementary Metal-Oxide-Semiconductor technology. This technology is generally employed due to its low power consumption and high efficiency. A CMOS layer typically consists of intricate arrangements of p-type and n-type transistors, allowing it to perform various electronic functions . It forms the basis for many integrated circuits ( ICs) , such as microprocessors, memory chips, and image sensors .

[0079] A CIS (CMOS Image Sensor) is a specialized type of a semiconductor device designed to capture light and convert it into an electrical signal . It incorporates CMOS technology to integrate photodiodes and readout circuitry within a single chip, enabling efficient and compact designs . The photodiodes in a CIS detect incoming light, while the readout circuitry processes the captured signals .

[0080] By incorporating the image-sensing functionality directly within the CMOS layer, the system benefits from reduced complexity and a more compact design. This integration allows for faster signal processing, as the photodiodes and readout circuits are fabricated on the same substrate, minimizing signal loss and latency.

[0081] Additionally, leveraging CMOS technology in the CIS enhances power efficiency, making it ideal for battery-powered devices such as smartphones and portable cameras . The use of a CMOSbased CIS also facilitates scalability and cost-effectiveness in manufacturing, as it can be produced using standard CMOS fabrication processes while delivering high-quality image capture .

[0082] In an embodiment of the invention, the step of applying electrical connections onto the structure may be performed after the step of forming at least one TSV in the structure .2024PF00753

[0083] - 10 -

[0084] Applying electrical connections after forming at least one through-silicon via (TSV) in the structure reduces the process complexity. Completing the TSV formation first minimizes also the risk of damaging delicate electrical connections during later processing steps, which might involve high temperatures or mechanical stresses .

[0085] In an embodiment of the invention, the permanent handling layer may comprise glass .

[0086] Glass offers high mechanical stability and strength, making it suitable for the handling and processing of delicate structures .

[0087] In an embodiment of the invention, the hybrid filter layer may comprise an active and a passive component .

[0088] The active components, such as transistors or amplifiers, actively manipulate electrical signals by amplifying, switching, or modulating them. These components require an external power source .

[0089] The passive components, such as resistors, capacitors, inductors or even barrier films function without requiring an external power source . Barrier films, in particular, act as passive elements by protecting the underlying layers from environmental factors like moisture or contaminants .

[0090] By combining the dynamic control provided by active components with the stable and noise-filtering properties of passive components, the hybrid filter layer achieves better signal precision and noise suppression.

[0091] In an embodiment of the invention, the active component may be an Integrated Circuit ( IC) .2024PF00753

[0092] 11

[0093] An Integrated Circuit ( IC) is a compact assembly of electronic components such as transistors, resistors, capacitors, and diodes, all fabricated onto a single semiconductor substrate or chip . ICs are used to perform specific electronic functions, ranging from simple tasks like signal amplification to complex operations such as processing and computation in microprocessors .

[0094] ICs can integrate multiple functions into a single component, enabling advanced signal processing capabilities within a compact design. This increases the functionality of the hybrid filter while maintaining a small form factor .

[0095] Furthermore, the small footprint of ICs allows for more efficient use of space in the semiconductor device .

[0096] Additionally, ICs provide consistent and high-speed operation with lower power consumption compared to discrete components, resulting in improved performance .

[0097] In an embodiment of the invention, the passive component may be a barrier film layer with at least one aperture in it .

[0098] A barrier film layer is a material designed to provide protection, typically against contamination, moisture, or electrical interference . The inclusion of apertures within the barrier film allows selective passage of signals or materials, depending on the application, while still maintaining its protective role .

[0099] Thus, the barrier film layer ensures that sensitive components in the semiconductor device are shielded from external contaminants and environmental factors .

[0100] The apertures allow for precise control of the interaction between layers or external systems, such as the transmission of light or electrical signals through the filter, without compromising the protective function of the barrier .2024PF00753

[0101] 12

[0102] In an embodiment of the invention, the permanent handling layer may comprise silicon.

[0103] Silicon provides excellent mechanical strength, ensuring the layer remains stable during various manufacturing processes and handling. This stability minimizes the risk of layer breakage or deformation, which could otherwise lead to costly defects and disruptions in the manufacturing process .

[0104] The robust nature of silicon allows it to withstand the physical stresses encountered during high-precision fabrication steps, including etching, layering, and bonding.

[0105] Furthermore, the invention proposes a structure adapted for further processing in the forming of a semiconductor device and formed by a method comprising the steps of :

[0106] - providing a filter layer comprising

[0107] - A permanent handling layer,

[0108] - A bulk oxide layer on top of the permanent handling layer,

[0109] - A hybrid filter layer arranged on top of the bulk oxide layer, and

[0110] - A passivation layer arranged on top of the hybrid filter layer,

[0111] - providing a CMOS layer, comprising a passivation layer arranged on top of the CMOS layer,

[0112] - arranging the filter layer on top of the CMOS layer so that the passivation layer of the filter layer is contacting the passivation layer of the CMOS layer,

[0113] - bonding the filter layer and the CMOS layer,

[0114] - forming at least one TSV in the structure,

[0115] - applying electrical connections onto the structure, wherein the steps of :

[0116] - arranging the filter layer on top of the CMOS layer so that the passivation layer of the filter layer is contacting the passivation layer of the CMOS layer

[0117] and

[0118] - bonding the filter layer and the CMOS layer

[0119] are performed before the step of :2024PF00753

[0120] 13

[0121] - forming the at least one TSV in the structure .

[0122] The features and advantages described with respect to the method apply equally to the structure formed by the method, and vice versa .

[0123] The invention proposes with this a new layer arrangement in the structure for a semiconductor device that differs from traditional methods .

[0124] This method to achieve this new layer arrangement begins with the deposition of hybrid filters onto the TSV' s permanent handling layer . In this approach, the filter structure is processed first, followed by the bonding of the filter layer to the CMOS layer .

[0125] This arrangement enhances protection and isolation due to the multiple layers of passivation, which shield the underlying components from contamination and electrical interference, and provides mechanical stability through the bulk oxide layer .

[0126] In contrast, the traditional method typically starts with depositing the CMOS layer onto a temporary carrier layer, creating TSVs, applying a passivation oxide layer, and then depositing hybrid filters . The conventional approach includes the need for a second handling layer to provide mechanical support during further processing steps . This results in a structure where the CMOS is arranged on the handling layer (to be removed) , followed by the bulk oxide layer, passivation layer, and hybrid filter layer .

[0127] By performing the new method, which begins with arranging the permanent handling layer followed by arranging on it the bulk oxide layer, hybrid filter layer, passivation layer, and finally the CMOS layer, the manufacturing process is streamlined, resulting in enhanced stability, fewer defects, and a more efficient workflow. This new arrangement helps avoid scrapping CMOS layers due to filter process issues and eliminates defects caused by temporary bonding voids .2024PF00753

[0128] Furthermore, the invention proposes a structure for a semiconductor device, comprising:

[0129] - a filter layer, which includes :

[0130] - a permanent handling layer,

[0131] - a bulk oxide layer,

[0132] - a hybrid filter layer arranged on top of the bulk oxide layer,

[0133] - a passivation layer arranged on top of the hybrid filter layer,

[0134] a CMOS layer comprising another passivation layer, at least one TSV formed in the structure,

[0135] electrical connections arranged onto the structure, and wherein the another passivation layer of the CMOS layer is arranged on top of the passivation layer of the filter layer .

[0136] With regard to this structure, what has been said about the method applies analogously to the Structure, and vice versa .

[0137] This design provides enhanced protection and isolation due to the multiple layers of passivation, which shield the underlying components from contamination and electrical interference . The bulk oxide layer adds mechanical stability, supporting the integrity of the semiconductor device during manufacturing and usage .

[0138] By arranging the passivation layer of the CMOS layer directly on top of the passivation layer of the filter layer, the structure achieves improved alignment and connectivity, facilitating efficient electrical connections and reducing the risk of misalignment .

[0139] The inclusion of TSVs allows for vertical connections, enabling 3D stacking of components, which maximizes space utilization and improves performance .

[0140] The invention proposes a new layer arrangement in the structure for a semiconductor device that differs from2024PF00753

[0141] 15

[0142] traditional ones and this new layer arrangement is achieved by a certain process .

[0143] With this, the process begins with the deposition of hybrid filters onto the TSV' s permanent handling layer . This approach means that the filter structure is processed first, followed by the bonding of the filter layer to the CMOS layer .

[0144] The traditional method for forming such a structure typically starts with depositing the CMOS layer onto a temporary carrier layer, creating TSVs, applying a passivation oxide layer, and then depositing hybrid filters . The conventional approach also includes the need for a second handling layer to provide mechanical support during further processing steps . The traditional method results in a structure, where the CMOS is arranged on the handling layer (to be removed) , followed by the Bulk-Oxide-Layer, the passivation layer and the hybrid filter layer .

[0145] By performing the new method, which begins with arranging the permanent handling layer followed by arranging on it the bulk oxide layer, hybrid filter layer, passivation layer, and finally the CMOS layer, the manufacturing process is streamlined, resulting in enhanced stability, fewer defects, and a more efficient workflow. This new arrangement helps avoid scrapping CMOS layers due to filter process issues and eliminates defects caused by temporary bonding voids .

[0146] This new procedure, resulting in a new arrangement of the structure' s layers helps avoid scrapping CMOS layers due to filter process issues and eliminates defects caused by temporary bonding voids .

[0147] In an embodiment of the invention, the CMOS layer may comprise a P-substrate layer .

[0148] The P-substrate layer is a heavily doped layer of silicon that forms the base of the layer . The "P" indicates that the2024PF00753

[0149] 16

[0150] substrate is doped with acceptor impurities (such as boron) to create an abundance of positive charge carriers (holes) .

[0151] The purpose of the P-substrate layer is to provide a stable and conductive foundation for the epitaxial layer and the entire semiconductor device .

[0152] The P-substrate layer, being heavily doped, offers a stable and conductive foundation, managing the overall electrical behavior and ensuring mechanical integrity.

[0153] In an embodiment of the invention, the CMOS layer may comprise a P-EPI layer .

[0154] The P-EPI ( P-Epitaxial ) Layer is a lightly doped layer of silicon that is grown on top of a heavily doped substrate using a process called epitaxial growth.

[0155] The doping level in the P-EPI layer is controlled to achieve the desired electrical properties . The purpose of the P-EPI layer is to create a crystal structure with fewer defects . It also allows for better control over the electrical characteristics and isolation between different regions of the device .

[0156] The P-EPI layer, being lightly doped and epitaxially grown, enhances the electrical performance by providing precise control over the doping profile and reducing defects .

[0157] Furthermore, a sensor comprising the structure for a semiconductor device and a handheld or wearable device comprising the structure for a semiconductor device is proposed by the invention.

[0158] The steps of the method described herein are not required to be performed in the specific sequence listed unless explicitly stated otherwise . Certain steps may be executed concurrently or in parallel, depending on the implementation. Additionally, one or more steps may be optional, and their inclusion may2024PF00753

[0159] 17

[0160] vary based on the specific application. Steps that are functionally dependent on each other must follow the required sequence, while independent steps may be performed in any order . Furthermore, the method may include additional steps not explicitly described, or variations of the described steps, provided such steps or variations achieve substantially the same result .

[0161] Directional terms such as ' left, ' ' right, ' ' top, ' 'bottom, ' ' front, ' and 'back' are used herein for illustrative purposes and are not intended to limit the scope of the invention.

[0162] These terms are defined relative to the orientation of the device as illustrated and may vary depending on the context of use . Similarly, references to specific positions, orientations, or configurations, as well as optional components, are intended to describe illustrative examples and are not limiting. The invention may include variations, modifications, or additional features that achieve the same or equivalent function.

[0163] BRIEF DESCRIPTION OF THE DRAWINGS

[0164] In the following, the invention will be described in further detail with reference to the accompanying drawings, wherein:

[0165] FIG. 1 depicts an embodiment of a structure adapted for further processing for forming a semiconductor device, and

[0166] FIG. 2 depicts an embodiment of a structure adapted for further processing for forming a semiconductor device before and after bonding a CMOS and a filter layer together .

[0167] Identical parts are labelled by the same reference signs .2024PF00753

[0168] 18

[0169] DETAILED DESCRIPTION

[0170] The invention relates to a method for forming a structure 1 adapted for further processing for forming a semiconductor device, a structure 1 adapted for further processing in the forming of a semiconductor device being formed by such a method and a structure 1 for a semiconductor device .

[0171] In FIG. 1 such a structure 1 adapted for further processing in the forming of a semiconductor device being formed by such a method is depicted:

[0172] This structure 1 includes a filter layer 2 with a permanent handling layer 6, a bulk oxide layer 8 on top of the permanent handling layer 6, a hybrid filter layer 10 on top of the bulk oxide layer 8, and a passivation layer 12 on top of the hybrid filter layer 10.

[0173] Moreover, it comprises a CMOS layer 4 with another passivation layer 14, at least one TSV formed within the structure 1 (not shown) , and electrical connections arranged onto it (also not shown) .

[0174] The CMOS layer 4 may comprise a P-substrate layer 24.

[0175] The P-Substrate layer 24 is a heavily doped layer of silicon that forms the base of the layer . The "P" indicates that the substrate is doped with acceptor impurities (such as boron) to create an abundance of positive charge carriers (holes) .

[0176] The passivation layer 14 of the CMOS layer 4 contacts the passivation layer 12 of the filter layer 2.

[0177] Furthermore, the hybrid filter layer 10 comprises active and passive components 22 providing a balanced and efficient approach to signal processing.

[0178] The active components 20, such as transistors or amplifiers, actively manipulate electrical signals by amplifying,2024PF00753

[0179] 19

[0180] switching, or modulating them. These components require an external power source .

[0181] The passive components 22, such as resistors, capacitors, inductors or even barrier films function without requiring an external power source . Barrier films act as passive elements by protecting the underlying layers from environmental factors like moisture or contaminants .

[0182] By combining the dynamic control provided by active components 20 with the stable and noise-filtering properties of passive components 22, the hybrid filter layer 10 achieves enhanced signal precision and improved noise suppression.

[0183] FIG. 2 shows the process of combining and bonding the filter layer 2 and the CMOS layer 4. Also, the layers are depicted in more detail :

[0184] The active component 20 is depicted, which comprises intermediate frequencies serving as an active component for signal processing tasks such as modulation, demodulation, or amplification .

[0185] Typically implemented as an electronic circuit, the active component 20 converts a signal to an intermediate frequency that is easier to process or filter . In a hybrid filter, the active component 20 stage operates in conjunction with passive component 22 to achieve frequency selection and signal enhancement .

[0186] In this embodiment, the passive component 22 is a barrier film. A barrier film in semiconductor devices is a thin layer of material applied to prevent unwanted diffusion or interaction between different layers or materials .

[0187] The CMOS layer 4 depicted in the FIG. 2 comprises several layers arranged from top to bottom. At the top, there is the passivation layer 14, which serves as a protective shield,2024PF00753

[0188] 20

[0189] preventing contamination and providing electrical isolation for the underlying components .

[0190] Below the passivation layer 14 is the first oxide layer 30, which provides additional insulation. Next, there is a metal layer 32 embedded within this oxide layer 30, forming the electrical connections necessary for communication between different parts of the semiconductor device . Beneath this, there is a second oxide layer 30, further insulating and protecting the metal connections .

[0191] Within a P-EPI layer 26 of the CMOS layer 4, Nwells 28 are arranged, representing n-type wells formed in the p-type epitaxial layer . These Nwells 28 are for forming the n-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) in the CMOS layer 4 .

[0192] The P-EPI layer 26 is a thin, high-quality crystalline silicon layer that is lightly doped with acceptor impurities, providing a stable foundation for the CMOS layer 4 .

[0193] At the bottom, the P+ substrate layer, a heavily doped p-type substrate, offers a robust base for the entire structure 1, ensuring mechanical stability and proper electrical functioning .

[0194] The structure 1 may be formed by a certain method, which begins with providing a filter layer 2, which includes a permanent handling layer 6, a bulk oxide layer 8 on top of the handling layer, a hybrid filter layer 10 on the bulk oxide layer 8, and a passivation layer 12 on top of the hybrid filter layer 10. A CMOS (Complementary Metal-Oxide-Semiconductor) layer, which includes another passivation layer 14, is then provided.

[0195] The filter layer 2 is arranged on top of the CMOS layer 4 so that the passivation layers 12, 14 of both layers are in contact, as it can be seen from FIG. 2. The filter layer 2 and CMOS layer 4 are bonded together, after which at least one TSV2024PF00753

[0196] ( Through-Silicon Via) is formed in the structure 1. The process continues by applying electrical connections to the structure 1 .

[0197] In another embodiment, the permanent handling layer 6 comprises silicon or glass . Silicon and glass both have mechanical stability, thermal conductivity, and compatibility. This ensures that the layer provides robust support throughout the various stages of manufacturing, protecting the delicate layers and components of the semiconductor device .

[0198] This method is different to traditional methods, which typically start with depositing the CMOS layer 4 onto a temporary carrier layer followed by creating TSVs, applying a passivation layer 14, and then depositing hybrid filters .

[0199] Said new process helps avoid scrapping the CMOS layer 4 due to filter process issues, eliminates defects caused by temporary bonding voids, reduces the risk of damage, and streamlines the manufacturing process by eliminating the need for temporary bonding and debonding steps .

[0200] As used herein, the term ' layer ' refers to any structural or functional element forming part of the described structure, including, but not limited to, oxide layers, filter layers, substrate layers, handling layers, and wafers . The use of the term ' layer ' is not intended to limit the elements to thin film-like structures; it encompasses elements of varying thicknesses, compositions, and functionalities .

[0201] List of abbreviations :

[0202] spin-on glass SOG

[0203] Complementary Metal-Oxide- CMOS

[0204] S emi conductor

[0205] Through-Silicon Vias TSV

[0206] Integrated Circuit IC

[0207] Ball Grid Array BGA

[0208]

[0209] Waf er-to-waf er W2W2024PF00753

[0210] - 22 -

[0211] CMOS Image Sensor CIS

[0212] P-Epitaxial P-EPI Silicon dioxide SiO2Deep Reactive Ion Etching DRIE Me tai -Oxide- Semi conduct or MOSFET

[0213]

[0214] Field-Effect Transistor2024PF00753

[0215] - 23 -

[0216] LIST OF REFERENCE SIGNS

[0217] Structure 1 Filter layer 2 CMOS layer 4 Permanent handling layer 6 Bulk oxide layer 8 Hybrid filter layer 10 Passivation layer (of Filter layer) 12 Passivation layer (of CMOS layer) 14 Active component 20 Passive component 22 P-Substrate layer 24 P-EPI layer 26 Nwells 28 Oxide layer 30 Metal layer 32

Claims

2024PF0075324CLAIMS1 . A method for forming a structure adapted for further processing for forming a semiconductor device , comprising the steps of :- providing a filter layer ( 2 ) comprising- a permanent handling layer ( 6 ) ,- a bulk oxide layer ( 8 ) on top of the permanent handling layer ( 6 ) ,- a hybrid filter layer ( 10 ) arranged on top of the bulk oxide layer ( 8 ) , and- a passivation layer ( 12 ) arranged on top of the hybrid filter layer ( 10 ) ,- providing a CMOS ( Complementary Metal-Oxide- Semiconductor ) layer, comprising another passivation layer ( 14 ) arranged on top of the CMOS layer ( 4 ) , - arranging the filter layer ( 2 ) on top of the CMOS layer ( 4 ) ,so that the passivation layer ( 12 ) of the filter layer ( 2 ) is contacting the passivation layer ( 14 ) of the CMOS layer ( 4 ) ,- bonding the filter layer ( 2 ) and the CMOS layer ( 4 ) , - forming at least one TSV in the structure ( 1 ) ,- applying electrical connections onto the structure ( 1 ) , wherein the steps of- arranging the filter layer ( 2 ) on top of the CMOS layer ( 4 ) ,so that the passivation layer ( 12 ) of the filter layer ( 2 ) is contacting the CMOS layer ( 4 ) ,and- bonding the filter layer ( 2 ) and the CMOS layer ( 4 ) are performed before the step of- forming the at least one TSV in the structure ( 1 ) .2 . A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to claim 1 ,2024PF0075325wherein the CMOS layer (4 ) comprises a CMOS Image Sensor (CIS) .

3. A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to claim 1 or 2,wherein the step of- applying electrical connections onto the structure ( 1 ) is performed after the step offorming at least one TSV in the structure ( 1 ) .

4. A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to any one of the preceding claims,wherein the permanent handling layer ( 6) comprises glass .

5. A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to any one of the preceding claims,wherein the hybrid filter layer ( 10) comprises an active (20) and a passive (22 ) component .

6. A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to claim 5,wherein the active component (20) is an Integrated Circuit (IC) .

7. A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to claim 5 or 6,wherein the passive component (22 ) is a barrier film layer with at least one aperture in it .

8. A method for forming a structure ( 1 ) adapted for further processing for forming a semiconductor device according to any one of claims 1 to 3 and 5 to 7,wherein the permanent handling layer ( 6) comprises silicon.2024PF00753269 . A structure ( 1 ) adapted for further processing in the forming of a semiconductor device and formed by a method comprising the steps of :- providing a filter layer ( 2 ) comprising- A permanent handling layer ( 6 ) ,- A bulk oxide layer ( 8 ) on top of the permanent handling layer ( 6 ) ,- A hybrid filter layer ( 10 ) arranged on top of the bulk oxide layer ( 8 ) , and- A passivation layer ( 12 ) arranged on top of the hybrid filter layer ( 10 ) ,- providing a CMOS layer ( 4 ) , comprising a passivation layer ( 14 ) arranged on top of the CMOS layer ( 4 ) , - arranging the filter layer ( 2 ) on top of the CMOS layer ( 4 ) so that the passivation layer ( 12 ) of the filter layer ( 2 ) is contacting the passivation layer ( 14 ) of the CMOS layer ( 4 ) ,- bonding the filter layer ( 2 ) and the CMOS layer ( 4 ) , - forming at least one TSV in the structure ( 1 ) ,- applying electrical connections onto the structure ( 1 ) , wherein the steps of :- arranging the filter layer ( 2 ) on top of the CMOS layer ( 4 ) so that the passivation layer ( 12 ) of the filter layer ( 2 ) is contacting the passivation layer ( 14 ) of the CMOS layer ( 4 )and- bonding the filter layer ( 2 ) and the CMOS layer ( 4 ) are performed before the step of :- forming the at least one TSV in the structure ( 1 ) .10 . A structure ( 1 ) for a semiconductor device , comprising :- a filter layer ( 2 ) , which includes :a permanent handling layer ( 6 ) ,- a bulk oxide layer ( 8 ) ,- a hybrid filter layer ( 10 ) arranged on top of the bulk oxide layer ( 8 ) ,- a passivation layer ( 12 ) arranged on top of the hybrid filter layer ( 10 ) ,2024PF00753a CMOS layer ( 4 ) comprising another passivation layer ( 14 ) ,at least one TSV formed in the structure ( 1 ) , electrical connections arranged onto the structure ( 1 ) , andwherein the another passivation layer ( 14 ) of the CMOS layer ( 4 ) is arranged on top of the passivation layer ( 12 ) of the filter layer ( 2 ) .11 . A structure ( 1 ) for a semiconductor device according to claim 10 ,wherein the CMOS layer ( 4 ) comprises a P-substrate layer ( 24 ) .12 . A structure ( 1 ) for a semiconductor device according to claim 10 or 11 ,wherein the CMOS layer ( 4 ) comprises a P-EPI layer ( 26 ) .13 . A sensor comprising the structure ( 1 ) for a semiconductor device according to any one of claims 10 to 12 .14 . A handheld or wearable device comprising the structure ( 1 ) for a semiconductor device according to any one of claims 10 to 12 .

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